Microelectronic Circuits

Amplifier design

Bits, pilani

MOSFET AMPLIFIER

Bits, pilani
Aim

Design an amplifier of gain 30 v/v

Choose the device (MOS , BJT)

Set DC bias

Choose a circuit topology

Design

Analyse

Re-design

Bits, pilani
MOSFET

TRANSCONDUCTANCE

----defines gain
Bits, pilani
SYMBOLS

Bits, pilani
CHOICE OF INPUT AND OUTPUT

3 parameters---VGS, VDS, ID, (Vsb= for advanced course)

ID (VGS, VDS)

ID---captures variation----output

either VGS / VDS can be input

but if VDS is input, no other terminal is
available for output

so only VGS can be the input

Now what should be Vds?
Where to bias ?

Max gain-------MAX IDRD------------MAX ID

Min distortion

I D= f (VGS)------SATURATION REGION

Max current, ID captures variations of VGS
faithfully

ID= f (VGS, VDS)-----------LINEAR REGION

Min current, ID varies with VGS , VDS ---(extra
variation)

Bits, pilani
MOS equations
Transfer charac.

Bits, pilani
Output charac.load line

Bits, pilani
MOS AMPLIFIER

Bits, pilani
DC BIAS

Bits, pilani
Understanding MOS

Bits, pilani
Bits, pilani
Bits, pilani
Bits, pilani
MODEL

Bits, pilani
SECONDARY EFFECTS

Bits, pilani
CHANNEL LENGTH MODULATION

Bits, pilani
ID increases with VDS
MODIFIED MODEL & equ

W
I D = K ' [VGS VT 0 ] (1 + VDS )
2

L
Bits, pilani
BODY BIAS EFFECT

VT= VTO + [(2F + VSB) (2F) ]

2qN A s
=
C ox
W
I D = K ' [VGS VT ] (1 + VDS )
2

ID reduces
Bits, pilani
Impact of body bias
Id Vsb1 Vsb2 Vsb3

Vt1 Vt2 Vt3

Vgs

Vsb1< Vsb2 < Vsb3

Temperature effects

Vt, K , are temperature sensitive

Vt reduces at a rate of 2mv per degree rise in
temp.

Breakdown---

Oxide breakdown, punch through

Bits, pilani
Techniques to set DC bias--
DISCRETE CKT.

Using two supply voltages or generate VGS

Bits, pilani
STABILITY OF Q POINT FIX VGS

Vt reduces at high temperature

Vt

Fix VG, but VS can adjust. ID rolls back

Using degeneration resistance

VG = VGS + I D RS
Id

Q
Id2
Q
Id1

-1/Rs

Vt1 Vgs1
Vt2 Vgs
Using single DC supply

POTENTIAL DIVIDER BIAS

Bits, pilani VG = VGS + I D RS

Q point stability

Case-1------Vg increases due to power supply
fluctuation
Vg Vgs Id (Id Rs) Vgs

Case-2----- VT decreases due to temperature

fluctuation
VT ( Vgs VT ) Id (Id Rs) Vgs ( Vgs VT )

Bits, pilani
Setting DC BIAS

DRAIN TO GATE FEEDBACK BIAS

V DD = VGS + I D RD

Bits, pilani
Sensitivity
 Sensitivity of Id to Vdd fluctuation

[V G V GS ]= I R1=1M
R2=10K
D Rs=1k
Rs ID=1mA
If Vgs constant
Vdd=10v
R2
R + R I D
1 2 I D 0.1
Vdd
=S
= ID Vdd
Rs Vdd
If Vgs not constant

2I D
VGS = Vt +
' (W )
Kn
L

ID

Substitute Vgs and recalculate SV
DD
Sensitivity of Id to Temp. change

VG VGS I D Rs
T T = Rs T + I D T

Bits, pilani
Bits, pilani
Bits, pilani
IC BIASINGcurrent bias

Bits, pilani
PMOS Current Mirror

Bits, pilani
Matched transistors keep fab.
conditions same

Bits, pilani
Bits, pilani
Why current biasing for ICs?

To do away with coupling capacitors

Bits, pilani
Why do we need coupling capacitors?

To isolate the d.c bias voltges of two adjacent

amplifiers biased using voltage biasing technique

Bits, pilani
GAIN EXPRESSION

Bits, pilani
Amplifier equ.

y, x voltage or current

For a narrow range of x

Bits, pilani
Current expression in sat. region

Bits, pilani
Output voltage/ gain expression

Bits, pilani
Distortion

Bits, pilani
SMALL SIGNAL APPROX

HOW MUCH SMALL?

Vgs << 2Vov

Bits, pilani
GAIN IN SATURATION REGION, IN LINEAR

AV= - RD KN(W/L) (VOV) (more)

AV= - VDD RD KN(W/L) / [1+ RD KN(W/L) VOV]2

(less)

Bits, pilani
Gain in saturation

Av= - gm RD (effect of ro not taken into account)

AV= - RD KN(W/L) (VOV)

gm = KN (W/L) (VOV)---trans-conductance

= 2 ID/ Vov

= [2 KN(W/L) ID]
Bits, pilani
gm

Bits, pilani
SMALL SIGNAL PARAMETERS

gm --transconductance

rodrain resistance

gmb---body transconductance

iD= f (vDS, vGS. VSB)

Bits, pilani
iD= f (vDS, vGS, VSB)Taylor approx.

iD iD iD
iD |Q vGS + vDS + vSB
vGS vDS vSB
iD iD iD
I D + id I D + vgs + vds + vsb
vGS vDS vSB
iD iD iD
id = [ vgs + vds + vsb ]Q
vGS vDS vSB
id = g m vgs + g d vds + g mb vsb
Bits, pilani
Plot the graphs---do yourself

gm vs. w/L for Id constant

gm vs. w/L for Vov. Constant

gm vs. Id for Vov. Constant

Bits, pilani
 With

Correction in book is required

Bits, pilani
Bits, pilani
Bits, pilani
Model parameters

Bits, pilani
Complete AC model

Bits, pilani
NMOS

Bits, pilani
PMOS

Bits, pilani
 Converting to T model

Figure 4.39 Development of the T equivalent-circuit model for the MOSFET. For simplicity, ro has been omitted but can
be added between D and S in the T model of (d).
Bits, pilani
How to draw AC model of amplifier?

For amplification, only

AC behaviour needs
to be considered

Replace MOS by its

model in the circuit

Bits, pilani
2 Sources in ckt.1 ac, 1dc

Bits, pilani
Bits, pilani
Using superposition

Source Vdd/or
Source Ibias
voutDC = Vdd I bias RD
ro
voutDC = Vdd
RD + ro

Source i voutAC = i [ro || RD ]

Bits, pilani
Considering only AC

voutAC = i [ro || RD ]
Bits, pilani
Bits, pilani