Speedgoat Solutions and Use

2011 The MathWorks, Inc.1

What Engineers Want to Design:
Complex Products

What have these products in common?

All designed with the help of Speedgoat real-time target machines, and Simulink Real-Time
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Table of Contents

Speedgoat at a glance
Introduction to Speedgoat and the global sales network

Real-Time Simulation and Testing Introduction

Simulink Real-Time and Speedgoat target machines are expressly designed to
work together to create real-time systems for desktop, lab, and field environments

Connect and interface with your hardware under test

Gain access to all available I/O connectivity of your target machine via the
Speedgoat driver library, and leverage the power of multicore CPUs and FPGAs

Speedgoat target machines, I/O, and protocols

Turnkey real-time target machines for office, lab, field, and in-vehicle use, and a
large portfolio of 150+ I/O modules

Characterization of your real-time target machine

Specifying sample time, I/O, and protocol requirements for your application

Delivery, Setup, Commissioning, and Maintenance

Speedgoat support and service offerings

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Speedgoat at a glance

2011 The MathWorks, Inc.4

About Speedgoat

Highly specialized developer of Real-time target machines,

expressly designed to work with Simulink and Simulink Real-Time
Incorporated in 2007 by MathWorks employees
Average annual revenue growth rates of 45% since foundation
Over 2000 Real-time target machines sold
Located in Bern, the Swiss capital, world-wide distribution network
Customers: 40% EMEA, 40% AMER, 20% APAC

Office Examples
Impressions
from Bern

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About Speedgoat
Global Sales Network

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Real-Time Simulation and Testing
Introduction

2011 The MathWorks, Inc.7

Sometimes its nice to have
something that works really
quick!

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 Real-Time Simulation and Testing

Build, Run, and Test Real-Time Applications!

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 Real-Time Simulation and Testing
Always Real-Time

Simulink Real-Time and Speedgoats real-time target

machine(s) together form a hard real-time system

Execution Reaction-time deterministic

tied to the
wall clock + Guaranteed by real-time
kernel on target computer

Hard real-time systems operate within the confines of a stringent

deadline. The application is considered to have failed if it does not
complete its function within the allotted sample time. Overruns can
however be allowed if required.

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 Real-Time Simulation and Testing
Applications

Industrial A&M
Aerospace
Medical Devices Automotive
& Defense Energy Production
Industry
Lens Subsystems Mechatronics / Robotics Off-highway
UAVs Power electronics Heavy equipment
Integration & iron birds Protocol-heavy Electric/hybrid
Research/concepts Hearing aids Racing
One-off products Renewable energy Research/concepts
Advanced academic Research/concepts One-off products
One-off products Advanced academic
Advanced academic

Application Controls DSP & Vision Systems

Lens Rapid Control Prototyping (RCP) Prototyping
Hardware-In-the-Loop Simulation Closed-loop
(HIL) Sample- & small-frame-based
Functional separable units Part of a larger controls application
Proof of concept Simulink centric
One-off products Research/concepts
Advanced academic One-off products

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Real-Time Simulation and Testing
Typical Tasks

Typical real-time simulation and testing tasks supported include:

Rapid Control Prototyping

DSP and Vision System Prototyping

Hardware-in-the-Loop (HiL) simulation

Hybrid electric bus Jet engine Hearing aid device

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Connect and interface with your
hardware under test and leverage the
power of CPUs and FPGAs

2011 The MathWorks, Inc.

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Connect with your hardware under test

Drag & drop driver blocks for I/O modules installed

in target machine to your model
Connect I/O ports of driver blocks with your design

Speedgoat driver library

Simulink model

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 Connect with your hardware under test

Simulink model
Configure I/O and protocols
settings through dialog fields
Automatically create and run
a real-time application from
your Simulink model on the
target machine

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 Concurrent Execution, Distributed Systems

1. Accelerate real-time execution by leveraging powerful multi-core

CPUs through concurrent execution features of Simulink Real-
Time
2. Scale up performance by using multiple target machines,
connected via fiber optic link. Execution of multiple, synchronized
distributed models at lowest closed-loop sample rates
speedgoat
1 2 real- time target machine

%% Display Profiling Data Shared

memory
profileInfo.modelname =
12345.mdl';
profData =
profile_xpc(profileInfo); optical cable

speedgoat
real- time target machine
CPU2 CPU1

Shared
memory

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 Create FPGA I/O and algorithmic subsystems

Requirements Example of FPGA-based I/O module

HDL Coder and Xilinx ISE (Vivado) software

Speedgoat real-time target machine with installed
FPGA-based I/O module(s)
Fixed-point Simulink model

Key features

Very fast design iterations and verification and

IO331 I/O module with IO331-6 front plug-in
validation of Simulink algorithms on FPGAs
- Spartan 6 with 147k logic cells and
Achieve closed-loop sample rates up to several MHz fundamental clock rate of 75MHz
by execution parts of your real-time application on Powerful I/O connectivity
FPGA(s), eliminating PCI bus communication - 16 simultaneous analog inputs
- 8 analog outputs
Seamless workflow for concurrent execution of
- 64 digital 2.5 LVCMOS, or 3.3/5V TTL lines
model components on FPGAs mounted on I/O
modules also providing a broad range of I/O
Connect multiple FPGA-based I/O modules with
high-speed inter-module communication links

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Create FPGA I/O and algorithmic subsystems

Key tasks

Design subsystems for FPGA

execution
Configure I/O communication using
Workflow Advisor, provided with
MathWorkss HDL Coder
Integrate Speedgoat Netlists
(PWM generation and caputure,
encoder measurement ans
simulation, SPI, I2C,
synchronization, )
Automatically generate HDL code for
the Simulink FPGA subsystems
Place the generated blackbox
subsystem to your main Simulink
model

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Create FPGA I/O and algorithmic subsystems
Demo FPGA Model

PWM Capture
FPGA Code Module

PWM Generation
FPGA Design

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 Create FPGA I/O and algorithmic subsystems
Demo Workflow Advisor

Select Simulink Real-Time FPGA

I/O workflow
Select the desired Speedgoat I/O
module
Map I/O of I/O module to input and
output ports of the FPGA subsystem
Generate HDL Code and perform
synthesis and analysis using Xilinx
ISE (provided with Xilinx Vivado
Design Suite)
Create FPGA bitstream and Simulink
driver block, acting as interface for
Simulink Real-Time

Workflow Advisor of HDL Coder

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Create FPGA I/O and algorithmic subsystems
Demo Workflow Advisor Results

FPGA subsystem block of real-time

application running on IO331

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Create FPGA I/O and algorithmic subsystems
Demo Simulink Real-Time model

FPGA subsystem block of real-

time application running on IO331
Multi-rate
concurrent
execution

Scopes and
displays to
Slider gains: tune monitor
parameters during signals
real-time execution

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Instrument your Real-Time Applications

Simulink Real-Time provides flexible

instrumentation to interface with the
target computer and the running real-
time application
Simulink Real-Time Explorer (host scopes)
Target display (target scopes)
Analysis of logged data (file scopes)
Simulink External Mode
MATLAB functions and objects for automation
Stand-alone User Interfaces
(MATLAB UI, external APIs, 3rd party tools)
Reactive Automated Testing with TPT from Piketec
Manage and control multiple target machines
simultaneously

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Instrument your Real-Time Applications
Simulink Real-Time Explorer

Manage and control Real-time target machines and applications

Graphical controls and displays to design and run instrument panels
Monitor signals using scopes, and log data on the fly
Tune parameters individually or as groups

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Instrument your Real-Time Applications
High-Resolution Target Display to Monitor and Control Signals

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 Instrument your Real-Time Applications
Versatile interfacing options

Simulink Data logging

External
Click to
Mode
Start

>> tg = xpc; % Create xPC Target object

>> tg.load('mct_xpcClosedLoop'); % Load application MATLAB TPT from PikeTec
>> tg.start; % Start application scripts Reactive Automated Testing
>> Amp=tg.getparamid('Signal Generator', 'Amplitude');
>> tg.setparam(Amp,2) % Change Amplitude value

ans =
parIndexVec: 2
OldValues: 0.5000
NewValues: 2

>> tg.stop; % Stop application

>> plot(tg.TimeLog,tg.OutputLog(:,[1 2])) % Plot data

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 Creating Stand-Alone Applications and GUIs

Embed real-time applications

Simple: Simply select standalone mode

Normal mode: Target machine is connected to

development computer with Ethernet cable,
application parameters are dynamically tunable
during real-time runs

Standalone mode: Real-time application and

real-time kernel are combined to a single
executable. Applications starts at power-up of
target machine

Standalone User Interfaces

Run Simulink Real-Time Explorer in standalone
mode, or leverage C or .NET APIs

Royalty Free
One license, many target machines

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Overview of Speedgoat target machines,
I/O, and protocol interface hardware

2011 The MathWorks, Inc.

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Real-time target machines

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Turnkey Real-Time Target Machines for
office, lab, field, and in-vehicle use

Performance real-time Mobile real-time Education real-time

target machine target machine target machine

Office and lab Field and in-vehicle use Academic use

Audio real-time Openframe real-time Modular real-time

target machine target machine target machine

Confined and harsh

Audio applications environments cPCI/PXI-based solutions

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Turnkey Real-Time Target Machines for
office, lab, field, and in-vehicle use

Performance real-time target machine

State-of-the-art Intel Core i7 3.5 GHz quad core

Intel CPU and optional Xilinx FPGA technology
Concurrent multicore, multi target, and FPGA
real-time application execution
Flexible expansion concept:
install 50+ I/O modules
Flexible mounting
and I/O access

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Use Case Proterra, USA
User Story

Application

ECU test bench for all-electric,

zero emission transit bus
The bus rapidly recharges at
on-route charging stations
2-3 hour range

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Turnkey Real-Time Target Machines for
office, lab, field, and in-vehicle use

Mobile real-time target machine

Up to Intel Core i7 2.53 GHz

dual core CPU
Very robust and fanless design,
extended temperature support
Stack up: 1-4 layers with 3
PMC/XMC modules each
Two additional I/O slots for I/O modules in the mPCIe form factor
Over 200 I/O modules offering a very broad range of connectivity
Gigabit link for data exchange between FPGA-based I/O modules
Built-in support for EtherCAT Master, real-time UDP, and serial I/O

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Use Case Levant Power, USA
User Story

Application

Development of worlds first hydraulic

regenerative active suspension
System recognizes and adapts to
driver behavior, acceleration, braking,
cornering, and road conditions
Energy-neutral operation

GenShock shock absorber

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Turnkey Real-Time Target Machines for
office, lab, field, and in-vehicle use

Performance real-time Mobile real-time Education real-time Attractive price tag

target machine target machine target machine
Industrial-grade solution to
study, teach, and research

Office and lab Field and in-vehicle use Academic use

Audio real-time Openframe real-time Modular real-time

target machine target machine target machine

Confined and harsh

Audio applications environments cPCI/PXI-based solutions
Example: Position control (Bachelor thesis, FH Aalen,
Germany)

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I/O connectivity

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I/O connectivity

Configurable Static
I/O Type Functionality (FPGA)

Analog A/D, D/A, frame support x x

Digital TTL, LVCMOS, LVDS, RS422, RS485 x x

Pulse train PWM generation and capture, interrupt, negation X

Encoders Absolute and incremental encoder (quadrature and SSI), EnDAT X

2.2, SSI2, and BiSS encoder measurement and emulation
Video USB (Webcams), CameraLink x

LVDT/RVDT, LVDT, RVDT, Synchro, and Resolver measurement and x

Synchro/ Resolver simulation
Shared memory Shared and reflective memory x

Temperature Thermocouple, RTD, and NTC measurement and simulation

Strain, pressure Strain gauges and pressure sensor measurement and simulation x

Accelerometers IEPE/ICP measurement x

Switching Resistor, potentiometer, reed relay (SPDT, DPST, SPST), and x

fault insertion

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Protocol interfaces

Configurable Static
Protocol Functionality (FPGA)

SPI SPI Master, SPI Slave x

I2C I2C Master, I2C Slave x

CAN CAN, LIN, SAE J1939, CANopen x

Serial (UART) RS232, RS422, RS485, SDLC, HDLC x x

Ethernet Real-time UDP, Raw Ethernet, TCP/IP x

EtherCAT EtherCAT Master, EtherCAT Slave x

EtherNet/IP EtherNet/IP Scanner, EtherNet/IP Adapter x

Profibus, Profinet Profibus and Profinet Master and Slave x

Modbus Modbus TCP and RTU (Gateway) x

Aerospace ARINC429, MIL-STD-1553 x

XCP XCP over CAN and Ethernet x

FlexRay FlexRay x

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Specify functionality, select, and
maintain your Real-time target machine

2011 The MathWorks, Inc.

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Characterization of Physical Systems
Under Test

1. Deriving the fundamental sample time for a real-time

application
2. Software and hardware considerations for different
sample time requirements

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Deriving the fundamental sample time

Time constants (how quickly a system responds)

derived from domain knowledge or system analysis

Step or impulse response (linear or linearized; non-linear)

Time constant is ~37% of the time it takes to reach steady-state
Sample time of real-time application: 1/10 to 1/20 of (smallest) time
constant for quasi-continuous behavior (allows for continuous
states at fundamental sample time and higher-order integration
algorithms)
Discrete real-time application (controller) design might increase
sample time
Eigenvalues of a linearized system around an operational point

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Deriving the fundamental sample time

Defined by application or a standard.

Example:
Audio (sound) sample frequency standard 44.10 kHz
Reduced bandwith for hearing aid (voice) 22.05 kHz
= sample time 45.35us

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Deriving the fundamental sample time

Derived from simulation/linearization of plant model.

Requires (benefits from) a Simulink model of the physical (dynamic)
system (plant)
Model complexity dependent on required fidelity level
Stimuli-response simulations -> time constants
Linearization and obtaining state-space description around operational
point with Simulink Control Design
Eigenvalues lead to time constant(s)
Apply again 1/10 to 1/20 of time constant rule to derive fundamental
sample time for real-time application
For quasi-continuous behavior
Study and verify sampling behavior with Simulink model
Existing plant model facilitates HIL simulation and testing

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Sample rate ranges, SW/HW considerations

A 1 ms

Usually of no concern, plenty of headroom

Watch out for heavy algorithms, mainly plant models
for real-time simulation described using physical
modeling blocks

B 250us 1 ms

Usually of no concern for applications with analog and

digital I/O
Watch out for low-bandwidth protocol interface I/O like
asynchronous serial communication such as RS232
(115200 kb/s) or CAN (1Mb/s)

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Sample rate ranges, SW/HW considerations

C 50us .. 250 us

Microsecond granularity (interrupt latency) of multi-

tasking kernel becomes a factor
For all I/O and protocol interfaces connecting to the
physical system, latency calculations need to be
conducted
Mid-sidzed algorithms even if expressed with native
Simulink blocks might signifcantly impact computational
load
Headroom might shrink below the recommended 20%
Fast I/O modules for given I/O types, such as
simultaneous sampling analog input modules, might be
required

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Sample rate ranges, SW/HW considerations

D 15us .. 50 us

5us interrupt latency of Simulink Real-Time kernel

becomes an important factor
Fastest I/O module technology required. Example:
highest conversion-rate ADCs with simultaneous
sampling (one ADC per input channel), DMA acquisition
Any protocol interface at this sample time becomes an
issue change these to different sample rates using
multi-rate modeling
I/O latency calculations are mandatory
Consider to outsource I/O and algorithmic sub-functions
to FPGAs

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Sample rate ranges, SW/HW considerations

E 0.01us 15us
Consider polling mode for simple controllers with few I/Os (>= 8us)
Run algorithms and I/O on FPGA subsystems

FPGA
I/O
Module

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Specifying sample time, I/O, and protocol
requirements for a specific application

2011 The MathWorks, Inc.

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Specifying sample time, I/O, and protocol
requirements for a specific application

Three example use cases

1. Rapid Controller Prototyping (RCP) for development and test of

control strategies for a hybrid drive concept

2. DSP System Prototyping of next generation hearing aid devices

3. Hardware in-the-loop (HIL) lab simulator for jet engine simulation

Hearing aid device Jet engine Hybrid electric bus

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Use case 1 Hybrid electric bus

Customers Vision
Development and test of control strategies for a hybrid
drive concept. The existing real-time setup is based on a
do-it-yourself hardware configuration. It is no longer
feasible to maintain real-time testing hardware in-house
because of the increasing complexity of the system.
Hybrid electric bus
Customers Hardware requirements
In-vehicle use, only DC power supply available
Harsh environment, temperatures up to 50C
Closed-loop sample rate of 1kHz, on-target data logging
CAN (J1939), and real-time UDP communication
Analog and digital connectivity

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Use case 1 Hybrid electric bus
Receipt of Technical Specification/Application

Technical team at MathWorks and

Speedgoat takes care of your
requirements specification
Technical ales are available by email or
phone to answer your questions
Fill in your technical specifications to
the requirements worksheet
The worksheet is available for download
on the Speedgoat webpage

Requirements worksheet

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Use case 1 Hybrid electric bus
Custom Solution Proposal

Technical Sales Engineers discuss requirements and prepare a specific

solution proposal for a real-time target machine
For this case, we propose:
Mobile real-time target machine
Robust SSD drive
1x IO101 for analog and digital
2x IO601 for CAN communication
Extended temperature option for
all components
The customer receives the quotation, and a solution proposal document
outlining the technical aspects of the proposed hardware configuration

The requirements worksheet document is a great common technical starting point

to work towards your tailored real-time testing solution!

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Use case 1 Hybrid electric bus
Custom Solution Proposal

Technical Sales Engineers demonstrate

capabilities of the proposed solution
online, by phone, or on-site

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Use case 2 Hearing aid devices
Technical Specification/Application

Customers Vision
Development of next generation hearing aid devices. A flexible real-time
testing development platform is needed to quickly test new ideas on how to
optimize sound quality and at the same time reduce the power consumption
of the device. The system must deal with complex model algorithms and base
sample rates up to 20.48 kHz.

Customers Hardware requirements

The highest performance real-time system for lab use
Frame-based sampling of high resolution analog channels
XLR panels for easy access of individual channels
Hearing aid device
Simulation of stereo audio channels at a later time

DSP System Prototyping

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Use case 2 Hearing aid devices
Solution Proposal

Solution
Performance real time target machine with the fastest Intel Core i7, quad-
core, 3.5GHz CPU
IO108 I/O module with 8 balanced, differential analog output channels,
dedicated D/A converter per channel and 16-bit resolution
IO109 I/O module with 12 differential analog input channels, simultaneous
sampling,
dedicated Sigma-Delta A/D converter and 24-bit resolution
Dedicated XLR Panels, mounted into portable, robust rack
Optional shared memory I/O modules to connect two target machines

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Use case 3 Engine simulation
Technical Specification/Application

Customers Vision
Simulation of complete jet engine to avoid having to
develop expensive hardware prototypes, and to be
able to continuously test controllers in the lab.
Jet engine
Customers Hardware requirements
HIL lab system for engine simulation
Interface to engine controller through multiple
simulation and measurement I/O points
Isolated digital I/O channels
Differential analog I/O channels Hardware under test:
FADEC, full authority
LVDT simulation
digital engine controller
Encoder simulation
RTD simulation
Shared memory interface

Hardware in-the-loop Simulation

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Use case 3 Engine simulation
Solution Proposal

Solution

Development/target computer Ethernet switch

6 LVDT Simulation channels (IO422)

Shared/Reflective Memory (IO902 )

FPGA 16 Encoder Emulation channels (IO312)

32 24V digital input channels (IO206)

32 24V/0.5A digital output channels (IO205)

16 DIFF 16-bit analog output channels (IO107)

32 SE/16 DIFF 16-bit analog input, 4 SE analog

output, 8 TTL digital input, 8 TTL digital
output channels (IO102)

RTD simulation (IO926)

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Delivery, Setup, Commissioning,
and Maintenance

2011 The MathWorks, Inc.

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Delivery, Initial Setup and Acceptance
Testing
Speedgoat team takes care to carefully
assemble, test, and deliver hardware to
your needs.

Systems Engineering

Engineering Services

Operations

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Delivery, Initial Setup and Acceptance
Testing
Systems Engineering
All Speedgoat real-time target machines are
assembled and tested at our facility
Optimized for your required MATLAB release
Firmware upgrades and compatibility considerations
Optimization of BIOS settings and interrupts
for all I/O modules
Real-time kernel updates
Complete 24 hour system test of all I/O
connectivity to ensure fault-free operation and
best real-time performance

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Delivery, Initial Setup and Acceptance
Testing
Speedgoat Engineering Services
Speedgoat FPGA bitstreams
PWM signals
Incremental/absoute encoders
Protocol support
Available for simulation and emulation
Driver development for custom I/O modules
Simulink driver blocks
C/C++ driver blocks
VHDL implementations
Advanced training / consulting services

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Delivery, Initial Setup and Acceptance
Testing
Operations
Typical lead time: 4 weeks after receipt of
purchase order. Shipping time: 1-2 days
Delivery via your preferred carrier
Option for partial delivery available

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Building, running, and testing your real-time
applications
Contents of delivery include:

Real-time target machine I/O modules installed in target machine

I/O cables Terminal boards Driver blocks Simulink test models Documentation

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Building, running, and testing your real-time
applications
Software prerequisites
The following MathWorks software is minimally required:
MATLAB (32-bit or 64-bit)
Simulink
MATLAB Coder
Simulink Coder
Simulink Real-Time (xPC Target)

To build the generated code a compiler is required:

Microsoft Windows SDK 7.1 (available at no charge)
Microsoft Professional 2013, 2012, 2010 and 2008 compilers
See www.mathworks.com/support/compilers

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Building, running, and testing your real-time
applications
Simulink test model
The delivery includes a Simulink test model, prepared for the required
software release. This model contains Speedgoat driver blocks for all
available I/O connectivity and applies a loop-back test to ensure flawless
execution of the complete real-time testing hardware.

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Support, upgrades, and maintenance of
your Speedgoat target real-time system
Hardware Warranty and Maintenance
Each Speedgoat real-time target machine is provided with flexible services
packages to protect your investments and ensure continuous maintenance
of your real-time system.

Long-term Supply
Expand your existing real-time hardware with
additional I/O modules / expansion chassis
Long-term availability of all hardware
components

Technical Support
Speedgoat support webpage
MathWorks support webpage
After sales engineering services available

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User Story Examples - Developing Complex
Products meeting Future Demands

Proterra, Greenville, SC, USA

Zero-Emmission Battery Electric Bus
Hardware-in-the-Loop simulation

Mobileye, Jerusalem, Israel

Advanced Driver Assistance Systems, and
fully Autonomous Vehicles
In-vehicle Rapid Controller Prototyping

AGCO, France/Germany/USA
Agricultural vehicles with most energy
efficient gearboxes
Hardware-in-the-loop simulation

www.speedgoat.ch/userstories

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Support, upgrades, and maintenance of
your Speedgoat target real-time system

www.speedgoat.ch www.mathworks.com

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