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D Q
CLK
1
page 2
The Selector
Truth Table
A 0
Q S Q
B 1 0 A
1 B
B
Truth Table AB
S 00 01 11 10
S Q 0 00 11 11 00
0 A
1 B 1 00 00 11 11 S
2
page 3
Selectors K-Map
B
AB
S 00 01 11 10
A 0
P2
0 0 0 1 1
B 1 1 0 1 1 0 S
S P1 A
S
P1
B
3
page 4
S:
P1
P2
Hazards
Static Hazards:
Output Enters Forbidden Zone
Unnecessarily
1-Hazards
0-Hazards
Dynamic Hazards:
Output Enters Same Valid Zone Again after
Entering Opposite Valid Zone
0-1 Hazards
1-0 Hazards
4
page 5
S TTpd
pdmax
max
TTcd
cd==t tpd
pdmin
min
S
Q
5
page 6
Fundamental Mode
SIC (Single Input Change) rule
Only 1 Input Bit Can Change At a
Time
> Tw
How Computers Work Lecture 7 Page 11
B
AB A
S 00 01 11 10
0 0 0 1 1
1 0 1 1 0 S
S
A B
6
page 7
MUX Implementation
of the Transparent Latch
D
0
Q G
D 1
Q
G
7
page 8
State Diagram
of D-Latch
GD
G+D 0 1 G +D
GD
D Q
Definition:
Fundamental Mode
Finite State Machine (FSM)
Finite # of States
Output = f(State, Input)
May just be f(State)
State Transitions occur asynchronously
due to asynchronous (no clock) input
level changes.
8
page 9
Architecture of
Fundamental Mode FSM
IN OUT
C.L.
STATE
Fundamental Mode
SIC (Single Input Change) rule
Only 1 Input Bit Can Change At a
Time
> Tw
How Computers Work Lecture 7 Page 18
9
page 10
Hold time
Th = ________________
Hold time
Setup time
Ts = ____________________
Setup time
S S
S 0 1 S+R
R S
How Computers Work Lecture 7 Page 20
10
page 11
Q R Q
R
Set 0 1 Reset
Reset
11
page 12
Building a Latch
from an SR Flop
R
__
Q
_____
Q
D S QQ
_____
G
12
page 13
CLK
D Q
CLK
Q
D D Q D Q Q
G G
CLK
H
CLK=_________
H
L
CLK=_________
L
13
page 14
CLK
Hold Time
Th = ________________
Hold Time
Setup Time
Ts = ____________________
Setup Time
A Pneumatic Flip-Flop
14
page 15
A Mechanical Flip-Flop
Clock Escapement
Another Example
of a Flip-Flop
15