2015 International Conference on Information and Communication Technology Research (ICTRC2015)
Hardware Accelerators for Information Retrieval and
Data Mining
Valery Sklyarov, Iouliia Skliarova, Joo Silva
Department of Electronics, Telecommunications and
Informatics/IEETA,
University of Aveiro,
Aveiro, Portugal
Abstract Many algorithms in informatics require a set of
objects with similar properties to be grouped (clustered) on the
basis of some predefined criteria. The proposed technique
involves hierarchical merging in which software, responsible for
solving the entire problem, is enhanced with highly parallel
networks in hardware accelerators. Additional improvements are
achieved with the aid of support methods that are sort and
verification of object intersections that may also be autonomously
used for other types of information processing and database
management. It is shown and experimentally proved that the
proposed solutions are efficient. They can be used in such areas
as health care, statistical data manipulation and so on.
Keywordshardware accelerator; FPGA; parallel processing;
information retrieval; data mining
I. INTRODUCTION
Information retrieval is required in many algorithms. Let us
consider some examples. Clustering is an activity that permits a
given set of objects with similar properties to be grouped [1].
Hierarchical clustering methods represent a major technique
allowing the desired set to be built through searching common
attributes and combining objects with such attributes. Similar
problems arise in statistical data manipulation and other data
mining algorithms. In [2] an analogy to a shopping card is
shown and discussed. A basket is a set of items purchased at
one time. A frequent item is an item that often occurs in a
database. A frequent set of items often occur together in the
same basket. A researcher can request a particular support
value and find the items which occur together in a basket either
a maximum or a minimum number of times within the database
[2]. Similar problems appear to determine frequent inquiries at
the Internet, customer transactions, credit card purchases, etc.
producing very large volumes of data in the span of a day [2].
Computing subsets of the most frequent or the less frequent
items in large data sets permits the relevant data mining
algorithms to be simplified and accelerated. Sorting is involved
in many known algorithms from this area [e.g. 3-5].
Let us consider (bottom-up) clustering method [1] that
begins with L objects that are merged in the desired number of
clusters (K) in such a way that at the first step individual
objects are merged and in subsequent steps the previously built
clusters are also joined in accordance with some pre-given
criteria. Similar steps are executed in merge sort [6]: 1) at the
978-1-4799-8966-9/15/$31.00 2015 IEEE
Alexander Sudnitson, Artjom Rjabov
Department of Computer Engineering,
Tallinn University of Technology
Tallinn, Estonia
first step individual data items are merged into 2-item blocks;
2) at the second step 2-item blocks are merged into 4-item
blocks and this process is continued until a single sorted set is
built. Acceleration can be achieved if some initial steps may be
executed faster and subsequent merging is started with such
inputs that are relatively large blocks instead of individual
items. Similar fast partial merge can be used in the bottom-up
clustering method [1]. Note that discovering common attributes
is significantly simplified if such attributes are presorted for
objects and clusters.
We suggest below the following technique:
1. Pre-processing in hardware accelerators which enable
core subtasks to be done significantly faster than in
software. Note that the complete merge in hardware
cannot be done in practice due to the large volume of
processing data and constraints that are common to
hardware accelerators (e.g. limits in the available
resources).
2. Subsequent processing in software beginning with
relatively large blocks instead of individual objects.
The remainder of the paper is organized in six sections.
Section II describes the background. Section III discusses the
proposed clustering method. Section IV is dedicated to sorting
of individual items which has to be done in the proposed
method. Section V explains how individual objects are merged
in clusters. Section VI reports the results of implementation
and experiments. The conclusion is given in Section VII.
II. BACKGROUND
Combining capabilities of software and hardware permits
many characteristics of developed applications to be improved.
The earliest work in this direction was done at the University of
California at Los Angeles [7]. The idea was to create a fixed +
variable structure computer and to augment a standard
processor by an array of reconfigurable logic assuming that this
logic can be utilized to solve some processor tasks faster and
more efficiently. Such combination of flexibility of software
with speed of hardware was considered as a new way to evolve
higher performance computing from any general-purpose
computer. The level of technology in 1959-1960 did not permit
this idea to be put in practice. Today a very similar technique
has been implemented in Zynq-7000 microchips combining
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 2015 International Conference on Information and Communication Technology Research (ICTRC2015)
multi-core high-performance dual-core processors Cortex-A9,
embedded blocks, and advanced reconfigurable logic [8].
Existing design tools such as Software Development Kit [9]
and Vivado Design Suite [10] permit the complete system to be
developed, implemented and tested. Two available books
[11,12] dedicated to the design techniques for Zynq-7000
present all necessary details. Acceleration of software with the
aid of hardware can also be done for a general-purpose PC
interacting with accelerators through PCI express bus. Two-
level systems including the level of general-purpose software
in PC and the level of application-specific hardware
implemented in Field-Programmable Gate Arrays (FPGA) are
widely used in practical designs such as [13]. Three-level
systems PC, Zynq Processing System (PS), and Zynq
Programmable Logic (PL) can also be used and functionality of
such systems is described in [12].
Software/hardware co-design for data sort is studied in
detail in [14-19]. It is shown in [17] that the fastest known
even-odd merge and bitonic merge circuits [20] are very
resource consuming and can only be used effectively in
existing FPGAs for sorting very small data sets. An alternative
solution is based on an iterative even-odd transition network
[17] that is very regular and can be implemented efficiently in
FPGAs for larger data sets. Besides, for many practical
applications the effective throughput is higher than in other
known networks, which is demonstrated in [17] on the results
of numerous experiments in FPGA. The size of blocks (sub-
sets of data) sorted in FPGA is increased but it is still small and
constrained by the available FPGA resources. Additional
experiments were done with the expensive prototyping system
VC 707 from Xilinx [21], but even using the advanced FPGA
XC7VX485T from Xilinx Virtex-7 family, the maximum size
N of one block is limited to 4,096 32-bit items. To sort more
data items with significantly cheaper microchips, we propose
to split the problem into two parts [17], one executed in the
reconfigurable logic and the other in software running on
embedded high-performance processors. Zynq All
Programmable Systems-on-Chip (APSoC) are very appropriate
for such decomposition.
III. THE METHOD
The following steps have been applied for the proposed
hierarchical bottom-up clustering method:
1. Objects are collected and saved in memory by the PS.
Dependently on the number of objects either on-chip
memory (OCM) or external DDR memory is used and it
is accessed from the PS and from the PL (the memory is
shared by the PS and PL).
2. Attributes for each object are read from memory by the
PL, sorted using fast and highly parallel iterative
networks from [17], and the sorted attributes are copied
back to the same memory.
3. Dependently on available resources and performance
requirements subsequent steps can be either executed in
software of the PS or partitioned once again between
software of the PS and hardware of the PL.
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4. Final steps for producing the desired number of clusters
are done in software of the PS.
Note that in practical cases (such as that were reported in
[1]) the number of attributes (for objects that have to be
clustered) is limited and they can be completely sorted in the
PL. However, we would like to develop a data sorter that could
also be used for significantly more complex tasks, such as
sorting millions of data items. Thus, the following two
directions were proposed and studied:
1. Sorting just in the PL assuming that hardware resources
are sufficient.
2. Sorting blocks in the PL and subsequent merge of the
sorted blocks in the PS.
The second direction will be described below since it
incorporates the first one.
IV. SORTING INDIVIDUAL ITEMS
If an initial set of data items requires more resources that
are available in the PL then a large set of data is divided into
such blocks which can be sorted in the PL with the aid of
iterative networks [17] and further merged in the PS. For
example, the APSoC available on ZedBoard [22] can sort up to
N=512 32-bit data items [12]. The blocks are saved in memory
which can be either DDR or OCM. The PL reads blocks from
memory, sorts them by the iterative network [17], and copies
the sorted blocks to the same location in memory (i.e. unsorted
data will be replaced with the sorted data). As soon as the
sorted subsets are ready, the PL forms an interrupt to the PS
indicating that further processing can be started. The PS reads
the sorted blocks from memory and merges them producing the
results of sorting. If merging is not needed, it is just skipped
and the problem becomes less complicated.
Let us compare the described above hardware/software
sorter with a sorter that is implemented in software only with
the C function qsort. The comparison is done as follows (see
Fig. 1):
1. Two copies of data are prepared in the DDR
memory that are kept in different memory areas.
2. The first copy is used by the software only sorter
and the second copy by the developed
hardware/software sorter.
3. Execution times are measured, compared and
conclusions are drawn. Clearly, all the involved
communication overheads are taken into account.
The results will be reported in section VI.
V. MERGING OBJECTS
We mentioned in section III that merging can be done in
software (in the PS) and in hardware/software (in the PL and
PS). In both cases at the beginning, the number of common
attributes is found as shown in Fig. 2. Let Bi and Bj be sorted
attributes for objects Oi and Oj. The component C in Fig. 2
compares the smallest values (bi and bj) in the sets Bi and Bj. If
bi = bj then the number of common attributes (which initially is
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 2015 International Conference on Information and Communication Technology Research (ICTRC2015)

equal to 0) is incremented and all the values Bi and Bj are
shifted allowing the next pair of smallest values to be
compared. If bi < bj then only the values of Bi are shifted and if
bi > bj then only the values of Bj are shifted. This process is
finished as soon as any set (Bi, Bj or both) is empty. It permits
the number of common attributes for objects Oi and Oj to be
found.
Hardware in the PL
Interaction with
Software in the PS
Final merging (that is based on the number of common
attributes) is done in software of the PS as follows. At the first
step, objects that have the maximum number of common
attributes are sequentially merged, i.e. two objects that have the
maximum number of common attributes are merged, then
among the remaining objects two objects that have the next
maximum number of common attributes are merged, etc. until
all pairs of objects are merged. Similar operations are executed
for partially merged clusters. The number of final clusters is
pre-defined by the requirements.

hardware including
interrupt handler
VI. IMPLEMENTATION AND EXPERIMENTS
Initial data are either generated randomly in software of the
Application-specific PS with the aid of C language rand function (see Fig. 1) or
merge function prepared in the host PC. In the last case data may be either
running in software Iterative randomly generated by rand or other functions or copied from
sorting benchmarks. Files with data items are copied from the host PC
Sorting data in network to the APSoC using projects from [12]. Two separate scenarios
were tested that are sorting and clustering.
software only by C [17] for N
function qsort items Sorting is done completely in Zynq APSoCs available on
ZyBo [23] and ZedBoard [22] and using methods described in
section IV. The results are verified in software running either in
C function rand which the PS or in the host PC. Functions for verifications of the
generates items of an results are given in [12]. Verification time is not taken into
unsorted set randomly Data transfer account in the measurements below.
Execution time for sorting different sets of data was
measured. Fig. 3 presents the results of experiments with
software only and software/hardware data sorters and reports
(L) 32-bit (L) 32-bit the achieved acceleration. Synthesis and implementation of the
data items = data items
Memory projects were done in Xilinx Vivado 2014.4 and SDK 2014.4.

L varies from N to 38,400,000

Two identical areas in memory

with L 32-bit data items

Fig. 1. Software/hardware architecture for sorting blocks in the PL and

merging sorted blocks in the PS.

Shift Bi bi < bj
(bj = bi) (+1)
Bi bi Shift Bi and Bj
C
Bj bj
bj < bi Fig. 3. Experiments with software only and software/hardware sorters
Shift Bj (acceleration of hardware/software sorters over software only sorters is by a
factor ranging from 4.08 to 1.13).
Fig. 2. Counting the number of common attributes.
Objects for clustering were either created using examples
Similar operations (that are shown in Fig. 2 for individual from [1] or generated randomly. We found that the most time
objects) are executed for partially merged clusters. In this case consuming part is the sort of attributes that is done significantly
the sets Bi and Bj contain attributes that are included in all faster in hardware than in software. In all the design cases just
objects of the first cluster (for the set Bi) and all objects of the one block is sorted and acceleration by using larger blocks, i.e.
second cluster (for the set Bj). by processing up to 512 attributes (instead of 64 attributes
shown in Fig. 3) ranges from 4 to 10. Experiments for up to
128 attributes were done with ZyBo [23] and for up to 512

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 2015 International Conference on Information and Communication Technology Research (ICTRC2015)
attributes with ZedBoard [22]. The latter contains a more
advanced Zynq-7000 device and permits more complicated
problems to be solved. [4]
Finding common attributes in a set of objects (or clusters)
was tested in software and in hardware. The results differ [5]
insignificantly mainly due to the involved communication
overheads. In all the experiments AXI ACP (Advanced
[6]
eXtensible Interface Accelerator Coherency Port) [24] port was
used for communications between the PS and PL.
[7]
Future work will be continued in the following directions.
We intend to consider the next two designs:
[8]
PC FPGA interacting through PCI-express which is
possible for the prototyping system [21]. The main
advantage of the system [21] is availability of very large
[9]
programmable resources, which permits the complexity
of designs to be increased drastically. This is very
important for autonomous data sorters. [10]
PC Zynq (PS and PL) working in such a way that the [11]
problem is split in two levels of software (PC and Zynq
[12]
PS) and one level of hardware (Zynq PL) operating in
parallel and interacting through PCI-express (PC-Zynq)
and high-performance (HP) on-chip interfaces such as [13]
AXI HP and AXI ACP in Zynq devices. This is a true
three-level system. The support for PCI-express
communications is provided in the advanced [14]
prototyping systems with Zynq APSoC [25].
[15]
VII. CONCLUSION
The paper describes a method for clustering objects based
on the number of their common attributes. There are two basic [16]
steps in the method that are sorting of the attributes and
[17]
merging objects (partially merged clusters). It is proved in
numerous experiments that the proposed hardware/software
solutions are faster (with all protocol and communication [18]
overheads taken into account). Besides, the sorting method can
autonomously be used and this permits very large data sets to [19]
be processed.
ACKNOWLEDGMENT
This research was supported by EU through European [20]
Regional Development Funds, the institutional research
[21]
funding IUT 19-1 of the Estonian Ministry of Education and
Research, ESF grant 9251, and Portuguese National Funds
through FCT - Foundation for Science and Technology, in the
context of the projects PEst-OE/EEI/UI0127/2014 and [22]
Incentivo/EEI/UI0127/2014.
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