Вы находитесь на странице: 1из 60

8

7

6

5

4

3

2

1

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

N66 MLB - PVT

LAST_MODIFICATION=Thu Jul 30 15:54:57 2015

PAGE

<CSA>

CONTENTS

SYNC

DATE

PAGE

<CSA>

CONTENTS

1

1

TABLE OF CONTENTS

2

3

SYSTEM:BOM TABLES

3

4

SYSTEM:N66 SPECIFIC

4

5

SYSTEM: MECHANICAL COMPONENTS

5

6

SOC:JTAG,USB,XTAL

6

7

SOC:PCIE

7

8

SOC:CAMERA & DISPLAY

8

9

SOC:SERIAL & GPIO

9

10

SOC:OWL

10

11

SOC:POWER (1/3)

11

12

SOC:POWER (2/3)

12

13

SOC:POWER (3/3)

13

15

NAND

14

20

SYSTEM POWER:PMU (1/3)

15

21

SYSTEM POWER:PMU (2/3)

16

22

SYSTEM POWER:PMU (3/3)

17

23

SYSTEM POWER:CHARGER

18

24

SYSTEM POWER:BATTERY CONN

19

30

SENSORS:MOTION SENSORS

20

31

CAMERA:FRONT CAMERA B2B

21

32

CAMERA:REAR CAMERA B2B

22

33

CAMERA:STROBE DRIVER

23

34

CAMERA: SPHERE DRIVER

24

35

AUDIO:CALTRA CODEC (1/2)

25

36

AUDIO:CALTRA CODEC (2/2)

26

37

AUDIO:SPEAKER DRIVER

27

38

AUDIO:ARC DRIVER

28

40

DISPLAY:POWER

29

41

TOUCH:ORB & MESA B2B

30

42

DISPLAY:LCM B2B

SCH 051-00094 BRD 820-00040 MCO 056-00472

BOM 639-00299 (BETTER, DB30) BOM 639-00301 (ULTRA, DB30) BOM 639-00302 (SUPREME, DB30) BOM 639-01063 (BETTER, B30) BOM 639-01064 (ULTRA, B30) BOM 639-01065 (SUPREME, B30)

SYNC

REV

ECN

DESCRIPTION OF REVISION

CK APPD DATE
CK
APPD
DATE

2015-07-30

A

0004600844

PRODUCTION RELEASED

D

C

B

A

D

C

B

A

DATE

31

45

I/O:TRISTAR 2

32

46

I/O:DOCK FLEX B2B

33

47

I/O:BUTTON FLEX B2B

34

49

BASEBAND:RADIO SYMBOL

35

TABLE OF CONTENTS

36

ELNA & UAT ANT FEED

37

CELLULAR FRONT END: ANTENNA CONNECTORS AND FEEDS

38

WLAN LAT 2.4GHZ BAW BPF

39

DEBUG CONN & TEST POINTS

40

CELLULAR BASEBAND: POWER1

41

CELLULAR BASEBAND: POWER2

42

CELLULAR BASEBAND: CONTROL AND INTERFACES

43

CELLULAR BASEBAND: GPIOS

44

CELLULAR PMU: CONTROL AND CLOCKS

45

CELLULAR PMU: SWITCHERS AND LDOS

46

CELLULAR PMU: ET MODULATOR

47

CELLULAR TRANSCEIVER: POWER

48

CELLULAR TRANSCEIVER: PRX PORTS

49

CELLULAR TRANSCEIVER: DRX/GPS PORTS

50

CELLULAR TRANSCEIVER: TX PORTS

51

CELLULAR FRONT END: LB PAD

52

CELLULAR FRONT END: MB PAD

53

CELLULAR FRONT END: HB PAD

54

CELLULAR FRONT END: 2G PA

55

CELLULAR FRONT END: LB ASM

56

CELLULAR FRONT END: MB-HB ASM

57

CELLULAR FRONT END: DIVERSITY

58

SIM

59

WIFI/BT: WIFI/BT MODULE

60

STOCKHOLM

TABLE OF CONTENTS

DRAWING TITLE

SCHEM,MLB,N66

R
R

Apple Inc.

DRAWING NUMBER

SIZE

D

051-00094

REVISION

A.0.0

BRANCH

PAGE

1 OF 49

SHEET

1 OF 60

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

1

8 7 6 5 4 3 2 1 Active Diode Alternate Schematic & PCB Callouts
8
7
6
5
4
3
2
1
Active Diode Alternate
Schematic & PCB Callouts
SOC/PMU SUB BOMS
TABLE_5_HEAD
TABLE_ALT_HEAD
TABLE_5_HEAD
PART#
QTY
DESCRIPTION
REFERENCE DESIGNATOR(S)
BOM OPTION
PART NUMBER
ALTERNATE FOR
BOM OPTION
REF DES
COMMENTS:
PART#
QTY
DESCRIPTION
REFERENCE DESIGNATOR(S)
CRITICAL
BOM OPTION
PART NUMBER
TABLE_5_ITEM
TABLE_5_ITEM
685-00071
1
SUBBOM,MLB,MAUI,N66
SUBBOM_SOC
COMMON
TABLE_ALT_ITEM
051-00094
1
SCH,SINGLE_BRD,N66
SCH
CRITICAL
?
376S00106
376S00047
ALTERNATE
Q2300
DIODES INC. ACT DIODE
TABLE_5_ITEM
TABLE_5_ITEM
338S00120
1
IC,PMU,ANTIGUA,A1,AL,WLCSP380
U2000
MAUI
820-00040
1
PCBF,SINGLE_BRD,N66
PCB
CRITICAL
?
TABLE_5_ITEM
TABLE_5_ITEM
118S0631
1
RES,MF,100 OHM,1%,1/32W,01005
R0730
MAUI
825-6838
1
EEEE CODE FOR 639-00299
EEEE_G360
CRITICAL
EEEE_BETTER_DB30
TABLE_5_ITEM
TABLE_5_ITEM
NAND BOM Options
131S0307
1
CAP,CER,NP0/C0G,100PF,5%,16V,01005
C0730
MAUI
825-6838
1
EEEE CODE FOR 639-00301
EEEE_G35W
CRITICAL
EEEE_ULTRA_DB30
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_HEAD
339S00112
1
PROD FUSED, H DRAM
U0600
MAUI
825-6838
1
EEEE CODE FOR 639-00302
EEEE_G35V
CRITICAL
EEEE_SUPREME_DB30
PART#
QTY
DESCRIPTION
REFERENCE DESIGNATOR(S)
CRITICAL
BOM OPTION
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
117S0161
1
RES, MF, 0 OHM, 01005
R0651
MAUI
825-6838
1
EEEE CODE FOR 639-01063
EEEE_GKKY
CRITICAL
EEEE_BETTER_B30
335S00039
1
NAND,1YNM,16GX8,S3E,64G,T,SLGA70
U1500
CRITICAL
NAND_16G
TABLE_5_ITEM
TABLE_5_ITEM
825-6838
1
EEEE CODE FOR 639-01064
EEEE_GKL0
CRITICAL
EEEE_ULTRA_B30
335S00075
1
NAND,1YNM,64GX8,S3E,MLB,64G,H,SLGA70
U1500
CRITICAL
NAND_64G
TABLE_5_HEAD
PART#
QTY
DESCRIPTION
REFERENCE DESIGNATOR(S)
BOM OPTION
TABLE_5_ITEM
TABLE_5_ITEM
825-6838
1
EEEE CODE FOR 639-01065
EEEE_GKL1
CRITICAL
EEEE_SUPREME_B30
335S00079
1
NAND,1YNM,64GX8,S3E,128G,H,SLGA70
U1500
CRITICAL
NAND_128G
TABLE_5_ITEM
338S00122
1
IC,PMU,ANTIGUA,A1,ZL,WLCSP380
U2000
MALTA
TABLE_5_ITEM
825-6838
1
EEEE CODE FOR 939-01539
EEEE_GPMW
CRITICAL
EEEE_BETTER_DARWIN
TABLE_5_ITEM
118S00009
1
RES,MF,3.01KOHM,1%,1/32W,01005
R0730
MALTA
TABLE_ALT_HEAD
TABLE_5_ITEM
PART NUMBER
ALTERNATE FOR
BOM OPTION
REF DES
COMMENTS:
131S0307
1
CAP,CER,NP0/C0G,100PF,5%,16V,01005
C0730
NOSTUFF
PART NUMBER
Global Capacitor Alternates
TABLE_5_ITEM
339S00124
1
M PROD FUSED, M DRAM
U0600
MALTA
335S00074
335S00039
NAND_16G
U1500
HYNIX 16G SLGA70 C DIE
TABLE_5_ITEM
TABLE_ALT_HEAD
TABLE_ALT_ITEM
118S00025
1
RES, MF, 330 OHM, 1%, 1/32W, 01005
R0651
MALTA
PART NUMBER
ALTERNATE FOR
BOM OPTION
REF DES
COMMENTS:
335S00078
335S00075
NAND_64G
U1500
HYNIX 64G SLGA70
PART NUMBER
TABLE_ALT_ITEM
TABLE_ALT_ITEM
335S00064
335S00075
NAND_64G
U1500
SANDISK 64G SLGA70 1Z
118S0764
118S0717
ALTERNATE
?
RES, 3.92K, 0.1%, 0201
TABLE_ALT_HEAD
TABLE_ALT_ITEM
TABLE_ALT_ITEM
PART NUMBER
ALTERNATE FOR
BOM OPTION
REF DES
COMMENTS:
335S00065
335S00079
NAND_128G
U1500
SANDISK 128G SLGA70
138S0702
138S0657
ALTERNATE
?
CAP, X5R, 4.3UF, 4V, 0610
PART NUMBER
TABLE_ALT_ITEM
TABLE_ALT_ITEM
138S00006
138S0835
ALTERNATE
?
685-00072
685-00071
ALTERNATE
SUBBOM,MLB,MALTA,N66
CAP, 3-TERM, 4.3UF, 4V, 0402
SUBBOM_SOC
TABLE_ALT_ITEM
Carbon BOM Options
138S00005
138S00003
ALTERNATE
?
CAP,X5R,15UF,6.3V,0.65MM,0402,TAIYO
AP Alternates
TABLE_ALT_ITEM
TABLE_5_HEAD
138S00048
138S00003
ALTERNATE
?
CAP,X5R,15UF,6.3V,0.65MM,0402,KYOCERA
PART#
QTY
DESCRIPTION
REFERENCE DESIGNATOR(S)
CRITICAL
BOM OPTION
TABLE_ALT_ITEM
TABLE_ALT_HEAD
TABLE_5_ITEM
138S0648
138S0652
ALTERNATE
?
PART NUMBER
ALTERNATE FOR
BOM OPTION
REF DES
COMMENTS:
CAP,X5R,4.7UF,6.3V,0.65MM,0402,TAIYO
338S1163
1
DISCRETE ACCEL, BOSCH
U3030
CRITICAL
NOSTUFF
PART NUMBER
TABLE_ALT_ITEM
TABLE_5_ITEM
132S0400
132S0436
ALTERNATE
?
TABLE_ALT_ITEM
CAP,X5R,0.22UF,6.3V,01005,TDK
338S1163
1
DISCRETE ACCEL, BOSCH
U3030
CRITICAL
CARBON_INVENSENSE
339S00113
339S00112
MAUI
U0600
PROD FUSED, M DRAM
TABLE_ALT_ITEM
TABLE_5_ITEM
138S00032
138S0831
ALTERNATE
?
TABLE_ALT_ITEM
CAP,X5R,2.2UF,6.3V,0201,TAIYO
338S00017
1
CARBON, INVENSENSE
U3010
CRITICAL
CARBON_INVENSENSE
339S00114
339S00112
MAUI
U0600
PROD FUSED, S DRAM
TABLE_ALT_ITEM
TABLE_5_ITEM
138S00049
138S0831
ALTERNATE
?
CAP,X5R,2.2UF,6.3V,0201,KYOCERA
338S00087
1
CARBON, INVENSENSE MPU-6800
U3010
CRITICAL
CARBON_INVENSENSE_6800
TABLE_ALT_ITEM
138S00024
138S0986
ALTERNATE
?
TABLE_ALT_ITEM
CAP,CER,3-TERM,7.5UF,20%,4V,0402,TAIYO/TDK
339S00125
339S00124
MALTA
U0600
M
PROD FUSED, H DRAM, ATK
TABLE_ALT_ITEM
Power Inductor Alternates
138S0706
138S0739
ALTERNATE
?
TABLE_ALT_ITEM
CAP,CER,1UF,20%,10V,X5R,0201,MURATA
339S00126
339S00124
MALTA
U0600
M
PROD FUSED, S DRAM, ATK
TABLE_ALT_ITEM
TABLE_ALT_HEAD
138S0945
138S0739
ALTERNATE
?
TABLE_ALT_ITEM
CAP,CER,1UF,20%,10V,X5R,0201,KYOCERA
PART NUMBER
ALTERNATE FOR
BOM OPTION
REF DES
COMMENTS:
339S00127
339S00124
MALTA
U0600
M
PROD FUSED, M DRAM, SCK
PART NUMBER
TABLE_ALT_ITEM
TABLE_ALT_ITEM
Global Ferrite Alternates
339S00128
339S00124
MALTA
U0600
M
PROD FUSED, H DRAM, SCK
152S00118
152S00075
ALTERNATE
$?
IND,PWR,SHLD,1.2 UH,3.0A,0.080 OHM,2016
TABLE_ALT_ITEM
TABLE_ALT_ITEM
339S00129
339S00124
MALTA
U0600
M
PROD FUSED, S DRAM, SCK
TABLE_ALT_HEAD
152S00120
152S00077
ALTERNATE
$?
IND,PWR,SHLD,1.0 UH,2.25A,0.150 OHM,2016
PART NUMBER
ALTERNATE FOR
BOM OPTION
REF DES
COMMENTS:
PART NUMBER
TABLE_ALT_ITEM
152S2052
152S1929
ALTERNATE
$?
IND,MULT,1UH,1.2A,0.320 OHM,0603
TABLE_ALT_ITEM
152S2052
152S1929
ALTERNATE
?
IND, 1UH, 1.2A, 0603
Shield Callouts
TABLE_ALT_ITEM
DDR PLL Alternate
155S0773
155S0453
ALTERNATE
?
FERR, 120OHM, 0.8OHM DCR, 01005
TABLE_5_HEAD
TABLE_ALT_ITEM
PART#
QTY
DESCRIPTION
REFERENCE DESIGNATOR(S)
CRITICAL
BOM OPTION
155S0653
155S0511
ALTERNATE
?
FERR, 33OHM, 0.09OHM DCR, 0201
TABLE_5_ITEM
TABLE_ALT_HEAD
TABLE_ALT_ITEM
806-04265
1
LOWER FRONT SHIELD
SH0501
CRITICAL
COMMON
PART NUMBER
ALTERNATE FOR
BOM OPTION
REF DES
COMMENTS:
155S00067
155S0581
ALTERNATE
?
FERR, 240OHM, 0.38OHM DCR, 0201
PART NUMBER
TABLE_ALT_ITEM
TABLE_ALT_ITEM
155S00012
155S00009
ALTERNATE
?
FLTR, 65 OHMS, 0605
155S00095
155S00068
ALTERNATE
FL1280
FERR BD,100OHM,25%,100MA,2OHM,01005
TABLE_ALT_ITEM
SIM Callouts
155S0960
155S0941
ALTERNATE
?
FERR, 70 OHMS, 01005
TABLE_ALT_ITEM
TABLE_5_HEAD
SEP EEPROM Alternate
155S0660
155S0513
ALTERNATE
?
FERR, 22 OHMS, 0201
PART#
QTY
DESCRIPTION
REFERENCE DESIGNATOR(S)
CRITICAL
BOM OPTION
TABLE_5_ITEM
TABLE_ALT_HEAD
512S00013
1
SIM, Integrated Eject, N66
J3001_RF
CRITICAL
COMMON
PART NUMBER
ALTERNATE FOR
BOM OPTION
REF DES
COMMENTS:
Global Varistor Alternates
PART NUMBER
TABLE_ALT_ITEM
335S00066
335S0946
ALTERNATE
U0900
TABLE_ALT_HEAD
IC,EEPROM,16KX8,1.8V,I2C,WLCSP4,ONSEMI
PART NUMBER
ALTERNATE FOR
BOM OPTION
REF DES
COMMENTS:
PART NUMBER
TABLE_ALT_ITEM
Low Noise Caps
377S0168
377S0140
ALTERNATE
?
VARISTOR, 6.8V, 100PF, 01005
TABLE_5_HEAD
Inductor Sub BOMs
PART#
QTY
DESCRIPTION
REFERENCE DESIGNATOR(S)
BOM OPTION
TABLE_5_ITEM
TABLE_5_HEAD
138S0867
3
C2085, C2086, C2087
CAPS_NORMAL
CAP,X5R,10UF,20%,6.3V,0.65MM,HRZTL,0402
PART#
QTY
DESCRIPTION
REFERENCE DESIGNATOR(S)
BOM OPTION
TABLE_5_ITEM
TABLE_5_ITEM
998-01223
3
C2085, C2086, C2087
CAPS_LOW_NOISE
CAP,X5R,10UF,20%,6.3V,0.65MM,0402,INTPOSER
685-00083
1
SUBBOM,SINGLE,BRD,CYNTEC,N66
SUBBOM_IND
COMMON
TABLE_5_ITEM
152S00074
12
CYNTEC
IND,PWR,SHLD,1.0UH,3.6A,0.060O HM,2016
L2000,L2002,L2010,L2012,L2020,L2030,L2040,L2050,L2300,L3300,L4021,L4051
TABLE_5_ITEM
152S00081
6
CYNTEC
IND,PWR,SHLD,0.47UH,3.8A,0.048 OHM,2012
L2001,L2003,L2011,L2013,L2021,L2041
TABLE_5_HEAD
PART#
QTY
DESCRIPTION
REFERENCE DESIGNATOR(S)
BOM OPTION
TABLE_5_ITEM
152S00117
12
TAIYO
IND,PWR,SHLD,1.0UH,3.6A,0.060O HM,2016
L2000,L2002,L2010,L2012,L2020,L2030,L2040,L2050,L2300,L3300,L4021,L4051
TABLE_5_ITEM
152S00121
6
TAIYO
IND,PWR,SHLD,0.47UH,3.8A,0.048 OHM,2012
L2001,L2003,L2011,L2013,L2021,L2041
TABLE_ALT_HEAD
PART NUMBER
ALTERNATE FOR
BOM OPTION
REF DES
COMMENTS:
PART NUMBER
TABLE_ALT_ITEM
685-00082
685-00083
ALTERNATE
SUBBOM_IND
SUBBOM,SINGLE,BRD,TAIYO,N66
PAGE TITLE
SYSTEM:BOM TABLES
DRAWING NUMBER
SIZE
051-00094
D
Apple Inc.
REVISION
R
A.0.0
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
3
OF 49
II NOT TO REPRODUCE OR COPY IT
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
2
OF 60
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
1

D

C

B

A

D

C

B

A

8 7 6 5 4 3 2 1 TESTPOINTS UAT GND Ring Opening N66 I2C
8
7
6
5
4
3
2
1
TESTPOINTS
UAT GND Ring Opening
N66 I2C DEVICE MAP
AMUX
PP09
I2C BUS
DEVICE
BINARY
7-BIT HEX
8-BIT HEX
TP16
0.50MM
PMU_AMUX_AY
1
GND
SM
16
A
ANALOG MUX A OUTPUT
1
PP
POWER
I2C0
ANTIGUA PMU
1110100X
0X74
0XE8
TP-P55
ROOM=TEST
ROOM=TEST
CHESTNUT
0100111X
0X27
0X4E
TP17
TP00
PMU_AMUX_BY
1
1
16
A
ANALOG MUX B OUTPUT
A POWER GROUND
BACKLIGHT 1
1100011X
0X62
0XC4
VOLTAGE=0V
TP-P55
TP-P5
ROOM=TEST
ROOM=TEST
MOJAVE
I2C1
TIGRIS
1110101X
0X75
0XEA
TP01
PP5V0_USB
1
32 31 17
A VBUS
ARC DRIVER
1000001X
0X41
0X82
TP-P55
ROOM=TEST
TP18
MESA_TO_BOOST_EN
1
29
28
A
SPEAKER AMP
1000000X
0X40
0X80
TP-P55
TP02
ROOM=TEST
PP_BATT_VCC
1
VBATT
TRISTAR
0011010X
0X1A
0X34
18 17
A
TP19
TP-P5
PP16V5_MESA
1
ROOM=TEST
29
28
A
TP-P55
TP03
ALS
1
ROOM=TEST
I2C2
0101001X
0X29
0X52
A
TP-P5
ROOM=TEST
LCM
DISP EEPROM
1010001X
0X51
0XA2
TP04
1
0X62
0XC4
A
POWER GROUND
BACKLIGHT 2
1100011X
TP-P5
TP20
ROOM=TEST
PP_LCM_BL_CAT1_CONN
1
LCM BACKLIGHT SINK1
30
A
TP-P55
OWL
UNUSED
N/A
N/A
N/A
ROOM=TEST
RESET
TP21
PP_LCM_BL_CAT2_CONN
1
30
A
LCM BACKLIGHT SINK2
ISP I2C0
REAR CAM
TBD
TBD
TBD
PP06
TP-P55
P4MM-NSM
ROOM=TEST
SM
LED DRIVER
1100011X
0X63
0XC6
PMU_TO_SYSTEM_COLD_RESET_L
1
34
16
9
5
SOC & BB RESET
PP
TP22
ROOM=TEST
PP_LCM_BL_ANODE_CONN
1
LCM BACKLIGHT SOURCE
30
A
TP-P55
ISP I2C1
FRONT CAM
0010000X
0X10
0X20
DFU
ROOM=TEST
TP23
PP_LCM_BL_CAT3_CONN
TP07
1
LCM BACKLIGHT SINK3
TOUCH I2C
MESON
1000000X
0x40
0x80
30
FORCE_DFU
1
A
34
8
A
FORCE DFU
TP-P55
TP-P55
MAMBA
1100000X
0x60
0xC0
ROOM=TEST
ROOM=TEST
TP24
PP07
PP_LCM_BL_CAT4_CONN
1
DOPPLER
1011000X
0x58
0xB0
30
A
LCM BACKLIGHT SINK4
P4MM-NSM
SM
TP-P55
PP1V8
1
21
20 17 14 13
12
9
8
7
6
5
3
ROOM=TEST
PP
34
30
SEP I2C
SEP EEPROM
1010001X
0x51
0xA2
ROOM=TEST
PP08
TP25
PP_LCM_BL34_ANODE_CONN
1
LCM BACKLIGHT SOURCE (3/4)
P4MM-NSM
30
A
SM
TP-P55
DFU_STATUS
1
34
8
PP
ROOM=TEST
ROOM=TEST
E75
BOOTSTRAPPING:BOARD REV
BOARD ID
BOOT CONFIG
TP08
TRISTAR_DP1_CONN_P
1
32
31
A
TP-P5
R0400
ROOM=SOC
1.00K
BOARD_REV3
1
2
PP1V8
8
3
5
6
7
8
9 12
13
14 17 20 21
ROOM=TEST
30 34
01005
MF
1/32W
5%
NOSTUFF
TP09
R0401
ROOM=SOC
1.00K
TRISTAR_DP1_CONN_N
1
BOARD_REV2
1
2
BOARD_REV[3:0]
32
31
A
8
01005
MF
1/32W
TP-P5
FLOAT=LOW, PULLUP=HIGH
5%
ROOM=TEST
NOSTUFF
1111
PROTO1
R0402
ROOM=SOC
1.00K
1110
PROTO2
TP10
BOARD_REV1
1
2
8
TRISTAR_DP2_CONN_P
1
1101
EVT
32
31
A
01005
MF
1/32W
5%
1100
EVT-MD
TP-P5
1011
CARRIER
ROOM=TEST
R0403
ROOM=SOC
1.00K
1010
DVT
BOARD_REV0
1
2
TP11
8
SELECTED -->
1001
PVT
TRISTAR_DP2_CONN_N
01005
MF
1/32W
1
5%
32
31
A
TP-P5
ROOM=TEST
TP12
PP_TRISTAR_ACC1
NOSTUFF
1
32
31
A
R0404 1
ROOM=SOC
1.00K
TP-P5
BOARD_ID4
2
8
ACCESSORY ID AND POWER
ROOM=TEST
01005
MF
1/32W
5%
NOSTUFF
TP13
PP_TRISTAR_ACC2
1
32
31
A
R0405 1
ROOM=SOC
1.00K
BOARD_ID3
2
8
TP-P5
01005
MF
1/32W
5%
ROOM=TEST
BOARD_ID[4:0]
TP14
R0406 1
ROOM=SOC
FLOAT=LOW, PULLUP=HIGH
1.00K
1
BOARD_ID2
2
A
8
TP IS TO HELP WITH USB SI
IN THE FACTORY FIXTURE.
00100
N71 MLB
01005
MF
1/32W
TP-P55
5%
00101
N71 DEV
ROOM=TEST
SELECTED -->
00110
N66 MLB
R0407
ROOM=SOC
1.00K
00111
N66 DEV
BOARD_ID1
1
2
8
TP15
01005
MF
1/32W
5%
TRISTAR_CON_DETECT_L
1
32
31
A
FOR DIAGS
NOSTUFF
TP-P55
R0408 1
ROOM=SOC
1.00K
BOARD_ID0
2
ROOM=TEST
8
01005
MF
1/32W
5%
PAGE TITLE
SYSTEM:N66 SPECIFIC
NOSTUFF
R0409
ROOM=SOC
1.00K
BOOT_CONFIG[2:0]
BOOT_CONFIG2
1
2
DRAWING NUMBER
SIZE
8
FLOAT=LOW, PULLUP=HIGH
01005
MF
1/32W
051-00094
D
5%
000
SPI0
Apple Inc.
REVISION
001
SPI0 TEST MODE
R0410 1
ROOM=SOC
R
1.00K
A.0.0
BOOT_CONFIG1
2
SELECTED -->
010
NVME0_X2
8
011
NVME0 X2 TEST
01005
MF
1/32W
NOTICE OF PROPRIETARY PROPERTY:
5%
BRANCH
100
NVME0 X1
NOSTUFF
101
NVME0 X1 TEST
R0411 1
ROOM=SOC
1.00K
BOOT_CONFIG0
2
111
FAST SPI0
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
8
01005
MF
1/32W
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
4
OF 49
5%
II NOT TO REPRODUCE OR COPY IT
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
3
OF 60
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
1

D

C

B

A

D

C

B

A

8 7 6 5 4 3 2 1 TUBE STANDOFF TUBE STANDOFF: STOCKHOLM FEED FIDUCIALS
8
7
6
5
4
3
2
1
TUBE STANDOFF
TUBE STANDOFF: STOCKHOLM FEED
FIDUCIALS
MLB NORTH PENINSULA AC CHASSIS SHORT
860-00177
860-5189
(BLOCKS DC CURRENT THROUGH COMPASS REGION)
CL0501
FD0501
NORTH_AC_GND_SCREW
D
D
33 4
SM
AP_TO_STOCKHOLM_ANT
FID
1
ROOM=ASSEMBLY
ROOM=ASSEMBLY
34
0P5SM1P0SQ-NSP
1
BS0530
BS0531
1
BS0520
1
C0550
1
C0551
1
C0552
1
C0553
TUBE STANDOFF
2
ROOM=ASSEMBLY
STDOFF-2.6OD0.648H-TH
STDOFF-2.6OD0.648H-TH
STDOFF-2.49OD1.4ID-1.25H-SM
220PF
100PF
100PF
4.7PF
860-00176
3
ROOM=ASSEMBLY
10%
5%
+/-0.1PF
1
1
10V
16V
16V 5%
16V
2
2
2
2
BS0513
NP0-C0G
4
X7R-CERM
NP0-C0G
NP0-C0G
1
01005
01005
01005
01005
COAX CLIP BRACE
5
STDOFF-2.6OD0.808H
NORTH_AC_GND_SCREW
33 4
806-02354
THREADED STANDOFF
ROOM=ASSEMBLY
ROOM=ASSEMBLY
ROOM=ASSEMBLY
ROOM=ASSEMBLY
ROOM=ASSEMBLY
FD0503
860-00175
CLIP-BRACE-COAX-N66
FID
BS0510
0P5SM1P0SQ-NSP
STDOFF-2.9OD0.888H-SM
1
TODO: TUNE AC CAPS FOR ANTENNA RF GND
ROOM=ASSEMBLY
1
ROOM=ASSEMBLY
FD0504
FID
0P5SM1P0SQ-NSP
1
ROOM=ASSEMBLY
THREADED STANDOFF
BOTTOM SIDE
FD0505
TOP SIDE
860-00175
FID
THREADED STANDOFF
BS0512
0P5SM1P0SQ-NSP
1
860-00175
STDOFF-2.9OD0.888H-SM
ROOM=ASSEMBLY
BS0511
1
FD0510
STDOFF-2.9OD0.888H-SM
FID
1
0P5SQ-SMP3SQ-NSP
1
ROOM=ASSEMBLY
ROOM=ASSEMBLY
ROOM=ASSEMBLY
FD0511
PLATED SLOTTED THRU-HOLE
FID
0P5SQ-SMP3SQ-NSP
998-00099
1
CL0502
ROOM=ASSEMBLY
TH-NSP
C
FD0512
1
C
FID
806-02352
SL-1.20X0.40-1.50X0.70-NSP
0P5SQ-SMP3SQ-NSP
SHLD-EMI-UPPER-BACK-N66
1
ROOM=ASSEMBLY
1
FD0513
806-02349
SH0503
FID
SHLD-EMI-UPPER-FRONT-N66
SM
0P5SQ-SMP3SQ-NSP
1
1
ROOM=ASSEMBLY
SH0500
ROOM=ASSEMBLY
FD0514
SM
FID
0P5SQ-SMP3SQ-NSP
1
ROOM=ASSEMBLY
ROOM=ASSEMBLY
FD0515
FID
0P5SQ-SMP3SQ-NSP
1
ROOM=ASSEMBLY
DOUBLE COAX CLIP
806-01802
CLIP-RETENTION-COAX-DOUBLE
FD0502
1
CL0500
FID
SM
0P5SM1P0SQ-NSP
PP_VCC_MAIN
1
28
27
26
25 23 22 21
17 15 14
34 29
ROOM=ASSEMBLY
B
B
806-04265
SHLD-EMI-LOWER-FRONT-CLOSE-N66
1
OMIT_TABLE
SH0501
806-02353
SM
SHLD-EMI-LOWER-BACK-N66
1
SH0504
ROOM=ASSEMBLY
SM
ROOM=ASSEMBLY
TIGRIS/SPKR INDUCTOR SHIELD
806-04068
SHLD-EMI-SA-OPEN-N66
1
SH0502
SM
A
ROOM=ASSEMBLY
A
PAGE TITLE
SYSTEM: MECHANICAL COMPONENTS
BS0500
DRAWING NUMBER
SIZE
STDOFF-2.6OD0.808H
051-00094
SOUTH TUBE STANDOFF
D
Apple Inc.
1
860-00176
REVISION
R
A.0.0
ROOM=ASSEMBLY
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
5
OF 49
II NOT TO REPRODUCE OR COPY IT
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
4
OF 60
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
1

8

7

6

5

4

3

2

1

MAUI - USB, JTAG, XTAL

VDD12_PLL_LPDP:1.14-1.26V @2mA MAX VDD12_PLL_SOC: 1.14-1.26V @12mA MAX VDD12_PLL_CPU: 1.14-1.26V @2mA MAX

R0600

0.00

VDD18_USB: 1.71-1.89V @20mA MAX VDD18_XTAL:1.62-1.98V @2mA MAX

7

6

PP1V2 1 2 PP1V2_PLL PP1V8 3 6 7 8 9 12 13 14 17 20
PP1V2
1
2
PP1V2_PLL
PP1V8
3
6
7
8
9 12
13
14 17 20 21
30
34
0%
VOLTAGE=1.2V
1/32W
1 C0612
MF
1 C0600
1 C0601
1 C0602
1 C0603
FL0610
01005
0.1UF
1KOHM-25%-0.2A
0.1UF
0.1UF
0.01UF
0.01UF
ROOM=SOC
20%
20%
20%
10%
10%
2
6.3V
PP1V8_XTAL
1
2
2
6.3V
2
6.3V
2
6.3V
2
6.3V
X5R-CERM
X5R-CERM
X5R-CERM
X5R
X5R
01005
VOLTAGE=1.8V
0201
01005
01005
01005
01005
ROOM=SOC
C0611
1 C0610
ROOM=SOC
ROOM=SOC
ROOM=SOC
ROOM=SOC
ROOM=SOC
1
2.2UF
0.1UF
20%
20%
6.3V
2
6.3V
2
X5R-CERM
X5R-CERM
0201
01005
ROOM=SOC
ROOM=SOC
PP3V3_USB
15
1
C0620
3.14-3.46V @5mA MAX
0.1UF
20%
6.3V
2
X5R-CERM
01005
ROOM=SOC
OMIT_TABLE
CRITICAL
U0600
MAUI-2GB-25NM-DDR-H
AN22
FCMSP
AP24
AP_TO_PMU_AMUX_OUT
UH1_HSIC0_DATA
ANALOGMUX_OUT
16
NC
AN21
SC58980B0B-A040
UH1_HSIC0_STB
NC
SYM 1 OF 14
ROOM=SOC
C16
UH2_HSIC1_DATA
NC
D15
UH2_HSIC1_STB
NC
AT20
USB_AP_DATA_P
USB_D_P
5
31
Y32
AT19
USB_AP_DATA_N
JTAG_SEL
USB_D_N
5
31
AC32
JTAG_TRST*
NC
AB31
JTAG_TDO
NC
AA32
AP19
USB_VBUS_DETECT
JTAG_TDI
USB_VBUS
17
NC
SWD_DOCK_BI_AP_SWDIO
AB32
JTAG_TMS
31
SWD_DOCK_TO_AP_SWCLK
AA31
AR19
JTAG_TCK
USB_ID
31
NC
PMU_TO_SYSTEM_COLD_RESET_L
AC31
COLD_RESET*
34
16
9
3
AP18
USB_REXT
USB_REXT
PMU_TO_OWL_ACTIVE_READY
H33
CFSB
31
28
16 9
1
R0640
AP_TO_PMU_TEST_CLKOUT
AR23
TST_CLKOUT
16 5
200
1%
1/32W
MF
AP_TO_NAND_RESET_L
AN23
S3E_RESET*
01005
13
2
ROOM=SOC
H32
Y33
AP_TO_PMU_WDOG_RESET
HOLD_RESET
WDOG
16
AF6
TESTMODE
AL22
AK35
XTAL_AP_24M_IN
FUSE1_FSRC
XI0
AG25
AL35
XTAL_AP_24M_OUT
FUSE2_FSRC
XO0
1
R0650
CRITICAL
511K
ROOM=SOC
1%
Y0600
OMIT_TABLE
1/32W
1.60X1.20MM-SM
MF
R0651
01005
24.000MHZ-30PPM-9.5PF-60OHM
2
0.00
ROOM=SOC
1
2
SOC_24M_O
1
3
0%
1/32W
2
4
1 C0650
MF
1
C0651
01005
12PF
12PF
ROOM=SOC
5%
5%
16V
2
16V
CERM
2
CERM
01005
01005
ROOM=SOC
ROOM=SOC
1
AP_XTAL_GND
VOLTAGE=0V
AP21
VDD12_UH1_HSIC0
C15
VDD12_UH2_HSIC1
F22
VDD12_PLL_LPDP
U20
T19
VDD12_PLL_SOC
W19
AF13
VDD12_PLL_CPU
AL21
VDD18_USB
AN20
VDD33_USB
AL34
VDD18_XTAL

15

PROBE POINTS

PCB: PLACE THIS XW AT U1, NEAR XI/XO

XW0650

USB_AP_DATA_P

1 SM

PP
PP

1 SM

PP
PP

1 SM

PP
PP

PP0600

P3MM-NSM

ROOM=SOC

PP0601

P3MM-NSM

ROOM=SOC

PP0610

P3MM-NSM

ROOM=SOC

31

31

16

5

5

USB_AP_DATA_N

SHORT-10L-0.1MM-SM

2

ROOM=SOC 31 31 16 5 5 USB_AP_DATA_N SHORT-10L-0.1MM-SM 2 ROOM=SOC 5 AP_TO_PMU_TEST_CLKOUT SYNC_MASTER=N71_SINGLE_BRD

ROOM=SOC

5

AP_TO_PMU_TEST_CLKOUT

SYNC_MASTER=N71_SINGLE_BRD

SYNC_DATE=05/29/2014

PAGE TITLE

SOC:JTAG,USB,XTAL

R
R

Apple Inc.

DRAWING NUMBER

051-00094

SIZE

D

REVISION

A.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

IV ALL RIGHTS RESERVED

BRANCH

PAGE

6 OF 49

SHEET

5 OF 60

8

7

6

5

4

3

2

1

D

C

B

A

D

C

B

A

8 7 6 5 4 3 2 1 MAUI - PCIE INTERFACES VDD12_PCIE_REFBUF:1.08-1.26V @50mA MAX
8
7
6
5
4
3
2
1
MAUI - PCIE INTERFACES
VDD12_PCIE_REFBUF:1.08-1.26V @50mA MAX
VDD12_PCIE_TXPLL: 1.08-1.32V @10mA MAX
VDD12_PCIE:
1.14-1.26V @115mA MAX
VDD085_PCIE:0.802-TBDV @TBDmA MAX
D
D
PP1V2
PP_FIXED
15
7
5
7 11 14
1
C0740
1
C0741
1
C0742
1
C0743
1
C0752
1
C0751
1
C0750
2.2UF
1.0UF
0.1UF
0.1UF
0.1UF
1.0UF
2.2UF
20%
20%
6.3V
6.3V 20%
6.3V 20%
6.3V 20%
6.3V 20%
6.3V 20%
6.3V
2
2
2
2
2
2
2
X5R-CERM
X5R
X5R-CERM
X5R-CERM
X5R-CERM
X5R
X5R-CERM
0201
0201-1
01005
01005
01005
0201-1
0201
ROOM=SOC
ROOM=SOC
ROOM=SOC
ROOM=SOC
ROOM=SOC
ROOM=SOC
ROOM=SOC
1 C0731
0.1UF
6.3V 20%
2 X5R-CERM
01005
ROOM=SOC
PCIE_EXT_C
AP29
PCIE_EXT_C
C0701
1
2
0.1UF
OMIT_TABLE
PCIE_NAND_TO_AP_RXD0_P
ROOM=SOC
PCIE_NAND_TO_AP_RXD0_C_P
AM30
CRITICAL
AN35
PCIE_AP_TO_NAND_REFCLK_P
20%
6.3V
PCIE_RX0_P
PCIE_REF_CLK0_P
13
13
X5R-CERM
01005
PCIE_NAND_TO_AP_RXD0_N
PCIE_NAND_TO_AP_RXD0_C_N
AN30
AP35
PCIE_AP_TO_NAND_REFCLK_N
PCIE_RX0_N
U0600
PCIE_REF_CLK0_N
13
13
C0702
1
2
0.1UF
MAUI-2GB-25NM-DDR-H
ROOM=SOC
20%
6.3V
AN34
PCIE_AP_TO_WLAN_REFCLK_P
X5R-CERM
01005
PCIE_REF_CLK1_P
34
FCMSP
AP34
PCIE_AP_TO_WLAN_REFCLK_N
PCIE_REF_CLK1_N
34
SC58980B0B-A040
C0703
1
2
0.1UF
SYM 2 OF 14
PCIE_AP_TO_NAND_TXD0_P
ROOM=SOC
PCIE_AP_TO_NAND_TXD0_C_P
AT32
AM32
PCIE_AP_TO_BB_REFCLK_P
20%
6.3V
PCIE_TX0_P
PCIE_REF_CLK2_P
13
34
ROOM=SOC
X5R-CERM
01005
PCIE_AP_TO_NAND_TXD0_N
PCIE_AP_TO_NAND_TXD0_C_N
AR32
AN32
PCIE_AP_TO_BB_REFCLK_N
PCIE_TX0_N
PCIE_REF_CLK2_N
13
34
C0704
1
2
0.1UF
PP1V8
ROOM=SOC
3
5
7
8
9 12
13
14
17 20 21 30
20%
6.3V
AM31
34
NOSTUFF
X5R-CERM
01005
PCIE_REF_CLK3_P
NC
C
1
1
1
C
AN31
R0720
R0721
R0722
PCIE_REF_CLK3_N
NC
100K
100K
100K
C0705
1
2
0.1UF
5%
5%
5%
PCIE_NAND_TO_AP_RXD1_P
ROOM=SOC
PCIE_NAND_TO_AP_RXD1_C_P
AM28
1/32W
1/32W
1/32W
20%
6.3V
PCIE_RX1_P
13
MF
MF
MF
X5R-CERM
01005
PCIE_NAND_TO_AP_RXD1_N
PCIE_NAND_TO_AP_RXD1_C_N
AN28
01005
01005
01005
PCIE_RX1_N
13
2
2
2
C0706
ROOM=SOC
ROOM=SOC
ROOM=SOC
1
2
0.1UF
ROOM=SOC
20%
6.3V
AT11
PCIE_NAND_TO_AP_CLKREQ_L
X5R-CERM
01005
PCIE_CLKREQ0*
13
AP12
PCIE_WLAN_TO_AP_CLKREQ_L
PCIE_CLKREQ1*
34
AR12
C0707
PCIE_BB_BI_AP_CLKREQ_L
1
2
0.1UF
PCIE_CLKREQ2*
34
PCIE_AP_TO_NAND_TXD1_P
ROOM=SOC
PCIE_AP_TO_NAND_TXD1_C_P
AT31
AT12
20%
6.3V
PCIE_TX1_P
PCIE_CLKREQ3*
13
NC
X5R-CERM
01005
PCIE_AP_TO_NAND_TXD1_N
PCIE_AP_TO_NAND_TXD1_C_N
AR31
PCIE_TX1_N
13
C0708
1
2
0.1UF
ROOM=SOC
20%
6.3V
X5R-CERM
01005
AR10
C0709
PCIE_AP_TO_NAND_RESET_L
1
2
0.1UF
PCIE_PERST0*
13
PCIE_WLAN_TO_AP_RXD_P
ROOM=SOC
PCIE_WLAN_TO_AP_RXD_C_P
AM27
AT10
PCIE_AP_TO_WLAN_RESET_L
20%
6.3V
PCIE_RX2_P
PCIE_PERST1*
34
34
X5R-CERM
01005
PCIE_WLAN_TO_AP_RXD_N
PCIE_WLAN_TO_AP_RXD_C_N
AN27
AP11
PCIE_AP_TO_BB_RESET_L
PCIE_RX2_N
PCIE_PERST2*
34
34
C0710
1
2
0.1UF
AR11
PCIE_PERST3*
ROOM=SOC
NC
20%
6.3V
X5R-CERM
01005
C0711
1
2
0.1UF
1
1
1
R0700
R0701
R0702
PCIE_AP_TO_WLAN_TXD_P
ROOM=SOC
PCIE_AP_TO_WLAN_TXD_C_P
AT28
AR33
20%
6.3V
PCIE_TX2_P
PCIE_EXT_REF_CLK_P
34
100K
100K
100K
X5R-CERM
01005
PCIE_AP_TO_WLAN_TXD_N
PCIE_AP_TO_WLAN_TXD_C_N
AR28
AT33
PCIE_TX2_N
PCIE_EXT_REF_CLK_N
5%
5%
5%
34
C0712
1
2
0.1UF
1/32W
1/32W
1/32W
MF
MF
MF
ROOM=SOC
20%
6.3V
01005
01005
01005
2
2
2
X5R-CERM
01005
ROOM=SOC
ROOM=SOC
ROOM=SOC
C0715
1
2
0.1UF
B
PCIE_BB_TO_AP_RXD_P
ROOM=SOC
PCIE_BB_TO_AP_RXD_C_P
AM26
AT29
B
20%
6.3V
6
PCIE_RX3_P
PCIE_RX_TX_BYPASS_CLK_P
34
X5R-CERM
01005
PCIE_BB_TO_AP_RXD_N
PCIE_BB_TO_AP_RXD_C_N
AN26
AR29
6
PCIE_RX3_N
PCIE_RX_TX_BYPASS_CLK_N
34
C0716
1
2
0.1UF
ROOM=SOC
20%
6.3V
X5R-CERM
01005
C0717
1
2
0.1UF
PCIE_AP_TO_BB_TXD_P
ROOM=SOC
PCIE_AP_TO_BB_TXD_C_P
AT26
20%
6.3V
PCIE_TX3_P
34
X5R-CERM
01005
PCIE_AP_TO_BB_TXD_N
PCIE_AP_TO_BB_TXD_C_N
AR26
PCIE_TX3_N
34
C0718
1
2
0.1UF
PROBE POINTS
ROOM=SOC
20%
6.3V
X5R-CERM
01005
PCIE RX CAPS ARE PLACED CLOSER TO TX DRIVERS
PROBE POINTS ADDED FOR MEASUREMENTS AT RX DRIVER
AM25
PCIE_RX4_P
1 SM
PP0706
NC
PCIE_BB_TO_AP_RXD_C_P
AN25
6
PP
P3MM-NSM
PCIE_RX4_N
NC
ROOM=SOC
1 SM
PP0707
PCIE_BB_TO_AP_RXD_C_N
6
PP
P3MM-NSM
PCIE_RCAL_P
ROOM=SOC
OMIT_TABLE
OMIT_TABLE
1
R0730
1 C0730
AR24
AT30
PCIE_TX4_P
PCIE_RCAL_P
100
NC
100PF
AT24
AR30
1%
5%
PCIE_TX4_N
PCIE_RCAL_N
NC
1/32W
16V
MF
2 NP0-C0G
01005
01005
2
ROOM=SOC
ROOM=SOC
PCIE_RCAL_N
A
A
SYNC_MASTER=N71_SINGLE_BRD
SYNC_DATE=05/29/2014
PAGE TITLE
SOC:PCIE
DRAWING NUMBER
SIZE
051-00094
D
Apple Inc.
REVISION
R
A.0.0
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
7
OF 49
II NOT TO REPRODUCE OR COPY IT
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
6
OF 60
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
1
PCIE LINK 2
PCIE LINK 1
PCIE LINK 0
AK28
AK25
VDD12_PCIE
AL24
AL27
AL26
VDD12_PCIE_TXPLL
AJ26
VDD12_PCIE_REFBUF
AH28
AJ25
AL23
AJ29
AL29
VDD085_PCIE
AJ24
AK27
AJ27
8 7 6 5 4 3 2 1 MAUI - CAMERA & DISPLAY INTERFACES 0.756-0.893V
8
7
6
5
4
3
2
1
MAUI - CAMERA & DISPLAY INTERFACES
0.756-0.893V @11mA MAX
1.62-1.98V @23mA MAX
PP_FIXED
PP1V8
14
11 6
3
5
6
7
8
9 12
13
14 17 20 21
30 34
1
C0814
1
C0801
1
C0802
1
C0815
0.1UF
0.1UF
0.1UF
0.1UF
6.3V 20%
6.3V 20%
20% 6.3V
6.3V 20%
2
2
2
2
X5R-CERM
X5R-CERM
X5R-CERM
X5R-CERM
01005
01005
01005
01005
NOTE:VDD12_LPDP SHOULD BE POWERED
EVEN WHEN LPDP IS NOT USED
ROOM=SOC
ROOM=SOC
ROOM=SOC
ROOM=SOC
PP1V2
15
6
5
PP1V8
3
5
6
7
8
9 12
13
14 17 20 21
30 34
CRITICAL
U0600
1
1
1
1
R0804
R0805
R0806
R0807
MAUI-2GB-25NM-DDR-H
1.00K
1.00K
1.00K
1.00K
5%
5%
5%
5%
FCMSP
1/32W
1/32W
1/32W
1/32W
MF
MF
MF
MF
SC58980B0B-A040
01005
01005
01005
01005
2
2
2
2
ROOM=SOC
ROOM=SOC
ROOM=SOC
ROOM=SOC
SYM 3 OF 14
MIPI_RCAM_TO_AP_DATA0_CONN_P
B8
G31
I2C_ISP_TO_RCAM_SCL
MIPI0C_DATA0_P
ISP_I2C0_SCL
21
21
22
ROOM=SOC
CRITICAL
MIPI_RCAM_TO_AP_DATA0_CONN_N
A8
G32
I2C_ISP_BI_RCAM_SDA
MIPI0C_DATA0_N
OMIT_TABLE
ISP_I2C0_SDA
21
21
22
U0600
MIPI_RCAM_TO_AP_DATA1_CONN_P
A9
F35
I2C_ISP_TO_FCAM_SCL
MAUI-2GB-25NM-DDR-H
MIPI0C_DATA1_P
ISP_I2C1_SCL
21
20
MIPI_RCAM_TO_AP_DATA1_CONN_N
B9
G34
I2C_ISP_BI_FCAM_SDA
A29
FCMSP
MIPI0C_DATA1_N
ISP_I2C1_SDA
LPDP_AUX_P
21
20
NC
B29
SC58980B0B-A040
LPDP_AUX_N
NC
MIPI_RCAM_TO_AP_DATA2_CONN_P
A13
SYM 4 OF 14
MIPI0C_DATA2_P
21
A33
R0808
ROOM=SOC
LPDP_TX0_P
MIPI_RCAM_TO_AP_DATA2_CONN_N
B13
NC
MIPI0C_DATA2_N
OMIT_TABLE
21
33.2
B33
LPDP_TX0_N
D33
AP_TO_RCAM_CLK_R
1
2
AP_TO_RCAM_CLK
NC
SENSOR0_CLK
21
1%
MF
1/32W
MIPI_RCAM_TO_AP_DATA3_CONN_P
B14
D32
AP_TO_RCAM_SHUTDOWN_L
MIPI0C_DATA3_P
SENSOR0_RST
01005
A32
LPDP_TX1_P
21
21
R0809
ROOM=SOC
NC
MIPI_RCAM_TO_AP_DATA3_CONN_N
A14
B32
MIPI0C_DATA3_N
LPDP_TX1_N
21
33.2
NC
F33
AP_TO_FCAM_CLK_R
1
2
AP_TO_FCAM_CLK
SENSOR1_CLK
20
1% MF
1/32W
A31
LPDP_TX2_P
MIPI_RCAM_TO_AP_CLK_CONN_P
A12
E34
AP_TO_FCAM_SHUTDOWN_L
NC
MIPI0C_CLK_P
SENSOR1_RST
01005
21
20
ROOM=SOC
B31
LPDP_TX2_N
MIPI_RCAM_TO_AP_CLK_CONN_N
B12
NC
MIPI0C_CLK_N
21
A30
LPDP_TX3_P
RCAM_REXT
D12
NC
MIPI0C_REXT
D34
AP_TO_SPHERE_BUCK_EN
B30
SENSOR0_ISTRB
LPDP_TX3_N
23
NC
MIPI_AP_TO_LCM_DATA0_P
A3
F32
AP_TO_STOCKHOLM_DWLD_REQUEST
MIPID_DATA0_P
SENSOR0_XSHUTDOWN
30
34
D24
LPDP_CAL_DRV_OUT
MIPI_AP_TO_LCM_DATA0_N
B3
NC
MIPID_DATA0_N
30
C35
SENSOR1_ISTRB
NC
D25
LPDP_CAL_VSS_EXT
C34
AP_TO_MUON_BL_STROBE_EN
NC
SENSOR1_XSHUTDOWN
28
MIPI_AP_TO_LCM_DATA1_P
B4
MIPID_DATA1_P
30
AL4
EDP_HPD
MIPI_AP_TO_LCM_DATA1_N
A4
G35
NC
MIPID_DATA1_N
MIPICSI_MUXSEL
30
NC
H35
DP_WAKEUP
D14
FCAM_REXT
NC
MIPI1C_REXT
MIPI_AP_TO_LCM_DATA2_P
B6
MIPID_DATA2_P
30
MIPI_AP_TO_LCM_DATA2_N
A6
B17
MIPI_FCAM_TO_AP_DATA0_P
MIPID_DATA2_N
MIPI1C_DATA0_P
30
20
A17
MIPI_FCAM_TO_AP_DATA0_N
MIPI1C_DATA0_N
20
MIPI_AP_TO_LCM_DATA3_P
A7
MIPID_DATA3_P
30
MIPI_AP_TO_LCM_DATA3_N
B7
B19
MIPI_FCAM_TO_AP_DATA1_P
MIPID_DATA3_N
MIPI1C_DATA1_P
30
20
A19
MIPI_FCAM_TO_AP_DATA1_N
MIPI1C_DATA1_N
20
MIPI_AP_TO_LCM_CLK_P
A5
MIPID_CLK_P
30
MIPI_AP_TO_LCM_CLK_N
B5
A18
MIPI_FCAM_TO_AP_CLK_P
MIPID_CLK_N
MIPI1C_CLK_P
30
20
B18
MIPI_FCAM_TO_AP_CLK_N
MIPI1C_CLK_N
20
LCM_REXT
D9
MIPID_REXT
1 R0803
R0801 1
R0802 1
4.02K
4.02K
4.02K
1%
1%
1%
1/32W
1/32W
1/32W
MF
MF
MF
01005
01005
01005
2 ROOM=SOC
2
2
ROOM=SOC
ROOM=SOC
SYNC_MASTER=N71_SINGLE_BRD
SYNC_DATE=05/29/2014
PAGE TITLE
SOC:CAMERA & DISPLAY
DRAWING NUMBER
SIZE
051-00094
D
Apple Inc.
REVISION
R
A.0.0
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
8
OF 49
II NOT TO REPRODUCE OR COPY IT
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
7
OF 60
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
1
E10
E13
VDD085_MIPI
E8
D13
D10
E7
D8
VDD18_MIPI
E11
E14
E23
E25
VDD12_LPDP
E27
F24

D

C

B

A

D

C

B

A

8 7 6 5 4 3 2 1 MAUI - GPIO & SERIAL INTERFACES PP1V8
8
7
6
5
4
3
2
1
MAUI - GPIO & SERIAL INTERFACES
PP1V8
3
5
6
7
8
9
12
13
14 17 20 21
30 34
R0900 1
R0901 1
R0902 1
R0903 1
R0904 1
R0905 1
1.00K
2.2K
2.2K
2.2K
1.00K
1.33K
D
D
5%
5%
5%
5%
5%
1%
1/32W
1/32W
1/32W
1/32W
1/32W
1/32W
MF
MF
MF
MF
MF
MF
01005 2
01005 2
01005 2
01005 2
01005 2
01005 2
ROOM=SOC
ROOM=SOC
ROOM=SOC
ROOM=SOC
ROOM=SOC
ROOM=SOC
R0920
33.2
I2S_AP_TO_CODEC_MCLK
1
2
I2S_AP_TO_CODEC_MCLK_R
P34
E31
I2C0_AP_SCL
I2S0_MCK
I2C0_SCL
25
8
16 28 34
U0600
I2S_AP_TO_ARC_MCLK
1%
I2S_AP_OWL_TO_CODEC_XSP_BCLK
R34
D35
I2C0_AP_SDA
I2S0_BCLK
I2C0_SDA
27
25
9
8
16 28 34
1/32W
MAUI-2GB-25NM-DDR-H
I2S_AP_TO_SPEAKERAMP_MCLK
MF
I2S_AP_OWL_TO_CODEC_XSP_LRCLK
N34
I2S0_LRCK
26
25
9
AP_TO_HP_HS3_CTRL
01005
C1
FCMSP
GPIO_0
32
I2S_CODEC_TO_AP_OWL_XSP_DIN
N35
AH1
I2C1_AP_SCL
U0600
ROOM=SOC
I2S0_DIN
I2C1_SCL
25
9
8
17
26 27 31 34
AP_TO_HP_HS4_CTRL
D2
SC58980B0B-A040
GPIO_1
32
I2S_AP_TO_CODEC_XSP_DOUT
M33
AG4
I2C1_AP_SDA
MAUI-2GB-25NM-DDR-H
I2S0_DOUT
I2C1_SDA
25
8
17
26 27 31 34
BUTTON_VOL_UP_L
D1
R0921
SYM 6 OF 14
GPIO_2
34
33
16
FCMSP
33.2
CRITICAL
BUTTON_VOL_DOWN_L
F1
GPIO_3
34
33
16
1
2
I2S_AP_TO_ARC_MCLK_R
M4
L31
I2S1_MCK
ROOM=SOC
I2C2_SCL
SC58980B0B-A040
I2C2_AP_SCL
20
28 30
SPEAKERAMP_TO_AP_INT_L
E2
GPIO_4
26
1%
I2S_AP_TO_BT_BCLK
M3
OMIT_TABLE
M32
I2C2_AP_SDA
I2S1_BCLK
I2C2_SDA
34
20
28 30
SYM 5 OF 14
AP_TO_SPEAKERAMP_STAYIN_ALIVE
1/32W
F3
AE1
AP_TO_SPHERE_BUCK_MODE
GPIO_5
TMR32_PWM0
26
CRITICAL
23
MF
I2S_AP_TO_BT_LRCLK
P1
I2S1_LRCK
34
AP_TO_SPEAKERAMP_RESET_L
01005
F2
AF2
PP1V8
GPIO_6
26
ROOM=SOC
TMR32_PWM1
I2S_BT_TO_AP_DIN
N3
3
5
6
7
8
9
12
13
14 17 20 21
NC
ROOM=SOC
I2S1_DIN
34
30 34
AP_TO_BT_WAKE
H3
OMIT_TABLE
AF3
GPIO_7
TMR32_PWM2
34
I2S_AP_TO_BT_DOUT
L4
NC
I2S1_DOUT
34
AP_TO_BB_RESET_L
G3
R0922
GPIO_8
R0906 1
R0907 1
34
33.2
PCIE_AP_TO_WLAN_DEV_WAKE
J1
AE3
UART_AP_DEBUG_RXD
2.2K
2.2K
GPIO_9
UART0_RXD
34
31 34
1
2
I2S_AP_TO_SPEAKERAMP_MCLK_R
U32
I2S2_MCK
5%
5%
AP_TO_LED_DRIVER_EN
H4
AE4
UART_AP_DEBUG_TXD
GPIO_10
UART0_TXD
22
31 34
1%
I2S_AP_TO_CODEC_ASP_BCLK
V33
W3
1/32W
1/32W
I2S2_BCLK
SEP_SPI0_SCLK
27
26
25
NC
MF
MF
AP_TO_TOUCH_RESET_L
1/32W
K1
GPIO_11
01005
01005
29
MF
I2S_AP_TO_CODEC_ASP_LRCLK
U33
AA4
I2S2_LRCK
SEP_SPI0_MISO
2
2
27
26
25
NC
ROOM=SOC
ROOM=SOC
AP_TO_LCM_RESET_L
01005
J3
K31
UART_BT_TO_AP_CTS_L
GPIO_12
UART1_CTS*
30
34
I2S_CODEC_TO_AP_ASP_DIN
T33
U2
ROOM=SOC
I2S2_DIN
SEP_SPI0_MOSI
27
26
25
NC
PMU_TO_AP_IRQ_L
K2
K32
UART_AP_TO_BT_RTS_L
GPIO_13
UART1_RTS*
16
34
I2S_AP_TO_CODEC_ASP_DOUT
V34
I2S2_DOUT
27
26
25
AP_TO_BB_PCIE_DEV_WAKE
J4
L33
UART_BT_TO_AP_RXD
GPIO_14
UART1_RXD
34
34
AP_TO_STOCKHOLM_DEV_WAKE
L2
L32
UART_AP_TO_BT_TXD
GPIO_15
UART1_TXD
34
34
ALS_TO_AP_INT_L
AM3
V3
I2S3_MCK
SEP_I2C_SCL
20
I2C_SEP_TO_EEPROM_SCL
8
BOARD_ID3
K3
GPIO_16
3
I2S_AP_TO_BB_BCLK
AM4
Y4
I2S3_BCLK
SEP_I2C_SDA
34
I2C_SEP_BI_EEPROM_SDA
8
NO_TEST=1
NC_AP_TO_STOCKHOLM_SIM_SEL
L3
AT23
GPIO_17
UART2_CTS*
I2S_AP_TO_BB_LRCLK
AN2
NC
I2S3_LRCK
34
BOOT_CONFIG0
N1
AR20
C
GPIO_18
UART2_RTS*
CAM_EXT_LDO_EN
3
21
I2S_BB_TO_AP_DIN
AP1
C
I2S3_DIN
34
AP_TO_ARC_RESET_L
AH2
AP23
GPIO_19
UART2_RXD
27
I2S_AP_TO_BB_DOUT
AN1
Y3
NC
I2S3_DOUT
SEP_GPIO0
34
NC
LCM_TO_OWL_BSYNC
AH3
AP22
GPIO_20
UART2_TXD
34
30 9
AB4
NC
SEP_GPIO1
NC
ARC_TO_AP_INT_L
AH4
GPIO_21
27
TRISTAR_TO_AP_INT
R32
I2S4_MCK
31
16
BB_TO_AP_GPS_TIME_MARK
AJ1
N4
UART_STOCKHOLM_TO_AP_CTS_L
GPIO_22
UART3_CTS*
34
34
I2S_AP_TO_CODEC_MSP_BCLK
R31
I2S4_BCLK
25
PP1V8
3
5
6
7
8
9
12
13
14 17 20 21
AP_TO_ARC_STAYIN_ALIVE
AJ2
P3
UART_AP_TO_STOCKHOLM_RTS_L
GPIO_23
UART3_RTS*
30 34
27
34
I2S_AP_TO_CODEC_MSP_LRCLK
V32
I2S4_LRCK
25
PP1V8_ALWAYS
BB_TO_AP_RESET_DETECT_L
AJ3
R3
UART_STOCKHOLM_TO_AP_RXD
8 12
15 17
GPIO_24
UART3_RXD
34
34
I2S_CODEC_TO_AP_MSP_DIN
P31
I2S4_DIN
25
NOSTUFF
BOOT_CONFIG1
AJ4
R2
UART_AP_TO_STOCKHOLM_TXD
GPIO_25
UART3_TXD
3
34
I2S_AP_TO_CODEC_MSP_DOUT
P32
I2S4_DOUT
R0909 1
1 R0910
1 R0941
25
FORCE_DFU
AK1
GPIO_26
34
3
10K
10K
10K
DFU_STATUS
AP3
J33
UART_WLAN_TO_AP_CTS_L
5%
5%
5%
GPIO_27
UART4_CTS*
34
3
34
1/32W
1/32W
1/32W
BOOT_CONFIG2
AN4
J34
UART_AP_TO_WLAN_RTS_L
MF
MF
MF
GPIO_28
UART4_RTS*
3
34
01005
01005
01005
2 2
2
BOARD_ID4
AP4
J35
UART_WLAN_TO_AP_RXD
ROOM=SOC
ROOM=SOC
ROOM=SOC
GPIO_29
UART4_RXD
3
34
BOARD_ID2
AD4
SPI0_MISO
3
CODEC_TO_AP_PMU_INT_L
AP5
K33
UART_AP_TO_WLAN_TXD
GPIO_30
UART4_TXD
25 16
34
BOARD_ID1
AC3
SPI0_MOSI
3
AP_TO_BB_RADIO_UP_L
AR2
GPIO_31
34
BOARD_ID0
AB2
SPI0_SCLK
3
AP_TO_NAND_FW_STRAP
AR3
T32
SWI_AP_BI_TIGRIS
GPIO_32
UART5_RTXD
13
9 17
AD3
ROOM=SOC
SPI0_SSIN
NC
TOUCH_TO_AP_INT_L
AR4
R0940
GPIO_33
30
0.00
BOARD_REV3
AP6
GPIO_34
3
SPI_CODEC_TO_AP_MISO
P33
AM1
PMU_TO_AP_SOCHOT0_R_L
1
2 PMU_TO_AP_SOCHOT0_L
SPI1_MISO
SOCHOT0
25
16
BOARD_REV2
1/32W
AT3
GPIO_35
3
SPI_AP_TO_CODEC_MOSI
V35
SPI1_MOSI
0% MF 01005
25
BOARD_REV1
AT4
GPIO_36
3
SPI_AP_TO_CODEC_SCLK
N32
SPI1_SCLK
25
BOARD_REV0
AR6
AF1
UART_ACCESSORY_TO_AP_RXD
GPIO_37
UART6_RXD
3
31
SPI_AP_TO_CODEC_CS_L
M31
AM2
AP_TO_PMU_SOCHOT1_L
SPI1_SSIN
25
AP_TO_BB_COREDUMP
AP7
AE2
UART_AP_TO_ACCESSORY_TXD
GPIO_38
UART6_TXD
34
31
BB_IPC_GPIO
AT5
SOCHOT1
16
GPIO_39
34
SPI_TOUCH_TO_AP_MISO
E33
SPI2_MISO
30 8
BUTTON_RINGER_A
AP8
J31
R0960
GPIO_40
UART7_RXD
34
33
16 8
SPI_AP_TO_TOUCH_MOSI
E35
SPI2_MOSI
30
0.00
AP_TO_BB_MESA_ON_L
AP9
J32
SPI_AP_TO_TOUCH_SCLK
GPIO_41
UART7_TXD
34
SPI_AP_TO_TOUCH_SCLK_R
F34
NC
1
2
SPI2_SCLK
30
MAMBA_EXT_LDO_EN
AP10
GPIO_42
29
SPI_AP_TO_TOUCH_CS_L
F31
H31
0%
SPI2_SSIN
CPU_ACTIVE_STATUS
30
NC
1/32W
MF
SPI_MESA_TO_AP_MISO
AA2
01005
SPI3_MISO
29
B
ROOM=SOC
R0930
B
SPI_AP_TO_MESA_MOSI
Y2
H34
AP_TO_TOUCH_CLK32K_RESET_L
SPI3_MOSI
CLK32K_OUT
29
30
PP1V8
0.00
21
20 17 14 13
12
9
8
7
6
5
3
29 SPI_AP_TO_MESA_SCLK
1
2
SPI_AP_TO_MESA_SCLK_R
AA3
34 30
SPI3_SCLK
R0945
MESA_TO_AP_INT
AC4
AM24
AP_TO_NAND_SYS_CLK_R
0%
SPI3_SSIN
NAND_SYS_CLK
29
0.00
ANALOG_PROX
1/32W
1
2
AP_TO_NAND_SYS_CLK
MF
13
R0911 1
01005
0%
1.00K
ROOM=SOC
1/32W
5%
MF
1/32W
01005
MF
ROOM=SOC
01005 2
ROOM=SOC
PROX_SELECT
SPI PROBE POINTS
I2C PROBE POINTS
PIN J31 (UART7_RXD) SHOULD BE
SET TO INTERNAL PULL-DOWN.
STUFF R0911 FOR ANALOG PROX.
NOSTUFF R0911 FOR DOPPLER PROX.
1 SM
PP0900
SM
PP0906
I2C0_AP_SCL
SPI_TOUCH_TO_AP_MISO
1
34
28 16
8
PP
P3MM-NSM
30 8
PP
P3MM-NSM
ROOM=SOC
ROOM=SOC
PLACE_SIDE=TOP
1 SM
PP0901
I2C0_AP_SDA
34
28
16 8
PP
P3MM-NSM
ROOM=SOC
ANTI-ROLLBACK EEPROM
BUTTON PULL-UP RESISTORS
1 SM
PP0902
I2C1_AP_SCL
34
31 27
26 17
8
PP
P3MM-NSM
ROOM=SOC
PLACE_SIDE=TOP
128kbit
1 SM
PP0903
I2C1_AP_SDA
34
31 27
26 17
8
APN:335S0946
PP
P3MM-NSM
ROOM=SOC
PLACE_SIDE=TOP
PP1V8_SDRAM
12
14
15
16
25
28 31 32 34
1
R0950
1
PP1V8
R0951
21 20 17
14
13 12
9
8
7
6
5
3
34 30
191K
100K
1%
5%
1
C0900
CRITICAL
1/32W
1/32W
1.0UF
MF
MF
01005
01005
2
2
ROOM=SOC
A
6.3V 20%
BUTTON_MENU_KEY_L
ROOM=SOC
2
X5R
34
29
16 9
A
SYNC_MASTER=N71_SINGLE_BRD
0201-1
SYNC_DATE=05/29/2014
U0900
BUTTON_RINGER_A
34
33
16 8
ROOM=SOC
PAGE TITLE
M34128-FCS6_P/T
SOC:SERIAL & GPIO
PP1V8_ALWAYS
B1
A2
I2C_SEP_BI_EEPROM_SDA
8 12
15 17
SCL
WLCSP
SDA
8
I2C_SEP_TO_EEPROM_SCL
DRAWING NUMBER
SIZE
8
1
R0952
051-00094
D
220K
Apple Inc.
5%
REVISION
ROOM=SOC
1/32W
R
A.0.0
MF
01005
2
ROOM=SOC
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
BUTTON_HOLD_KEY_L
34
33
16 9
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
9
OF 49
II NOT TO REPRODUCE OR COPY IT
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
8
OF 60
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
1
.
A1B2
VCCVSS
GRP1
GRP3 GRP1GRP3GRP1GRP1
GRP1GRP2
GRP3
GRP1GRP1
GRP3
8 7 6 5 4 3 2 1 MAUI - OWL POWER STATE CONTROL PROBE
8
7
6
5
4
3
2
1
MAUI - OWL
POWER STATE CONTROL PROBE POINTS
1 SM
OWL_TO_PMU_ACTIVE_REQUEST
PP1020
16
9
PP
P3MM-NSM
ROOM=SOC
1 SM
PMU_TO_OWL_ACTIVE_READY
PP1021
31
28
16
9
5
PP
P3MM-NSM
ROOM=SOC
1 SM
PP1022
OWL_TO_PMU_SLEEP1_REQUEST
16
9
PP
P3MM-NSM
ROOM=SOC
PMU_TO_OWL_SLEEP1_READY
1 SM
PP1023
16
11 9
PP
P3MM-NSM
ROOM=SOC
PP1V8
3
5
6
7
8 12
13
14
17 20 21 30
34
NOSTUFF
1
R1002
1.00K
5%
1/32W
MF
01005
2
U0600
MAUI-2GB-25NM-DDR-H
FCMSP
SC58980B0B-A040
SYM 7 OF 14
OWL_TO_PMU_SLEEP1_REQUEST
AD30
W33
PMU_TO_SYSTEM_COLD_RESET_L
OWL_DDR_REQ
CFSB_AOP
16
9
3
5 16 34
PMU_TO_OWL_SLEEP1_READY
AB33
CRITICAL
OWL_DDR_RESET*
16
11 9
AA33
AWAKE_REQ
OWL_TO_PMU_ACTIVE_REQUEST
ROOM=SOC
9
16
SPI_OWL_TO_COMPASS_CS_L
AF35
OMIT_TABLE
AD32
OWL_FUNC_0
AWAKE_RESET*
PMU_TO_OWL_ACTIVE_READY
19
5
9 16
28 31
COMPASS_TO_OWL_INT
AH32
OWL_FUNC_1
19
AL2
DWI_PMU_TO_PMGR_MISO
PMGR_MISO
16
DISCRETE_ACCEL_TO_OWL_INT2
AG32
OWL_FUNC_2
19
AL1
DWI_PMGR_TO_PMU_BACKLIGHT_MOSI
PMGR_MOSI
16
28
ACCEL_GYRO_TO_OWL_INT1
AG31
OWL_FUNC_3
19
AK4
DWI_PMGR_TO_PMU_SCLK
PMGR_SCLK0
16
SPI_OWL_TO_ACCEL_GYRO_CS_L
AG30
OWL_FUNC_4
19
AL3
DWI_PMGR_TO_BACKLIGHT_SCLK
PMGR_SSCLK1
28
ACCEL_GYRO_TO_OWL_INT2
AF33
OWL_FUNC_5
19
SPI_OWL_TO_PHOSPHOROUS_CS_L
AE34
AD31
OWL_FUNC_6
RT_CLK32768
PMU_TO_OWL_CLK32K
19
16
LCM_TO_OWL_BSYNC
AF34
OWL_FUNC_7
34
30 8
AE33
SWD_AP_PERIPHERAL_SWCLK
OWL_SWD_TCK_OUT
13
34
OWL_TO_PMU_SHDN_BI_TIGRIS_SWI
AF31
OWL_FUNC_8
9
AD35
OWL_SWD_TMS0
PHOSPHORUS_TO_OWL_IRQ
AF32
OWL_FUNC_9
19
EXT OSC IN
AC33
SWD_AP_BI_BB_SWDIO
OWL_SWD_TMS1
34
SPI_OWL_TO_DISCRETE_ACCEL_CS_L
AH31
U31
SWD_AP_BI_NAND_SWDIO
OWL_I2CM_SCL
SWD_TMS2
19
GPO
13
DISCRETE_ACCEL_TO_OWL_INT1
AH33
T31
OWL_I2CM_SDA
SWD_TMS3
19
NC
SPI_IMU_TO_OWL_MISO
AK31
U3
BUTTON_HOLD_KEY_L
OWL_SPI_MISO
HOLD_KEY*
19
8
16 33 34
SPI_OWL_TO_IMU_MOSI
AK32
OWL_SPI_MOSI
19
GPO
W4
SKEY*
VDD_SOC
SPI_OWL_TO_IMU_SCLK
AL33
NC
OWL_SPI_SCLK
19
GPO
V4
BUTTON_MENU_KEY_L
MENU_KEY*
8
16 29 34
UART_BB_TO_OWL_RXD
AJ32
OWL_UART0_RXD
34
UART_OWL_TO_BB_TXD
AK33
OWL_UART0_TXD
34
OWL_TO_WLAN_CONTEXT_B
AH30
OWL_UART1_RXD
34
OWL_TO_WLAN_CONTEXT_A
AJ31
OWL_UART1_TXD
34
TOUCH_TO_OWL_ACCEL_DATA_REQUEST
AJ34
OWL_UART2_RXD
30
UART_OWL_TO_TOUCH_TXD
AJ33
OWL_UART2_TXD
30
I2S_AP_OWL_TO_CODEC_XSP_BCLK
AD34
OWL_I2S_BCLK
25
8
I2S_CODEC_TO_AP_OWL_XSP_DIN
AA34
OWL_I2S_DIN
25
8
AE32
OWL_I2S_MCK
NC
I2S_AP_OWL_TO_CODEC_XSP_LRCLK
AE31
OWL_I2S_LRCK
25
8
OWL SYSTEM SHUTDOWN OPTION
NOSTUFF
R1020
10
1
2
1/32W
SWI_AP_BI_TIGRIS
8 17
MF 5%
01005
ROOM=SOC
OWL_TO_PMU_SHDN_BI_TIGRIS_SWI
9
NOSTUFF
R1021
10
SYNC_MASTER=N71_SINGLE_BRD
SYNC_DATE=05/29/2014
1
2
1/32W
OWL_TO_PMU_SHDN
16
MF 5%
01005
PAGE TITLE
ROOM=SOC
SOC:OWL
DRAWING NUMBER
SIZE
051-00094
D
Apple Inc.
REVISION
R
A.0.0
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
10 OF 49
II NOT TO REPRODUCE OR COPY IT
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
9 OF 60
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
1

D

C

B

A

D

C

B

A

8

7

6

5

4

3

2

1

14 10

14 10

MAUI - CPU, GPU & SOC RAILS

PP_SOC

14 0.825V @4.7A MAX 0.725V @TBDA MAX 1 C1151 AA17 W23 10UF U0600 AA19 Y14
14
0.825V @4.7A MAX
0.725V @TBDA MAX
1
C1151
AA17
W23
10UF
U0600
AA19
Y14
6.3V 20%
XW1120
MAUI-2GB-25NM-DDR-H
2
CERM-X5R
SHORT-10L-0.1MM-SM
AA23
Y16
0402-9
1
2
BUCK2_PP_SOC_FB
FCMSP
ROOM=SOC
14
AB14
Y20
PP_GPU
ROOM=SOC
SC58980B0B-A040
AB16
Y22
0.8V @10.5A MAX
SYM 9 OF 14
AB20
Y24
CRITICAL
1
C1101
1
C1102
1
C1103
1
C1104
1
C1105
AB22
Y26
ROOM=SOC
10UF
10UF
2.2UF
2.2UF
2.2UF
AB24
OMIT_TABLE
VDD_SOC
G29
ROOM=SOC
ROOM=SOC
ROOM=SOC
ROOM=SOC
ROOM=SOC
20%
20%
20%
TP1120
C1153
C1154
C1155
C1156
C1157
6.3V 20%
6.3V 20%
6.3V
6.3V
6.3V
AB26
AA27
2
2
2
2
2
CERM-X5R
CERM-X5R
X5R-CERM
X5R-CERM
X5R-CERM
0.50MM
0402-9
0402-9
0201
0201
0201
4.3UF
1UF
1UF
0.47UF
0.47UF
AC17
F17
SM
PP_GPU
1
ROOM=SOC
ROOM=SOC
ROOM=SOC
ROOM=SOC
ROOM=SOC
20%
20%
20%
20%
20%
10 14
PP
AC19
F20
4V
4V
4V
6.3V
6.3V
CERM
CERM
CERM
CERM
CERM
AC23
L29
0402
0402
0402
0402
0402
1
3
1
3
1
3
1
3
1
3
AD16
N29
AD20
V28
ROOM=SOC
ROOM=SOC
ROOM=SOC
ROOM=SOC
ROOM=SOC
ROOM=SOC
AA7
G15
2
4
2
4
2
4
2
4
2
4
C1106
C1107
C1108
C1109
C1110
C1111
AD22
AA9
U0600
W13
AD24
4.3UF
7.5UF
4.3UF
7.5UF
4.3UF
7.5UF
AA11
MAUI-2GB-25NM-DDR-H
T12
20%
20%
20%
20%
20%
20%
AD26
4V
4V
4V
4V
4V
4V
AB6
M6
FCMSP
CERM
CERM
CERM
CERM
CERM
CERM
AE5
0402
0402
0402
0402
0402
0402
AB10
U9
L22
SC58980B0B-A040
1
3
1
3
1
3
1
3
1
3
1
3
AE15
AB12
V12
L24
SYM 8 OF 14
CRITICAL
AE17
AC13
W9
L26
2
4
2
4
2
4
2
4
2
4
2
4
ROOM=SOC
AE19
AD6
M12
L28
OMIT_TABLE
AE23
AD8
M18
M1
AF14
AD10
N15
M5
AF16
AD12
N21
M7
AF20
ROOM=SOC
ROOM=SOC
ROOM=SOC
ROOM=SOC
ROOM=SOC
ROOM=SOC
AE7
N9
M9
C1112
C1113
C1114
C1115
C1116
C1117
AF22
AE9
F10
M11
AF24
1UF
1UF
1UF
1UF
0.47UF
0.47UF
AE11
H14
M13
20%
20%
20%
20%
20%
20%
AF26
4V
4V
4V
4V
6.3V
6.3V
AE13
H16
M17
CERM
CERM
CERM
CERM
CERM
CERM
AG17
0402
0402
0402
0402
0402
0402
AF8
H20
M21
1
3
1
3
1
3
1
3
1
3
1
3
AG19
AF10
H22
M23
AG23
AF12
H6
M25
2
4
2
4
2
4
2
4
2
4
2
4
AH16
AH6
H8
M27
AH20
AH8
J11
M29
AH22
AH10
J13
M35
XW1110
AH24
AH12
J17
N6
SHORT-10L-0.1MM-SM
VDD_CPU
AH26
BUCK1_PP_GPU_FB
2
1
AJ5
J19
N10
14
AJ15
ROOM=SOC
AJ7
J23
N12
AJ17
AJ9
J7
N14
PP_CPU
AJ19
0.625V @TBDA MAX
AJ11
K10
N16
AJ23
0.9V
@10.5A MAX
AJ13
K14
N18
1.0V
@12.5A MAX
1
C1121
C1122
AK14
1
C1120
1
1
C1123
1
C1124
1
C1125
AK6
K16
G19
10UF
10UF
2.2UF
2.2UF
2.2UF
2.2UF
J29
VDD_SOC
AK10
K20
N22
20%
20%
20%
20%
6.3V 20%
6.3V 20%
G23
6.3V
6.3V
6.3V
6.3V
TP1100
2
2
2
2
2
2
AL7
CERM-X5R
CERM-X5R
K22
N24
X5R-CERM
X5R-CERM
X5R-CERM
X5R-CERM
0.50MM
0402-9
0402-9
AK22
0201
0201
0201
0201
AL9
K6
N26
SM
PP_CPU
ROOM=SOC
ROOM=SOC
ROOM=SOC
ROOM=SOC
ROOM=SOC
ROOM=SOC
1
F6
10
PP
AL11
K8
N28
14
F14
AM6
L11
N30
AL15
AM8
L13
N33
AM5
AM10
L15
P9
ROOM=SOC
ROOM=SOC
ROOM=SOC
ROOM=SOC
ROOM=SOC
ROOM=SOC
G25
C1126
C1127
C1128
C1129
C1130
C1131
AN7
L17
P11
G27
7.5UF
7.5UF
4.3UF
4.3UF
4.3UF
7.5UF
AN11
L19
P13
H24
20%
20%
20%
20%
20%
20%
AL13
L21
P15
4V
4V
4V
4V
4V
4V
VDD_GPU
H26
CERM
CERM
CERM
CERM
CERM
CERM
Y8
M24
P17
0402
0402
0402
0402
0402
0402
H28
1
3
1
3
1
3
1
3
1
3
1
3
Y10
L7
P19
VSS
J27
Y12
L9
P21
K24
2
4
2
4
2
4
2
4
2
4
2
4
AM12
F8
P23
K26
M8
P25
K28
N11
P27
L27
N13
P29
L23
N17
P35
M26
ROOM=SOC
ROOM=SOC
ROOM=SOC
ROOM=SOC
ROOM=SOC
ROOM=SOC
N19
R4
C1132
C1133
C1134
C1135
C1136
C1137
M28
P10
R6
4.3UF
7.5UF
1UF
1UF
1UF
1UF
AL19
G11
R8
20%
20%
20%
20%
20%
20%
N7
4V
4V
4V
4V
4V
4V
P12
R10
CERM
CERM
CERM
CERM
CERM
CERM
N27
0402
0402
0402
0402
0402
0402
P14
R12
1
3
1
3
1
3
1
3
1
3
1
3
P24
P16
R14
P26
P20
M19
2
4
2
4
2
4
2
4
2
4
2
4
P28
R15
R18
R17
R19
R20
R27
G13
R22
R29
R9
R24
T22
T10
R26
ROOM=SOC
ROOM=SOC
ROOM=SOC
ROOM=SOC
T26
C1138
C1139
C1140
C1141
T14
R28
T7
0.47UF
0.47UF
0.47UF
0.47UF
T16
R30
T28
20%
20%
20%
20%
U11
T1
6.3V
6.3V
6.3V
6.3V
U17
CERM
CERM
CERM
CERM
V14
T2
0402
0402
0402
0402
V8
1
3
1
3
1
3
1
3
V16
R33
V20
G7
T9
V22
2
4
2
4
2
4
2
4
R23
T11
V24
G9
T13
V26
H10
T15
W7
T24
T17
XW1100
W11
P22
P7
SHORT-10L-0.1MM-SM
Y28
BUCK0_PP_CPU_FB
2
1
W17
T23
14
SM
ROOM=SOC
N23
PP1105
1
AP_SOC_SENSE_P
AJ20
T25
VDD_SOC_SENSE
PP
P2MM-NSM
ROOM=SOC
G17
T27
SM
PP1104
1
AP_SOC_SENSE_N
AK21
VSS_SOC_SENSE
G21
PP
T30
P2MM-NSM
ROOM=SOC
SYNC_MASTER=N71_SINGLE_BRD
T18
T35
PAGE TITLE
T20
U6
SOC:POWER (1/3)
U10
SM
PP1100
1
AP_CPU_SENSE_P
Y6
G20
AP_GPU_SENSE_P
P2MM-NSM
VDD_CPU_SENSE
VDD_GPU_SENSE
16
DRAWING NUMBER
SIZE
PP
U12
ROOM=SOC
051-00094
SM
SM
D
PP1101
1
AP_CPU_SENSE_N
Y7
H19
AP_GPU_SENSE_N
1
PP1102
VSS_CPU_SENSE
VSS_GPU_SENSE
Apple Inc.
P2MM-NSM
PP
PP
ROOM=SOC
ROOM=SOC
P2MM-NSM
REVISION
R
A.0.0
NOTE: AP_GPU_SENSE_P probe location @ R2205.2
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
11
OF 49
II NOT TO REPRODUCE OR COPY IT
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
10
OF 60
IV ALL RIGHTS RESERVED

D

C

B

D

C

B

A

A

SYNC_DATE=05/29/2014

8

7

6

5

4

3

2

1

8 7 6 5 4 3 2 1 MAUI - POWER SUPPLIES DDR IMPEDANCE CONTROL
8
7
6
5
4
3
2
1
MAUI - POWER SUPPLIES
DDR IMPEDANCE CONTROL
PP1V1
D
D
14 11
1
1
1
1
PP1V1
R1200
R1201
R1202
R1203
1
R1204
1
R1205
14 11
240
240
240
240
240
240
1%
1%
1%
1%
1%
1%
1
C1240
1
C1241
1
C1242
1
C1243
1
C1244
1
C1248
1/32W
1/32W
1/32W
1/32W
1/32W
1/32W
MF
MF
MF
MF
10UF
2.2UF
2.2UF
2.2UF
2.2UF
2.2UF
MF
MF
01005
01005
01005
01005
2
2
2
2
01005
01005
20%
20%
20%
20%
20%
20%
ROOM=SOC
ROOM=SOC
ROOM=SOC
ROOM=SOC
2
2
ROOM=SOC
ROOM=SOC
6.3V
6.3V
6.3V
6.3V
6.3V
6.3V
2
2
2
2
2
2
CERM-X5R
X5R-CERM
X5R-CERM
X5R-CERM
X5R-CERM
X5R-CERM
0402-9
0201
0201
0201
0201
0201
A20
C21
DDR0_RREF
DDR0_RREF
ROOM=SOC
ROOM=SOC
ROOM=SOC
ROOM=SOC
ROOM=SOC
ROOM=SOC
A22
U0600
AP17
DDR1_RREF
DDR1_RREF
B11
V31
MAUI-2GB-25NM-DDR-H
DDR2_RREF
DDR2_RREF
B15
P5
DDR3_RREF
FCMSP
DDR3_RREF
ROOM=SOC
ROOM=SOC
ROOM=SOC
B23
SC58980B0B-A040
C1245
C1246
C1247
B25
B21
DDR0_ZQ
SYM 11 OF 14
DDR0_ZQ
4.3UF
1UF
0.47UF
D16
CRITICAL
P2
DDR3_ZQ
VDDIO11_DDR0
DDR3_ZQ
20%
20%
20%
ROOM=SOC
4V
4V
6.3V
D20
CERM
CERM
CERM
OMIT_TABLE
0402
0402
0402
D22
C18
PMU_TO_OWL_SLEEP1_READY
DDR0_RET*
9 16
1
3
1
3
1
3
E15
AP15
DDR1_RET*
E17
Y31
DDR2_RET*
2
4
2
4
2
4
E19
U4
FL1280
DDR3_RET*
100OHM-25%-0.12A
E21
1.1V @7mA MAX
F19
PP1V1_DDR_PLL
1
2
PP1V1
11 14
AN19
VDDIO11_PLL_DDR
AR18
AK18
VOLTAGE=1.1V
01005
ROOM=SOC
W26
1
C1280
P8
0.22UF
AR21
20%
0.8V @TBDA MAX
0.9V @TBDA MAX
1.0V @1.0A MAX
6.3V
2
AR8
X5R
01005-1
AT13
ROOM=SOC
0.802-TBDV @1.1A MAX
AT16
C
C
PP_FIXED
14
7
6
AA15
AC11
PP_CPU_SRAM
AM14
VDDIO11_DDR1
14
U0600
AA21
AC7
AM16
MAUI-2GB-25NM-DDR-H
ROOM=SOC
ROOM=SOC
ROOM=SOC
AA25
ROOM=SOC
ROOM=SOC
ROOM=SOC
AC9
AM18
1
C1200
C1201
C1202
C1203
C1220
C1221
C1222
1
C1223
FCMSP
AA13
D19
10UF
AB18
AM20
2.2UF
12 14 15
4.3UF
1UF
0.47UF
SC58980B0B-A040
0.47UF
1UF
4.3UF
20%
AC15
VDD_CPU_SRAM
AG11
20%
AR15
AN17
20%
20%
20%
20%
20%
20%
6.3V
6.3V
2
CERM-X5R
4V
4V
6.3V
AC21
6.3V
4V
4V
2
AG7
X5R-CERM
AN13
VDDIO11_RET_DDR
W31
CERM
CERM
CERM
SYM 10 OF 14
CERM
CERM