CIPS 2016 - 9th International Conference on Integrated Power Electronics Systems

Monitoring of IGBT modules temperature and degradation simula-

tion
Kristian Bonderup Pedersen1, Mads Brincker1, Pramod Ghimire2, Kjeld Pedersen1
1
Department of Physics and Nanotechnology, Aalborg University, Denmark
2
Department of Energy Technology, Aalborg University, Denmark

Abstract
This paper presents an overview of the challenges in online monitoring of on-state voltage in high power insulated gate
bipolar transistor modules used for temperature and degradation assessment. Through a detailed simulation approach,
based on the finite element method, an estimation of the impact on on-state voltage from inhomogeneous temperature
fields and material degradation of interconnects are presented. Temperature estimation from on-state voltage is normal-
ly based on a steady state calibration procedure which compared to real life application with dynamic loads are insuffi-
cient. Similarly, change in on-state voltage from degradation of multiple interconnects is difficult to separate into spe-
cific contributors and thereby apply in lifetime estimation models. Therefore simulation results are sought combined
with experimental data to increase accuracy of estimation of temperature and degradation of individual elements.

1 Introduction mechanical induced degradation of interconnects bond

In power electronic systems, device reliability has always
been a key element. Especially with regard to semicon-
ductor devices, being the primary active part of a system,
maintaining a high degree of reliability is crucial [1].
While reliability has been greatly improved in recent
years the demands are also increasing. Additionally, load
specifications as well as surrounding environment are
continuously changing [2]. Taking this into consideration,
monitoring component performance through online pa-
rameters is an intelligent way to catch possible problems
prior to catastrophic failure by substituting the device or
calibrate the loading according to device limitations [3].
Monitoring of collector emitter and forward voltage,
respectively ( ), in high power insulated gate bipolar
transistor (IGBT) modules, is commonly used for estimat-
ing load through the semiconductor chip junction temper-
ature and degree of degradation by change in interconnec-
tion resistance [3], [4] [5]. The reason for monitoring par-
ticularly the junction temperature as the primary stressor
is based on the commonly known impact on device life-
time from increase in junction temperature variation ( ).
The coupling between device lifetime and has for
many years been modelled using the Coffin-Manson
(CM) model: [6] [7]
. (1)
While the CM model has been updated on several occa-
sions to include additional degradation contributing fac-
tors [6] [8] [9], the CM power law connection between
and number of cycles to failure ( ) remains the same.
This indicates the impact from running a device under el-
evated temperature conditions, and therefore the necessity
of online monitoring.
However, obtaining accurate temperatures as well as
degradation estimations from on-state voltage is compli-
cated due to several reasons. Power modules subjected to
power cycling conditions normally fail from thermo-
wire fatigue, solder fatigue, metallization reconstruction,
etc. [6]. All of these affect the on-state voltage in different
ways and thereby online temperature as well as degrada-
tion assessment.
In this paper the potential pitfalls in temperature esti-
mation from is discussed from a theoretical perspec-
tive together with presenting possible monitoring strate-
gies trying to overcome this. Additionally, the impact on
on-state voltage from degradation of interconnects is sim-
ulated using 3D finite element models (FEM) and are
compared to experimental data. This is introduced to fully
understand the time evolution of the during a device
lifetime.
2 Online monitoring
The following section is divided into two branches tem-
perature estimation and degradation assessment from on-
state voltage, respectively.
Simulation data are compared to online monitoring
data from two test setups. A standard DC pulse test [10]
and a more advanced active power cycling setup [11]. The
former is a standard accelerated test setup where the de-
vice is heated with a high DC current pulse and after-
wards cooled down. The latter simulates conditions simi-
lar to a doubly fed induction generator for wind power
conversion. Monitoring methodologies are identical for
both systems and are discussed in detail in [11].
2.1 Temperature estimation from TSEPs
Temperature estimation from thermoelectric sensitive pa-
rameters (TSEPs) is an approach normally used for devic-
es in real life operation. Other estimation methods like
thermocouples or IR thermography is limited by compo-
nent accessibility or equipment limitation. The general
idea of estimation from TSEPs is to use the device chips
as sensors (internal gate resistor, gate threshold voltage,
collector-emitter voltage, etc.) [5]. In field use, it is most

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 CIPS 2016 - 9th International Conference on Integrated Power Electronics Systems
convenient to use the to estimate chip temperature
( ) from calibration data. The problem with this ap-
proach is to determine the proportionality between
and [4]. This is normally sought solved by doing a
-calibration under steady state conditions, e.g. by
placing the device on a hot plate at a given temperature
and obtaining the after reaching steady state. If carried
out at several temperatures this yields a calibration matrix
from which the online temperature can be estimated from
the [12]:
, (2)
where is the temperature coefficient, and are
the reference parameters from calibration.
In steady state conditions this connection is clear.
With enough calibration points and a constant tempera-
ture field the linear approximation of Eq. (2) yields accu-
rate results. However, in real life operation the chip tem-
perature is not homogeneous and a difference in surface
temperature from center to edge of up to is not un-
common [4], this needs to be corrected for. Additionally,
depending on the calibration time another correction
might have to be inserted to ensure contributions from
power loss heat-up during calibration. Both of these as-
pects are included in the presently used temperature esti-
mation model:
(3)
where is the temperature correction from heat-up
during calibration, and is the contribution from a
non-homogeneous chip temperature. The former is in-
cluded directly as a temperature correction to the refer-
ence point and as shown in [11] is approximated well with
a linear thermal network model. The , however, is a
bit more complicated. An IGBT chip consists of millions
of transistor channels [13] and with a non-homogenous
temperature all of these will have a unique local tempera-
ture and thereby a different . The current distribution
will therefore depend highly on the local transistor chan-
nel and evidently affect the measured effective . This is
complicated to model analytically or from a standard elec-
trical network. The present proposition is based on an
electro-thermal FEM model with component geometry
and before mentioned calibration matrix as input.
2.2 Degradation monitoring
The on-state voltage used for temperature estimation is
also used to monitor changes in interconnection resistance
[3]. In a typical IGBT module architecture the semicon-
ductor chips are soldered to a direct copper bonded
(DCB) substrate using a standard solder paste. This con-
nection provides good electrical connection to the
pads and the primary thermal path to the DCB backside
cooling. Chip topsides are normally connected to adjoin-
ing pads using heavy bond wires ultrasonically
bonded to the chip metallization. Similarly to the solder
ISBN 978-3-8007-4171-7
connection, the bond wires provide an alternative thermal
route but orders of magnitude from the primary path [13].
The difference in the purpose of the interconnections
highly reflects the impact on the on-state voltage. Bond
wires and metallization are primarily electrical contacts
and as such degradation of the connections are expected
to directly affect the device resistance. In contrast due to
the volume of the soldered connection fractures are not
expected to have significant impact on electrical proper-
ties of the device, but more the thermal impedance.
Therefore changes in are expected to be more indirect
through an increased chip mean temperature [3].
For degradation monitoring two strategies are neces-
sary in order to monitor interconnections on both chip
sides:
, (4)
, (5)
where is the mean on-state voltage at the measure-
ment current ( ) of the first 100 cycles, and the (+/-) sign
indicate the measurement is taken with a time difference
in between but at same current. The time difference there-
by displays the chip thermal impedance. Accordingly,
displays changes in electrical resistance and the
thermal response.
To use the change in on-state parameters it either has
to be coupled with an absolute failure criteria (increment
of of or of thermal re-
sistance from [3] and the LV324 standard, respective-
ly) or lifetime estimation models, see Figure 1.
Figure 1: On-state from standard DC pulse test setup.
[10]
3 Electro-thermal simulation
The effect on from temperature and interconnection
degradation is difficult to separate only from absolute
values. In the present paper the change in is simulated
to overcome this. To simulate effects from temperature
fields and device degradation, these are applied to a spe-
cific geometry. Temperature fields are simulated at vary-
ing load conditions to induce a temperature gradient from
the hot spot to the edge. Degradation is induced by utiliz-
ing experimental data to change physical proper-
ties/geometry, accordingly. In [14] and [15] bond wire
fatigue and metallization reconstruction, respectively, is
investigated experimentally by electrical parameters as a
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 CIPS 2016 - 9th International Conference on Integrated Power Electronics Systems

function of number of cycles. This is implemented into imental values obtained using IR thermography is com-
the electrostatic simulation on the geometry in Figure 2. pared to a simulated curve:
Simulations of the electrostatic potential are carried out
using a finite element approach based on COMSOL mul-
tiphysics.
The equations needed to be solved are the general
electrostatic problem and the convection-reaction-
diffusion equation for the temperature field:

(6)

(7)

where are the electrostatic field and potential, re-

spectively, is the heat flux, is the heat conductivity,
is the density, and is the pressure specific heat capaci-
ty. These equations are ideal for an FEM based approach
which reduces the problem to specifying proper boundary
conditions. In all cases the device backside is simulated
with a Von Neumann boundary condition to represent di-
rect water cooling [13]. All other external faces are re-
garded as thermally isolated.
Figure 2: Illustration of power module geometry with
regions included in the LS device electrical calculations
highlighted. Units are in [mm].
Primarily four problems are considered, effects on on-
state voltage from: (1) calibration heat-up, (2) inhomoge-
neous temperature field compared to calibration condi-
tions, (3) degradation of interconnects, and (4) change of
thermal impedance.
Figure 3: Calibration heat-up error on DUT HS IGBT.
The asterisk indicates experimental values obtained by
IR thermography and the solid curves are simulated.
The heat-up calibration test presented in Figure 3 is car-
ried out in the advanced active power cycling setup [11].
The calibration current is raised to as quickly as
possible ( ) and is afterwards allowed to drop together
with the capacitor and inductor bank of the system. The
current drops almost linearly and after the current
is . Chip surface temperature is measured using IR
thermography on an open module painted black. The sim-
ulated heat-up curve is obtained by using a standard linear
thermal network, see [16], where the thermal impedance
values are obtained from FEM simulation on the geome-
try depicted in Figure 2.
With regards to the effect from non-homogeneous
temperature fields linear thermal networks are no longer
sufficient. To incorporate the effect from the local tem-
perature a full 3D electro-thermal simulation need to be
carried out. In Figure 4 the difference in between
steady state conditions and an inhomogeneous tempera-
ture field is presented at various temperature differences
( ) from hot spot to edge at several currents and varying
mean temperature. To achieve these conditions the load
profile is varied while maintaining within standard test
specifications.

4 Results
4.1 TSEP monitoring correction
Online temperature estimation from TSEPs is carried out
from a steady state calibration procedure. This gives two
clear errors calibration heating and inhomogeneous
fields in real application.
Calibration heat-up depends primarily on two parame-
ters: calibration time and peak current. The mean temper-
ature will cause a shift as well, but this will merely
change the slope of the heat-up curve. In Figure 3 exper-
Figure 4: from inhomogeneous chip temperature.

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 CIPS 2016 - 9th International Conference on Integrated Power Electronics Systems
Clearly the voltage difference in Figure 4 is non-linear
and actually has a tendency to change sign. The mean er-
ror is observed to be smaller at higher currents and mean
temperatures.
4.2 Wire fatigue and metallization reconstruction
In Figure 5 the change in effective resistance of different
bond wires on a chip and the chip metallization induced
by power cycling conditions are presented. The effective
resistance is seen to increase proportional to the number
of cycles and depends on temperature variation. The rea-
son for spread in the specified in Figure 2 is due to the
power cycling conditions, see [11]. Furthermore, if one
implements the change in relative resistance into the elec-
tro-thermal model the change in is obtained, see Table
1:
Figure 5: Change in effective resistance of bond wires
[7] and metallization sheet resistance [8] induced by ac-
tive power cycling (a) and passive thermal cycling (b).
BW fatigue Met. recon.
4.5mV 1.6mV
Lift-off (new 12.9mV 3.1mV
Combined 17.9mV 4.7mV
Table 1: Degradation effects on from bond wire fa-
tigue and metallization reconstruction.
ISBN 978-3-8007-4171-7
The simulation is carried out with a load current of
1000A, similar to test conditions in Figure 1, and a water
cooling temperature of .
4.3 Solder degradation
Figure 6 presents the simulated change in created by
an increase in solder thermal resistance. As previously
stated the change in electrical parameters is assumed neg-
ligible, and therefore the only effect on chip power loss is
due to an increase in mean temperature due to increase of
thermal resistance. In Figure 6 five curves are presented
for increasing power loss conditions from as
initial conditions and with a cooling water temperature of
. The effect on chip thermal resistance from
the degree of solder degradation is included as text inserts
in percentage. So prior to reaching the failure criteria
the can rise more than depending on monitor-
ing current and cooling temperature.
Figure 6: Change in from increased thermal re-
sistance through solder degradation. The text inserts
show the percentage-wise increase of chip thermal re-
sistance ( ).
5 Discussion
5.1 Temperature estimation
In Figure 3 and Figure 4 the simulated possible errors in
temperature estimation from created by calibration
heat-up and in-homogeneous temperature fields is pre-
sented.
Figure 3 presents the simulated chip heat up as a func-
tion of time with calibration current conditions at different
temperatures. To validate the model experimental values
are obtained using IR thermography on black painted
modules. There is a general tendency of overshoot in the
beginning and undershooting later. This is accredited to
the thermal response time of the black paint covering the
chip which is not included in the thermal model. In gen-
eral there appears to be good agreement between the sim-
ple 1D thermal network model and the experimental val-
ues. This provides a clear indication that the calibration
procedure should be conducted as fast as possible as
would be expected, but even so there is a clear possibility
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 CIPS 2016 - 9th International Conference on Integrated Power Electronics Systems
that the estimated thermal coefficient from Eq. (2) will
provide a temperature overshoot if not corrected. Fur-
thermore, this overshoot will increase at higher tempera-
tures, which are problematic as this is often the operation
area of interest.
Similarly, to the error created by calibration heat-up
the difference between steady state calibration and dy-
namic inhomogeneous field conditions seen in Figure 4
also present a clear error. As would be expected the dif-
ference in mean is proportional to the temperature dif-
ference across the chip and is proportional to the load cur-
rent. It is clearly necessary to include corrections in the
temperature estimation equation as the difference between
calibration and real life application easily cause an error
of (the K-factor is normally on the scale of
depending on current level). However, the
dependence between correction and mean temperature
indicates that including it in praxis is a non-trivial task. At
present the optimal solution is to conduct detailed 3D
FEM simulations of the difference under operation condi-
tions, see [13]. However, later it might be necessary to
validate the error estimation by local probing of the chip
under transient and steady state conditions.
5.2 Interconnection degradation
Sections 4.2 and 0 present the effect on from intercon-
nection degradation through change of electrical and
thermal resistance.
Simulation of effects on from degradation of inter-
connects verifies earlier theories that metallization degra-
dation may cause gradual wear over time and lift-off
cause singular bumps, see [11]. However, the gradual ef-
fect from metallization reconstruction is not linear, but
more resembling an s-curve with different phases [15].
This means the contribution from it flattens out in the fi-
nal phase. Furthermore, wire fatigue also contributes to
gradual increase in due to fracturing of wire interfac-
es. If one regards all wires to be degraded at the lowest
level observed in a wire from experiments the change in
is significant, see Table 1.
Figure 6 presents the change in from an increasing
chip thermal resistance through solder degradation. By
imposing a virtual degradation on the chip solder in the
geometry depicted in Figure 2 the on-state under dif-
ferent power loss conditions is obtained. By subtracting
the values from the example without solder degradation
the voltage increase due to increase of thermal resistance
is obtained. It is seen that depending on load current and
mean temperature the can increase above be-
fore reaching the failure criteria of increase of . or by a more detailed calibration procedure.
In contrast to metallization reconstruction and wire lift-off
the solder degradation is expected to continuously de-
grade and cause gradual increase in . This is expected
because of the compliant nature of the solder layer and the
degradation process being more visco-plastic and there-
fore time-dependent [17].
However, if one compares the change in observed
in a standard DC pulse test, see Figure 1, to the contribu-
ISBN 978-3-8007-4171-7
tions from bond wire lift-off and metallization reconstruc-
tion a clear difference in scale is observed. Prior to device
failure a gradual increase of more than is observed.
This can only be explained through a combined effect of
all degrading elements with a primary contribution from
the change in thermal resistance through solder degrada-
tion. Degradation impact simulations are carried out on
each interconnection as an isolated case. With all ele-
ments degrading gradually a cross-coupling effect is to be
expected where the increase in effective electrical re-
sistance cause an increase in mean temperature and there-
by increase the impact from high thermal resistance. This
also indicates the problematic of using a simple power
model as the Coffin-Manson-Arrhenius, see Eq. (1), for
lifetime estimation. The model relies on fitting to experi-
mental data under accelerated conditions and extrapola-
tion to normal operation. However, as clearly indicated
the change in on-state voltage and thereby the degree of
device degradation, depend heavily on the balance be-
tween failure modes which are load, environment, and
device dependent. This also indicate the necessity of a
new monitoring protocol as introduced in Eqs. (4)-(5) to
separate change in electrical and thermal resistance.
6 Conclusion
The present paper focus on two aspects in online monitor-
ing from a theoretical point of view: temperature estima-
tion and degradation monitoring.
The former is focused on temperature estimation from
the on-state collector-emitter voltage ( ). The purpose is
to ensure the device always operate within product speci-
fications and to provide information which may be used
for device load optimization and lifetime estimation. The
commonly used approach is that one calibrates the device
of interest under steady state conditions and obtains a
temperature coefficient. Two clear problems arise with
the concept: calibration heat-up and non-homogeneous
temperature fields. These are outlined and investigated
theoretically. Calibration heat-up is simulated using a
simple 1D thermal network with good agreement to ex-
perimental data, see Figure 3. A clear tendency of a cali-
bration error is observed which increases with calibration
load and mean temperature. Similarly, the effect of non-
homogeneous temperature fields provides a clear error in
on-state voltage compared to calibration conditions, see
Figure 4. This indicate the necessity to expand the tem-
perature estimation function to include corrections ob-
tained either through simulations, as suggested presently,
Degradation monitoring is intended as an approach to
avoid early catastrophic events but also to provide early
estimations of device lifetime through extrapolation. The
former rely on well-defined failure criteria and the latter
on a good extrapolation model. Both are closely connect-
ed to the failure mode. This require significant amount of
knowledge on the effect on the on-state voltage from dif-
ferent degradation mechanism to interpret the pattern.
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 CIPS 2016 - 9th International Conference on Integrated Power Electronics Systems
These are sought simulated by inducing normally experi-
enced device degradation in the power module intercon-
nects. In contrast to earlier beliefs bond wire lift-off
seems to provide gradual change in the on-state voltage
all the way up until lifting and metallization reconstruc-
tion seems to follow a more non-linear degradation pro-
cess, which is illustrated in Figure 5. In common of both
lift-off and reconstruction is that the scale of effect on on-
state voltage is far below what is normally observed over
time in standard DC pulse tests, see Figure 1. This require
a contribution from other interconnections e.g. the chip
solder connection which is clearly seen to be possible
from Figure 6. However, the most likely situation is a
cross-coupling effect between all failure modes. The in-
crease of electrical resistance induces additional power
loss and the following device heat-up is boosted by an in-
creased thermal resistance. This is then repeated each
power cycle inducing the avalanche effect seen near the
end of the device lifetime. The cross-coupling effect un-
derlines the necessity separating change in electrical and
thermal resistance as introduced in Eq. (4) and (5).
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