ELECTRONICS II

KHURRAM ALI khurram.ali@comsats.edu.pk

Department of Electrical Engineering
 Course Title: Electronics II
Course Code:EEE232

Course Instructor: Khurram Ali

Lab Instructor: Khurram Ali

Contact me at khurram.ali@comsats.edu.pk

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 Text Books
1.Microelectronic Circuits by Sedra and Smith, 6th edition

2. Microelectronics Circuits Analysis and Design by Donald

A. Neamen.

Reference Book: Electronic Devices and Circuit theory, 9th

edition, Robert L. Boylestad

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 Assessment Plan
Theory
Quizzes (minimum 4) 15%
Assignments (minimum 4) 10%
Sessional exams I 10%
Sessional exams II 15%
Terminal exam (3 hours) 50%
Lab Work:
Sessional exams I & II 25%
Lab Assignments 25%
Project and Terminal exam 50%
Final marks: Theory marks * 0.75 + Lab marks * 0.25
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 What do we already know
Diodes
Load line
Rectification
Clipper/Clampers
Zener Voltage Regulators
Transistors (BJTs)
CE, CB and CC configurations
Various biasing techniques (fixed bias, self bias, voltage
divider bias)
DC Bias Analysis and Design
AC Analysis (Hybrid- model, voltage gain, current gain,
impedances)

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 What is expected from you?
1. Learning construction, small-signal analysis and operating
features of MOSFET devices.
2. Learning Bode plots to analyze the frequency performance
of a MOSFET circuit. Frequency dependent phenomenon
(Miller effect and Miller capacitance).
3. Learning MOS based differential amplifiers with small-signal
analysis. Studying negative feedback in circuits, stability, and
feedback topologies (like shunt-shunt, shunt-series, etc.).
4. Learning operational-amplifier circuits: design, analysis and
applications. Designing active filters and oscillators using Op-
Amps.
5. Designing power amplifiers for different classes of operation.

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 Transistor
A transistor is a semiconductor device used to amplify or
switch electronic signals and electrical power

A transistor regulates current or voltage flow and acts as a

switch or gate for electronic signals.

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 Types of Transistor
TRANSISTOR

BJT FET

NPN PNP JFET MOSFET

Depletion Depletion Enhancement

Mode Mode Mode

N-Channel P-Channel N-Channel P-Channel N-Channel P-Channel

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 BJT Vs MOSFET
BJT MOSFET
1 It is a Bipolar Device It is majority carrier Device

2 Current control Device Voltage control Device.

Output is controlled by controlling base

3 Output is controlled by controlling gate voltage
current

4 Negative temperature coefficient Positive temperature coefficient

5 So paralleling of BJT is difficult. So paralleling of this device is easy.

Dive circuit is complex. It should provide Dive circuit is simple. It should provide constant
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constant current(Base current) voltage(gate voltage)

7 Losses are low. Losses are higher than BJTs.

8 So used in high power applications. Used in low power applications.

9 BJTs have high voltage and current ratings. They have less voltage and current ratings.

10 Switching frequency is lower than MOSFET. Switching frequency is high.

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 MOSFET

BJT and MOSFET transistors allow controlled

current flow between two terminals from a third
terminal

Either the current (BJT) or voltage (FET) of the

third pin is the controlled factor

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 Depletion & Enhancement Modes
Enhancement-mode MOSFETs are the
common switching elements in most MOS.
These devices are off at zero gatesource
voltage
It can be turned on by pulling the gate
voltage either higher than the source voltage,
for NMOS, or lower than the source voltage,
for PMOS.
In most circuits, this means pulling an
enhancement-mode MOSFET's gate voltage
towards its drain voltage turns it ON.

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 Depletion & Enhancement Modes
In a depletion-mode MOSFET, the device is
normally ON at zero gatesource voltage.
For a depletion type MOSFET, everything is
the same except only that the channel is
already implanted in the substrate through
diffusion.
A current can flow between the source and
drain even at Vgs=0 Volt

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 Depletion & Enhancement Modes
Summary:

Enhancement-mode MOSFETs devices are off at

zero gatesource voltage

In a depletion-mode MOSFET, the device is

normally ON at zero gatesource voltage.

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 MOSFET Construction
As discussed before, as MOSFET allows controlled
current flow between two of its terminals
The amount of current flow is controlled by density of
charges & the density of charges is controlled by the
third terminal
The heart of MOSFET is like a capacitor
Larger the voltage applied the more charge would accumulate
This charge will be used for current flow

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 MOSFET with p-type substrate

Electron inversion layer is formed

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 MOSFET with n-type substrate

Hole inversion layer is formed

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 Enhancement mode
The term enhancement mode means that a voltage must
be applied to the gate to create an inversion layer.

For the MOS capacitor with a p-type substrate, a positive

gate voltage must be applied to create the electron
inversion layer

For the MOS capacitor with an n-type substrate, a

negative gate voltage must be applied to create the hole
inversion layer.

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 n-Channel Enhancement-Mode MOSFET
Figure shows the MOSFET, which has

P-type substrate
Two n+-type source
Drain terminals
A space between drain
and source terminals,
called channel
The capacitor, we discussed earlier
When a chip (IC) is fabricated, multiple
transistors have a shared substrate

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 Basic Transistor Operation
With zero bias applied to the gate, the source and drain terminals are
separated by the p-region, there is no inversion layer
No current flow is possible
It is like a two back to back diodes between Drain and Source

When a large positive gate voltage is applied

A channel is formed between drain and source

Since a positive gate voltage is required for operation

This transistor is called enhancement-mode MOSFET
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 Basic Transistor Operation cont.

Upon application of positive gate voltage

All there regions (drain, substrate and source) will
have excess elections
Current flow is possible
Is there any current flow between gate to source
(or substrate)?

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 Ideal IV characteristics NMOS device
Threshold voltage ( ) of a n-channel MOSFET
Is the minimum voltage required to create an inversion layer
A positive value for n-channel MOSFET (NMOS)
Consider an NMOS with source and substrate
connected to ground
< >

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 Ideal IV characteristics NMOS device cont.
When > , and for small value of , we obtain the
graph Showing almost linear relationship between and

However, when increases

There comes a point
where <
The inversion layer vanishes near
the drain
Further increase in does not
increase (theoretically)
This is called saturation region, where >

() = from =

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