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Test Report
SPICE to Qucs conversion: Test File 4
Mike Brinson
Copyright
c 2007 Mike Brinson <mbrin72043@yahoo.co.uk>
Permission is granted to copy, distribute and/or modify this document under the
terms of the GNU Free Documentation License, Version 1.1 or any later version
published by the Free Software Foundation. A copy of the license is included in
the section entitled GNU Free Documentation License.
Introduction
Title
SPICE 2g6 and 3f5 capacitors.
SPICE specification
Format: SPICE 2g61 :
Notes:
5. Equations:
2. Semiconductor capacitors:
CX N+ N- [value] [mname] [L=length] [W=width] [IC=VAL]
Notes:
1
2. Capacitors begin with letter C.
9. Equations:
CAP =
CJ (L N ARROW ) (W N ARROW ) + 2 CJSW (L + W 2 N ARROW )
SPICE t o Qucs s y n t a x t e s t f i l e
SPICE 2 g6 and 3 f 5 l i n e a r c a p a c i t o r s .
DC and AC t e s t s .
2
v4ac 6 5 ac 1v
r 5 6 p04 10 k
c4 p04 0 1u i c = 10 v
v3 7 0 dc 1v ac 1v
r 6 7 p05 10 k
c5 p05 0 1u
v4 8 0 dc 1v ac 1v
r 7 8 p06 10 k
c6 p06 0 1u i c = 10 v
. ends
. end
SPICE t o Qucs s y n t a x t e s t f i l e
SPICE 2 g6 and 3 f 5 l i n e a r c a p a c i t o r s .
Pulse t e s t s .
3
X1
File=S2Q_test4_a.cir
dc simulation vp01 P01 P02 vp02
DC1
AC1
Type=log Ref
Start=1 Hz
Stop=100kHz
Points=100
number vp01.V vp02.V vp03.V vp04.V vp05.V vp06.V
1 1 1 2 2 1 1
Figure 1: March 22: SPICE to Qucs conversion: Test4 schematic plus dc output
table for SPICE 2g6 and 3f5 linear capacitors test
NOTE: It would appear that the value of a branch AC voltage source is being
added to DC sources in the same branch during the DC simulation. This is
incorrect. Qucs correctly computes the DC conditions from a schematic, see
Fig. 2. ERROR in SPICE to Qucs conversion process.
4
dc simulation
DC1 vp01
C1
ac simulation R1 C=1 uF
R=10k
AC1
Type=log
Start=1 Hz V2
Stop=10 MHz U=1 V Equation
Points=200
Eqn1
vp01_dB=dB(vp01.v)
number vp01.V V1
1 1 U=1 V
1 0
vp01_dB
vp01.v
-50
0.5
-100
0
1 10 100 1e3 1e4 1e5 1e6 1e7 1 10 100 1e3 1e4 1e5 1e6 1e7
acfrequency acfrequency
5
Qucs netlist:
# Qucs 0 . 0 . 11 / media / hda2 /S2Q t e s t 4 p r j /S2Q( t e s t 4 a ) . s c h
6
7
1
1
vp02.v
vp01.v
0.5
0.5
0
0
1 10 100 1e3 1e4 1e5
1 10 100 1e3 1e4 1e5 acfrequency
acfrequency
1 1
vp03.v
vp04.v
0.5 0.5
0 0
1 1
vp05.v
vp06.v
0.5 0.5
0 0
Qucs netlist:
# Qucs 0 . 0 . 11 / media / hda2 /S2Q t e s t 4 p r j /S2Q( t e s t 4 b ) . s c h
8
X1
File=S2Q_test4_b.cir
vp01 P01 P02 vp02
dc simulation
DC1 vp03 P03 P04 vp04
spice
vp05 P05
transient
simulation Ref
TR1
Type=lin
Start=0 number vp01.V vp02.V vp03.V vp04.V vp05.V
Stop=400ms
initialDC=yes 1 0.667 0.667 1.67 1.67 1.67
Figure 4: March 22: SPICE to Qucs conversion: Test4 schematic plus dc output
table for SPICE 2g6 and 3f5 linear capacitors pulse test
9
C: C6 netP05 r e f C=1u V=1V
. Def : End
Sub : X1 r e f netP01 netP02 netP03 netP04 netP05 Type=S2Q TEST4 B
. Def : End
10
1
1
vp01.Vt
vp02.Vt
0.5
0
0
-1
0 0.1 0.2 0.3 0.4
time 0 0.1 0.2 0.3 0.4
time
2 2
vp03.Vt
vp04.Vt
1
0
2
vp05.Vt
Figure 5: March 22: Pulse test waveforms for SPICE 2g6 and 3f5 linear capacitors
11
D: Combined DC, AC and transient source test.
SPICE code: File S2Q_test4_c.cir
SPICE t o Qucs s y n t a x t e s t f i l e
SPICE 2 g6 and 3 f 5 c a p a c i t o r s .
P u l s e t e s t with dc and ac s o u r c e
in s e r i e s with p u l s e v o l t a g e s o u r c e .
. s u b c k t S2Q t e s t 4 c p06
12
X1
dc simulation vp06 File=S2Q_test4_c.cir transient
P06 simulation
DC1 spice
Ref TR1
Type=lin
Start=0
ac simulation Stop=300 ms
IntegrationMethod=Gear
AC1 Order=6
Type=log number vp06.V reltol=0.01
Start=1 Hz 1 1.67 abstol=100 pA
Stop=10 kHz vntol=100 uV
Points=400
1
vp06.v
0.5
Figure 6: March 22: Test circuit for combined dc, ac and pulse source test
Qucs netlist:
# Qucs 0 . 0 . 11 / media / hda2 /S2Q t e s t 4 p r j /S2Q( t e s t 4 c ) . s c h
13
E: SPICE 2g6 non-linear capacitor tests.
NO results - Qucs 0.0.11 does not allow non-linear capacitors of the SPICE 2g6
form. Nonlinear capacitors will be added to both Qucs and QUCSCONV
sometime in the future when the nonlinear independent voltage and current
sources are implemented, see the todo list..
v2 2 0 dc 1v ac 1v
r 3 2 p02 10 k
c2 p02 0 1u i c = 10 v
v3dc 3 0 dc 1v
v3ac 4 3 ac 1v
r 4 4 p03 10 k
c3 p03 0 1u i c = 10v
v4dc 5 0 dc 1v
v4ac 6 5 ac 1v
r 5 6 p04 10 k
c4 p04 0 cmod1 L=10u W=1u
. model cmod1 C(CJ=50u CJSW=20p NARROW=0 . 1u )
v3 7 0 dc 1v ac 1v
r 6 7 p05 10 k
c5 p05 0 cmod1 L=10u W=1u
v4 8 0 dc 1v ac 1v
r 7 8 p06 10 k
c6 p06 0 cmod2 L=10u
. model cmod2 C(DEFW=1u CJ=50u CJSW=20p NARROW=0 . 1u )
. ends
. end
14
. Def : S2Q t e s t 4 e c i r netP01 netP02 netP03 netP04 netP05 netP06 r e f
. Def : S2Q TEST4 E r e f netP01 netP02 netP03 netP04 netP05 netP06
Vac : V4 n e t 8 c n e t 5 U=1V
Vac : V3 n e t 7 c n e t 4 U=1V
Vac :V4AC n e t 6 c n e t 3 U=1V
Vac :V3AC n e t 4 c n e t 2 U=1V
Vac : V2 n e t 2 c n e t 1 U=1V
Vac : V1 n e t 1 c n e t 0 U=1V
Vdc : V1 c n e t 0 r e f U=1V
R: R1 n e t 1 netP01 R=10 k
C: C1 netP01 r e f C=1u
Vdc : V2 c n e t 1 r e f U=1V
R: R3 n e t 2 netP02 R=10 k
C: C2 netP02 r e f C=1u V=10V
Vdc :V3DC n e t 3 r e f U=1V
Vdc :V3AC c n e t 2 n e t 3 U=1
R: R4 n e t 4 netP03 R=10 k
C: C3 netP03 r e f C=1u V=10V
Vdc :V4DC n e t 5 r e f U=1V
Vdc :V4AC c n e t 3 n e t 5 U=1
R: R5 n e t 6 netP04 R=10 k
C: C4 netP04 r e f L=10u W=1u C=1 e 12
Vdc : V3 c n e t 4 r e f U=1V
R: R6 n e t 7 netP05 R=10 k
C: C5 netP05 r e f L=10u W=1u C=1 e 12
Vdc : V4 c n e t 5 r e f U=1V
R: R7 n e t 8 netP06 R=10 k
C: C6 netP06 r e f L=10u C=1 e 12
. Def : End
Sub : X1 r e f netP01 netP02 netP03 netP04 netP05 netP06 Type=S2Q TEST4 E
. Def : End
RESULTS:
line 25: checker error, extraneous property L is invalid in C:C4
line 25: checker error, extraneous property W is invalid in C:C4
line 28: checker error, extraneous property L is invalid in C:C5
line 28: checker error, extraneous property W is invalid in C:C5
line 31: checker error, extraneous property L is invalid in C:C6
15
March 25 2007, Simulation tests by Mike Brinson
Code modifications:
16
vp06
V3 R1
U=1 V R=10k
TH=0.100002 C1
TL=0.04998 C=1u
Tr=1 us V=-1
Tf=1 us
Td=50 ms
V2 number vp06.V
U=1 V dc simulation
1 1.67
DC1
step for satisfactory accuracy and hence the simulation takes a long time
and appears to hang. SPICE on the other hand considers the AC source to
be only applicable to small signal AC analysis and does NOT include it in
time domain simulation. Yet another example of the difference between
SPICE and Qucs.
RECOMMENDATIONS:
1. Mix DC, AC and time domain source elements in SPICE independent
voltage sources with care when converting code to be simulated with
Qucs.
2. When simulating SPICE netlists in the time domain ensure capacitors
have their initial condition voltages set to known values. This ensures
that the correct DC conditions form the starting point for a transient
circuit simulation.
References
1. A. Vladimirescu, Kaihe Zhang, A.R. Newton, D.O Pederson A. Sangiovanni-
Vincentelli, SPICE 2G Users Guide (10 Aug 1981), Department of Electrical
Engineering and Computer Sciences, University of California, Berkeley, Ca.,
94720.
17
2. B. Johnson, T. Quarles, A.R. Newton, P.O. Pederson, A.Sangiovanni-Vincentelli,
SPICE3 Version 3f Users Manual (October 1972), Department of Electrical
Engineering and Computer Sciences, University of California, Berkeley, Ca.,
94720.
3. Andrei Vladimirescu, THE SPICE book,1994, John Wiley and Sons. Inc.,
ISBN 0-471-609-26-9.
18