Elements of physical design

Unit-3
 Basic concepts of physical design
Physical design is the actual
process of creating circuits on
silicon.
Schematic diagrams are
carefully translated in to sets of
geometric patterns (polygons)
Electric characteristic of a logic
gate depends on the aspect
ratio of the transistors.
The process of physical design is
performed using a computer
tool called a layout editor.
Library, cells, instances
 CAD toolsets
Physical design is based on the CAD tools that simplify the process and aid in the
verification process.
 CAD toolsets
Translates polygon patterns
Extraction routine
in to electrical networks

Checks the layout and

Layout V/S schematic schematic

Layout database and checks

Design rule check every occurrence of the design
rule list on the layout

Automatically finding viable

Place and route wiring routes between 2
points

Electrical rule checker Highlights the connecting paths

 Layout of basic structures
P substrate (n-well technology)
1. Start with p-type substrate
2. N-well
3. Active
4. Polysilicon
5. P select
6. N select
7. Active contacts
8. Polysilicon contact
9. Metal1
10. Via
11. Metal2
12. Over glass
 p-type substrate
Oxide layers are grown or deposited between the conducting layers above
the substrate
The actual values of W and S depend on the layer.
Manhattan geometries deals with turns are multiple of 90. Right angle
layout but doesn't give the best packing density. Many layout editors allow
you to select the angles in an arbitrary manner.

s
 N-wells
An n-well is required at every location where a p-FET is to be
made.

Wnw= minimum width of a n-well mask feature.

Snw-nw= minimum edge to edge spacing of adjacent n wells.
 Active area
Silicon devices are built on active areas of the
substrate.
Active area is flat and provides access to the top
of the silicon wafer.

Wa = Minimum width of an active feature.

Sa-a= minimum edge to edge spacing of active
mask polygon.
 Doped silicon regions
To create n+ and p+ regions. These are known as ndiff and pdiff respectively.
Thermal technique called diffusion is used instead of implantation.
n+ regions are by ion implanting arsenic or phosphorous ions in to the
substrate in areas selected by the n-select mask. This process is done after the
isolation process.
n+=(n select)(active)
Wa = Minimum width of an active area.
Sa-a= minimum active to n select spacing.

P+ region are by ion implanting Boron

p+=(p select)(active)(nwell)
Wa = Minimum active area width.
Sa-a= minimum active to p select spacing.
 MOSFETs
MOSFET structure exist every time a poly gate line completely crosses an n+ or p+ region.
Poly line is deposited before the ion implantation and adds to block do pants from entering
the silicon.

L= Wp = minimum poly width

Sp-p = minimum poly to poly spacing
dpo=minimum extension of poly beyond active.

The minimum poly line width is the same as the drawn channel length for a FET.
Gate ovehang distance: dpo is required to insure the formation of the self aligned FET if a
small registration error occurs in the lithography.
n-FET =(n-select) (active)(poly) this is where channel is formed.
 P-MOSFETs
Cross-section view and layout view of P-MOSETS

pFET= (pSelect) (Active) (Poly) (nWell)

p+=(pSelect) (Active) (nWell) (NOT *Poly+ )