MASTER EPA _ M1 Examen Final FPGA

2014/2015

Exercice 1 (4pts) : Soit le schma ci-dessous

 MASTER EPA _ M1 Examen Final FPGA
2014/2015

Raliser les connections pour avoir lquation LCDFM valide.

/LC
LC
/LF
LF
/HF
HF
/HC
HC
/H2
H2
/H1
H1
1
H2
1
HC
1

&
&
1
&
& LCDFM
 HF
1 LCDFM = H1 * H2 * HF * LF + H1 * LC
LF + H1 * H2 * LC+ H1 * HF * LC
MASTER1EPA _ M1 +Examen
H1 * LF Final
* LC FPGA
LC 2014/2015
1

Exercice 2 (6pts):H1
Soit le schma ci-dessous

1. Ecrire le programme VHDL correspondant au circuit prcdent en

comportemental
2. Faite la mme chose en structurelle.

Exercice 3 : (5pts) : Soit le programme VHDL suivant.

library IEEE; 1. Donner le schma quivalent du

use IEEE.STD_LOGIC_1164.ALL; circuit
use IEEE.STD_LOGIC_ARITH.ALL; 2. Quel est le rle de la variable
use IEEE.STD_LOGIC_UNSIGNED.ALL; temp.
3. En supposant que Input = 1010,
entity Exemple1 is
port( Clock: in std_logic;
L,w: in std_logic;
Output: out std_logic_vector(3 downto 0);
Input: in std_logic_vector( 3 downto 0));
end exemple1;

Architecture Behavioral of Exemple1 is

signal temp : std_logic_vector (3 downto 0);
begin
process
begin
wait until Clock'event and Clock='1';
if L='1' then
temp <= Input;
else
for i in 0 to 2 loop
temp(i) <= temp(i+1);
end loop;
temp(3) <= w;
end if;
end process;
Output <= temp;
end Behavioral;

Exercice 4 (5pts) : Soit le programme

1. Donner
VHDLle schma
suivant.quivalent du
circuit.
ENTITY Alarm is 2. Quel est le type du signal etat ?
PORT( 3. Quel est la liste de sensibilit du
clock, Key, Trip : IN BIT;
Process ?
4. Essayer dtablir un organigramme
pour la partie architecture.
 MASTER EPA _ M1 Examen Final FPGA
2014/2015

Ring : OUT BIT );

END Alarm;

ARCHITECTURE ar of Alarm is
TYPE typetat is (Armed, Off, Ringing);
SIGNAL etat : typetat;
BEGIN
PROCESS (clock, etat) BEGIN
IF Clock ='1' AND Clock 'EVENT THEN
CASE etat is
WHEN Off => IF key ='1' THEN etat <= Armed;
ELSE etat <= Off;
END IF;
WHEN Armed => IF Key = '0' THEN
etat <= Off;
ELSIF Trip ='1' THEN
etat <= Ringing;
ELSE etat <= Armed;
END IF;
WHEN Ringing => IF Key ='0' THEN
etat <= Off;
ELSE etat <= Ringing;
END IF;
END CASE;
END IF;
IF etat=Ringing THEN
Ring<='1';
ELSE Ring <='0';
ENDIF
END PROCESS;
END ar;