ACADEMIC PLAN FOR 2nd SEM M.Tech(VLSI Design), Jan.

2014

Class: 2nd SEM M.Tech(VLSI Design) Subject code: MVD-502

Credits:4 Subject: Device Modeling & Circuit simulation

S.No Topics to be covered Total No.

1st Term of L/ T
1 Overview of MOS transistor physics, Two-Terminal MOS structure , Flat 1
-band voltage,
2 Effect of Gate-substrate voltage on surface condition, Inversion, Small 1
signal capacitance,
3 Three-Terminal MOS structure, Body effect, Regions of inversion, Pinch- 2
off voltage,
4 Four Terminal MOS Transistor, Regions of inversion, 2
5 Charge sheet model, Interpolation model, Body referenced model 3
6 MOS transistor large-signal modeling, Quasi-static operation, 3
7 Limitations of quasi-static model, Introduction to non-quasi static model, 3
Total 15L
1st MID SEM EXAM
8 MOS transistor small-signal modeling, low & medium frequency model, 2
9 High frequency model, considerations in MOS modeling for RF 2
applications,
10 Gate resistance, transition frequency, maximum frequency of oscillation, 2
11 Noise model 1
12 MOSFET modeling for circuit simulation, Types of models, 1
13 System for data acquisition and parameter extraction, 2
14 Properties of good models, 1
15 Introduction to SPICE modeling, Model parameters, 1
16 Modeling of resistor, capacitor, inductor, diode, BJT, JFET, MOSFET, 3
Total 15L
2nd MID SEM EXAM
17 Circuit simulation techniques, 1
18 DC analysis, AC analysis, transient analysis, 1
19 SPICE Modeling of Process Variation, Process corners, 2
20 Monte Carlo simulation and sensitivity/worst case analysis, 1
21 Simulation of digital and analog circuits, transfer function 1
22 frequency response, Noise analysis 1
23 distortion and spectral analysis 1
24 Brief overview of BSIM and EKV model , Device and process simulator 2
END TERM EXAM Total: 40
 ACADEMIC PLAN FOR 2nd SEM M.Tech(VLSI Design), Jan. 2014

Class2nd SEM M.Tech (VLSI Design) Subject code: MVD-504

Credits: 4 Subject: VLSI subsystem design

S.No Topics to be covered T/L

1 Moores Law, technology node, ITRS 2
2 VLSI and systems, cost of design, types of chips, specialized standard parts 3
3 ASICs, System-on-Chips(SoCs), IC design techniques 3
4 Hierarchical Design, Design Abstraction 1

5 Computer-Aided Design, IC design flow 1

6 Transistors and layout, Wires and Vias 1
7 Design Rules, Layout Tools (10Hrs) 1
8 UNIT2---Chips and their subsystems, Combinational Shifter 1

9 Adder, ALU 1

10 Multiplier, high density Memory 1

15L
1st Mid Term Exam
11 Image sensor 1

12 FPGA, Programmable logic array 1

13 Buses and Networks-on-Chips, 2 2
14 Data Paths 1
15 Subsystem optimization, Pipelining 2
16 UNIT 3 Intellectual property (IP)-based design, IP types, IP Across the Design 3
Hierarchy
17 The IP Life Cycle, Creating IP 2

18 Using IP, VLSI subsystems as IP 1

19 Systems-on-chips and embedded CPUs 1

20 Multiprocessor System-on-Chip Design 1

15L
2nd Mid Term Exam
21 Chip-level layout, floorplanning methods 2

22 Block Placement, Channel Definition, Global Routing, Switchbox Routing, 2

Global Interconnect

23 Interconnect Properties and Wiring Plans, Power Distribution, Clock 2

Distribution

24 Floorplan Design 1
25 Design Validation 1

26 Off-Chip Connections, I/O Architecture 2

End Term Exam Total:40

 Academic Plan For M.Tech (VLSI Design), Session Jan. 2014

Class: 2nd SEM M.Tech(VLSI Design) Subject code: MVD-506

Credits:4 Subject: Integrated Circuits for Analog Signal Processing

S.No Topics to be covered L/ T

1 Signals, Information, Interference and noise 1
2 Signal classification, Dynamic Range, S/N ratio 1
3 Functions in Analog Signal Processing 1
4 Linear and Non-Linear functions, impedance adaptation 2
5 Amplitude and Level Matching, Terminal Matching 2
6 Buffering, filtering, linearization 2
7 Domain conversions, errors in analog signal processing 2
8 Voltage Amplification, practical voltage amplifiers 2
9 Effects of finite input impedance, building blocks for voltage amplifiers 2
Total 15L
1st Mid Term Exam
10 Current to voltage and voltage to current conversion 2
11 Current integrators, mirrors 2
12 Amplifiers, conveyors 2
13 CMOS analog integrated circuits 1
14 Analog building blocks 1
15 Op-amp design, practical op-amp characteristics and model 2
16 DC offset and DC bias currents, Gain 1
17 Bandwidth and slew rate, noise, Input stage and Output stage 1
18 CMOS OTA, ideal model 1
19 OTA building block circuits, design of simple OTA 2
Total 15L
2nd Mid Term Exam
20 Signal rectifications, AC/DC conversion 2
21 CMOS implementation of adder, subtractor, squarer, multiplier, divider 3
circuits
22 CMOS differentiator and integrator circuits 2
23 Impedance transformation and conversion 2
24 Analog multiplexers 1
End Term Exam Total:40
 ACADEMIC PLAN FOR 2nd SEM M.Tech (VLSI Design), Jan. 2014

Class: 2nd SEM M.Tech(VLSI Design) Subject code: MVD-510(Elective)

Credits:4 Subject: Deep Submicron CMOS ICs

S.No Topics to be covered L/ T

1 MOS Scaling, Classification 2
2 DSM effects on devices 1
3 Physical and Geometrical effects on the behavior of MOS transistor 2
4 Carrier mobility, channel length modulation 2
5 Short channel effects, Narrow channel effects 2
6 Drain feedback, Hot carrier effects 2
7 MOS Transistor leakage mechanism 2
8 Weak inversion behavior, Gate oxide tunneling 2

Ist Mid Term Exam 15L

9 Reverse bias junction leakage 1
10 Gate induced drain leakage, Impact ionization 1
11 Overall leakage interactions and considerations 1
12 Signal integrity, Cross talk and signal propagation 2
13 Power integrity, supply and ground bounce 2
14 Substrate bounce, EMC, Soft errors 2
15 Variability, Spatial & time based variations 2
16 Global & local variations, transistor matching 2
17 Parameter , Process comers, causes for variations 2

2nd Mid Term Exam 15L

18 Deep submicron IC reliability 1
19 Punch through, electromigration, 2
20 Negative bias temperature instability, latch-up 2
21 Electro-Static Discharge, hot carrier degradation 2
22 Charge injection during fabrication process 2
23 Effects of scaling on MOS IC design and consequences for the technology roadmap 1
for semiconductors.

End Term Exam 40(L)

 ACADEMIC PLAN FOR 2nd SEM M.Tech(VLSI Design), Jan. 2014

Class: 2nd SEM M.Tech(VLSI Design) Subject code: MVD-518(Elective)

Credits:4 S ubject: CMOS Mixed-Signal VLSI Design

S.No Topics to be covered Total No. of

Lectures/ Tutorials
1 Analog and discrete-time signal processing 1
2 Analog integrated continuous-time filters 1
3 Discrete-time filters 1
4 Passive and active filters 2
5 Basics of analog discrete-time filters 2
6 Z-transform 2
7 Switched-capacitor filters 1
8 Nonidealities in switched-capacitor filters 1
9 Switched capacitor filter architectures 2
10 Switched capacitor filter applications 2
Total 15L
1st MID SEM EXAM
1 Basics of data converters, 1
2 Successive approximation ADCs 1
3 Dual slope ADCs, 1
4 Flash ADC 1
5 Pipeline ADC 1
6 Hybrid ADC structures, high resolution ADC 2
7 DAC 2
8 Mixed signal layout 2
9 Interconnects and data transmission 2
10 Voltage-mode signaling and data transmission 1
11 Current-mode signaling and data transmission 1
Total 15L
2nd MID SEM EXAM
1 Introduction to frequency synthesizers and synchronization 1
2 Basics of (Phase Locked Loop)PLL, PLL implementation 3
techniques
3 Digital and Analog PLL 2
4 Performance parameters 1
5 Delay Locked Loop(DLL), characteristics, advantages over 3
PLL, implementation techniques
END TERM EXAM Total: 40