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CMP Introduction & CCP Training

DFM - CMP Group

March 23, 2015

CMP Introduction & CCP Training DFM - CMP Group March 23, 2015

Outline

Brief CMP Introduction

Manufacturing issues due to thickness variation

CCP Introduction (Cadence CMP Predictor)

CCP Flow and Setup

VCMP setup

Block Robustness Analysis Flow

CCP-RC Extraction Flow

2 © 2012 Cadence Design Systems, Inc. Cadence confidential.

Block Robustness Analysis Flow • CCP-RC Extraction Flow 2 © 2012 Cadence Design Systems, Inc. Cadence

Interconnect Thickness Variation

Within-Chip Variation is Huge!

Thickness Variation

Surface Height/Topography Variation

Due to Design Impact on Manufacturing

Varying Feature Density

Varying Feature Widths

Variation Leads to Over-Compensation in Design

Timing Failures

Decreased Performance

Increased Power Consumption

Variation Has Impact on Manufacturing

Functional Yield Loss

Wafer Level Variation

Wafer
Wafer
– Functional Yield Loss Wafer Level Variation Wafer Chip Surface Surface Within-Chip Variation Oxide Loss
– Functional Yield Loss Wafer Level Variation Wafer Chip Surface Surface Within-Chip Variation Oxide Loss
Chip Surface
Chip
Surface

Surface

Within-Chip

Level Variation Wafer Chip Surface Surface Within-Chip Variation Oxide Loss Dishing Total Copper Loss Isolated

Variation

Oxide Loss Dishing Total Copper Loss Isolated Isolated Dense Array Dense Array Thin-Lines Wide-Lines Thin-Lines
Oxide Loss
Dishing
Total Copper Loss
Isolated
Isolated
Dense Array
Dense Array
Thin-Lines
Wide-Lines
Thin-Lines
Wide-Lines

3 © 2012 Cadence Design Systems, Inc. Cadence confidential.

Dense Array Thin-Lines Wide-Lines Thin-Lines Wide-Lines 3 © 2012 Cadence Design Systems, Inc. Cadence confidential.

Physical Impact: Bridging/Pooling

Physical Impact: Bridging/Pooling Customer Pooling Case Metal X+1 Metal X SHORTING BETWEEN LINES • Topography from

Customer Pooling Case

Physical Impact: Bridging/Pooling Customer Pooling Case Metal X+1 Metal X SHORTING BETWEEN LINES • Topography from

Metal X+1

Impact: Bridging/Pooling Customer Pooling Case Metal X+1 Metal X SHORTING BETWEEN LINES • Topography from one

Metal X

SHORTING BETWEEN LINES
SHORTING BETWEEN
LINES
Pooling Case Metal X+1 Metal X SHORTING BETWEEN LINES • Topography from one level impacts upper

Topography from one level impacts upper levels

Results in pooling & other physical problems

Seen at multiple customers

4

© 2012 Cadence Design Systems, Inc. Cadence confidential.

Problem: Depth of Focus Issues Metal Defocus n • Large height variations due to multi-level

Problem: Depth of Focus Issues

Metal Defocus n
Metal
Defocus
n

Large height variations due to multi-level CMP effects

CMP topography variation is cumulative

The surface height variation at the mid to upper metal levels can be such that lithography tolerance of depth of focus (DOF) are surpassed, leading to printability issues

5

© 2012 Cadence Design Systems, Inc. Cadence confidential.

5 © 2012 Cadence Design Systems, Inc. Cadence confidential.

Problem: Timing Failures

Source: IBM VMIC 2004
Source: IBM VMIC 2004

6 © 2012 Cadence Design Systems, Inc. Cadence confidential.

Problem: Timing Failures Source: IBM VMIC 2004 6 © 2012 Cadence Design Systems, Inc. Cadence confidential.

Cadence CMP Predictor Features/Applications

Full-Chip Thickness Prediction

Surface height, thickness, density, etc.

Multi-level effects; Short,

medium, & long-range

effects

Viewing and Analysis

Command Line or GUI

Image & Histogram

Hotspot Checking

Built-in or foundry-defined hotspot rules

Custom hotspot scripting

Block Level Analysis

– Check block’s robustness

RC Extraction Interfaces

7

EDA tools (RC extraction)

Generic thickness export file

© 2012 Cadence Design Systems, Inc. Cadence confidential.

EDA tools (RC extraction) – Generic thickness export file © 2012 Cadence Design Systems, Inc. Cadence
EDA tools (RC extraction) – Generic thickness export file © 2012 Cadence Design Systems, Inc. Cadence

VCMP Simulation Flow: Serial Run

Setup

VMP, Techmap & Working Directory

Specify TSMC DDK

Process File (.enc file) Library File (.so file)

TSMC DDK Process File (.enc file) Library File (.so file) Load Design Data GDS / OASIS

Load Design Data

GDS / OASIS

Run Geometry Extraction

Initial Setup

Specify TSMC DDK

Load Design DB

do_extraction

Geometry extraction

do_prediction

CMP prediction

save_psgdb

Run Prediction Export Prediction Save Results View Results Run Hotspot Fix Hint Generation for RC
Run Prediction
Export Prediction
Save Results
View Results
Run Hotspot Fix
Hint Generation
for RC Extraction Interface

8 © 2012 Cadence Design Systems, Inc. Cadence confidential.

Run Hotspot Fix Hint Generation for RC Extraction Interface 8 © 2012 Cadence Design Systems, Inc.

CMP Simulation Basic Flow: Pipeline Run

Setup

VMP, Techmap & Working Directory

Specify TSMC DDK

Process File (.enc file) Library File (.so file)

TSMC DDK Process File (.enc file) Library File (.so file) Load Design Data GDS / OASIS

Load Design Data

GDS / OASIS

Initial Setup

Specify TSMC DDK

Load Design DB

do_simulation

Geometry extraction

CMP prediction

• save_psgdb Run Simulation Export Prediction Save Results View Results Run Hotspot Fix Hint Generation
save_psgdb
Run Simulation
Export Prediction
Save Results
View Results
Run Hotspot Fix
Hint Generation
for RC Extraction Interface

9 © 2012 Cadence Design Systems, Inc. Cadence confidential.

Run Hotspot Fix Hint Generation for RC Extraction Interface 9 © 2012 Cadence Design Systems, Inc.

Overall CMP Simulation Flow

Initial Setup

10 © 2012 Cadence Design Systems, Inc. Cadence confidential.

Overall CMP Simulation Flow • Initial Setup 10 © 2012 Cadence Design Systems, Inc. Cadence confidential.

Inputs / Outputs for CCP

Techmap File Design / Layout Data VMP Mapping of GDS/Layout Layers to Metal Levels GDS
Techmap File
Design / Layout Data
VMP
Mapping of GDS/Layout Layers to Metal Levels
GDS / OASIS
Virtual Manufacturing Process Information
TSMC DDK
CCP Software
Cadence CMP Predictor

Outputs Topography maps

1. Copper Thickness

2. ILD Thickness

3. ILD Height

4. Surface Height

11 © 2012 Cadence Design Systems, Inc. Cadence confidential.

2. ILD Thickness 3. ILD Height 4. Surface Height 11 © 2012 Cadence Design Systems, Inc.

Tech Map File Goal

Tech map maps GDS layout info to manufacturing process

Translate layer number and data type to physical process

Tech map also specifies what vmp to use for prediction

12 © 2012 Cadence Design Systems, Inc. Cadence confidential.

• Tech map also specifies what vmp to use for prediction 12 © 2012 Cadence Design

Example of Tech Map File

<tech version="1.0"> <techmap name="mask_tsmc16FF" vmp="tsmc_N16FF" description="TSMC 16FF" db_scale="1000" db_unit="um"> <level name="M1" minfeature="0"> <layer gds_id="31,0" type="metal" /> <layer gds_id="31,1" type="dummy" /> </level> <level name="M2" minfeature="0"> <layer gds_id="32,70" type="metal" /> <layer gds_id="32,71" type="dummy" />

</level>

<level name="M3" minfeature="0"> <layer gds_id="33,70" type="metal" /> <layer gds_id="33,71" type="dummy" /> </level> <level name="M4" minfeature="0"> <layer gds_id="34,150" type="metal" /> <layer gds_id="34,151" type="dummy" /> </level> <level name="M5" minfeature="0"> <layer gds_id="35,240" type="metal" /> <layer gds_id="35,241" type="dummy" /> </level> </techmap>

</tech>

13 © 2012 Cadence Design Systems, Inc. Cadence confidential.

/> </level> </techmap> </tech> 13 © 2012 Cadence Design Systems, Inc. Cadence confidential.

Inputs / Outputs for CCP

Techmap File Design / Layout Data VMP Mapping of GDS/Layout Layers to Metal Levels GDS
Techmap File
Design / Layout Data
VMP
Mapping of GDS/Layout Layers to Metal Levels
GDS / OASIS
TSMC DDK
CCP Software
Cadence CMP Predictor

Virtual Manufacturing Process Information

Outputs Topography maps

1. Copper Thickness

2. ILD Thickness

3. ILD Height

4. Surface Height

14 © 2012 Cadence Design Systems, Inc. Cadence confidential.

2. ILD Thickness 3. ILD Height 4. Surface Height 14 © 2012 Cadence Design Systems, Inc.

Design

File Format Needs to be:

GDS

Or

OASIS

15 © 2012 Cadence Design Systems, Inc. Cadence confidential.

Design • File Format Needs to be: – GDS Or – OASIS 15 © 2012 Cadence

Inputs / Outputs for CCP

Techmap File Design / Layout Data VMP Mapping of GDS/Layout Layers to Metal Levels GDS
Techmap File
Design / Layout Data
VMP
Mapping of GDS/Layout Layers to Metal Levels
GDS / OASIS
Virtual Manufacturing Process Information
TSMC DDK
CCP Software
Cadence CMP Predictor

Outputs Topography maps

1. Copper Thickness

2. ILD Thickness

3. ILD Height

4. Surface Height

16 © 2012 Cadence Design Systems, Inc. Cadence confidential.

2. ILD Thickness 3. ILD Height 4. Surface Height 16 © 2012 Cadence Design Systems, Inc.

VMP Files

VMP Files Defines Process Condition for Each Metal Level

Contains metal stacking information, for process node of interest

Example: M1MxaMxaMxdMxeMxeMxeMrMr

VMP file is put together by the user

– It is not part of TSMC’s DDK

17 © 2012 Cadence Design Systems, Inc. Cadence confidential.

put together by the user – It is not part of TSMC’s DDK 17 © 2012

VMP File Film Stack Layer Composition

<?xml version="1.0"?>

<calibrations xml_version="0.3.3">

<calibrations xml_version="0.3.3"> <ml_calibration name="tsmc_N16FF"

<ml_calibration name="tsmc_N16FF" mode="Golden" description="TSMC 16nm VCMP Example"> <level name="M1" description="Metal 1" calibration="TSMC.M1" /> <level name="M2" description="Metal 2" calibration="TSMC.Mxa" /> <level name="M3" description="Metal 3" calibration="TSMC.Mxa" /> <level name="M4" description="Metal 4" calibration="TSMC.Mxd" /> <level name="M5" description="Metal 5" calibration="TSMC.Mxe" /> <level name="M6" description="Metal 6" calibration="TSMC.Mxe" /> <level name="M7" description="Metal 7" calibration="TSMC.Mxe" /> <level name="M8" description="Metal 8" calibration="TSMC.Mr" /> <level name="M9" description="Metal 9" calibration="TSMC.Mr" /> </ml_calibration> </calibrations> -------------------------------------------------------SAMPLE TECH MAP FILE (shown below)-------------------------------------------

<tech version="1.0">

<tech version="1.0"> <techmap name="mask_tsmc16FF"

<techmap name="mask_tsmc16FF" vmp="tsmc_N16FF" description="TSMC 16FF" db_scale="1000" db_unit="um"> <level name="M1" minfeature="0"> <layer gds_id="31,0" type="metal" /> <layer gds_id="31,1" type="dummy" /> </level>

<level name="M2" minfeature="0">

<layer gds_id="32,70" type="metal" /> <layer gds_id="32,71" type="dummy" /> </level>

</techmap>

18 © 2012 Cadence Design Systems, Inc. Cadence confidential.

/> </level> … </techmap> 18 © 2012 Cadence Design Systems, Inc. Cadence confidential.

Inputs / Outputs for CCP

Techmap File Design / Layout Data VMP Mapping of GDS/Layout Layers to Metal Levels GDS
Techmap File
Design / Layout Data
VMP
Mapping of GDS/Layout Layers to Metal Levels
GDS / OASIS
Virtual Manufacturing Process Information
TSMC DDK
CCP Software
Cadence CMP Predictor

Outputs Topography maps

1. Copper Thickness

2. ILD Thickness

3. ILD Height

4. Surface Height

19 © 2012 Cadence Design Systems, Inc. Cadence confidential.

2. ILD Thickness 3. ILD Height 4. Surface Height 19 © 2012 Cadence Design Systems, Inc.

TSMC DDK

Design House Can Get DDK Directly from Foundry

PDK/DDK contains model parameter and process settings info

It is encrypted

Without TSMC DDK, TSMC VCMP cannot be run

User needs to specify (in CCP run script) the following from the DDK:

Process File (.enc file)

VCMP File (.so file)

Example:

set psg_tsmc_vcmp <path_to_DDK>/VCMP/linux64/libvcmpDynamic.so set psg_tsmc_procfile <path_to_DDK>/VCMP/VCMP_N16_V197.enc

Use Report VMP Library to Find Out Available Calibrated Models in the TSMC DDK

report_vmp_library -calibration

20 © 2012 Cadence Design Systems, Inc. Cadence confidential.

Models in the TSMC DDK report_vmp_library -calibration 20 © 2012 Cadence Design Systems, Inc. Cadence confidential.

Inputs / Outputs for CCP

Techmap File Design / Layout Data VMP Mapping of GDS/Layout Layers to Metal Levels GDS
Techmap File
Design / Layout Data
VMP
Mapping of GDS/Layout Layers to Metal Levels
GDS / OASIS
Virtual Manufacturing Process Information
TSMC DDK
CCP Software
Cadence CMP Predictor
Outputs – Topography maps 1. Copper Thickness 2. ILD Thickness 3. ILD Height 4. Surface
Outputs – Topography maps
1. Copper Thickness
2. ILD Thickness
3. ILD Height
4. Surface Height

21 © 2012 Cadence Design Systems, Inc. Cadence confidential.

2. ILD Thickness 3. ILD Height 4. Surface Height 21 © 2012 Cadence Design Systems, Inc.

Explanation of Prediction Outputs

Explanation of Prediction Outputs • Copper thickness – The distance from the top of the copper

Copper thickness

The distance from the top of the copper to the bottom of the etched trench. This includes the barrier thickness at the bottom of the trench.

ILD thickness (Inter Layer Dielectric thickness)

The distance from the top of the dielectric to the top of the capping/etch stop layer immediately below the dielectric.

ILD height (Inter Layer Dielectric height)

The distance from the top of the dielectric to the bottom of the etched trench.

Surface height

The density weighted average of the copper and oxide heights referenced from the top of the density weighted surface to the bottom of the M1 etch stop layer.

22 © 2012 Cadence Design Systems, Inc. Cadence confidential.

weighted surface to the bottom of the M1 etch stop layer. 22 © 2012 Cadence Design

Running CCP Batch Mode: Serial Run

Sample Batch Mode Script (for VCMP)

# for LSF Command

set psg_lsf_command "bsub -P DVIP_MGE -W 96:00 -q lnx64 -R \\\"OSREL==EE50 && OSBIT==64 && mem>14000 rusage\[mem=14000\]\\\"

-oo %s %s"

# Specify TSMC’s DDK

set psg_tsmc_vcmp <path to TSMC DDK>/VCMP/linux64/libvcmpDynamic.so

set psg_tsmc_procfile <path to TSMC DDK>/VCMP/VCMP_N16_V197.enc

# Specify VMP & Techmap files

set psg_vmp_path /my_home/cmp_simulations/VCMP/tsmc_vmp_16nm.xml

set psg_tech_path /my_home/cmp_simulations/VCMP/tech_mask_16nm.xml

#Specify techmap of interest within specified techmap file

set techmap mask_tsmc16FF

current_techmap $techmap

#set working directory

set psg_working_path /my_home/cmp_simulations/VCMP/working_dir_1

#Open design

open_design mask.gds

#Do geometry extraction

do_extraction -techmap $techmap -start_level {M1} -end_level {M7} ignore lsf 8

#Do prediction

do_prediction

#Save simulation results (extraction and prediction) into CCP database file

save_psgdb -output mask_gds_16nm.psg

#Report hotspots (Not required)

report_hotspot

Source batch script

23 © 2012 Cadence Design Systems, Inc. Cadence confidential.

(Not required) report_hotspot • Source batch script 23 © 2012 Cadence Design Systems, Inc. Cadence confidential.

Running CCP Batch Mode: Pipeline Run

Sample Batch Mode Script (for VCMP)

# for LSF Command

set psg_lsf_command "bsub -P DVIP_MGE -W 96:00 -q lnx64 -R \\\"OSREL==EE50 && OSBIT==64 && mem>14000 rusage\[mem=14000\]\\\"

-oo %s %s"

# Specify TSMCs DDK

set psg_tsmc_vcmp <path to TSMC DDK>/VCMP/linux64/libvcmpDynamic.so

set psg_tsmc_procfile <path to TSMC DDK>/VCMP/VCMP_N16_V197.enc

# Specify VMP & Techmap files

set psg_vmp_path /my_home/cmp_simulations/VCMP/tsmc_vmp_16nm.xml

set psg_tech_path /my_home/cmp_simulations/VCMP/tech_mask_16nm.xml

#Specify techmap of interest within specified techmap file

set techmap mask_tsmc16FF

current_techmap $techmap

#set working directory

set psg_working_path /my_home/cmp_simulations/VCMP/working_dir_1

#Open design

open_design mask.gds

#Do Simulation

do_simulation -techmap $techmap -start_level {M1} -end_level {M7} -ignore lsf 8

#Save simulation results (extraction and prediction) into CCP database file

save_psgdb -output mask_gds_16nm.psg

#Report hotspots (Not required)

report_hotspot

Source batch script

24 © 2012 Cadence Design Systems, Inc. Cadence confidential.

(Not required) report_hotspot • Source batch script 24 © 2012 Cadence Design Systems, Inc. Cadence confidential.

Review Results

Hotspots Check

VCMP computes two (2) Hotspots

Dishing Hotspots (Called R4 hotspots in CCP)

Depth of Focus Hotspots (Called R5 Hotspots in CCP)

Thickness Variation

Note: For BEOL (back end-of line) process, dishing is the difference between

the ILD height in the space and the copper height in the trench, within the grid

of interest.

Some publications use the term step-height instead of dishing. The term step-height is more generic than dishing. It refers to the height difference between any two neighboring points.

25 © 2012 Cadence Design Systems, Inc. Cadence confidential.

to the height difference between any two neighboring points. 25 © 2012 Cadence Design Systems, Inc.

Block Robustness Analysis Flow

Goal: Run CMP Analysis During Block Implementation

It may be too late to make correction at sign-off

– It may be too late to make correction at sign-off Halo with different contexts Cadence
– It may be too late to make correction at sign-off Halo with different contexts Cadence
– It may be too late to make correction at sign-off Halo with different contexts Cadence
– It may be too late to make correction at sign-off Halo with different contexts Cadence
– It may be too late to make correction at sign-off Halo with different contexts Cadence

Halo with different contexts

Cadence CMP Predictor

Yes Adv. Hotspot Black Box Meets Detection Spec? CMP Model No Layout Optimization
Yes
Adv. Hotspot
Black Box
Meets
Detection
Spec?
CMP Model
No
Layout Optimization

Block

Detection Spec? CMP Model No Layout Optimization Block 26 © 2012 Cadence Design Systems, Inc. Cadence
Detection Spec? CMP Model No Layout Optimization Block 26 © 2012 Cadence Design Systems, Inc. Cadence

26 © 2012 Cadence Design Systems, Inc. Cadence confidential.

Detection Spec? CMP Model No Layout Optimization Block 26 © 2012 Cadence Design Systems, Inc. Cadence

CCP-QUANTUS-TEMPUS Flow

1.

2.

3.

Cadence

QUANTUS

Extraction

(CMP-Aware

Parasitic

Extraction)

QUANTUS Extraction (CMP-Aware Parasitic Extraction) Cadence CMP Predictor Adv. Hotspot Detection Thickness
QUANTUS Extraction (CMP-Aware Parasitic Extraction) Cadence CMP Predictor Adv. Hotspot Detection Thickness
Cadence CMP Predictor Adv. Hotspot Detection Thickness Results Sign-off CMP Model CCP Generated
Cadence CMP Predictor
Adv. Hotspot
Detection
Thickness
Results
Sign-off CMP Model
CCP
Generated

Erosion File

CMP-Aware RC Results

Run CCP simulation (geometry extraction and prediction) or load CCP results database for an already completed simulation

Generate Erosion File within CCP

Run QUANTUS at the corner of interest, with the CCP erosion file obtained in 3 above, and the appropriate ICT file for the corner of interest

Cadence Tempus (CMP-Aware Timing Analysis)

of interest Cadence Tempus (CMP-Aware Timing Analysis) CMP-Aware Timing Results 4. Run Timing Analysis 27 ©

CMP-Aware

Timing

Results

4.

Run Timing Analysis

27 © 2012 Cadence Design Systems, Inc. Cadence confidential.

Analysis) CMP-Aware Timing Results 4. Run Timing Analysis 27 © 2012 Cadence Design Systems, Inc. Cadence
28 © 2012 Cadence Design Systems, Inc. Cadence confidential.

28 © 2012 Cadence Design Systems, Inc. Cadence confidential.

28 © 2012 Cadence Design Systems, Inc. Cadence confidential.