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Compal Confidential
Model Name : VIUS3/S4
File Name : LA-8951PR01
1 1

BOM P/N:43

Compal Confidential
2 2

VIUS3/S4 M/B Schematics Document


Intel Ivy Bridge ULV Processor + Panther Point PCH
AMD Seymour XT

3 2011-12-28 3

REV:0.1

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


2011/06/24 2012/07/12 Title
Issued Date Deciphered Date Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Sherry and Royal
Date: Thursday, February 02, 2012 Sheet 1 of 55
A B C D E
A B C D E

Compal confidential
File Name :VIUS3/VIUS4
Chief River
AMD Seymour XT Intel DDR3-SO-DIMM X1
1 23mm *23mm PCI-E X16 IVY Bridge SV/ULV BANK 0, 1
1

VRAM 128MB*16 Gen 2 (Sandy Bridge)


gDDR3*4 UP TO 1G Processor Dual Channel
BGA1023 DDR3-1066/1333(1.5V) for Sandy Bridge
DDR3-1600(1.5V) for Ivy Bridge
SATA3.0 HDD CONN
FDI *8 DMI2 *4
100MHz 100MHz SATA3.0 HDD (SSD)
Std HDMI HDMI 1.4a 2.7GT/s 5GT/s
Connector 6*SATA
(port0,1 Support SATA3)
2 2
PX 5.0
LVDS Intel 4*USB3.0
Connector
Panther Point 14*USB2.0

PCI Express (Half) USB(WiMAX)


USB PORT 3.0 x1 (Left)
6*PCI-E x1
Mini card Slot 1 PCI-E(WLAN)
HM77/HM70
WLAN/WiMAX
USB PORT 2.0 x2 (Right)
FCBGA 989 Balls
IO Board
PCI Express (Full) 25mm*25mm
mSATA(SSD) HD Audio
Mini card Slot 2 Card Reader RTS 5178 (2in1)
IO Board
SSD Gen 2

SPI ROM LPC BUS CMOS Camera


BIOS BlueTooth CONN
3 3
4MB*1
2MB*1 EC WLAN/WiMAX
ENE KB9012
WWAN
WLAN/WiMAX LAN(10/100/Giga)
Realtek 2Channel Speaker
8105E-VD (10/100)
8111F-VL (Giga)
Int.KBD
Audio Codec Single Digital MIC
Touch Pad RealTek
RJ45 CONN ALC259-VC2
Audio Combo Jack
Sub-borad (APPLE type)
Thermal Sensor HeadPhone Output
4 Microphone Input 4
POWER BOARD EMC1403
IO Board

LED BOARD
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/07/21 Deciphered Date 2012/12/31 Title

IO Board THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MB Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 02, 2012 Sheet 2 of 55
A B C D E
A B C D E

SIGNAL
Voltage Rails STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

Full ON HIGH HIGH HIGH HIGH ON ON ON ON

+5VS S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW


+3VS
power S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
plane +1.5VS
1
+1.05VS_VTT S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF 1

+5VALW +1.5V +CPU_CORE


S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+B +VGA_CORE
+3VALW +1.5V_IO +VCC_GFXCORE_AXG
+1.8VS BOARD ID Table Board ID / SKU ID Table for AD channel
State +0.75VS Vcc 3.3V +/- 5%
Board ID PCB Revision
Ra/Rc/Re 100K +/- 5%
0 0.1 Board ID Porject Phase
Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
1 G-series
0 0 0 V 0 V 0 V MP
2 G-series
1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V PVT
3 G-series
2 18K +/- 5% 0.436 V 0.503 V 0.538 V DVT
4 G-series
3 33K +/- 5% 0.712 V 0.819 V 0.875 V EVT
S0
5 Y-series
O O O O 4 56K +/- 5% 1.036 V 1.185 V 1.264 V EVT
6 Y-series
5 100K +/- 5% 1.453 V 1.650 V 1.759 V DVT
7 Y-series
6 200K +/- 5% 1.935 V 2.200 V 2.341 V PVT
S3 Y-series
O O O X 7 NC 2.500 V 3.300 V 3.300 V MP
2 2

S5 S4/AC
O O X X USB Port Table BOM Structure Table
S5 S4/ Battery only
3 External BTO Item BOM Structure
O X X X USB 3.0 USB 2.0 Port USB Port INTEL UMA only UMA@
S5 S4/AC & Battery
xHCI1 0 GPU:Seymour XT PX@ PX5@
X X X X UHCI0
don't exist xHCI2 1 USB 3.0 Port (Left Side) HDMI HDMI@
Address xHCI3 2 Mini Card(WLAN) HDD1 (HM77 SATA 3.0) HDD1@
EC SM Bus1 address EC SM Bus2 address UHCI1
xHCI4 3 HDD2 (HM70 SATA 2.0) HDD2@
EHCI1
4 X (USB PORT disabled on HM70 ) Interna-Intel-USB3.0 IU3@
Device Device Address UHCI2
Smart Battery 0001 011X b Thermal Sensor F75303M 1001_101xb
5 X (USB PORT disabled on HM70 ) Interna-Intel-USB2.0 IU2@
6 X (USB PORT disabled on HM70 ) Blue Tooth BT@
UHCI3
7 X (USB PORT disabled on HM70 ) 10/100 LAN 8105E@
PCH SM Bus address 8 USB/B (Right Side USB-BD) GIGA LAN 8111F@
UHCI4
9 USB/B (Right Side USB-BD) Connector ME@
Device Address
DDR DIMM0
10 USB Port (Right Side CR-BD) 45 LEVEL 45@
1001 000Xb EHCI2 UHCI5
DDR DIMM2 1001 010Xb
11 Camera (LVDS) Unpop @
3 3
12 X (USB PORT disabled on HM70 )
UHCI6
13 X (USB PORT disabled on HM70 )
AMD-GPU SM Bus address
HM70 Disable xHCI3,xHCI4
Device Address

Internal thermal sensor 1001 111Xb (0x9E)


SATA Port Table PCIe Port Table
SMBUS Control Table SATA
HM77 HM70
P0 GEN3/2/1 GEN3/2/1 SSD PCIe P1
HM77
Enable
HM70
Enable LAN
Thermal SATA P1 GEN3/2/1 Disable HDD (HM77) PCIe P2 Enable Enable WLAN
WLAN Sensor
SOURCE VGA BATT KB9012 SODIMM WWAN PCH SATA P2 GEN2/1 GEN2/1 HDD (HM70) PCIe P3 Enable Enable
SATA P3 GEN2/1 Disable PCIe P4 Enable Enable
SMB_EC_CK1
SMB_EC_DA1
KB9012
+3VALW
X V
+3VALW
X X X X X SATA P4 GEN2/1 GEN2/1 PCIe P5 Enable Disable
SATA P5 GEN2/1 GEN2/1 PCIe P6 Enable Disable
SMB_EC_CK2
SMB_EC_DA2
KB9012
+3VALW
X X X X X X V
+3VS HM70 Disable P1,P3
PCIe P7 Enable Disable
PCIe P8 Enable Disable
SMBCLK
X X X V V X X
4 4

PCH
SMBDATA +3VALW +3VS +3VS HM70 Disable P5,P6,P7,P8
SML0CLK
SML0DATA
PCH
+3VALW
X X X X X X X
Compal Electronics, Inc.
V X V X X V X
Compal Secret Data
SML1CLK
Security Classification
PCH Issued Date 2011/06/15 2012/07/11 Title
SML1DATA +3VS +3VS +3VS
Deciphered Date
+3VALW THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7981P
Date: Friday, February 03, 2012 Sheet 3 of 55
A B C D E
5 4 3 2 1

Without BACO option :


Power-Up/Down Sequence PXS_RST# : Low -> Reset dGPU ; High ->Normal operation
1. All the ASIC supplies must fully reach their respective nominal voltages within 20 ms of the start of the ramp-up PXS_PWREN : Low -> dGPU Power OFF ; High -> dGPU Power ON
sequence, though a shorter ramp-up duration is preferred.
BACO option :
D D
2. VDDR3 should ramp-up before or simultaneously with VDDC. PXS_RST# : High ->Normal operation (dGPU is not reset on BACO mode)
PXS_PWREN : Low -> dGPU Power OFF ; High -> dGPU Power ON (always High)
3. For LVDS, DPx_VDD10 should ramp-up before DPx_VDD18 and the PCIe Reference clock should begin before
DPx_VDD18. For power-down, DPx_VDD18 should ramp-down before DPx_VDD10. dGPU Power Pins Voltage PX 3.0 BACO Mode Max current
4. The external pull-ups on the DDC/AUX signals (if applicable) should ramp-up before or after both VDDC and PCIE_PVDD, PCIE_VDDR, TSVDD, VDDR4, VDD_CT, 1.8V OFF ON 1679mA
VDD_CT have ramped up. DPE_PVDD, DP[F:E]_VDD18, DP[D:A]_PVDD,
DP[D:A]_VDD18, AVDD, VDD1DI, A2VDDQ, VDD2DI,
5.VDDC and VDD_CT should not ramp-up simultaneously. (e.g., VDDC should reach 90% before VDD_CT starts to
DPLL_PVDD, MPV18, and SPV18
ramp-up (or vice versa).)
DP[F:E]_VDD10, DP[D:A]_VDD10, DPLL_VDDC, and 1.0V OFF ON 575mA
SPV10
PCIE_VDDC 1.0V OFF ON 2A
VDDR3(3.3VGS) Note: Do not drive any IOs before VDDR3 is ramped up.
VDDR3 , and A2VDD 3.3V OFF ON 190mA
BIF_VDDC (current consumption = 55mA@1.0V, in Same as OFF ON 70mA
PCIE_VDDC(1.0V) BACO mode) VDDC Same as
PCIE_VDDC
BIF_VDDC=VGA_CORE When GPU enable
BIF_VDDC=1.0V When BACO
VDDR1(1.5VGS) VDDR1 1.5V OFF OFF 2.8A
VDDC/VDDCI 1.12V OFF OFF 12.9A
C C
VDDC/VDDCI(1.12V)

VDD_CT(1.8V)
PXS_RST# PE_EN BACO Switch
iGPU dGPU
PERSTb BIF_VDDC

PXS_PWREN

REFCLK PX_mode

+3.3VALW MOS
+3.3VGS
Straps Reset 1
+1.5V SI4800
+1.5VGS
Straps Valid +1.0V +1.0VGS
Regulator
2 3

B
Global ASIC Reset B
+B Regulator
+VGA_CORE
+1.8V +1.8VGS
T4+16clock
SI4800
5 4
PWRGOOD

CPU part PCB part


ZZZ2 ZZZ1 ZZZ3 ZZZ4
UCPU1 CPU1@ UCPU1 CPU2@ UCPU1 CPU3@ UCPU1 CPU4@ ZZZ5

Hynix Hynix Hynix Hynix


I3_3217 1.8G I5_3427 1.8G I5_2557 1.4G 977_1.4G PCB 0R LA-8951P REV0 M/B S512@ H512@ S1G@ H1G@
SA00005L510 SA00005L900 SA00004VZ00 SA00005BJ40 DA60000TO00 X7641338L01 X7641338L02 X7641338L03 X7641338L04

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA Notes List
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7981P
Date: Thursday, February 02, 2012 Sheet 4 of 55
5 4 3 2 1
A B C D E

PEG_ICOMPI and RCOMPO signals should be


shorted and routed
+1.05VS_VTT with - max length = 500 mils - typical
impedance = 43 mohms
PEG_ICOMPO signals should be routed with -

1
R249 max length = 500 mils
24.9_0402_1%
- typical impedance = 14.5 mohms
UCPU1A
W=12mil L=500mil S=15mil

2
1 G3 PEG_COMP 1
PEG_ICOMPI G1
[15] DMI_CRX_PTX_N0 M2
DMI_RX#[0]
PEG_ICOMPO
PEG_RCOMPO
G4 Layout placement: Place close to U8 (GPU)
[15] DMI_CRX_PTX_N1 P6
P1 DMI_RX#[1]
[15] DMI_CRX_PTX_N2 DMI_RX#[2]
[15] DMI_CRX_PTX_N3 P10 H22 PEG_GTX_C_HRX_N0 C259 1 2 PX@ 0.22U_0402_6.3V6K PEG_GTX_HRX_N0
DMI_RX#[3] PEG_RX#[0] J21 PEG_GTX_C_HRX_N1 C276 1 2 PX@ 0.22U_0402_6.3V6K PEG_GTX_HRX_N1
N3 PEG_RX#[1] B22 PEG_GTX_C_HRX_N2 C257 1 2 PX@ 0.22U_0402_6.3V6K PEG_GTX_HRX_N2
[15] DMI_CRX_PTX_P0 DMI_RX[0] PEG_RX#[2]
[15] DMI_CRX_PTX_P1 P7 D21 PEG_GTX_C_HRX_N3 C274 1 2 PX@ 0.22U_0402_6.3V6K PEG_GTX_HRX_N3
DMI_RX[1] PEG_RX#[3] PEG_GTX_HRX_N[0..15] [22]

DMI
[15] DMI_CRX_PTX_P2 P3 A19 PEG_GTX_C_HRX_N4 C254 1 2 PX@ 0.22U_0402_6.3V6K PEG_GTX_HRX_N4
DMI_RX[2] PEG_RX#[4] PEG_GTX_HRX_P[0..15] [22]
[15] DMI_CRX_PTX_P3 P11 D17 PEG_GTX_C_HRX_N5 C272 1 2 PX@ 0.22U_0402_6.3V6K PEG_GTX_HRX_N5
DMI_RX[3] PEG_RX#[5] B14 PEG_GTX_C_HRX_N6 C252 1 2 PX@ 0.22U_0402_6.3V6K PEG_GTX_HRX_N6
PEG_RX#[6] PEG_HTX_C_GRX_N[0..15] [22]
K1 D13 PEG_GTX_C_HRX_N7 C270 1 2 PX@ 0.22U_0402_6.3V6K PEG_GTX_HRX_N7
[15] DMI_CTX_PRX_N0 DMI_TX#[0] PEG_RX#[7] PEG_HTX_C_GRX_P[0..15] [22]
M8 A11 PEG_GTX_C_HRX_N8 C250 1 2 PX@ 0.22U_0402_6.3V6K PEG_GTX_HRX_N8
[15] DMI_CTX_PRX_N1 DMI_TX#[1] PEG_RX#[8]
N4 B10 PEG_GTX_C_HRX_N9 C268 1 2 PX@ 0.22U_0402_6.3V6K PEG_GTX_HRX_N9
[15] DMI_CTX_PRX_N2 DMI_TX#[2] PEG_RX#[9]
R2 G8 PEG_GTX_C_HRX_N10 C248 1 2 PX@ 0.22U_0402_6.3V6K PEG_GTX_HRX_N10
[15] DMI_CTX_PRX_N3 DMI_TX#[3] PEG_RX#[10] A8 PEG_GTX_C_HRX_N11 C267 1 2 PX@ 0.22U_0402_6.3V6K PEG_GTX_HRX_N11
K3 PEG_RX#[11] B6 PEG_GTX_C_HRX_N12 C246 1 2 PX@ 0.22U_0402_6.3V6K PEG_GTX_HRX_N12
[15] DMI_CTX_PRX_P0 DMI_TX[0] PEG_RX#[12]
M7 H8 PEG_GTX_C_HRX_N13 C264 1 2 PX@ 0.22U_0402_6.3V6K PEG_GTX_HRX_N13
[15] DMI_CTX_PRX_P1 DMI_TX[1] PEG_RX#[13]
P4 E5 PEG_GTX_C_HRX_N14 C244 1 2 PX@ 0.22U_0402_6.3V6K PEG_GTX_HRX_N14
[15] DMI_CTX_PRX_P2 DMI_TX[2] PEG_RX#[14]
T3 K7 PEG_GTX_C_HRX_N15 C262 1 2 PX@ 0.22U_0402_6.3V6K PEG_GTX_HRX_N15
[15] DMI_CTX_PRX_P3 DMI_TX[3] PEG_RX#[15]
K22 PEG_GTX_C_HRX_P0 C258 1 2 PX@ 0.22U_0402_6.3V6K PEG_GTX_HRX_P0
PEG_RX[0] K19 PEG_GTX_C_HRX_P1 C277 1 2 PX@ 0.22U_0402_6.3V6K PEG_GTX_HRX_P1
PEG_RX[1] C21 PEG_GTX_C_HRX_P2 C256 1 2 PX@ 0.22U_0402_6.3V6K PEG_GTX_HRX_P2
U7 PEG_RX[2] D19 PEG_GTX_C_HRX_P3 C275 1 2 PX@ 0.22U_0402_6.3V6K PEG_GTX_HRX_P3
[15] FDI_CTX_PRX_N0 FDI0_TX#[0] PEG_RX[3]
W11 C19 PEG_GTX_C_HRX_P4 C255 1 2 PX@ 0.22U_0402_6.3V6K PEG_GTX_HRX_P4
[15] FDI_CTX_PRX_N1 FDI0_TX#[1] PEG_RX[4]
W1 D16 PEG_GTX_C_HRX_P5 C273 1 2 PX@ 0.22U_0402_6.3V6K PEG_GTX_HRX_P5
[15] FDI_CTX_PRX_N2 FDI0_TX#[2] PEG_RX[5]
AA6 C13 PEG_GTX_C_HRX_P6 C253 1 2 PX@ 0.22U_0402_6.3V6K PEG_GTX_HRX_P6
[15] FDI_CTX_PRX_N3 FDI0_TX#[3] PEG_RX[6]
2 W6 D12 PEG_GTX_C_HRX_P7 C271 1 2 PX@ 0.22U_0402_6.3V6K PEG_GTX_HRX_P7 2
[15] FDI_CTX_PRX_N4 FDI1_TX#[0] PEG_RX[7]
V4 C11 PEG_GTX_C_HRX_P8 C251 1 2 PX@ 0.22U_0402_6.3V6K PEG_GTX_HRX_P8

PCI EXPRESS -- GRAPHICS


[15] FDI_CTX_PRX_N5 FDI1_TX#[1] PEG_RX[8]
Y2 C9 PEG_GTX_C_HRX_P9 C269 1 2 PX@ 0.22U_0402_6.3V6K PEG_GTX_HRX_P9
[15] FDI_CTX_PRX_N6 FDI1_TX#[2] PEG_RX[9]
AC9 F8 PEG_GTX_C_HRX_P10 C249 1 2 PX@ 0.22U_0402_6.3V6K PEG_GTX_HRX_P10
[15] FDI_CTX_PRX_N7 FDI1_TX#[3] PEG_RX[10]

Intel(R) FDI
C8 PEG_GTX_C_HRX_P11 C266 1 2 PX@ 0.22U_0402_6.3V6K PEG_GTX_HRX_P11
PEG_RX[11] C5 PEG_GTX_C_HRX_P12 C247 1 2 PX@ 0.22U_0402_6.3V6K PEG_GTX_HRX_P12
U6 PEG_RX[12] H6 PEG_GTX_C_HRX_P13 C265 1 2 PX@ 0.22U_0402_6.3V6K PEG_GTX_HRX_P13
[15] FDI_CTX_PRX_P0 FDI0_TX[0] PEG_RX[13]
W10 F6 PEG_GTX_C_HRX_P14 C245 1 2 PX@ 0.22U_0402_6.3V6K PEG_GTX_HRX_P14
[15] FDI_CTX_PRX_P1 FDI0_TX[1] PEG_RX[14]
W3 K6 PEG_GTX_C_HRX_P15 C263 1 2 PX@ 0.22U_0402_6.3V6K PEG_GTX_HRX_P15
[15] FDI_CTX_PRX_P2 FDI0_TX[2] PEG_RX[15]
AA7
[15] FDI_CTX_PRX_P3 FDI0_TX[3]
W7 G22 PEG_HTX_GRX_N0 C562 1 2 PX@ 0.22U_0402_6.3V6K PEG_HTX_C_GRX_N0
[15] FDI_CTX_PRX_P4 FDI1_TX[0] PEG_TX#[0]
T4 C23 PEG_HTX_GRX_N1 C582 1 2 PX@ 0.22U_0402_6.3V6K PEG_HTX_C_GRX_N1
[15] FDI_CTX_PRX_P5 FDI1_TX[1] PEG_TX#[1]
AA3 D23 PEG_HTX_GRX_N2 C564 1 2 PX@ 0.22U_0402_6.3V6K PEG_HTX_C_GRX_N2
[15] FDI_CTX_PRX_P6 FDI1_TX[2] PEG_TX#[2]
AC8 F21 PEG_HTX_GRX_N3 C584 1 2 PX@ 0.22U_0402_6.3V6K PEG_HTX_C_GRX_N3
[15] FDI_CTX_PRX_P7 FDI1_TX[3] PEG_TX#[3] H19 PEG_HTX_GRX_N4 C566 1 2 PX@ 0.22U_0402_6.3V6K PEG_HTX_C_GRX_N4
+1.05VS_VTT AA11 PEG_TX#[4] C17 PEG_HTX_GRX_N5 C587 1 2 PX@ 0.22U_0402_6.3V6K PEG_HTX_C_GRX_N5
[15] FDI_FSYNC0 FDI0_FSYNC PEG_TX#[5]
eDP_COMPIO and ICOMPO signals [15] FDI_FSYNC1 AC12 K15 PEG_HTX_GRX_N6 C568 1 2 PX@ 0.22U_0402_6.3V6K PEG_HTX_C_GRX_N6
FDI1_FSYNC PEG_TX#[6] F17 PEG_HTX_GRX_N7 C589 1 2 PX@ 0.22U_0402_6.3V6K PEG_HTX_C_GRX_N7
should be shorted near balls and U11 PEG_TX#[7] F14 PEG_HTX_GRX_N8 C570 1 2 PX@ 0.22U_0402_6.3V6K PEG_HTX_C_GRX_N8
[15] FDI_INT FDI_INT PEG_TX#[8]
routed with typical impedance PEG_TX#[9]
A15 PEG_HTX_GRX_N9 C591 1 2 PX@ 0.22U_0402_6.3V6K PEG_HTX_C_GRX_N9
1

AA10 J14 PEG_HTX_GRX_N10 C572 1 2 PX@ 0.22U_0402_6.3V6K PEG_HTX_C_GRX_N10


<25 mohms R247
[15] FDI_LSYNC0
AG8 FDI0_LSYNC PEG_TX#[10] H13 PEG_HTX_GRX_N11 C593 1 2 PX@ 0.22U_0402_6.3V6K PEG_HTX_C_GRX_N11
[15] FDI_LSYNC1 FDI1_LSYNC PEG_TX#[11]
can't be left floating 24.9_0402_1% M10 PEG_HTX_GRX_N12 C574 1 2 PX@ 0.22U_0402_6.3V6K PEG_HTX_C_GRX_N12
PEG_TX#[12] F10 PEG_HTX_GRX_N13 C594 1 2 PX@ 0.22U_0402_6.3V6K PEG_HTX_C_GRX_N13
,even if disable eDP function... PEG_TX#[13] D9 PEG_HTX_GRX_N14 C576 1 2 PX@ 0.22U_0402_6.3V6K PEG_HTX_C_GRX_N14
W=12mil L=500mil S=15mil
2

PEG_TX#[14] J4 PEG_HTX_GRX_N15 C597 1 2 PX@ 0.22U_0402_6.3V6K PEG_HTX_C_GRX_N15


EDP_COMP AF3 PEG_TX#[15]
AD2 eDP_COMPIO F22 PEG_HTX_GRX_P0 C561 1 2 PX@ 0.22U_0402_6.3V6K PEG_HTX_C_GRX_P0
AG11 eDP_ICOMPO PEG_TX[0] A23 PEG_HTX_GRX_P1 C583 1 2 PX@ 0.22U_0402_6.3V6K PEG_HTX_C_GRX_P1
3 eDP_HPD# PEG_TX[1] D24 PEG_HTX_GRX_P2 C563 1 2 PX@ 0.22U_0402_6.3V6K PEG_HTX_C_GRX_P2 3
PEG_TX[2] E21 PEG_HTX_GRX_P3 C585 1 2 PX@ 0.22U_0402_6.3V6K PEG_HTX_C_GRX_P3
AG4 PEG_TX[3] G19 PEG_HTX_GRX_P4 C565 1 2 PX@ 0.22U_0402_6.3V6K PEG_HTX_C_GRX_P4
AF4 eDP_AUX# PEG_TX[4] B18 PEG_HTX_GRX_P5 C586 1 2 PX@ 0.22U_0402_6.3V6K PEG_HTX_C_GRX_P5
eDP_AUX PEG_TX[5] K17 PEG_HTX_GRX_P6 C567 1 2 PX@ 0.22U_0402_6.3V6K PEG_HTX_C_GRX_P6
PEG_TX[6]
eDP
G17 PEG_HTX_GRX_P7 C588 1 2 PX@ 0.22U_0402_6.3V6K PEG_HTX_C_GRX_P7
AC3 PEG_TX[7] E14 PEG_HTX_GRX_P8 C569 1 2 PX@ 0.22U_0402_6.3V6K PEG_HTX_C_GRX_P8
AC4 eDP_TX#[0] PEG_TX[8] C15 PEG_HTX_GRX_P9 C590 1 2 PX@ 0.22U_0402_6.3V6K PEG_HTX_C_GRX_P9
AE11 eDP_TX#[1] PEG_TX[9] K13 PEG_HTX_GRX_P10 C571 1 2 PX@ 0.22U_0402_6.3V6K PEG_HTX_C_GRX_P10
AE7 eDP_TX#[2] PEG_TX[10] G13 PEG_HTX_GRX_P11 C592 1 2 PX@ 0.22U_0402_6.3V6K PEG_HTX_C_GRX_P11
eDP_TX#[3] PEG_TX[11] K10 PEG_HTX_GRX_P12 C573 1 2 PX@ 0.22U_0402_6.3V6K PEG_HTX_C_GRX_P12
AC1 PEG_TX[12] G10 PEG_HTX_GRX_P13 C595 1 2 PX@ 0.22U_0402_6.3V6K PEG_HTX_C_GRX_P13
AA4 eDP_TX[0] PEG_TX[13] D8 PEG_HTX_GRX_P14 C575 1 2 PX@ 0.22U_0402_6.3V6K PEG_HTX_C_GRX_P14
AE10 eDP_TX[1] PEG_TX[14] K4 PEG_HTX_GRX_P15 C596 1 2 PX@ 0.22U_0402_6.3V6K PEG_HTX_C_GRX_P15
AE6 eDP_TX[2] PEG_TX[15]
eDP_TX[3]

IVY-BRIDGE_BGA1023
@
Typ- suggest 220nF. The change in AC capacitor
value from 100nF to 220nF is to enable
compatibility with future platforms having PCIE
Gen3 (8GT/s)

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


2011/06/24 2012/07/12 Title
Issued Date Deciphered Date PROCESSOR(1/7) DMI,FDI,PEG
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Sherry and Royal
Date: Thursday, February 02, 2012 Sheet 5 of 55
A B C D E
A B C D E

+1.05VS_VTT

CLK_CPU_DPLL# R517 2 1 1K_0402_5%

CLK_CPU_DPLL R516 2 1 1K_0402_5%

Checklist1.5 P.67 Graphis Disable Guide


DIS only SKU eDP disable
DPLL_REF_SSCLK PD 1K_5% to GND
DPLL_REF_SSCLK# PH 1K_5% to +1.05VS_VTT
1 1
UCPU1B
PROC_SELECT# J3


PCH->CPU PH VCPLL and connect to PCH DF_TVS BCLK H2 CLK_CPU_DMI [14]
UNCOREPWRGOOD: CORE OK BCLK# CLK_CPU_DMI# [14]

MISC

CLOCKS
F49


SM_DRAMPWROK:DRAM power ok [17] H_SNB_IVB# PROC_SELECT# AG3 CLK_CPU_DPLL
RESET#: ok CPU reset DPLL_REF_CLK AG1 CLK_CPU_DPLL#

CPU
C57 DPLL_REF_CLK#
PROC_DETECT#
SM_RCOMP0,SM_RCOMP1
Follow DG 1.5& Tacoma_Fall2 1.0 W=20mil L=500mil S=13mil
reserve XBOX T33 PAD @ H_CATERR# C49
CATERR# SM_RCOMP2
W=15mil L=500mil S=13mil

THERMAL
@
C614 2 1 0.1U_0402_16V4Z H_CPUPWRGD_R
follow Checklist 1.5 H_PECI A48 AT30 SM_DRAMRST#
[18,37] H_PECI PECI SM_DRAMRST# SM_DRAMRST# [7]
R292 2 1 10K_0402_5% +1.05VS_VTT R534 2 1 62_0402_5% R533 1
56_0402_5% BF44 SM_RCOMP0 R272 2 1 140_0402_1% @ C82
SM_RCOMP[0]

DDR3
MISC
[37,42] H_PROCHOT# H_PROCHOT# 1 2 H_PROCHOT#_R C45 BE43 SM_RCOMP1 R273 2 1 25.5_0402_1%
PROCHOT# SM_RCOMP[1] BG43 SM_RCOMP2 R267 2 1 200_0402_1% 100P_0402_50V8J
SM_RCOMP[2] 2
DDR3 Compensation Signals
D45
[18] H_THERMTRIP# THERMTRIP#

N53
PRDY# N55
PREQ# ESD
TCK
L56
L55
XDP_TCK C Reserve
XDP_TMS
TMS

PWR MANAGEMENT
J58 XDP_TRST#
TRST#

JTAG & BPM


2 C48 M60 XDP_TDI 2
[15] H_PM_SYNC

COREOK
PM_SYNC TDI L59 XDP_TDO
TDO
UNCOREPWRGOOD:
PU/PD for JTAG signals +1.05VS_VTT
[18] H_CPUPWRGD
1 2 H_CPUPWRGD_R B46
R305 0_0402_5% UNCOREPWRGOOD K58 XDP_DBRESET#
DBR#
R237 XDP_TMS R20 2 1 51_0402_5%
1 2 VDDPWRGOOD_R BE45 G58 XDP_TDI R39 2 1 51_0402_5%
130_0402_1% SM_DRAMPWROK BPM#[0] E55 XDP_TDO R37 2 1 51_0402_5%
BPM#[1] E59 @
SM_DRAMPWROK:DRAM power ok BPM#[2] G55 XDP_TCK 2 1 51_0402_5%
R40
BPM#[3] G59 +3VS XDP_TRST# R28 2 1 51_0402_5%
BUF_CPU_RST# D44 BPM#[4] H60
RESET# BPM#[5] J59 XDP_DBRESET# R312 2 1 1K_0402_5%
BPM#[6] J61
BPM#[7]
Tacoma_Fall2 1.0 PH 1K +3VS
Check list 1.5 PH 1K +3VS
Debug port DG1.1-1.3 50~5K ohm

IVY-BRIDGE_BGA1023
@

+3VALW
Buffered reset to CPU

+3VS +1.5V_CPU_VDDQ
1

3 C228 +3VS 3
1

0.1U_0402_16V4Z
R31
10K_0402_5% R238
2

1 2 200_0402_5%
U22 +1.05VS_VTT

1
@ C617
R35
2
5

10K_0402_5% 0.1U_0402_16V4Z

1
1 2 1
P

[15] SYS_PWROK

2
B 4PM_SYS_PWRGD_BUF R546
2 O 75_0402_5%
[15] PM_DRAM_PWRGD A
G

5
74AHC1G09GW_TSSOP5 R544 U45
3

2
43_0402_5% 1

P
@ R38 BUF_CPU_RST# 1 2 BUFO_CPU_RST# 4 NC
39_0402_5% Y 2PCH_PLTRST#
A PCH_PLTRST# [17]

G
SN74LVC1G07DCKR_SC70-5
1 2

C43

3
0.1U_0402_16V4Z
D @
2

[10] RUN_ON_CPU1.5VS3# RUN_ON_CPU1.5VS3# 2


G
Q4 S
2N7002K_SOT23-3
3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


2011/06/24 2012/07/12 Title
Issued Date Deciphered Date PROCESSOR(3/7) DDRIII
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Sherry and Royal
Date: Thursday, February 02, 2012 Sheet 6 of 55
A B C D E
A B C D E

UCPU1C UCPU1D
[12] DDR_A_D[0..63]
DDR_A_D0 AG6 AL4
DDR_A_D1 AJ6 SA_DQ[0] AU36 AL1 SB_DQ[0] BA34
DDR_A_D2 AP11 SA_DQ[1] SA_CK[0] AV36 SA_CLK_DDR0 [12] AN3 SB_DQ[1] SB_CK[0] AY34
DDR_A_D3 AL6 SA_DQ[2] SA_CK#[0] AY26 SA_CLK_DDR#0 [12] AR4 SB_DQ[2] SB_CK#[0] AR22
AJ10 SA_DQ[3] SA_CKE[0] DDRA_CKE0_DIMMA [12] AK4 SB_DQ[3] SB_CKE[0]
DDR_A_D4
1 DDR_A_D5 AJ8 SA_DQ[4] AK3 SB_DQ[4] 1
DDR_A_D6 AL8 SA_DQ[5] AN4 SB_DQ[5]
DDR_A_D7 AL7 SA_DQ[6] AR1 SB_DQ[6]
DDR_A_D8 AR11 SA_DQ[7] AU4 SB_DQ[7]
DDR_A_D9 AP6 SA_DQ[8] AT40 AT2 SB_DQ[8] BA36
AU6 SA_DQ[9] SA_CK[1] AU40 SA_CLK_DDR1 [12] AV4 SB_DQ[9] SB_CK[1] BB36
DDR_A_D10
DDR_A_D11 AV9 SA_DQ[10] SA_CK#[1] BB26 SA_CLK_DDR#1 [12] BA4 SB_DQ[10] SB_CK#[1] BF27
DDR_A_D12 AR6 SA_DQ[11] SA_CKE[1] DDRA_CKE1_DIMMA [12] AU3 SB_DQ[11] SB_CKE[1]
DDR_A_D13 AP8 SA_DQ[12] AR3 SB_DQ[12]
DDR_A_D14 AT13 SA_DQ[13] AY2 SB_DQ[13]
DDR_A_D15 AU13 SA_DQ[14] BA3 SB_DQ[14]
DDR_A_D16 BC7 SA_DQ[15] BE9 SB_DQ[15]
DDR_A_D17 BB7 SA_DQ[16] BB40 BD9 SB_DQ[16] BE41
BA13 SA_DQ[17] SA_CS#[0] BC41 DDRA_CS0_DIMMA# [12] BD13 SB_DQ[17] SB_CS#[0] BE47
DDR_A_D18
DDR_A_D19 BB11 SA_DQ[18] SA_CS#[1] DDRA_CS1_DIMMA# [12] BF12 SB_DQ[18] SB_CS#[1]
DDR_A_D20 BA7 SA_DQ[19] BF8 SB_DQ[19]
DDR_A_D21 BA9 SA_DQ[20] BD10 SB_DQ[20]
DDR_A_D22 BB9 SA_DQ[21] BD14 SB_DQ[21]
DDR_A_D23 AY13 SA_DQ[22] BE13 SB_DQ[22]
DDR_A_D24 AV14 SA_DQ[23] AY40 BF16 SB_DQ[23] AT43
AR14 SA_DQ[24] SA_ODT[0] BA41 SA_ODT0 [12] BE17 SB_DQ[24] SB_ODT[0] BG47
DDR_A_D25
DDR_A_D26 AY17 SA_DQ[25] SA_ODT[1] SA_ODT1 [12] BE18 SB_DQ[25] SB_ODT[1]
DDR_A_D27 AR19 SA_DQ[26] BE21 SB_DQ[26]
DDR_A_D28 BA14 SA_DQ[27] BE14 SB_DQ[27]
DDR_A_D29 AU14 SA_DQ[28] BG14 SB_DQ[28]
DDR_A_D30 BB14 SA_DQ[29] BG18 SB_DQ[29]
DDR_A_D31 BB17 SA_DQ[30] AL11 DDR_A_DQS#0 DDR_A_DQS#[0..7] [12] BF19 SB_DQ[30] AL3
DDR_A_D32 BA45 SA_DQ[31] SA_DQS#[0] AR8 DDR_A_DQS#1 BD50 SB_DQ[31] SB_DQS#[0] AV3
DDR_A_D33 AR43 SA_DQ[32] SA_DQS#[1] AV11 DDR_A_DQS#2 BF48 SB_DQ[32] SB_DQS#[1] BG11
DDR_A_D34 AW48 SA_DQ[33] SA_DQS#[2] AT17 DDR_A_DQS#3 BD53 SB_DQ[33] SB_DQS#[2] BD17
DDR_A_D35 BC48 SA_DQ[34] SA_DQS#[3] AV45 DDR_A_DQS#4 BF52 SB_DQ[34] SB_DQS#[3] BG51
DDR_A_D36 BC45 SA_DQ[35] SA_DQS#[4] AY51 DDR_A_DQS#5 BD49 SB_DQ[35] SB_DQS#[4] BA59
2 DDR_A_D37 AR45 SA_DQ[36] SA_DQS#[5] AT55 DDR_A_DQS#6 BE49 SB_DQ[36] SB_DQS#[5] AT60 2

DDR SYSTEM MEMORY A


SA_DQ[37] SA_DQS#[6] SB_DQ[37] SB_DQS#[6]

DDR SYSTEM MEMORY B


DDR_A_D38 AT48 AK55 DDR_A_DQS#7 BD54 AK59
DDR_A_D39 AY48 SA_DQ[38] SA_DQS#[7] BE53 SB_DQ[38] SB_DQS#[7]
DDR_A_D40 BA49 SA_DQ[39] BF56 SB_DQ[39]
DDR_A_D41 AV49 SA_DQ[40] BE57 SB_DQ[40]
DDR_A_D42 BB51 SA_DQ[41] BC59 SB_DQ[41]
DDR_A_D43 AY53 SA_DQ[42] AY60 SB_DQ[42]
DDR_A_D44 BB49 SA_DQ[43] BE54 SB_DQ[43]
DDR_A_D45 AU49 SA_DQ[44] AJ11 DDR_A_DQS0 DDR_A_DQS[0..7] [12] BG54 SB_DQ[44]
DDR_A_D46 BA53 SA_DQ[45] SA_DQS[0] AR10 DDR_A_DQS1 BA58 SB_DQ[45] AM2
DDR_A_D47 BB55 SA_DQ[46] SA_DQS[1] AY11 DDR_A_DQS2 AW59 SB_DQ[46] SB_DQS[0] AV1
DDR_A_D48 BA55 SA_DQ[47] SA_DQS[2] AU17 DDR_A_DQS3 AW58 SB_DQ[47] SB_DQS[1] BE11
DDR_A_D49 AV56 SA_DQ[48] SA_DQS[3] AW45 DDR_A_DQS4 AU58 SB_DQ[48] SB_DQS[2] BD18
DDR_A_D50 AP50 SA_DQ[49] SA_DQS[4] AV51 DDR_A_DQS5 AN61 SB_DQ[49] SB_DQS[3] BE51
DDR_A_D51 AP53 SA_DQ[50] SA_DQS[5] AT56 DDR_A_DQS6 AN59 SB_DQ[50] SB_DQS[4] BA61
DDR_A_D52 AV54 SA_DQ[51] SA_DQS[6] AK54 DDR_A_DQS7 AU59 SB_DQ[51] SB_DQS[5] AR59
DDR_A_D53 AT54 SA_DQ[52] SA_DQS[7] AU61 SB_DQ[52] SB_DQS[6] AK61
DDR_A_D54 AP56 SA_DQ[53] AN58 SB_DQ[53] SB_DQS[7]
DDR_A_D55 AP52 SA_DQ[54] AR58 SB_DQ[54]
DDR_A_D56 AN57 SA_DQ[55] AK58 SB_DQ[55]
DDR_A_D57 AN53 SA_DQ[56] AL58 SB_DQ[56]
DDR_A_D58 AG56 SA_DQ[57] AG58 SB_DQ[57]
DDR_A_D59 AG53 SA_DQ[58] AG59 SB_DQ[58]
DDR_A_D60 AN55 SA_DQ[59] AM60 SB_DQ[59]
DDR_A_D61 AN52 SA_DQ[60] BG35 DDR_A_MA0 DDR_A_MA[0..15] [12] AL59 SB_DQ[60] BF32
DDR_A_D62 AG55 SA_DQ[61] SA_MA[0] BB34 DDR_A_MA1 AF61 SB_DQ[61] SB_MA[0] BE33
DDR_A_D63 AK56 SA_DQ[62] SA_MA[1] BE35 DDR_A_MA2 AH60 SB_DQ[62] SB_MA[1] BD33
SA_DQ[63] SA_MA[2] BD35 DDR_A_MA3 SB_DQ[63] SB_MA[2] AU30
SA_MA[3] AT34 DDR_A_MA4 SB_MA[3] BD30
SA_MA[4] AU34 DDR_A_MA5 SB_MA[4] AV30
SA_MA[5] BB32 DDR_A_MA6 SB_MA[5] BG30
BD37 SA_MA[6] AT32 DDR_A_MA7 BG39 SB_MA[6] BD29
3 [12] DDR_A_BS0 BF36 SA_BS[0] SA_MA[7] AY32 BD42 SB_BS[0] SB_MA[7] BE30 3
DDR_A_MA8
[12] DDR_A_BS1 BA28 SA_BS[1] SA_MA[8] AV32 AT22 SB_BS[1] SB_MA[8] BE28
DDR_A_MA9
[12] DDR_A_BS2 SA_BS[2] SA_MA[9] BE37 DDR_A_MA10 SB_BS[2] SB_MA[9] BD43
SA_MA[10] BA30 DDR_A_MA11 SB_MA[10] AT28
SA_MA[11] BC30 DDR_A_MA12 SB_MA[11] AV28
BE39 SA_MA[12] AW41 DDR_A_MA13 AV43 SB_MA[12] BD46
[12] DDR_A_CAS# BD39 SA_CAS# SA_MA[13] AY28 BF40 SB_CAS# SB_MA[13] AT26
DDR_A_MA14
[12] DDR_A_RAS# AT41 SA_RAS# SA_MA[14] AU26 DDR_A_MA15 BD45 SB_RAS# SB_MA[14] AU22
[12] DDR_A_WE# SA_WE# SA_MA[15] SB_WE# SB_MA[15]

IVY-BRIDGE_BGA1023 IVY-BRIDGE_BGA1023
@ @

Follow CRB1.0 +1.5V


1

R216
0_0402_5% R212
1 2 1K_0402_5%

CPU DIMMreset @
2

3 1 1 2
S

[6] SM_DRAMRST# SM_DRAMRST# DIMM_DRAMRST#_R


DIMM_DRAMRST# [12]
Q16 R219 1K_0402_5%
2

BSS138_NL_SOT23-3
R217 S0
G
2

4.99K_0402_1%
DRAMRST_CNTRL_PCH hgih ,MOS ON
SM_DRAMRST# HIGH,DDR3 DRAMRST# HIGH
1

4 Dimm not reset 4

S3
[14] DRAMRST_CNTRL_PCH
1 2 DRAMRST_CNTRL DRAMRST_CNTRL_PCH Low ,MOS OFF
R62 0_0402_5% SM_DRAMRST# lo,DDR3 DRAMRST# HIGH
[10] DRAMRST_CNTRL Dimm not reset
1 2
[37] DRAMRST_CNTRL_EC
R64 0_0402_5%
S4,5 Security Classification Compal Secret Data Compal Electronics, Inc.
1
DS3@ C190 DRAMRST_CNTRL_PCH Low ,MOS OFF 2011/06/24 2012/07/12 Title
For DS3 0.047U_0402_16V7K SM_DRAMRST# lo,DDR3 DRAMRST# low
Issued Date Deciphered Date PROCESSOR(3/7) DDRIII
2 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Dimm reset AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Sherry and Royal
Date: Thursday, February 02, 2012 Sheet 7 of 55
A B C D E
A B C D E

CFG Straps for Processor


CFG2
UCPU1E

1
R296
T32 PAD @ CFG0 B50 N59 1K_0402_1%
C51 CFG[0] BCLK_ITP N58

2
CFG2 B54 CFG[1] BCLK_ITP#
D53 CFG[2]
+CPU_CORE CFG4 A51 CFG[3] N42
1 1
CFG5 C53 CFG[4] RSVD30 L42
CFG6 C55 CFG[5] RSVD31 L45
PEG Static Lane Reversal - CFG2 is for the 16x
CFG[6] RSVD32
2

CFG7 H49 L47 1: Normal Operation; Lane # definition matches


R302 A55 CFG[7] RSVD33
H51 CFG[8] socket pin map definition
49.9_0402_1% K49 CFG[9] M13
CFG2
K53 CFG[10] RSVD34 M14 0:Lane Reversed
*
1

VCC_VAL_SENSE F53 CFG[11] RSVD35 U14


G53 CFG[12] RSVD36 W14
L51 CFG[13] RSVD37 P13


CFG[14] RSVD38
2

F51
R91 D52 CFG[15] CFG4 UMA,Optimus eDP

100_0402_1% L53 CFG[16] AT49
CFG[17] RSVD39 DISO eDP

1
@ K24
RSVD40
1

RESERVED
VCC_VAL_SENSE H43 @ R293
VSS_VAL_SENSE VSS_VAL_SENSE K43 VCC_VAL_SENSE AH2 1K_0402_1%
VSS_VAL_SENSE RSVD41 AG13

2
RSVD42
2

AM14
R306 VAXG_VAL_SENSE H45 RSVD43 AM15
VSSAXG_VAL_SENSE K45 VAXG_VAL_SENSE RSVD44
49.9_0402_1% VSSAXG_VAL_SENSE
N50 eDP enable
1

T18 PAD @ F48 RSVD45


VCC_DIE_SENSE
1:Disable
H48
K48 RSVD6
RSVD7
CFG4 * 0:Enable
2 A4 2
DC_TEST_A4 C4
BA19 DC_TEST_C4 D3 CFG6
AV19 RSVD8 DC_TEST_D3 D1 CFG5
+VGFX_CORE AT21 RSVD9 DC_TEST_D1 A58
BB21 RSVD10 DC_TEST_A58 A59
RSVD11 DC_TEST_A59

1
BB19 C59
AY21 RSVD12 DC_TEST_C59 A61 R543 R541
RSVD13 DC_TEST_A61
2

BA22 C61 1K_0402_1% 1K_0402_1%


R310 AY22 RSVD14 DC_TEST_C61 D61 @ @
AU19 RSVD15 DC_TEST_D61 BD61
These pins are for solder joint

2
49.9_0402_1% AU21 RSVD16 DC_TEST_BD61 BE61 reliability and non-critical to
BD21 RSVD17 DC_TEST_BE61 BE59
function. For BGA only.
1

VAXG_VAL_SENSE BD22 RSVD18 DC_TEST_BE59 BG61


BD25 RSVD19 DC_TEST_BG61 BG59
BD26 RSVD20 DC_TEST_BG59 BG58
RSVD21 DC_TEST_BG58
2

BG22 BG4
R95 BE22 RSVD22 DC_TEST_BG4 BG3
100_0402_1% BG26 RSVD23 DC_TEST_BG3 BE3
BE26 RSVD24 DC_TEST_BE3 BG1
PCIE Port Bifurcation Straps
@ RSVD25 DC_TEST_BG1
BF23 BE1
1

BE24 RSVD26 DC_TEST_BE1 BD1


VSSAXG_VAL_SENSE RSVD27 DC_TEST_BD1
CFG[6:5]
*11: (Default) 1x16 PCI Express
10: 2x8 PCI Express
2

R311 01: Reserved


IVY-BRIDGE_BGA1023
49.9_0402_1% @ 00: 1x8,2x4 PCI Express
1

3 3
CFG7

1
R297
@ 1K_0402_1%

2
PEG DEFER TRAINING Tacoma_Fall2 1.0 P.12

1: (Default) PEG Train immediately following


CFG7 xxRESETB de assertion
0: PEG Wait for BIOS for training

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


2011/06/24 2012/07/12 Title
Issued Date Deciphered Date PROCESSOR(4/7) RSVD,CFG
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Sherry and Royal
Date: Thursday, February 02, 2012 Sheet 8 of 55
A B C D E
A B C D E

UCPU1F POWER 8.5A


ULV type
+1.05VS_VTT
DC 33A
AF46
+CPU_CORE VCCIO[1] AG48
VCCIO[3] AG50
VCCIO[4] For DDR
A26 AG51
A29 VCC[1] VCCIO[5] AJ17
A31 VCC[2] VCCIO[6] AJ21
A34 VCC[3] VCCIO[7] AJ25
A35 VCC[4] VCCIO[8] AJ43 INTEL Recommend VCCIO
INTEL Recommend VCC A38 VCC[5] VCCIO[9] AJ47
A39 VCC[6] VCCIO[10] AK50 2*330UF,10*10uF(0603) and 26*1uF(0402)
1
4*470UF,12*22uF(0805) and 35*2.2uF(0402) A42 VCC[7]
VCC[8]
VCCIO[11]
VCCIO[12]
AK51
1

C26
VCC[9] VCCIO[13]
AL14
PD0.8
PD0.8 C27
VCC[10] VCCIO[14]
AL15
C32
VCC[11] VCCIO[15]
AL16
CAP at Power side
CAP at Power side C34
C37 VCC[12] VCCIO[16]
AL20
AL22
C39 VCC[13] VCCIO[17] AL26
C42 VCC[14] VCCIO[18] AL45
D27 VCC[15] VCCIO[19] AL48
D32 VCC[16] VCCIO[20] AM16
D34 VCC[17] VCCIO[21] AM17
D37 VCC[18] VCCIO[22] AM21
D39 VCC[19] VCCIO[23] AM43

PEG IO AND DDR IO


D42 VCC[20] VCCIO[24] AM47
E26 VCC[21] VCCIO[25] AN20
E28 VCC[22] VCCIO[26] AN42
E32 VCC[23] VCCIO[27] AN45
E34 VCC[24] VCCIO[28] AN48
E37 VCC[25] VCCIO[29]
E38 VCC[26]
VCC[27]

CORE SUPPLY
F25
F26 VCC[28]
F28 VCC[29]
F32 VCC[30]
F34 VCC[31]
F37 VCC[32] AA14
F38 VCC[33] VCCIO[30] AA15
VCC[34] VCCIO[31] For PEG
F42 AB17
G42 VCC[35] VCCIO[32] AB20
H25 VCC[36] VCCIO[33] AC13
H26 VCC[37] VCCIO[34] AD16
H28 VCC[38] VCCIO[35] AD18
H29 VCC[39] VCCIO[36] AD21
2 H32 VCC[40] VCCIO[37] AE14 2
H34 VCC[41] VCCIO[38] AE15
H35 VCC[42] VCCIO[39] AF16
H37 VCC[43] VCCIO[40] AF18
H38 VCC[44] VCCIO[41] AF20
H40 VCC[45] VCCIO[42] AG15
J25 VCC[46] VCCIO[43] AG16
J26 VCC[47] VCCIO[44] AG17 +3VS
J28 VCC[48] VCCIO[45] AG20
J29 VCC[49] VCCIO[46] AG21
VCC[50] VCCIO[47]

1
J32 AJ14
J34 VCC[51] VCCIO[48] AJ15 R521
J35 VCC[52] VCCIO[49] 10K_0402_5%
J37 VCC[53]
J38 VCC[54]

2
J40 VCC[55] +1.05VS_VTT
J42 VCC[56]
K26 VCC[57] W16 VCCIO_SEL
K27 VCC[58] VCCIO50 W17
VCC[59] VCCIO51 VCCIO_SEL after Ivy bridge ES2 Voltage support

1
K29
K32 VCC[60] R522
K34 VCC[61] 10K_0402_5% 1/NC : (Default) +1.05VS_VTT
K35
K37
VCC[62]
VCC[63]
@ BC22 * 0: +1.0VS_VTT

2
K39 VCC[64]
K42 VCC[66] BC22 VCCIO_SEL
L25 VCC[67] VCCIO_SEL
L28 VCC[68]
L33 VCC[69]
L36 VCC[70] +1.05VS_VTT
L40 VCC[71] +1.05VS_VTT +1.05VS_VTT
N26 VCC[72]
N30 VCC[73] AM25

QUIET
RAILS

1
3 N34 VCC[74] VCCPQE[1] AN22 3
N38 VCC[75] VCCPQE[2] R531 R529
Place the PU
VCC[76] 1 2 130_0402_5% 75_0402_5% resistors close to CPU
C553
1U_0402_6.3V6K

2
A44 H_CPU_SVIDALRT# R528 1 2 43_0402_1%
VIDALERT# VR_SVID_ALRT# [50]
B43 H_CPU_SVIDCLK R527 1 2 0_0402_5%
VIDSCLK VR_SVID_CLK [50]

SVID
C44 H_CPU_SVIDDAT R530 1 2 0_0402_5%
VIDSOUT VR_SVID_DAT [50]
+CPU_CORE

Place the PU

1
resistors close to VR 1 R79 2 R281
100_0402_1%
100_0402_1%
@

2
F43 VCCSENSE_R R282 1 2 0_0402_5%
SENSE LINES VCC_SENSE VCCSENSE [50]
G43 VSSSENSE_R R289 1 2 0_0402_5%
VSS_SENSE VSSSENSE [50]

1
R513 1 2 10_0402_5% +1.05VS_VTT
R288
AN16 VCCIO_SENSE 100_0402_1%
VCCIO_SENSE VCCIO_SENSE [47]
AN17 VSSIO_SENSE_L
VSS_SENSE_VCCIO VSSIO_SENSE_L [47]

2
1
R512 Should change to connect form
10_0402_5%
power cirucit & layout differential
IVY-BRIDGE_BGA1023
4 with VCCIO_SENSE. 4

2
@
Check list 1.5

Security Classification Compal Secret Data Compal Electronics, Inc.


2011/06/24 2012/07/12 Title
Issued Date Deciphered Date PROCESSOR(5/7) PWR,BYPASS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Sherry and Royal
Date: Thursday, February 02, 2012 Sheet 9 of 55
A B C D E
A B C D E

+1.5V +1.5V_CPU_VDDQ
@ J1
1 2

PAD-OPEN 4x4m
M3 Support

1
R86 1 @ 2 0_0402_5%
1 2 R80 @ C116
[40,45,46] SUSP 0_0402_5% R65 U11 AO4430L_SO8 220_0402_5% 0.1U_0402_10V6K +VREF_DQ_DIMMA

2
8 1
7 2

2
6 3 3

D
SA_DIMM_VREFDQ 1
+3VALW +VSB 5

1
BSS138_NL_SOT23-3
D Q2204

G
4

2
1
2 RUN_ON_CPU1.5VS3#

1
R85 Q7 G DRAMRST_CNTRL_PCH
R78 82K_0402_5% 2N7002K_SOT23-3 S DRAMRST_CNTRL [7]
1 100K_0402_5% @ 1

3
R175

2
15K_0402_1%

2
RUN_ON_CPU1.5VS3 1 2
RUN_ON_CPU1.5VS3#

1
1

1
1
@ D R77 C115
R81 2 1 0_0402_5% 2 D 330K_0402_5% 0.047U_0603_25V7K

2
[37,40] CPU1.5V_S3_GATE 2
G @

2
Q6 S G Q8
1 @ 2 2N7002K_SOT23-3 S 2N7002K_SOT23-3

3
[37,40,45,46,47,49] SUSP#
0_0402_5% R82 @

3
+1.5V_CPU_VDDQ
+1.5V
RUN_ON_CPU1.5VS3# [6]

+V_SM_VREF_CNT should
POWER

1
R117 2 @ 1 0_0402_5%
UCPU1G have 20 mil trace width R113 @ R76
1K_0402_1% 1K_0402_1%

+VGFX_CORE
DC 29A

2
AY43 3

D
+V_SM_VREF_CNT 1 +V_SM_VREF
AA46 SM_VREF Q11

VREF
VAXG[1]

1
AB47 AO3414_SOT23-3
VAXG[2]

1
AB50 BE7 SA_DIMM_VREFDQ C117 @ @ R116

G
2
VAXG[3] SA_DIMM_VREFDQ

1
AB51 BG7 SB_DIMM_VREFDQ 0.1U_0402_16V4Z 1K_0402_1%
AB52 VAXG[4] SB_DIMM_VREFDQ R124
INTEL Recommend VAXG

2
AB53 VAXG[5] 1K_0402_1% RUN_ON_CPU1.5VS3

2
VAXG[6]

1
AB55
2*470uF,6*22uF(0805) and 6*10uF(0603) AB56 VAXG[7]

2
AB58 VAXG[8] R519 @ R518 @
VAXG[9]
11*1U(0402) AB59
AC61 VAXG[10]
1K_0402_1% 1K_0402_1%
SA_DIMM_VREFDQ

2
AD47 VAXG[11]
PD0.8 AD48 VAXG[12]
VAXG[13]
5A SB_DIMM_VREFDQ
AD50
AD51 VAXG[14] AJ28
Check list1.5 P18 M1 default M3 no stuff

- 1.5V RAILS
AD52 VAXG[15] VDDQ[1] AJ33
AD53 VAXG[16] VDDQ[2] AJ36
2 AD55 VAXG[17] VDDQ[3] AJ40 +1.5V_CPU_VDDQ 2
AD56 VAXG[18] VDDQ[4] AL30
Place TOP IN BGA INTEL Recommend VDDQ
AD58 VAXG[19] VDDQ[5] AL34
AD59 VAXG[20]
VAXG[21]
VDDQ[6]
VDDQ[7]
AL38 C321 C329 C351 C348 C328 C312 C318 C320 C349 C316 1*330uF,8*10uF(0603) ,10*1uF(0402)

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
AE46 AL42 1
VAXG[22] VDDQ[8]
N45
VAXG[23] VDDQ[9]
AM33
PD0.8

1
P47 AM36 + C286
P48 VAXG[24] VDDQ[10] AM40 330U_D2_2V_Y
P50 VAXG[25] VDDQ[11] AN30

2
P51 VAXG[26] VDDQ[12] AN34 2
P52 VAXG[27] VDDQ[13] AN38
P53 VAXG[28] VDDQ[14] AR26 @ @ @ @ @ @ @ @ @ @

DDR3
P55 VAXG[29] VDDQ[15] AR28

GRAPHICS
P56 VAXG[30] VDDQ[16] AR30
P61 VAXG[31] VDDQ[17] AR32
Place BOT OUT BGA
T48 VAXG[32] VDDQ[18] AR34
T58 VAXG[33] VDDQ[19] AR36
T59 VAXG[34] VDDQ[20] AR40 C340 C337 C338 C296 C295 C299 C339 C298
VAXG[35] VDDQ[21]

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
T61 AV41 SGA20331E10 S POLY C 330U
VAXG[36] VDDQ[22]

1
U46 AW26
V47 VAXG[37] VDDQ[23] BA40 2V Y D2 LESR9M EEFSX H1.9
V48 VAXG[38] VDDQ[24] BB28

2
V50 VAXG[39] VDDQ[25] BG33
V51 VAXG[40] VDDQ[26]
V52 VAXG[41]
V53 VAXG[42]
V55 VAXG[43]
V56 VAXG[44]
V58 VAXG[45]
V59 VAXG[46]
W50 VAXG[47]
W51 VAXG[48]
W52 VAXG[49]
CR CheckList Rev1.5 W53 VAXG[50]
W55 VAXG[51]
W56 VAXG[52]
W61 VAXG[53]
+VGFX_CORE Y48 VAXG[54]
INTEL Recommend VCCPLL Y61 VAXG[55]
VAXG[56]
1

3
1*330uF,2*1uF(0402) R308
1 R87 2 3

PD0.8 100_0402_5%
100_0402_1%
+1.5V_CPU_VDDQ
2

QUIET RAILS

AM28 +1.5V_CPU_VDDQ +1.5V


SENSE
LINES

@ VCCDQ[1]
F45 AN26
[50] VCC_AXG_SENSE G45 VAXG_SENSE VCCDQ[2]
[50] VSS_AXG_SENSE VSSAXG_SENSE

1
C150 2 1 0.1U_0402_10V7K
1

C317
R309 1U_0402_6.3V6K

2
C151 2 1 0.1U_0402_10V7K
100_0402_5% 1.2A
1.8V RAIL
2

+1.8VS BB3 C152 2 1 0.1U_0402_10V7K


Place BOT OUT Conn BC1 VCCPLL[1]
BC4 VCCPLL[2]
VCCPLL[3] C157 2 1 0.1U_0402_10V7K
22U_0805_6.3V6M

C633
10U_0603_6.3V6M

C153

1U_0402_6.3V6K
C281

1U_0402_6.3V6K
C280

1 1
1

BC43
VDDQ_SENSE BA43
2

VSS_SENSE_VDDQ
SENSE LINES

2 2
6A L17
L21 VCCSA[1]
N16 VCCSA[2]
N20 VCCSA[3]
N22 VCCSA[4]
SA RAIL

P17 VCCSA[5]
+VCCSA P20 VCCSA[6] U10
VCCSA ULV
Place TOP IN BGA R16 VCCSA[7] VCCSA_SENSE +VCCSA_SENSE [48]
+VCCSA R18 VCCSA[8] CPU EDS1.3 P.93 VID0 VID1 Vout HR CR
VCCSA[9] VCCSA_VID0 Must PD
1

R21 0 0 0.9V V V
C309 C302 C300 C301 C308 U15 VCCSA[10]
VCCSA VID

1 VCCSA[11]
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

V16 @ R248 0 1 0.85V V V


VCCSA[12]
1

+ C242 V17 D48 0_0402_5%


VCCSA[13] VCCSA_VID[0]
lines

330U_D2_2V_Y V18 D49 1 0 0.775V X V


2

V21 VCCSA[14] VCCSA_VID[1]


SGA20331E10 S POLY C 330U
2

2 W20 VCCSA[15]
2V Y D2 LESR9M EEFSX H1.9 VCCSA[16] 1 1 0.75V X V
@
B phase Cost down proposal H_VCCSA_VID0
@ @ @ @ @
4
H_VCCSA_VID1 H_VCCSA_VID0 [48] 4
IVY-BRIDGE_BGA1023
H_VCCSA_VID1 [48]
Place BOT OUT BGA @

INTEL Recommend VCCSA C577 C560 C555 C579 C559


10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1*330uF,5*10uF(0603) ,5*1uF(0402)
1

PD0.8
2

Security Classification Compal Secret Data Compal Electronics, Inc.


2011/06/24 2012/07/12 Title
Issued Date Deciphered Date PROCESSOR(6/7) PWR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size
R&D Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Sherry and Royal
Date: Thursday, February 02, 2012 Sheet 10 of 55
A B C D E
A B C D E

UCPU1H

UCPU1I

A13 AM38
A17 VSS[1] VSS[91] AM4
A21 VSS[2] VSS[92] AM42 BG17 M4
A25 VSS[3] VSS[93] AM45 BG21 VSS[181] VSS[250] M58
A28 VSS[4] VSS[94] AM48 BG24 VSS[182] VSS[251] M6
A33 VSS[5] VSS[95] AM58 BG28 VSS[183] VSS[252] N1
A37 VSS[6] VSS[96] AN1 BG37 VSS[184] VSS[253] N17
1 1
A40 VSS[7] VSS[97] AN21 BG41 VSS[185] VSS[254] N21
A45 VSS[8] VSS[98] AN25 BG45 VSS[186] VSS[255] N25
A49 VSS[9] VSS[99] AN28 BG49 VSS[187] VSS[256] N28
A53 VSS[10] VSS[100] AN33 BG53 VSS[188] VSS[257] N33
A9 VSS[11] VSS[101] AN36 BG9 VSS[189] VSS[258] N36
AA1 VSS[12] VSS[102] AN40 C29 VSS[190] VSS[259] N40
AA13 VSS[13] VSS[103] AN43 C35 VSS[191] VSS[260] N43
AA50 VSS[14] VSS[104] AN47 C40 VSS[192] VSS[261] N47
AA51 VSS[15] VSS[105] AN50 D10 VSS[193] VSS[262] N48
AA52 VSS[16] VSS[106] AN54 D14 VSS[194] VSS[263] N51
AA53 VSS[17] VSS[107] AP10 D18 VSS[195] VSS[264] N52
AA55 VSS[18] VSS[108] AP51 D22 VSS[196] VSS[265] N56
AA56 VSS[19] VSS[109] AP55 D26 VSS[197] VSS[266] N61
AA8 VSS[20] VSS[110] AP7 D29 VSS[198] VSS[267] P14
AB16 VSS[21] VSS[111] AR13 D35 VSS[199] VSS[268] P16
AB18 VSS[22] VSS[112] AR17 D4 VSS[200] VSS[269] P18
AB21 VSS[23] VSS[113] AR21 D40 VSS[201] VSS[270] P21
AB48 VSS[24] VSS[114] AR41 D43 VSS[202] VSS[271] P58
AB61
AC10
VSS[25]
VSS[26]
VSS[27]
VSS[115]
VSS[116]
VSS[117]
AR48
AR61
D46
D50
VSS[203]
VSS[204]
VSS[205]
VSS VSS[272]
VSS[273]
VSS[274]
P59
P9
AC14 AR7 D54 R17
AC46 VSS[28] VSS[118] AT14 D58 VSS[206] VSS[275] R20
AC6 VSS[29] VSS[119] AT19 D6 VSS[207] VSS[276] R4
AD17 VSS[30] VSS[120] AT36 E25 VSS[208] VSS[277] R46
AD20 VSS[31] VSS[121] AT4 E29 VSS[209] VSS[278] T1
AD4 VSS[32] VSS[122] AT45 E3 VSS[210] VSS[279] T47
2 AD61
AE13
VSS[33]
VSS[34]
VSS[35]
VSS VSS[123]
VSS[124]
VSS[125]
AT52
AT58
E35
E40
VSS[211]
VSS[212]
VSS[213]
VSS[280]
VSS[281]
VSS[282]
T50
T51
2

AE8 AU1 F13 T52


AF1 VSS[36] VSS[126] AU11 F15 VSS[214] VSS[283] T53
AF17 VSS[37] VSS[127] AU28 F19 VSS[215] VSS[284] T55
AF21 VSS[38] VSS[128] AU32 F29 VSS[216] VSS[285] T56
AF47 VSS[39] VSS[129] AU51 F35 VSS[217] VSS[286] U13
AF48 VSS[40] VSS[130] AU7 F40 VSS[218] VSS[287] U8
AF50 VSS[41] VSS[131] AV17 F55 VSS[219] VSS[288] V20
AF51 VSS[42] VSS[132] AV21 G51 VSS[220] VSS[289] V61
AF52 VSS[43] VSS[133] AV22 G6 VSS[221] VSS[290] W13
AF53 VSS[44] VSS[134] AV34 G61 VSS[222] VSS[291] W15
AF55 VSS[45] VSS[135] AV40 H10 VSS[223] VSS[292] W18
AF56 VSS[46] VSS[136] AV48 H14 VSS[224] VSS[293] W21
AF58 VSS[47] VSS[137] AV55 H17 VSS[225] VSS[294] W46
AF59 VSS[48] VSS[138] AW13 H21 VSS[226] VSS[295] W8
AG10 VSS[49] VSS[139] AW43 H4 VSS[227] VSS[296] Y4
AG14 VSS[50] VSS[140] AW61 H53 VSS[228] VSS[297] Y47
AG18 VSS[51] VSS[141] AW7 H58 VSS[229] VSS[298] Y58
AG47 VSS[52] VSS[142] AY14 J1 VSS[230] VSS[299] Y59
AG52 VSS[53] VSS[143] AY19 J49 VSS[231] VSS[300] G48
AG61 VSS[54] VSS[144] AY30 J55 VSS[232] VSS[301]
AG7 VSS[55] VSS[145] AY36 K11 VSS[233]
AH4 VSS[56] VSS[146] AY4 K21 VSS[234]
AH58 VSS[57] VSS[147] AY41 K51 VSS[235]
AJ13 VSS[58] VSS[148] AY45 K8 VSS[236] A5
AJ16 VSS[59] VSS[149] AY49 L16 VSS[237] VSS_NCTF_1 A57
3 VSS[60] VSS[150] VSS[238] VSS_NCTF_2 3
AJ20 AY55 L20 BC61
AJ22 VSS[61] VSS[151] AY58 L22 VSS[239] VSS_NCTF_3 BD3
AJ26 VSS[62] VSS[152] AY9 L26 VSS[240] VSS_NCTF_4 BD59
AJ30 VSS[63] VSS[153] BA1 L30 VSS[241] NCTF VSS_NCTF_5 BE4
AJ34 VSS[64] VSS[154] BA11 L34 VSS[242] VSS_NCTF_6 BE58
AJ38 VSS[65] VSS[155] BA17 L38 VSS[243] VSS_NCTF_7 BG5
AJ42 VSS[66] VSS[156] BA21 L43 VSS[244] VSS_NCTF_8 BG57
AJ45 VSS[67] VSS[157] BA26 L48 VSS[245] VSS_NCTF_9 C3
AJ48 VSS[68] VSS[158] BA32 L61 VSS[246] VSS_NCTF_10 C58
AJ7 VSS[69] VSS[159] BA48 M11 VSS[247] VSS_NCTF_11 D59
AK1 VSS[70] VSS[160] BA51 M15 VSS[248] VSS_NCTF_12 E1
AK52 VSS[71] VSS[161] BB53 VSS[249] VSS_NCTF_13 E61
AL10 VSS[72] VSS[162] BC13 VSS_NCTF_14
AL13 VSS[73] VSS[163] BC5
AL17 VSS[74] VSS[164] BC57
AL21 VSS[75] VSS[165] BD12
AL25 VSS[76] VSS[166] BD16
AL28 VSS[77] VSS[167] BD19 IVY-BRIDGE_BGA1023
AL33 VSS[78] VSS[168] BD23 @
AL36 VSS[79] VSS[169] BD27
AL40 VSS[80] VSS[170] BD32
AL43 VSS[81] VSS[171] BD36
AL47 VSS[82] VSS[172] BD40
AL61 VSS[83] VSS[173] BD44
AM13 VSS[84] VSS[174] BD48
AM20 VSS[85] VSS[175] BD52
AM22 VSS[86] VSS[176] BD56
4 4
AM26 VSS[87] VSS[177] BD8
AM30 VSS[88] VSS[178] BE5
AM34 VSS[89] VSS[179] BG13
VSS[90] VSS[180]
Security Classification Compal Secret Data Compal Electronics, Inc.
2011/06/24 2012/07/12 Title
Issued Date Deciphered Date PROCESSOR(7/7) VSS
IVY-BRIDGE_BGA1023 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
@ Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Sherry and Royal
Date: Thursday, February 02, 2012 Sheet 11 of 55
A B C D E
A B C D E

+1.5V
+VREF_DQ_DIMMA +1.5V +1.5V
JDIMM1

1
+VREF_DQ_DIMMA 1 2
R223 3 VREF_DQ VSS 4 DDR_A_D4
1K_0402_1% DDR_A_D0 5 VSS DQ4 6 DDR_A_D5
DDR_A_D1 7 DQ0 DQ5 8
9 DQ1 VSS 10 DDR_A_DQS#0

2
DDR_A0_DM0 11 VSS DQS0# 12 DDR_A_DQS0
13 DM0 DQS0 14

1
VSS VSS

0.1U_0402_16V4Z
C221
1 DDR_A_D2 15 16 DDR_A_D6
DQ2 DQ6

1
2.2U_0402_6.3V6M
C222
All VREF traces should DDR_A_D3 17 18 DDR_A_D7
R226 19 DQ3 DQ7 20
have 10 mil trace width 1K_0402_1% DDR_A_D8 21 VSS VSS 22 DDR_A_D12
1 1

2
2 DDR_A_D9 23 DQ8 DQ12 24 DDR_A_D13

2
25 DQ9 DQ13 26
DDR_A_DQS#1 27 VSS VSS 28 DDR_A0_DM1
DDR_A_DQS1 29 DQS1# DM1 30 DIMM_DRAMRST#
DQS1 RESET# DIMM_DRAMRST# [7]
31 32
DDR_A_DQS#[0..7] [7] VSS VSS
DDR_A_D10 33 34 DDR_A_D14
DDR_A_D11 35 DQ10 DQ14 36 DDR_A_D15
DDR_A_DQS[0..7] [7] DQ11 DQ15
37 38
DDR_A_D16 39 VSS VSS 40 DDR_A_D20
DDR_A_D[0..63] [7] DQ16 DQ20
DDR_A_D17 41 42 DDR_A_D21
43 DQ17 DQ21 44
DDR_A_MA[0..15] [7] VSS VSS
DDR_A_DQS#2 45 46 DDR_A0_DM2
DDR_A_DQS2 47 DQS2# DM2 48
49 DQS2 VSS 50 DDR_A_D22
DDR_A_D18 51 VSS DQ22 52 DDR_A_D23
DDR_A_D19 53 DQ18 DQ23 54
Layout Note: 55 DQ19 VSS 56 DDR_A_D28
Place near JDIMM1 DDR_A_D24 57 VSS DQ28 58 DDR_A_D29
+1.5V DDR_A_D25 59 DQ24 DQ29 60
61 DQ25 VSS 62 DDR_A_DQS#3
DDR_A0_DM3 63 VSS DQS3# 64 DDR_A_DQS3
65 DM3 DQS3 66
VSS VSS
1U_0402_6.3V6K
C294

1U_0402_6.3V6K
C326

1U_0402_6.3V6K
C291

1U_0402_6.3V6K
C310

DDR_A_D26 67 68 DDR_A_D30
DDR_A_D27 69 DQ26 DQ30 70 DDR_A_D31
1 1 1 1 DQ27 DQ31
71 72
VSS VSS

2 2 2 2 DDRA_CKE0_DIMMA 73 74 DDRA_CKE1_DIMMA
[7] DDRA_CKE0_DIMMA CKE0 CKE1 DDRA_CKE1_DIMMA [7]
75 76
77 VDD VDD 78 DDR_A_MA15
DDR_A_BS2 79 NC A15 80 DDR_A_MA14
[7] DDR_A_BS2 BA2 A14
81 82
DDR_A_MA12 83 VDD VDD 84 DDR_A_MA11
2 DDR_A_MA9 85 A12/BC# A11 86 DDR_A_MA7 2
+1.5V 87 A9 A7 88
DDR_A_MA8 89 VDD VDD 90 DDR_A_MA6
DDR_A_MA5 91 A8 A6 92 DDR_A_MA4
93 A5 A4 94
VDD VDD
10U_0603_6.3V6M
C287

10U_0603_6.3V6M
C284

10U_0603_6.3V6M
C314

10U_0603_6.3V6M
C289

DDR_A_MA3 95 96 DDR_A_MA2
DDR_A_MA1 97 A3 A2 98 DDR_A_MA0
1 1 1 1 A1 A0
99 100
SA_CLK_DDR0 101 VDD VDD 102 SA_CLK_DDR1
[7] SA_CLK_DDR0 CK0 CK1 SA_CLK_DDR1 [7]
[7] SA_CLK_DDR#0 SA_CLK_DDR#0 103 104 SA_CLK_DDR#1 SA_CLK_DDR#1 [7]
2 2 2 2 105 CK0# CK1# 106 +1.5V
DDR_A_MA10 107 VDD VDD 108 DDR_A_BS1
A10/AP BA1 DDR_A_BS1 [7]
[7] DDR_A_BS0 DDR_A_BS0 109 110 DDR_A_RAS# DDR_A_RAS# [7]
111 BA0 RAS# 112
VDD VDD

1
[7] DDR_A_WE# DDR_A_WE# 113 114 DDRA_CS0_DIMMA# DDRA_CS0_DIMMA# [7]
DDR_A_CAS# 115 WE# S0# 116 SA_ODT0 R265
[7] DDR_A_CAS# CAS# ODT0 SA_ODT0 [7]
117 118 1K_0402_1%
DDR_A_MA13 119 VDD VDD 120 SA_ODT1
+1.5V A13 ODT1 SA_ODT1 [7]
[7] DDRA_CS1_DIMMA# DDRA_CS1_DIMMA# 121 122

2
123 S1# NC 124
125 VDD VDD 126 +VREF_CA
127 TEST VREF_CA 128
VSS VSS
10U_0603_6.3V6M
C303

10U_0603_6.3V6M
C293

10U_0603_6.3V6M
C343

1 DDR_A_D32 129 130 DDR_A_D36

1
DQ32 DQ36
220U_B2_2.5VM_R35
C311

0.1U_0402_16V4Z
C353
1 1 1 DDR_A_D33 131 132 DDR_A_D37
+ 133 DQ33 DQ37 134 R269
VSS VSS 1

1
2.2U_0402_6.3V6M
C354
@ DDR_A_DQS#4 135 136 DDR_A0_DM4 1K_0402_1%
@ DDR_A_DQS4 137 DQS4# DM4 138
2 2 2 2 139 DQS4 VSS 140 DDR_A_D38

2
DDR_A_D34 141 VSS DQ38 142 DDR_A_D39 2
DDR_A_D35 143 DQ34 DQ39 144
145 DQ35 VSS 146 DDR_A_D44
DDR_A_D40 147 VSS DQ44 148 DDR_A_D45
DDR_A_D41 149 DQ40 DQ45 150
3 151 DQ41 VSS 152 DDR_A_DQS#5 3
DDR_A0_DM5 153 VSS DQS5# 154 DDR_A_DQS5
155 DM5 DQS5 156
DDR_A_D42 157 VSS VSS 158 DDR_A_D46
+0.75VS DDR_A_D43 159 DQ42 DQ46 160 DDR_A_D47
161 DQ43 DQ47 162
DDR_A_D48 163 VSS VSS 164 DDR_A_D52
DDR_A_D49 165 DQ48 DQ52 166 DDR_A_D53
DQ49 DQ53
1U_0402_6.3V6K
C411

1U_0402_6.3V6K
C412

1U_0402_6.3V6K
C413

1U_0402_6.3V6K
C414

167 168
DDR_A_DQS#6 169 VSS VSS 170 DDR_A0_DM6
1 1 1 1 DQS6# DM6
DDR_A_DQS6 171 172
173 DQS6 VSS 174 DDR_A_D54
DDR_A_D50 175 VSS DQ54 176 DDR_A_D55
2 2 2 2 DDR_A_D51 177 DQ50 DQ55 178
179 DQ51 VSS 180 DDR_A_D60
DDR_A_D56 181 VSS DQ60 182 DDR_A_D61
DDR_A_D57 183 DQ56 DQ61 184
185 DQ57 VSS 186 DDR_A_DQS#7
DDR_A0_DM7 187 VSS DQS7# 188 DDR_A_DQS7
189 DM7 DQS7 190
DDR_A_D58 191 VSS VSS 192 DDR_A_D62
Layout Note: DDR_A_D59 193 DQ58 DQ62 194 DDR_A_D63
Place near JDIMM1.203,204 195 DQ59 DQ63 196
197 VSS VSS 198
199 SA0 EVENT# 200 SMB_DATA_S3
+3VS VDDSPD SDA SMB_DATA_S3 [14,31,38]
201 202 SMB_CLK_S3
SA1 SCL SMB_CLK_S3 [14,31,38]
DDR_A0_DM0 +0.75VS 203 204 +0.75VS
DDR_A0_DM1 VTT VTT
2.2U_0402_6.3V6M
C409

0.1U_0402_16V4Z
C408

10K_0402_5%

DDR_A0_DM2 1 205 206


GND1 GND2
1

DDR_A0_DM3 207 208


DDR_A0_DM4 R336 BOSS1 BOSS2
DDR_A0_DM5
Channel A
2

R331

DDR_A0_DM6 2 10K_0402_5% TYCO_2-2013022-1


4 DDR_A0_DM7 4
1

ME@
DIMM_1 Standard H:4.0mm
<Address: SA1:SA0=00>

Security Classification Compal Secret Data Compal Electronics, Inc.


2011/06/24 2012/07/12 Title
Issued Date Deciphered Date DDRIII DIMMB
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Sherry and Royal
Date: Thursday, February 02, 2012 Sheet 12 of 55
A B C D E
A B C D E

RTCRST close to RAM door

1
1
R501
+RTCBATT C439 @ 0_0603_5%
1U_0402_6.3V6K U13A

2
PCH_RTCX1 A20 C38 LPC_AD0
1 2 RTCX1 FWH0 / LAD0 A38 LPC_AD0 [31,37]
PCH_RTCRST# LPC_AD1

LPC
FWH1 / LAD1 LPC_AD1 [31,37]
R356 20K_0402_5% PCH_RTCX2 C20 B37 LPC_AD2
RTCX2 FWH2 / LAD2 LPC_AD2 [31,37] +3VS
1 2 PCH_SRTCRST# C37 LPC_AD3
FWH3 / LAD3 LPC_AD3 [31,37]
R357 20K_0402_5% PCH_RTCRST# D20
RTCRST#

1
D36 LPC_FRAME# SERIRQ R118 2 1 10K_0402_5%
FWH4 / LFRAME# LPC_FRAME# [31,37]
1

1 R372 PCH_SRTCRST# G22 1


C440 @ 0_0603_5% SRTCRST# E36

RTC
1U_0402_6.3V6K SM_INTRUDER# K22 LDRQ0# K36
Prevent back drive issue.
2

INTRUDER# LDRQ1# / GPIO23


2

PCH_INTVRMEN C17 V5 SERIRQ


+5VS INTVRMEN SERIRQ SERIRQ [37]

AM3 SATA_PRX_DTX_C_N0 [31]


SATA0RXN

2
G
Q3 HDA_BITCLK_PCH N34 AM1
HDA_BCLK SATA0RXP SATA_PRX_DTX_C_P0 [31]

SATA 6G
BSS138_NL_SOT23-3 AP7 SATA_PTX_DRX_C_N0 2 1 C1185 0.01U_0402_16V7K SSD
+RTCBATT 3 1 L34 SATA0TXN AP5 2 1 C1208 0.01U_0402_16V7K SATA_PTX_DRX_N0 [31]
HDA_SYNC_PCH_R HDA_SYNC_PCH SATA_PTX_DRX_C_P0
HDA_SYNC SATA0TXP SATA_PTX_DRX_P0 [31]

D
R358 1 2 1M_0402_5% SM_INTRUDER# HDA_SPKR T10 AM10 SATA_DTX_C_R_PRX_N1 R148 HDD1@ 2 1 0_0402_5% SATA_DTX_C_PRX_N1 [35]
[36] HDA_SPKR SPKR SATA1RXN
R48 AM8 SATA_DTX_C_R_PRX_P1 R149 HDD1@ 2 1 0_0402_5% HDD0 w/ HM77
SATA1RXP SATA_DTX_C_PRX_P1 [35]
R355 1 2 330K_0402_5% PCH_INTVRMEN 1 2 HDA_RST_PCH# K34 AP11 SATA_PTX_DRX_N1 R150 HDD1@ 2 1 HDD1@ 2
0_0402_5% SATA_PTX_R_DRX_N1_CO 1 C1209 0.01U_0402_16V7K
HDA_RST# SATA1TXN AP10 2 1 SATA_PTX_R_DRX_N1 [35]
Disable w/ HM70
@ 0_0402_5% SATA_PTX_DRX_P1 R151 HDD1@ HDD1@ 2
0_0402_5% SATA_PTX_R_DRX_P1_CO 1 C1223 0.01U_0402_16V7K
INTVRMEN SATA_PTX_R_DRX_P1 [35]

Integrated VRM enable


SATA1TXP

1
H R29 HDA_SDIN0 E34 AD7 SATA_DTX_C_R_PRX_N2 R154 HDD2@ 2 1 0_0402_5% SATA_DTX_C_PRX_N1
* [36] HDA_SDIN0

LIntegrated VRM disable


HDA_SDIN0 SATA2RXN AD5 SATA_DTX_C_R_PRX_P2 R157 HDD2@ 2 1 0_0402_5% SATA_DTX_C_PRX_P1
1M_0402_5% SATA2RXP
G34 AH5 SATA_PTX_DRX_N2 R160 HDD2@ 2 1 0_0402_5% SATA_PTX_R_DRX_N1_CO HDD1 w/ HM70
HDA_SDIN1 SATA2TXN AH4 SATA_PTX_DRX_P2 R161 HDD2@ 2 1 0_0402_5% SATA_PTX_R_DRX_P1_CO

2
C34 SATA2TXP
(INTVRMEN should always be pull high.)

IHDA
HDA_SDIN2 AB8
A34 SATA3RXN AB10
+3VS HDA_SDIN3 SATA3RXP AF3
SATA3TXN AF1
Disable w/ HM70
R109 1 @ 2 1K_0402_5% HDA_SPKR HDA_SDOUT_PCH A36 SATA3TXP

SATA
HDA_SDO Y7
HIGH= Enable ( No Reboot)Disable TCO timer system reboot feature SATA4RXN Y5
R162 1 @ 2 1K_0402_1% PCH_GPIO33 C36 SATA4RXP AD3
* LOW= Disable (Default internal PD) HDA_DOCK_EN# / GPIO33 SATA4TXN AD1
R341 2 1 10K_0402_5% PCH_GPIO13 N32 SATA4TXP
+3V_PCH +3V_PCH HDA_DOCK_RST# / GPIO13
R46 Y3
2
1K_0402_5% R100 SATA5RXN Y1 2
@ SATA5RXP
2 @ 1 HDA_SDOUT_PCH 51_0402_5% AB3
R73 2 1 PCH_JTAG_TCK J3 SATA5TXN AB1
0_0402_5% JTAG_TCK SATA5TXP
2 1 PCH_JTAG_TMS H7 Y11 +1.05VS_VTT
L=500mil S=15mil

JTAG
[37] ME_FLASH JTAG_TMS SATAICOMPO
PCH_JTAG_TDI K5 Y10 SATA_COMP 1 2
HDA_SDO JTAG_TDI SATAICOMPI R121 37.4_0402_1%
ME debug mode,this signal has a weak internal PD PCH_JTAG_TDO H1
JTAG_TDO AB12 +1.05VS_VTT
* Low = Disabled (Default) SATA3RCOMPO L=500mil S=15mil
High = Enabled [Flash Descriptor Security Overide] +3VS
AB13 SATA3_COMP 1 2 GPIO19 has internal Pull up
SATA3COMPI R126 49.9_0402_1%
+3V_PCH GPIO21 Debug Port DG 1.2 PH 4.7K +3VS
SPI_CLK_PCH_R T3 AH1 RBIAS_SATA3 1 2
R47 2 1 1K_0402_5% HDA_SYNC_PCH SPI_CLK SATA3RBIAS R440 750_0402_1%
This signal has a weak internal pull-down SPI_SB_CS0# Y14
SPI_CS0#
SPI_SB_CS1# T1 BBS_BIT0_R R466 2 1 10K_0402_5%

SPI
SPI_CS1# P3 PCH_SATALED#
On Die PLL VR Select is supplied by SATALED# PCH_SATALED# R429 2 1 10K_0402_5%
SPI_SI V4 V14 PCH_GPIO21
*1.5V when sampled high SPI_MOSI SATA0GP / GPIO21 No use PH 10K +3VS PCH_GPIO21 R136 2 1 10K_0402_5%
1.8V when sampled low SPI_SO_R U3 P1 BBS_BIT0_R
SPI_MISO SATA1GP / GPIO19
Needs to be pulled High for Huron River platfrom
PANTHER_FCBGA989 Boot BIOS Strap
<BOM Structure>
R75
33_0402_5%
1 2 HDA_BITCLK_PCH
Boot BIOS GPIO51 GPIO19

8MB SPI ROM FOR ME


[36] HDA_BITCLK_AUDIO
R30
33_0402_5%
LPC 0 0

& Non-share ROM.


1 2 HDA_SYNC_PCH_R
3
[36] HDA_SYNC_AUDIO
R74
Reserved 0 1 3

33_0402_5%
1 2 HDA_RST_PCH#
- 1 0
[36] HDA_RST_AUDIO#
R72
33_0402_5% * SPI 1 1
1 2 HDA_SDOUT_PCH +3VS +3VS
[36] HDA_SDOUT_AUDIO
R172
R266 1 2 SPI_WP#1 0_0402_5% U46
+3V_PCH +3V_PCH +3V_PCH 3.3K_0402_5% SPI_SB_CS1# 2 1 CS1# 1 8 0_0402_5%
SPI_SO_R 1 2 SPI_SO1 2 CS# VCC 7 SPI_HOLD#1 R199
R221 1 2SPI_HOLD#1 SPI_WP#1 3 SO HOLD# 6 SPI_CLK1 1 2 SPI_CLK_PCH_R
WP# SCLK Reserve for EMI
1

3.3K_0402_5% R188 4 5 SPI_SI1 1 2 SPI_SI C459


R134 R143 R137 R127 1 2 SPI_WP# 33_0402_5% GND SI R196 10P_0402_50V8J
200_0402_5% 200_0402_5% 200_0402_5% 3.3K_0402_5% 33_0402_5% 1 2 2 1 SPI_CLK_PCH_R
16M W25Q16BVSSIG SOIC 8P @ R434 @ 33_0402_5%
R171 1 2SPI_HOLD#
2

PCH_JTAG_TDO PCH_JTAG_TMS PCH_JTAG_TDI 3.3K_0402_5%


1

R141 R140 R142 U6 Rersver 4M+2M Solution


100_0402_1% 100_0402_1% 100_0402_1%
+3VS
2

C191
1 2
PCH_RTCX1 R173
0_0402_5% U44 0.1U_0402_16V4Z
1 2 PCH_RTCX2 SPI_SB_CS0#2 1 CS# 1 8 0_0402_5%
R406 10M_0402_5% SPI_SO_R 1 2 SPI_SO_L 2 CS# VCC 7 SPI_HOLD# R168
SPI_WP# 3 SO HOLD# 6 SPI_CLK_PCH 1 2 SPI_CLK_PCH_R
4 33_0402_5% 4 WP# SCLK 5 SPI_SI_R 1 2 SPI_SI 4
Y2
1 2 R169 GND SI R170
32M W25Q32BVSSIG SOIC 8P 33_0402_5%
32.768KHZ_12.5PF_9H03200019
18P_0402_50V8J

1 1
C451
C452 18P_0402_50V8J
Security Classification Compal Secret Data Compal Electronics, Inc.
2011/06/24 2012/07/12 Title
2 2 Issued Date Deciphered Date PCH (1/9) SATA,HDA,SPI, LPC, XDP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Sherry and Royal
Date: Thursday, February 02, 2012 Sheet 13 of 55
A B C D E
A B C D E

U13B +3V_PCH

PCIE_DTX_C_PRX_N1 BG34
No use PH 10K +3VALW PCH_GPIO11 1 2
[32] PCIE_DTX_C_PRX_N1 R33 10K_0402_5%
PCIE_DTX_C_PRX_P1 BJ34 PERN1 E12 PCH_GPIO11
[32] PCIE_DTX_C_PRX_P1 PERP1 SMBALERT# / GPIO11 EC LID SW OUT
PCIE LAN C480 1 2 0.1U_0402_16V7K PCIE_PTX_DRX_N1 AV32
[32] PCIE_PTX_C_DRX_N1 1 2 0.1U_0402_16V7K PCIE_PTX_DRX_P1 AU32 PETN1 H14 PCH_SMBCLK PCH_SMBCLK 1 2
C478 DDR,WLAN,XDPSMBUS R405 2.2K_0402_5%
[32] PCIE_PTX_C_DRX_P1 PETP1 SMBCLK
PH 2.2K +3VALW
PCIE_PRX_DTX_N2 BE34 C9 PCH_SMBDATA PCH_SMBDATA R370 1 2 2.2K_0402_5%
[31] PCIE_PRX_DTX_N2 PERN2 SMBDATA
PCIE_PRX_DTX_P2 BF34
[31] PCIE_PRX_DTX_P2 PERP2
WLAN C482 1 2 0.1U_0402_16V7K PCIE_PTX_DRX_N2 BB32
[31] PCIE_PTX_C_DRX_N2 1 2 0.1U_0402_16V7K PCIE_PTX_DRX_P2 AY32 PETN2 DRAMRST_CNTRL_PCH 1 2
C481 R391 1K_0402_5%

SMBUS
[31] PCIE_PTX_C_DRX_P2 PETP2 A12 DRAMRST_CNTRL_PCH
BG36 SML0ALERT# / GPIO60 DRAMRST_CNTRL_PCH [7] 1 2
PCH_HOT# R392 10K_0402_5%
BJ36 PERN3 C8 PCH_SML0CLK
1 +3VS AV34 PERP3 SML0CLK S3 reduse No use PH 10K +3VALW 1
AU34 PETN3 G12 PCH_SML0DATA PCH_SML1CLK R403 1 2 2.2K_0402_5%
R424 2 1 10K_0402_5% WLAN_CLKREQ#_R PETP3 SML0DATA
BF36 PCH_SML1DATA R369 1 2 2.2K_0402_5%
R110 2 1 10K_0402_5% PCH_GPIO20 BE36 PERN4
AY34 PERP4 C13 PCH_HOT# UMA@
+3V_PCH BB34 PETN4 SML1ALERT# / PCHHOT# / GPIO74 PCH_HOT# [37] No use PH 10K +3VALW PEG_CLKREQ#_R 1 2
R25 10K_0402_5%
PETP4 E14 PCH_SML1CLK EC-PCH SMBUS

PCI-E*
R414 2 1 10K_0402_5% PCH_GPIO25 BG37 SML1CLK / GPIO58
BH37 PERN5 M16 PCH_SML1DATA
2 1 10K_0402_5% LAN_CLKREQ#_R AY36 PERP5 SML1DATA / GPIO75 PH 2.2K +3VALW +3VS
R389 HM70 not support For DDR
BB36 PETN5
R53 2 1 10K_0402_5% PCH_GPIO26 PCIE port 4-7 PETP5 R404
BJ38 2.2K_0402_5%
PERN6

2
R50 2 1 10K_0402_5% PCH_GPIO44 BG38 1 2
+3VS

Controller
AU36 PERP6 M7
R32 2 1 10K_0402_5% PCH_GPIO45 AV36 PETN6 CL_CLK1 PCH_SMBDATA 6 1 SMB_DATA_S3
PETP6 SMB_DATA_S3 [12,31,38]

Link
R51 2 1 10K_0402_5% PCH_GPIO46 BG40 T11 Q34A
BJ40 PERN7 CL_DATA1 DMN66D0LDW-7_SOT363-6 R371
R54 2 1 10K_0402_5% PCH_GPIO56 AY40 PERP7 @ 2.2K_0402_5%
PETN7

5
BB40 P10 2 R9 1 1 2
PETP7 CL_RST1# PEG_CLKREQ# [23] +3VS
0_0402_5%
BE38 PCH_SMBCLK 3 4 SMB_CLK_S3
PERN8 SMB_CLK_S3 [12,31,38]
BC38
AW 38 PERP8 Q34B
AY38 PETN8 No use PH 10K +3VALW
DMN66D0LDW-7_SOT363-6
PETP8 PX@
M10 PEG_CLKREQ#_R R56 1 210K_0402_5% +3VS
1 2 0_0402_5% CLK_PCIE_LAN#_R Y40 PEG_A_CLKRQ# / GPIO47 Pull up at EC side.
R153
[32] CLK_PCIE_LAN# CLKOUT_PCIE0N For VGA,EC,Thermal sensor
PCIE LAN R163 1 2 0_0402_5% CLK_PCIE_LAN_R Y39 R58 PX@0_0402_5%
[32] CLK_PCIE_LAN CLKOUT_PCIE0P AB37 2 1 CLK_PCIE_VGA#
2 CLK_PCIE_VGA#_R 2
CLK_PCIE_VGA# [22]

CLOCKS
CLKOUT_PEG_A_N

2
No use PH 10K +3VALW R164 1 2 0_0402_5% LAN_CLKREQ#_R J2 AB38 CLK_PCIE_VGA_R 2 1 CLK_PCIE_VGA
[32] LAN_CLKREQ# PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P CLK_PCIE_VGA [22]
R59 PX@0_0402_5%
PCH_SML1DATA 6 1 EC_SMB_DA2 EC_SMB_DA2 [23,34,37]
R165 1 2 0_0402_5% CLK_PCIE_WLAN1#_R AB49 AV22 CLK_CPU_DMI#
[31] CLK_PCIE_WLAN1# 1 2 0_0402_5% CLK_PCIE_WLAN1_R AB47 CLKOUT_PCIE1N CLKOUT_DMI_N AU22 CLK_CPU_DMI# [6]
R166 CLK_CPU_DMI Q33A
[31] CLK_PCIE_WLAN1 CLKOUT_PCIE1P CLKOUT_DMI_P CLK_CPU_DMI [6]
WLAN DMN66D0LDW-7_SOT363-6

5
R167 1 2 0_0402_5% WLAN_CLKREQ#_R M1
[31] WLAN_CLKREQ# PCIECLKRQ1# / GPIO18
No use PH 10K +3VS AM12
CLKOUT_DP_N / CLKOUT_BCLK1_N AM13 PCH_SML1CLK 3 4 EC_SMB_CK2
CLKOUT_DP_P / CLKOUT_BCLK1_P EC_SMB_CK2 [23,34,37]
AA48
AA47 CLKOUT_PCIE2N Q33B
CLKOUT_PCIE2P BF18 CLK_BUF_CPU_DMI# R152 1 2 10K_0402_5% DMN66D0LDW-7_SOT363-6
PCH_GPIO20 V10 CLKIN_DMI_N BE18 CLK_BUF_CPU_DMI R147 1 2 10K_0402_5%
No use PH 10K +3VS PCIECLKRQ2# / GPIO20 CLKIN_DMI_P

Y37 BJ30 CLKIN_GND1# R453 1 2 10K_0402_5%


Y36 CLKOUT_PCIE3N CLKIN_DMI2_N BG30 CLKIN_GND1 R452 1 2 10K_0402_5%
CLKOUT_PCIE3P CLKIN_DMI2_P +3V_PCH
No use PH 10K +3VALW PCH_GPIO25 A8
PCIECLKRQ3# / GPIO25 G24 CLK_BUF_DREF_96M# R99 1 2 10K_0402_5%
CLKIN_DOT_96N E24 CLK_BUF_DREF_96M R93 1 2 10K_0402_5%
CLKIN_DOT_96P Pull down 10K ohm

2
Y43
Y45 CLKOUT_PCIE4N for using internal Clock R551 R545
CLKOUT_PCIE4P AK7 CLK_BUF_PCIE_SATA# R139 1 2 10K_0402_5% 2.2K_0402_5%
CLKIN_SATA_N / CKSSCD_N 2.2K_0402_5%
No use PH 10K +3VALW PCH_GPIO26 L12 AK5 CLK_BUF_PCIE_SATA R138 1 2 10K_0402_5%
PCIECLKRQ4# / GPIO26 CLKIN_SATA_P / CKSSCD_P

1
PCH_SML0CLK
V45 K45 CLK_BUF_ICH_14M R101 1 2 10K_0402_5%
V46 CLKOUT_PCIE5N REFCLK14IN PCH_SML0DATA
CLKOUT_PCIE5P
No use PH 10K +3VALW PCH_GPIO44 L14 H45 CLK_PCI_LPBACK
3 PCIECLKRQ5# / GPIO44 CLKIN_PCILOOPBACK CLK_PCI_LPBACK [17] 3
2 1 1 2
R96 @ C29 @ 22P_0402_50V8J
AB42 V47 XTAL25_IN 33_0402_5%
AB40 CLKOUT_PEG_B_N XTAL25_IN V49 XTAL25_OUT
CLKOUT_PEG_B_P XTAL25_OUT Reserve for EMI please close to PCH
PCH_GPIO56 E6 R120 +1.05VS_VTT
No use PH 10K +3VALW PEG_B_CLKRQ# / GPIO56 W=12mil S=15mil
90.9_0402_1%
Y47 XCLK_RCOMP 1 2
V40 XCLK_RCOMP
V42 CLKOUT_PCIE6N
CLKOUT_PCIE6P +3VS
No use PH 10K +3VALW PCH_GPIO45 T13
PCIECLKRQ6# / GPIO45

1
V38 K43
V37 CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64 R421 XTAL25_IN
FLEX CLOCKS

CLKOUT_PCIE7P F47 UMA@


CLKOUTFLEX1 / GPIO65 10K_0402_5%
No use PH 10K +3VALW PCH_GPIO46 K12 XTAL25_OUT 1 2
PCIECLKRQ7# / GPIO46 H47 LAN_48M1 R207 @2 22_0402_5% R431 1M_0402_5%
PCH_LAN_48M

2
PCIE_CLK_8N AK14 CLKOUTFLEX2 / GPIO66 DGPU_PRSNT#
PCIE_CLK_8P AK13 CLKOUT_BCLK0_N / CLKOUT_PCIE8N K49 DGPU_PRSNT# 3 4
CLKOUT_BCLK0_P / CLKOUT_PCIE8P CLKOUTFLEX3 / GPIO67 OSC NC

2
R420 2 1
PANTHER_FCBGA989 PX@ 10K_0402_5% NC OSC
1 Y3 1
<BOM Structure> 25MHZ_10PF_7V25000014

1
C457 C468
10P_0402_50V8J 10P_0402_50V8J
2 2
GPIO67
DGPU_PRSNT#
4 4
DIS,Optimus 0
UMA 1

Security Classification Compal Secret Data Compal Electronics, Inc.


2011/06/24 2012/07/12 Title
Issued Date Deciphered Date PCH (2/9) PCIE, SMBUS, CLK
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Sherry and Royal
Date: Thursday, February 02, 2012 Sheet 14 of 55
A B C D E
A B C D E

U13C

[5] DMI_CTX_PRX_N0 DMI_CTX_PRX_N0 BC24 BJ14 FDI_CTX_PRX_N0 FDI_CTX_PRX_N0 [5]


DMI_CTX_PRX_N1 BE20 DMI0RXN FDI_RXN0 AY14 FDI_CTX_PRX_N1 +RTCBATT
[5] DMI_CTX_PRX_N1 DMI1RXN FDI_RXN1 FDI_CTX_PRX_N1 [5]
[5] DMI_CTX_PRX_N2 DMI_CTX_PRX_N2 BG18 BE14 FDI_CTX_PRX_N2 FDI_CTX_PRX_N2 [5]
+3V_PCH DMI_CTX_PRX_N3 BG20 DMI2RXN FDI_RXN2 BH13 FDI_CTX_PRX_N3
[5] DMI_CTX_PRX_N3 DMI3RXN FDI_RXN3 FDI_CTX_PRX_N3 [5]
BC12 FDI_CTX_PRX_N4 FDI_CTX_PRX_N4 [5] DSWODVREN R350 2 1 330K_0402_5%
DMI_CTX_PRX_P0 BE24 FDI_RXN4 BJ12 FDI_CTX_PRX_N5
[5] DMI_CTX_PRX_P0 DMI0RXP FDI_RXN5 FDI_CTX_PRX_N5 [5]
R26 2 1 200K_0402_5% AC_PRESENT_R [5] DMI_CTX_PRX_P1 DMI_CTX_PRX_P1 BC20 BG10 FDI_CTX_PRX_N6 FDI_CTX_PRX_N6 [5] R368 2 @ 1 330K_0402_5%
DMI_CTX_PRX_P2 BJ18 DMI1RXP FDI_RXN6 BG9 FDI_CTX_PRX_N7
[5] DMI_CTX_PRX_P2 DMI2RXP FDI_RXN7 FDI_CTX_PRX_N7 [5]


[5] DMI_CTX_PRX_P3 DMI_CTX_PRX_P3 BJ20 DSWODVREN - On Die DSW VR Enable
+3V_PCH DMI3RXP BG14 FDI_CTX_PRX_P0
FDI_RXP0 FDI_CTX_PRX_P0 [5]
* H Enable internal DSW +1.05VS

DMI_CRX_PTX_N0 AW24 BB14 FDI_CTX_PRX_P1 FDI_CTX_PRX_P1 [5]
1 [5] DMI_CRX_PTX_N0 DMI0TXN FDI_RXP1 1
DMI_CRX_PTX_N1 AW20 BF14 FDI_CTX_PRX_P2 FDI_CTX_PRX_P2 [5] L Disable
[5] DMI_CRX_PTX_N1 DMI1TXN FDI_RXP2
R34 2 1 10K_0402_5% SUSWARN#_R DMI_CRX_PTX_N2 BB18 BG13 FDI_CTX_PRX_P3 FDI_CTX_PRX_P3 [5] Must always PH at +RTCVCC
[5] DMI_CRX_PTX_N2 DMI2TXN FDI_RXP3
DMI_CRX_PTX_N3 AV18 BE12 FDI_CTX_PRX_P4 FDI_CTX_PRX_P4 [5]

DMI
FDI
[5] DMI_CRX_PTX_N3 DMI3TXN FDI_RXP4
R49 2 1 10K_0402_5% PCH_GPIO72 BG12 FDI_CTX_PRX_P5 FDI_CTX_PRX_P5 [5]
DMI_CRX_PTX_P0 AY24 FDI_RXP5 BJ10 FDI_CTX_PRX_P6
[5] DMI_CRX_PTX_P0 DMI0TXP FDI_RXP6 FDI_CTX_PRX_P6 [5] +3V_PCH
R390 2 1 10K_0402_5% RI# DMI_CRX_PTX_P1 AY20 BH9 FDI_CTX_PRX_P7 FDI_CTX_PRX_P7 [5]
[5] DMI_CRX_PTX_P1 DMI1TXP FDI_RXP7
DMI_CRX_PTX_P2 AY18
[5] DMI_CRX_PTX_P2 DMI2TXP
DMI_CRX_PTX_P3 AU18 PCH_PCIE_WAKE# R374 1 2 10K_0402_5%
[5] DMI_CRX_PTX_P3 DMI3TXP
R393 2 1 300_0402_5% PM_DRAM_PWRGD AW16 FDI_INT
FDI_INT FDI_INT [5]
Follow G +1.05VS_VTT BJ24 AV12 FDI_FSYNC0 PCH_GPIO29 R36 1 @ 2 10K_0402_5%
R394 2 1 10K_0402_5% PCH_RSMRST#
L=500mil S=15mil DMI_ZCOMP FDI_FSYNC0 FDI_FSYNC0 [5]
1 2 DMI_IRCOMP BG25 BC10 FDI_FSYNC1 +3VS
DMI_IRCOMP FDI_FSYNC1 FDI_FSYNC1 [5]
R156 49.9_0402_1% @
1 2 DMI2RBIAS BH21 AV14 FDI_LSYNC0 CLKRUN# R423 1 2 8.2K_0402_5%
DMI2RBIAS FDI_LSYNC0 FDI_LSYNC0 [5]
R155 750_0402_1%
+3VS BB10 FDI_LSYNC1
FDI_LSYNC1 FDI_LSYNC1 [5]
R397 @ 4mil width and place
2 1 200_0402_5% PM_DRAM_PWRGD PCH_DPWROK 2 R135 10_0402_5%
within 500mil of the PCH For DS3 DS3@
DPWROK_EC [37]
A18 DSWODVREN
For DS3 DSWVRMEN
not support Deep S4,S5 not support Deep S4,S5 DPWROK mux with RSMRST#

System Power Management


R1468 0_0402_5%
can be left unconnected. [37] SUSACK# 2 1 SUSACK#_R C12 E22 PCH_DPWROK 1 2 PCH_RSMRST# check list1.5 P.50
DS3@ SUSACK# DPWROK R133 0_0402_5%
Check list1.5 P.81 +3VS
1 2 XDP_DBRESET#_R K3 B9 PCH_PCIE_WAKE# PCH_PCIE_WAKE# [31,32]
R415 10K_0402_5% SYS_RESET# WAKE#
2 2

SYS_PWROK P12 N3 CLKRUN#


SYS_PWROK CLKRUN# / GPIO32
not support AMT APWROK can mux

1
with PWROK (check list1.5 P.47) PCH_PWROK 1 2 PCH_PWROK_R L22 G8 SUS_STAT# T1@ PAD R375
R107 0_0402_5% PWROK SUS_STAT# / GPIO61
10K_0402_5%

R303 1 @ 2 0_0402_5% APWROK L10 N14 SUSCLK 0111 Add R375 to GND
[37] PCH_APWROK SUSCLK [37]

2
PCH_PWROK_R 2 1 APWROK APWROK SUSCLK / GPIO62
R191 0_0402_5%
PM_DRAM_PWRGD B13 D10 PM_SLP_S5#
[6] PM_DRAM_PWRGD DRAMPWROK SLP_S5# / GPIO63 PM_SLP_S5# [37]
AEPWROK can be connect to
PWROK if iAMT disable
[37] EC_RSMRST# 1 2 PCH_RSMRST# C21 H4 PM_SLP_S4#
RSMRST# SLP_S4# PM_SLP_S4# [37]
R125 0_0402_5% Can be left NC
R1489 0_0402_5%
For Deep S3
For DS3 2 1 SUSWARN#_R K16 F4 PM_SLP_S3# when IAMT is not
+3VALW [37] SUSWARN# SUSWARN# / SUS_PWR_DN_ACK / GPIO30 SLP_S3# PM_SLP_S3# [37]
DS3@
support on the
DS3@ [37] PBTN_OUT# 1 2 PBTN_OUT#_R E20 G10 SLP_A# T4@ PAD platfrom
R195 2 1 200K_0402_5% AC_PRESENT_R R129 0_0402_5% PWRBTN# SLP_A#
D3
[23,37,43] ACIN 1 2 AC_PRESENT_R H20 G16 SLP_SUS# not support
ACPRESENT / GPIO31 SLP_SUS# SLP_SUS# [37,40]
RB751V-40_SOD323-2
For DS3 Deep S4,S5 can NC
No use PH 10K +3VALW PCH_GPIO72 E10 AP14 H_PM_SYNC
BATLOW# / GPIO72 PMSYNCH H_PM_SYNC [6] PCH EDS1.5 P.75
3 3
Ring Indicator CRB1.0 PH 10K +3VALW RI# A10 K14 PCH_GPIO29 If Intel LAN no use, can let be NC.
RI# SLP_LAN# / GPIO29

PANTHER_FCBGA989

<BOM Structure>

+3VS ALL power OK


tell PCH all power ok
but cpu core
5

U36
PCH_PWROK 2
P

[37] PCH_PWROK B 4 SYS_PWROK


Y SYS_PWROK [6]
[50] VGATE 1
A
G
1

MC74VHC1G08DFT2G_SC70-5 1
3

R104 R119 C52


10K_0402_5% 100K_0402_5%
0.047U_0402_16V7K
@2
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


2011/06/24 2012/07/12 Title
Issued Date Deciphered Date PCH (3/9) DMI,FDI,PM
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Sherry and Royal
Date: Thursday, February 02, 2012 Sheet 15 of 55
A B C D E
A B C D E

U13D
PCH_ENBKL J47 AP43 +3VS
[29] PCH_ENBKL L_BKLTEN SDVO_TVCLKINN
M45 AP45
[29] PCH_ENVDD L_VDD_EN SDVO_TVCLKINP
P45 AM42
[29] PCH_PWM L_BKLTCTL SDVO_STALLN

1
AM40
T40 SDVO_STALLP R144 R131
[29] EDID_CLK L_DDC_CLK
K47 AP39 2.2K_0402_5% 2.2K_0402_5%
[29] EDID_DATA L_DDC_DATA SDVO_INTN AP40 HDMI@ HDMI@
CTRL_CLK T45 SDVO_INTP
L=500mil S=20mil

2
+3VS Change to eDP only CTRL_DATA P39 L_CTRL_CLK
1 1
2.37K_0402_1% L_CTRL_DATA
R108 1 2 2.2K_0402_5% CTRL_CLK R132 2 1 LVDS_IBG AF37 P38 HDMICLK_NB
LVD_IBG SDVO_CTRLCLK HDMICLK_NB [30]
AF36 M39 HDMIDAT_NB
LVD_VBG SDVO_CTRLDATA HDMIDAT_NB [30]
R105 1 2 2.2K_0402_5% CTRL_DATA DIS only can NC W=10mil S=30mil LVD_VREF AE48
AE47 LVD_VREFH AT49
UMA LVDS DDC LVD_VREFL DDPB_AUXN AT47
R428 1 2 2.2K_0402_5% EDID_CLK DDPB_AUXP AT40 TMDS_B_HPD#
DDPB_HPD TMDS_B_HPD# [30]
LVDS_ACLK# AK39

LVDS
[29] LVDS_ACLK# LVDSA_CLK#
R425 1 2 2.2K_0402_5% EDID_DATA LVDS_ACLK AK40 AV42 TMDS_B_DATA2#_PCH HDMI@ C406 1 2 0.1U_0402_10V6K
[29] LVDS_ACLK LVDSA_CLK DDPB_0N HDMI_TX2-_CK [30]
AV40 TMDS_B_DATA2_PCH HDMI@ C352 1 2 0.1U_0402_10V6K HDMI D2
DDPB_0P HDMI_TX2+_CK [30]
Check list1.5 P.60 disable Graphics LVDS_A0# AN48 AV45 TMDS_B_DATA1#_PCH HDMI@ C539 1 2 0.1U_0402_10V6K
[29] LVDS_A0# LVDSA_DATA#0 DDPB_1N HDMI_TX1-_CK [30]
AM47 AV46 TMDS_B_DATA1_PCH 1 2

Digital Display Interface


LVDS_A1# HDMI@ C538 0.1U_0402_10V6K HDMI D1
[29] LVDS_A1# LVDSA_DATA#1 DDPB_1P HDMI_TX1+_CK [30]
ALL Can NC [29] LVDS_A2#
LVDS_A2# AK47
LVDSA_DATA#2 DDPB_2N
AU48 TMDS_B_DATA0#_PCH HDMI@ C535 1 2 0.1U_0402_10V6K
HDMI_TX0-_CK [30] HDMI
AJ48 AU47 TMDS_B_DATA0_PCH HDMI@ C534 1 2 0.1U_0402_10V6K HDMI D0
but DAC_IREF still need PD LVDSA_DATA#3 DDPB_2P AV47 TMDS_B_CLK#_PCH HDMI@ C537 1 2 0.1U_0402_10V6K
HDMI_TX0+_CK [30]
DDPB_3N HDMI_CLK-_CK [30]
LVDS_A0 AN47 AV49 TMDS_B_CLK_PCH HDMI@ C536 1 2 0.1U_0402_10V6K HDMI CLK
[29] LVDS_A0 LVDSA_DATA0 DDPB_3P HDMI_CLK+_CK [30]
LVDS_A1 AM49
[29] LVDS_A1 LVDSA_DATA1
LVDS disable: LVDS_A2 AK49
[29] LVDS_A2 LVDSA_DATA2
AJ47 P46
DATA/Clock/Control an NC LVDSA_DATA3 DDPC_CTRLCLK P42
DDPC_CTRLDATA
VCC_TX_LVDS,VCCA_LVDS PD to GND AF40
Place close to connector side
AF39 LVDSB_CLK# AP47
2 LVDSB_CLK DDPC_AUXN AP49 2
CRT disable: UM77 not support AH45 DDPC_AUXP AT38
DATA/Clock/Control an NC LVDS/CRT AH47 LVDSB_DATA#0 DDPC_HPD
AF49 LVDSB_DATA#1 AY47
VCCADAC connect to +3VS AF45 LVDSB_DATA#2 DDPC_0N AY49
DAC_IREF connect 1K_0402_5% LVDSB_DATA#3 DDPC_0P AY43
AH43 DDPC_1N AY45
AH49 LVDSB_DATA0 DDPC_1P BA47
AF47 LVDSB_DATA1 DDPC_2N BA48
AF43 LVDSB_DATA2 DDPC_2P BB47
LVDSB_DATA3 DDPC_3N BB49
DDPC_3P

N48 M43
P49 CRT_BLUE DDPD_CTRLCLK M36
T49 CRT_GREEN DDPD_CTRLDATA
CRT_RED
AT45

CRT
T39 DDPD_AUXN AT43
M40 CRT_DDC_CLK DDPD_AUXP BH41
CRT_DDC_DATA DDPD_HPD
BB43
M47 DDPD_0N BB45
M49 CRT_HSYNC DDPD_0P BF44
CRT_VSYNC DDPD_1N BE44
3 3
DDPD_1P BF42
CRT_IREF T43 DDPD_2N BE42
T42 DAC_IREF DDPD_2P BJ42
CRT_IRTN DDPD_3N BG42
DDPD_3P
1

R114 PANTHER_FCBGA989
1K_0402_5%
<BOM Structure>
CRT disable
2

use 1K_0402_5%

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


2011/06/24 2012/07/12 Title
Issued Date Deciphered Date PCH (4/9) LVDS,CRT,DP,HDMI
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Sherry and Royal
Date: Thursday, February 02, 2012 Sheet 16 of 55
A B C D E
A B C D E

U13E
+3VS AY7
NV_CE#0 AV7
R90 BG26 NV_CE#1 AU3
8 1 PCI_PIRQC# BJ26 TP1 NV_CE#2 BG4
7 2 PCI_PIRQB# BH25 TP2 NV_CE#3
6 3 PCI_PIRQA# BJ16 TP3 AT10
5 4 PCI_PIRQD# BG16 TP4 NV_DQS0 BC8
AH38 TP5 NV_DQS1
8.2K_1206_8P4R_5% AH37 TP6 AU2
1 AK43 TP7 NV_DQ0 / NV_IO0 AT4 1
R409 AK45 TP8 NV_DQ1 / NV_IO1 AT3
8 1 PCH_GPIO2 C18 TP9 NV_DQ2 / NV_IO2 AT1
7 2 PCH_GPIO3 N30 TP10 NV_DQ3 / NV_IO3 AY3
6 3 PCH_GPIO4 H3 TP11 NV_DQ4 / NV_IO4 AT5
5 4 PXS_PWREN_R AH12 TP12 NV_DQ5 / NV_IO5 AV3
TP13

NVRAM
AM4 NV_DQ6 / NV_IO6 AV1
8.2K_1206_8P4R_5% AM5 TP14 NV_DQ7 / NV_IO7 BB1
Y13 TP15 NV_DQ8 / NV_IO8 BA3
R408 1 2 8.2K_0402_5% PCH_GPIO51 K24 TP16 NV_DQ9 / NV_IO9 BB5
L24 TP17 NV_DQ10 / NV_IO10 BB3
R418 1 2 8.2K_0402_5% PCH_WL_OFF# AB46 TP18 NV_DQ11 / NV_IO11 BB7
AB45 TP19 NV_DQ12 / NV_IO12 BE8

RSVD
R432 1 2 8.2K_0402_5% PCH_GPIO53 TP20 NV_DQ13 / NV_IO13 BD4
NV_DQ14 / NV_IO14 BF6
R433 1 2 8.2K_0402_5% PCH_GPIO52 NV_DQ15 / NV_IO15
B21 AV5
R401 1 2 8.2K_0402_5% PCH_GPIO5 M20 TP21 NV_ALE AY1 DF_TVS
AY16 TP22 NV_CLE
BG46 TP23 AV10
DMI,FDI Termination Voltage
+3VS TP24 NV_RCOMP
AT8
Set to Vcc when HIGH HR CPU NC
1 2 NV_RB# DF_TVS
R66 8.2K_0402_5% BE28 AY5
Set to Vss when LOW CR CPU PD
USB3_RX2_N BC30 TP25 NV_RE#_WRB0 BA2
[39] USB3_RX2_N TP26 NV_RE#_WRB1
1 2 DGPU_HOLD_RST#_R BE32 CR Check list P.89 PH 2.2K series 1K
R41 @ 8.2K_0402_5% BJ32 TP27 AT12
BC28 TP28 NV_WE#_CK0 BF3
USB3_RX2_P BE30 TP29 NV_WE#_CK1
[39] USB3_RX2_P TP30 +1.8VS
BF32
BG32 TP31 C24
AV26 TP32 USBP0N A24
USB3.0 TP33 USBP0P

1
2 USB3_TX2_N BB26 C25 USB20_N1 2
[39] USB3_TX2_N TP34 USBP1N USB20_N1 [39]
AU28 B25 USB20_P1 USB3 (Left side) R145
TP35 USBP1P USB20_P1 [39]
Boot BIOS Strap AY30 C26 USB20_N2 2.2K_0402_5%
TP36 USBP2N USB20_N2 [31]
AU26 A26 USB20_P2 Mini Card (WLAN)
TP37 USBP2P USB20_P2 [31]
USB3_TX2_P AY26 K28
GPIO19 GPIO51 Boot BIOS [39] USB3_TX2_P

2
AV28 TP38 USBP3N H28 DF_TVS 2 1
TP39 USBP3P H_SNB_IVB# [6]
Bit11 Bit10 Destination AW30
TP40 USBP4N
E28
D28
EHCI 1 R146 1K_0402_5%
GNT1#/ USBP4P C28
GPIO51 0 1 Reserved USBP5N A28
CLOSE TO THE BRANCHING POINT
USBP5P C29
1 0 PCI USBP6N B29
HM70 not support USB port 4,5,6,7,12,13
USBP6P
Internal 1 1 SPI PCI_PIRQA# K40 N28
PH
* PCI Interrupt Requests PCI_PIRQB# K38 PIRQA# USBP7N M28

PCI
PCI_PIRQC# H38 PIRQB# USBP7P L30 USB20_N8
0 0 LPC PCI_PIRQD# G38 PIRQC# USBP8N K30 USB20_P8
USB20_N8 [38]
PIRQD# USBP8P G30 USB20_N9
USB20_P8 [38] USB2 (Right side)
USBP9N USB20_N9 [38] +3V_PCH
CR Check list 1.5 only use for GPIO DGPU_HOLD_RST# R55 2 1 0_0402_5% PX5@ DGPU_HOLD_RST#_R C46 E30 USB20_P9 USB2 (Right side)

USB
REQ1# / GPIO50 USBP9P USB20_P9 [38]
PCH_GPIO52 C44 C30 USB20_N10
REQ2# / GPIO52 USBP10N USB20_N10 [38]
No use PH +3VS [24,49] PXS_PWREN
R57 2 1 0_0402_5% PX5@ PXS_PWREN_R E40
REQ3# / GPIO54 USBP10P
A30 USB20_P10
USB20_P10 [38] Card Reader USB_OC0# 2 1
Only GPIO L32 USB20_N11 EHCI 2 R24 10K_0402_5%
USBP11N USB20_N11 [29]
PCH_GPIO51 D47 K32 USB20_P11


function CR Check list 1.5 only use for GPIO PCH_GPIO53 E42 GNT1# / GPIO51 USBP11P G32
USB20_P11 [29] CMOS Camera (LVDS) USB_OC7# 2 1
PH(Internal PH), GPIO PH +3VS PCH_WL_OFF# F46 GNT2# / GPIO53 USBP12N E32 0110 modify WLAN USB port to USB8 R367 10K_0402_5%
[31] PCH_WL_OFF# GNT3# / GPIO55 USBP12P Port9 is for debug.
C32 USB_OC5# 2 1
USBP13N A32 R378 10K_0402_5%
PCH_GPIO2 G42 USBP13P
PCH_GPIO3 G40 PIRQE# / GPIO2 USB_OC6# 2 1
C42 PIRQF# / GPIO3 C33 1 2
GPIO55 PCH_GPIO4
PIRQG# / GPIO4 USBRBIAS#
USBRBIAS R377 10K_0402_5%
PCH_GPIO5 D44 R399 22.6_0402_1%
PCH_WL_OFF# R215 1 @ 2 1K_0402_5% PIRQH# / GPIO5
B33 L=500mil S=15mil
3 PCI_PME# K10 USBRBIAS +3V_PCH 3
[37] PCI_PME# PME# R349
A16 swap overide Strap/Top-Block PCH_PLTRST# C6 A14 USB_OC0# USB_OC1# 4 5
[6] PCH_PLTRST# PLTRST# OC0# / GPIO59 K20
USB_OC0# [39] Card reader 3 6
Swap Override jumper OC1# / GPIO40
USB_OC1# USB_OC4#
B17 USB_OC2# USB_OC3# 2 7
R417 2 1 22_0402_5% H49 OC2# / GPIO41 C16 1 8
Low=A16 swap [14] CLK_PCI_LPBACK
CLK_PCI_LPBACK CLK_PCI0
CLKOUT_PCI0 OC3# / GPIO42
USB_OC3# USB_OC2#
override/Top-Block CLK_PCI_EC R84 1 2 22_0402_5% CLK_PCI1 H43 L16 USB_OC4#
[37] CLK_PCI_EC CLKOUT_PCI1 OC4# / GPIO43 USB_OC4# [38]
PCI_GNT3# Swap Override enabled CLK_PCI_DB R340 1 2 22_0402_5% CLK_PCI2 J48 A16 USB_OC5# 10K_1206_8P4R_5%
[31] CLK_PCI_DB CLKOUT_PCI2 OC5# / GPIO9
High=Default * @ K42 D14 USB_OC6#
H40 CLKOUT_PCI3 OC6# / GPIO10 C14 USB_OC7#
CLKOUT_PCI4 OC7# / GPIO14

PANTHER_FCBGA989

@
R10
0_0402_5%
2 1

+3VS
5

U25 @
PCH_PLTRST# 2
P

B 4
Y PLT_RST# [31,32,37]
1
A
G

R11
3

100K_0402_5%

MC74VHC1G08DFT2G_SC70-5
2

4 4
+3VS
5

U29 PX@ R6
2 0_0402_5%
P

B 4 2 1
Y GPU_RST# [22]
DGPU_HOLD_RST# 1
A
G

Security Classification Compal Secret Data Compal Electronics, Inc.


3

2011/06/24 2012/07/12 Title


Issued Date Deciphered Date PCH (5/9) PCI, USB, NVRAM
MC74VHC1G08DFT2G_SC70-5
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Sherry and Royal
Date: Thursday, February 02, 2012 Sheet 17 of 55
A B C D E
A B C D E

HDA_SYNC PH(PLL =+1.5VS)


+3VS +3VS
+3VS
GPIO28

1
On-Die PLL Voltage Regulator PCH_GPIO70 Function

1
R67 @ R69


This signal has a weak internal pull up 10K_0402_5% 10K_0402_5%@ R68
H On-Die PLL voltage regulator enable 0 13/14" 10K_0402_5%
* L On-Die PLL Voltage Regulator disable 1 NA @

2
PCH_GPIO69 PCH_GPIO70

2
PCH_GPIO71 PCH_GPIO71

2
+3V_PCH

2
R42 @ R44
Fan Tachometer Inputs 10K_0402_5% 200K_0402_5% 0 USB3.0 by PCH R43
1

1 200K_0402_5% 1
R411 TACH1~7 only on server 1 USB3.0 by NEC

1
10K_0402_5% can insted to GPIO

1
2

PCH_GPIO28 U13F
2

No use PH 10K +3VS PCH_GPIO0 T7 C40 PCH_GPIO68


R413 BMBUSY# / GPIO0 TACH4 / GPIO68 Need?
@ 1K_0402_5% No use PH 10K +3VS PCH_GPIO1 A42 B41 PCH_GPIO69
TACH1 / GPIO1 TACH5 / GPIO69
PCH_GPIO6 H36 C41 PCH_GPIO70 +3VS
No use PH 10K +3VS
1

TACH2 / GPIO6 TACH6 / GPIO70


Debug Port DG 1.2 PH 4.7K +3VALW_PCH EC_SCI# E38 A40 PCH_GPIO71
No use PH 10K +3VS [37] EC_SCI# TACH3 / GPIO7 TACH7 / GPIO71

2
No use PH 10K +3VALW EC_SMI# C10 R106
[37] EC_SMI# GPIO8
10K_0402_5%
Deep S4,S5 wake event signal No use PH +3VALW PCH_GPIO12 C4
LAN_PHY_PWR_CTRL / GPIO12

1
RTC alarm,Power BTN,GPIO27 No use PH +3VALW[37] EC_LID_OUT#
EC_LID_OUT# @1
@ 2 PCH_GPIO15 G2 P4
GATEA20 [37]
R60 0_0402_5% GPIO15 A20GATE
PCH_GPIO27 (Have internal Pull-High) AU16 PCH_PECI_R 1 2
@ PECI CPU-EC

CPU/MISC
Deep S4,S5 wake event signal mSATA_DET# U2 PECI H_PECI [37,6]
No use PH +3VS [31] mSATA_DET# 0_0402_5% R158
SATA4GP / GPIO16 P5 EC_KBRST#
+3VALW RCIN# KBRST# [37] CTRL+ALT+DEL
For DS3 No use PH +3VS

GPIO
R45 1 2 0_0402_5% VGA_PWRGD_R D40 AY11 non CPU power ok
[22,49] VGA_PWRGD TACH0 / GPIO17 PROCPWRGD H_CPUPWRGD [6]
DS3@
R208 2 1 10K_0402_5% No use PH 10K +3VS Blue Booth BT_DISABLE T5 AY10 PCH_THRMTRIP#_R 1 2 H_THERMTRIP# 130c shut down
[31] BT_DISABLE SCLOCK / GPIO22 THRMTRIP# H_THERMTRIP# [6]
R159 390_0402_5%
No use PH +3VALW DDR3 PCH_GPIO24 E8 T14
R83 1 @ 2 10K_0402_5% PCH_GPIO27 GPIO24 / MEM_LED INIT3_3V#
EC_LID_OUT# 1 2 PCH_GPIO27 E16
INIT3_3V Checklist1.5 P.69
2
No use PD 10K to GND R61 0_0402_5% GPIO27 +3VS 2
PCH_GPIO28 P8
This signal has weak internal
No use PH 10K +3VALW GPIO28 AH8 PU, can't pull low,leave NC
PCH_BT_ON# K1 NC_1
No use PH 10K +3VS BT ON/OFF [31] PCH_BT_ON# STP_PCI# / GPIO34 AK11 EC_KBRST# 1 2 10K_0402_5%
R103
R243 1 2 10K_0402_5% PCH_GPIO35 K4 NC_2
+3V_PCH
No use can NC GPIO35 AH10 PCH_GPIO68 1 2 10K_0402_5%
TS_VSS1~4 R400
PCH_GPIO36 V8 NC_3
1 2 1K_0402_5% EC_SMI#
Can't PH SATA2GP / GPIO36 AK10 PD to GND
R261 @
PCH_GPIO37 M5 NC_4
Can't PH SATA3GP / GPIO37 P37
OPTIMUS_EN# N2 NC_5
No use PH 10K +3VS Optimus(L)/ non optimus(H) SLOAD / GPIO38
SATA2GP/GPIO36 & SATA3GP/GPIO37 PCH_GPIO39 M3
Sampled at Rising edge of PWROK. No use PH 10K +3VS SDATAOUT0 / GPIO39
No use PH 10K +3VS PCH_GPIO48 V13 BG2
Weak internal pull-down. SDATAOUT1 / GPIO48 VSS_NCTF_15
(weak internal pull-down is disabled SATA5GP&TEMP_ALERT# CRB PH 10K +3VS PCH_GPIO49 V3
SATA5GP / GPIO49 VSS_NCTF_16
BG48 9/15 Layout
after PLTRST# de-asserts) PCH_GPIO57 D6 BH3 request remove
No use PH +3VALW GPIO57 VSS_NCTF_17
NOTE: This signal should NOT be Test point
BH47
pulled high when strap is sampled VSS_NCTF_18 They will route
+3VS A4 BJ4
VSS_NCTF_1 VSS_NCTF_19 by itself
UMA@ 9/15 Layout A44 BJ44
R427 1 2 10K_0402_5% OPTIMUS_EN# VSS_NCTF_2 VSS_NCTF_20
+3VS request remove A45 BJ45
PX@ VSS_NCTF_3 VSS_NCTF_21
Test point

NCTF
R112 1 2 10K_0402_5% PCH_GPIO0 R426 1 2 10K_0402_5% A46 BJ46
They will route VSS_NCTF_4 VSS_NCTF_22
R402 1 2 10K_0402_5% PCH_GPIO1 A5 BJ5
3 by itself VSS_NCTF_5 VSS_NCTF_23 3
R70 1 2 10K_0402_5% PCH_GPIO6 GPIO38 A6 BJ6
VSS_NCTF_6 VSS_NCTF_24
R115 1 2 10K_0402_5% MSATA_DET#
OPTIMUS_EN# B3 C2
VSS_NCTF_7 VSS_NCTF_25
R71 1 2 10K_0402_5% VGA_PWRGD_R
* Muxless 0 B47 C48
VSS_NCTF_8 VSS_NCTF_26
R419 1 2 10K_0402_5% PCH_GPIO39 nonMuxless 1 BD1 D1
VSS_NCTF_9 VSS_NCTF_27
R97 1 2 10K_0402_5% BT_DISABLE BD49 D49
VSS_NCTF_10 VSS_NCTF_28
R416 1 2 10K_0402_5% PCH_BT_ON# BE1 E1
+3VS +3VS VSS_NCTF_11 VSS_NCTF_29
R128 1 2 10K_0402_5% PCH_GPIO48 BE49 E49
VSS_NCTF_12 VSS_NCTF_30
1

R111 1 2 10K_0402_5% PCH_GPIO49 BF1 F1


R244 R245 VSS_NCTF_13 VSS_NCTF_31
10K_0402_5% 10K_0402_5% BF49 F49
+3V_PCH VSS_NCTF_14 VSS_NCTF_32
@ @
PCH_GPIO37 PCH_GPIO36
2

PANTHER_FCBGA989
1

R376 1 2 10K_0402_5% PCH_GPIO12


<BOM Structure>
R412 1 2 1K_0402_5% PCH_GPIO15 R881 R552
10K_0402_5% 10K_0402_5%
R52 1 2 10K_0402_5% PCH_GPIO57
2

R92 1 2 10K_0402_5% PCH_GPIO24

For DDR3L control

4
GPIO36/GPIO37 is Strap functionality 4
R63 @ 0_0402_5%
1 2 PCH_GPIO24 that requires internal pull down to be sampled at rising PWROK.
[46] DDR3L_EN#
When uses as SATA2GP/SATA3GP for mechanical presence detect
-use a external pull up 150K-200K ohm to Vcc3_3
When used as GP input
GPIO24 Unmultiplexed -ensure GPI is not driven high during strap sampling window
NOTE: GPIO24 configuration When Unused as GPIO or SATA*GP
register bits are not cleared by
Security Classification Compal Secret Data Compal Electronics, Inc.
-use 8.2K-10K pull-down 2011/06/24 2012/07/12 Title
CF9h reset event. check list page 47 Issued Date Deciphered Date PCH (6/9) GPIO, CPU, MISC
CRB1.0 PH10K to +3VALW THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Sherry and Royal
Date: Thursday, February 02, 2012 Sheet 18 of 55
A B C D E
A B C D E

Thermal Senser share with VCCADAC power rail


so can't remove this power

+1.05VS_VTT U13G POWER +3VS


L16
1300mA Place Near U48 MBK1608221YZF_2P
+1.05VS_VTT AA23 U48 +VCCADAC 2 1
AC23 VCCCORE[1] VCCADAC
VCCCORE[2] 1mA 1 1 1

10U_0603_6.3V6M
C106

1U_0402_6.3V6K
C64

1U_0402_6.3V6K
C67

1U_0402_6.3V6K
C75

CRT
1 1 1 1 AD21 C53 C54 C40
AD23 VCCCORE[3] U47 10U_0603_6.3V6M
AF21 VCCCORE[4] VSSADAC 0.01U_0402_16V7K 0.1U_0402_16V7K

VCC CORE
AF23 VCCCORE[5] 2 2 2
1 2 2 2 2 AG21 VCCCORE[6] +3VS 1
AG23 VCCCORE[7]
AG24 VCCCORE[8] AK36 +VCCA_LVDS 1 2
AG26 VCCCORE[9] VCCALVDS R442
Place Near AA23 AG27 VCCCORE[10] 1mA AK37 0_0603_5%
AG29 VCCCORE[11] VSSALVDS
AJ23 VCCCORE[12]

LVDS
AJ26 VCCCORE[13] AM37
AJ27 VCCCORE[14] VCCTX_LVDS[1]
AJ29 VCCCORE[15] AM38 L27 +1.8VS
AJ31 VCCCORE[16] VCCTX_LVDS[2] 0.1UH_MLF1608DR10KT_10%_1608
VCCCORE[17] AP36
Place Near AM37 +VCCTX_LVDS 2 1
+1.05VS_VTT 60mA VCCTX_LVDS[3] 1 1

1
AP37
AN19 VCCTX_LVDS[4] C91 C92 C108
VCCIO[28] 0.1uH inductor, 200mA
0.01U_0402_16V7K 22U_0603_6.3V6K

2
2 2
PAD T31 @ +VCCAPLLEXP BJ22 +3VS
VCCAPLLEXP 266mA 0.01U_0402_16V7K
On-Die PLL Voltage Regulator V33

HVCMOS

AN16 VCC3_3[6]
VCCIO[15] Place Near V33
H On-Die PLL voltage regulator AN17
1
enable VCCIO[16] V34
I/O Buffer Voltage
C61
VCC3_3[7]
VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2 AN21 2925mA 2
0.1U_0402_16V7K
,VCCAPLLSATA VCCIO[17]
PCH Power Rail Table
AN26 +1.5VS
VCCIO[18]
S0 Iccmax
AN27 AT16 Voltage Rail Voltage
VCCIO[19] VCCVRM[3] Current(A)
+1.05VS_VTT AP21 +1.05VS_VTT
Internal PLL and VRM(+1.5VS)
2 VCCIO[20] 2
AP23 AT20
V_PROC_IO 1.05 0.001 Processor I/F
VCCIO[21] VCCDMI[1]
1 DMI buffer logic

DMI
10U_0603_6.3V6M
C80

1U_0402_6.3V6K
C87

1U_0402_6.3V6K
C88

1U_0402_6.3V6K
C90

1U_0402_6.3V6K
C86

1 1 1 1 1 AP24 C96 V5REF 5 0.001 PCH Core Well Reference Voltage


VCCIO
VCCIO[22] 1U_0402_6.3V6K
AP26 20mA AB36
VCCIO[23] VCCIO[1] 2 place
2 2 2 2 2 AT24
V5REF_Sus 5 0.001 Suspend Well Reference Voltag
VCCIO[24] near AT20 Core Well I/O Buffer
AN33
Vcc3_3 3.3 0.266 I/O Buffer Voltage
Place Near AN16,AN21,AN33
VCCIO[25] 190mA Display DAC Analog Power. This power is
AN34 AG16 VccADAC 3.3 0.001
+3VS VCCIO[26] VCCPNAND[1] +1.8VS
VccDFTERM should PH +1.8VS or +3VS supplied by the core well.
NAND / SPI

BH29 AG17 VccADPLLA 1.05 0.08 Display PLL A power


VCC3_3[3] VCCPNAND[2]
1 1
C107 C81
0.1U_0402_16V7K +1.5VS AJ16 0.1U_0402_16V7K
VCCPNAND[3] VccADPLLB 1.05 0.08 Display PLL B power
Place Near 2 AP16 2 place
BH29 VCCVRM[2] AJ17
VCCPNAND[4] near AG16 VccCore 1.05 1.3 Internal Logic Voltage
PAD @ +1.05VS_VCCAPLL_FDI BG6
T17 VCCFDIPLL
+1.05VS_VTT +3VS
VccDMI 1.05 0.042 DMI Buffer Voltage
AP17
VCCIO[27]
FDI

V1 For SPI control logi VccIO 1.05 2.925 Core Well I/O buffers
VCCSPI
1 AU20 20mA 1 1.05 V Supply for Intel R Management
C98 VCCDMI[2]
VccASW 1.05 1.01 Engine and Integrated LAN
1U_0402_6.3V6K C60
3 PANTHER_FCBGA989 1U_0402_6.3V6K 3
2 Near 2
VccSPI 3.3 0.02 3.3 V Supply for SPI Controller Logic
AU20 <BOM Structure>

Trace 20mil VccDSW 3.3 0.003 3.3v supply for Deep S4/S5 well
On-Die PLL Voltage Regulator

H On-Die PLL voltage regulator VccpNAND 1.8 0.19 1.8V power supply for DF_TVS
enable
VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2 VccRTC 3.3 6 uA Battery Voltage
,VCCAPLLSATA
VccSus3_3 3.3 0.266 Suspend Well I/O Buffer Voltage
High Definition Audio Controller Suspend
VccSusHDA 3.3 / 1.5 0.01 Voltage
1.8 V Internal PLL and VRMs (1.8 V for
VccVRM 1.8 / 1.5 0.16 Desktop)
VccCLKDMI 1.05 0.02 DMI Clock Buffer Voltage

VccSSC 1.05 0.095 Spread Modulators Power Supply

VccDIFFCLKN 1.05 0.055 Differential Clock Buffers Power Supply


Analog power supply for LVDS (Mobile
4
VccALVDS 3.3 0.001 Only) 4

Analog power supply for LVDS (Mobile


VccTX_LVDS 1.8 0.06 Only)

Security Classification Compal Secret Data Compal Electronics, Inc.


2011/06/24 2012/07/12 Title
Issued Date Deciphered Date PCH (7/9) PWR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Sherry and Royal
Date: Thursday, February 02, 2012 Sheet 19 of 55
A B C D E
A B C D E

+3VS +1.05VS_VTT
+1.05V analog R430 @
VCC3_3 = 266mA detal waiting for newest spec
internal clock PLL 0_0603_5% VCCDMI = 42mA detal waiting for newest spec
2 1 +VCCACLK
L23
Can NC
10UH_LB2012T100MR_20%
1 2 +3VS_VCC_CLKF33
1 1 +VCCDSW3_3 U13J POWER +1.05VS_VTT

1U_0402_6.3V6K
C55
1
C71 C47 AD49 N26
10U_0603_6.3V6M 0.1U_0402_16V7K VCCACLK VCCIO[29]
2 2 Not support Deep S4,S5 P26
1
connect to +3VALW 2 T16 VCCIO[30] C51
1
Near T16 VCCDSW3_3 P28 1U_0402_6.3V6K 1
VCCIO[31] 2
Near T38 +PCH_VCCDSW V12 3mA T27
PAD T14 @
DCPSUSBYP VCCIO[32]
T29
Near N26
suppied by internal +3VS_VCC_CLKF33 T38 VCCIO[33] +3V_PCH
1.05V VR must NC VCC3_3[5]
GPIO28 T23
PAD T30 @ +VCCAPLL_CPY_PCH BH23 VCCSUS3_3[7]
On-Die PLL Voltage Regulator 119mA

VCCAPLLDMI2 T24
VCCSUS3_3[8] 1 1
+3VALW AL29 C46 C45
H On-Die PLL voltage regulator +1.05VS_VTT VCCIO[14] V23 0.1U_0402_16V7K 0.1U_0402_16V7K

USB
enable R407 VCCSUS3_3[9]
Near T23 Near T24
0_0603_5% PAD T15 @ +VCCSUS1 AL24 V24 2 2 +3V_PCH +5V_PCH
VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2 2 1 +VCCDSW3_3 DCPSUS[3] VCCSUS3_3[10]
,VCCAPLLSATA P24
VCCSUS3_3[6]

1
+1.05VS_VTT
AA19 D23 R348
VCCASW[1] T26 RB751V-40_SOD323-2 100_0402_5%
+1.05VS_VTT AA21 1010mA VCCIO[34]
Near M26
+1.05VS_VTT VCCASW[2]

2
AA24 M26 +PCH_V5REF_SUS
L25 @ VCCASW[3] 1mA V5REF_SUS 1 2
+3VS +5VS

22U_0603_6.3V6K
C113

22U_0603_6.3V6K
C110
10UH_LB2012T100MR_20% AA26 C37

Clock and Miscellaneous


VCCASW[4]

1
1 2 +1.05VS_VCCA_A_DPL AN23 +VCCA_USBSUS @ T16 0.1U_0402_16V7K
AA27 DCPSUS[4] PAD
VCCASW[5]

1
220U_B2_2.5VM_R35
C118

1U_0402_6.3V6K
C103

1 AN24 +3V_PCH suppied by internal

2
AA29 VCCSUS3_3[1] D29 R130
1 VCCASW[6] 1.05V VR Must NC
1

+ @ 100_0402_5%
Near BD47 R301 AA31 RB751V-40_SOD323-2
VCCASW[7]
0_0603_5%

2
2 2 AC26 P34 +PCH_V5REF_RUN
2
1 1 1
VCCASW[8] 1mA V5REF +3V_PCH 2
2

1
1U_0402_6.3V6K
C56

1U_0402_6.3V6K
C73

1U_0402_6.3V6K
C66
AC27
VCCASW[9] N20 C42

PCI/GPIO/LPC
1 2 +1.05VS_VCCA_B_DPL AC29 VCCSUS3_3[2] 1U_0402_6.3V6K
1

2
L26 2 2 2 VCCASW[10] N22 C38
VCCSUS3_3[3]
1U_0402_6.3V6K
C104

10UH_LB2012T100MR_20% AC31 1U_0402_6.3V6K


VCCASW[11]
22U_0805_6.3V6M
C187

1 1 1 P20 Near P34


VCCSUS3_3[4] 2
220U_B2_2.5VM_R35
C112

Near BF47 AD29 Near N20


+ VCCASW[12] P22 +3VS
AD31 VCCSUS3_3[5]
2 2 Near AA19 VCCASW[13]
2 W21 AA16
VCCASW[14] VCC3_3[1]
1 1 1
W23 W16 C471 C62 C49
VCCASW[15] VCC3_3[8] 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K
W24 T34
VCCASW[16] VCC3_3[4] 2 Place near 2 Place near 2 Place near
W26 AJ2 AA16,W16 T34
VCCASW[17]
W29
VCCASW[18]
W31 AJ2 +1.05VS_VTT
VCCASW[19] VCC3_3[2]
W33
VCCASW[20] AF13
Near M6 VCCIO[5] Near AH13,AH14,AF13
1
2 1 +VCCRTCEXT N16
C39 0.1U_0402_16V7K DCPRTC AH13 C76
VCCIO[12] 1U_0402_6.3V6K
Y49 AH14 2
+1.5VS VCCVRM[4] VCCIO[13]

3 AF14
GPIO28 3
+1.05VS_VCCA_A_DPL BD47 VCCIO[6]
80mA On-Die PLL Voltage Regulator

SATA

VCCADPLLA AK1 +VCCSATAPLL @ T29 PAD
+1.05VS_VTT
Place +1.05VS_VCCA_B_DPL BF47 VCCAPLLSATA +1.5VS
near AG33 VCCADPLLB 80mA H On-Die PLL voltage regulator
AF11 enable
AF17 VCCVRM[1]
+1.05VS_VTT AF33 VCCIO[7] VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2
1 C77 1 C79 AF34 VCCIO[8] AC16 +1.05VS_VTT ,VCCAPLLSATA
1U_0402_6.3V6K 1U_0402_6.3V6K AG34 VCCIO[9] 55mA VCCIO[2]
+1.05VS_VTT VCCIO[11] AC17
VCCIO[3] Near AC16
Place Place 1 C72
2 2 1U_0402_6.3V6K AG33 AD17
near AF17 near AG33 VCCIO[10] VCCIO[4] 1
1 C74 95mA C68
Place 1U_0402_6.3V6K 1U_0402_6.3V6K
2 2 1 +VCCSST V16
near AF33, Near V16 C57 0.1U_0402_16V7K DCPSST +1.05VS_VTT 2
2
AF34,AG34 PAD T13 @ +1.05VM_VCCSUS T17 T21
suppied by internal V19 DCPSUS[1] VCCASW[22]
DCPSUS[2]
MISC

1.05V VR Must NC
+1.05VS_VTT V21
VCCASW[23]
1mA
CPU

BJ8
V_PROC_IO T19
VCCASW[21]
1 1 1
+RTCBATT +3V_PCH
4.7U_0603_6.3V6K
C114

0.1U_0402_16V7K
C109

0.1U_0402_16V7K
C111

Need +3VALW and 0.1U close PCH


RTC

A22 P32
10mAVCCSUSHDA
HDA

2 2 2 VCCRTC
isolation between SSC (AG33)
1U_0402_6.3V6K
C445

0.1U_0402_16V7K
C450

0.1U_0402_16V7K
C453

1 1 1 1
and DIFFCLKN(AF33,AF34,AG34) PANTHER_FCBGA989 C41
4 0.1U_0402_16V4Z 4
18mil width(DIFFCLKN)
<BOM Structure>
10mil (SSC) Place 2 2 2 2

near BJ8 Near P32


Near A22
Security Classification Compal Secret Data Compal Electronics, Inc.
2011/06/24 2012/07/12 Title
Issued Date Deciphered Date PCH (8/9) PWR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Sherry and Royal
Date: Thursday, February 02, 2012 Sheet 20 of 55
A B C D E
A B C D E

U13I

AY4 H46
AY42 VSS[159] VSS[259] K18
AY46 VSS[160] VSS[260] K26
AY8 VSS[161] VSS[261] K39
B11 VSS[162] VSS[262] K46
1 U13H B15 VSS[163] VSS[263] K7 1
H5 B19 VSS[164] VSS[264] L18
VSS[0] B23 VSS[165] VSS[265] L2
AA17 AK38 B27 VSS[166] VSS[266] L20
AA2 VSS[1] VSS[80] AK4 B31 VSS[167] VSS[267] L26
AA3 VSS[2] VSS[81] AK42 B35 VSS[168] VSS[268] L28
AA33 VSS[3] VSS[82] AK46 B39 VSS[169] VSS[269] L36
AA34 VSS[4] VSS[83] AK8 B7 VSS[170] VSS[270] L48
AB11 VSS[5] VSS[84] AL16 F45 VSS[171] VSS[271] M12
AB14 VSS[6] VSS[85] AL17 BB12 VSS[172] VSS[272] P16
AB39 VSS[7] VSS[86] AL19 BB16 VSS[173] VSS[273] M18
AB4 VSS[8] VSS[87] AL2 BB20 VSS[174] VSS[274] M22
AB43 VSS[9] VSS[88] AL21 BB22 VSS[175] VSS[275] M24
AB5 VSS[10] VSS[89] AL23 BB24 VSS[176] VSS[276] M30
AB7 VSS[11] VSS[90] AL26 BB28 VSS[177] VSS[277] M32
AC19 VSS[12] VSS[91] AL27 BB30 VSS[178] VSS[278] M34
AC2 VSS[13] VSS[92] AL31 BB38 VSS[179] VSS[279] M38
AC21 VSS[14] VSS[93] AL33 BB4 VSS[180] VSS[280] M4
AC24 VSS[15] VSS[94] AL34 BB46 VSS[181] VSS[281] M42
AC33 VSS[16] VSS[95] AL48 BC14 VSS[182] VSS[282] M46
AC34 VSS[17] VSS[96] AM11 BC18 VSS[183] VSS[283] M8
AC48 VSS[18] VSS[97] AM14 BC2 VSS[184] VSS[284] N18
AD10 VSS[19] VSS[98] AM36 BC22 VSS[185] VSS[285] P30
AD11 VSS[20] VSS[99] AM39 BC26 VSS[186] VSS[286] N47
AD12 VSS[21] VSS[100] AM43 BC32 VSS[187] VSS[287] P11
AD13 VSS[22] VSS[101] AM45 BC34 VSS[188] VSS[288] P18
AD19 VSS[23] VSS[102] AM46 BC36 VSS[189] VSS[289] T33
AD24 VSS[24] VSS[103] AM7 BC40 VSS[190] VSS[290] P40
AD26 VSS[25] VSS[104] AN2 BC42 VSS[191] VSS[291] P43
AD27 VSS[26] VSS[105] AN29 BC48 VSS[192] VSS[292] P47
AD33 VSS[27] VSS[106] AN3 BD46 VSS[193] VSS[293] P7
AD34 VSS[28] VSS[107] AN31 BD5 VSS[194] VSS[294] R2
2 AD36 VSS[29] VSS[108] AP12 BE22 VSS[195] VSS[295] R48 2
AD37 VSS[30] VSS[109] AP19 BE26 VSS[196] VSS[296] T12
AD38 VSS[31] VSS[110] AP28 BE40 VSS[197] VSS[297] T31
AD39 VSS[32] VSS[111] AP30 BF10 VSS[198] VSS[298] T37
AD4 VSS[33] VSS[112] AP32 BF12 VSS[199] VSS[299] T4
AD40 VSS[34] VSS[113] AP38 BF16 VSS[200] VSS[300] W34
AD42 VSS[35] VSS[114] AP4 BF20 VSS[201] VSS[301] T46
AD43 VSS[36] VSS[115] AP42 BF22 VSS[202] VSS[302] T47
AD45 VSS[37] VSS[116] AP46 BF24 VSS[203] VSS[303] T8
AD46 VSS[38] VSS[117] AP8 BF26 VSS[204] VSS[304] V11
AD8 VSS[39] VSS[118] AR2 BF28 VSS[205] VSS[305] V17
AE2 VSS[40] VSS[119] AR48 BD3 VSS[206] VSS[306] V26
AE3 VSS[41] VSS[120] AT11 BF30 VSS[207] VSS[307] V27
AF10 VSS[42] VSS[121] AT13 BF38 VSS[208] VSS[308] V29
AF12 VSS[43] VSS[122] AT18 BF40 VSS[209] VSS[309] V31
AD14 VSS[44] VSS[123] AT22 BF8 VSS[210] VSS[310] V36
AD16 VSS[45] VSS[124] AT26 BG17 VSS[211] VSS[311] V39
AF16 VSS[46] VSS[125] AT28 BG21 VSS[212] VSS[312] V43
AF19 VSS[47] VSS[126] AT30 BG33 VSS[213] VSS[313] V7
AF24 VSS[48] VSS[127] AT32 BG44 VSS[214] VSS[314] W17
AF26 VSS[49] VSS[128] AT34 BG8 VSS[215] VSS[315] W19
AF27 VSS[50] VSS[129] AT39 BH11 VSS[216] VSS[316] W2
AF29 VSS[51] VSS[130] AT42 BH15 VSS[217] VSS[317] W27
AF31 VSS[52] VSS[131] AT46 BH17 VSS[218] VSS[318] W48
AF38 VSS[53] VSS[132] AT7 BH19 VSS[219] VSS[319] Y12
AF4 VSS[54] VSS[133] AU24 H10 VSS[220] VSS[320] Y38
AF42 VSS[55] VSS[134] AU30 BH27 VSS[221] VSS[321] Y4
AF46 VSS[56] VSS[135] AV16 BH31 VSS[222] VSS[322] Y42
AF5 VSS[57] VSS[136] AV20 BH33 VSS[223] VSS[323] Y46
AF7 VSS[58] VSS[137] AV24 BH35 VSS[224] VSS[324] Y8
AF8 VSS[59] VSS[138] AV30 BH39 VSS[225] VSS[325] BG29
AG19 VSS[60] VSS[139] AV38 BH43 VSS[226] VSS[328] N24
3 AG2 VSS[61] VSS[140] AV4 BH7 VSS[227] VSS[329] AJ3 3
AG31 VSS[62] VSS[141] AV43 D3 VSS[228] VSS[330] AD47
AG48 VSS[63] VSS[142] AV8 D12 VSS[229] VSS[331] B43
AH11 VSS[64] VSS[143] AW14 D16 VSS[230] VSS[333] BE10
AH3 VSS[65] VSS[144] AW18 D18 VSS[231] VSS[334] BG41
AH36 VSS[66] VSS[145] AW2 D22 VSS[232] VSS[335] G14
AH39 VSS[67] VSS[146] AW22 D24 VSS[233] VSS[337] H16
AH40 VSS[68] VSS[147] AW26 D26 VSS[234] VSS[338] T36
AH42 VSS[69] VSS[148] AW28 D30 VSS[235] VSS[340] BG22
AH46 VSS[70] VSS[149] AW32 D32 VSS[236] VSS[342] BG24
AH7 VSS[71] VSS[150] AW34 D34 VSS[237] VSS[343] C22
AJ19 VSS[72] VSS[151] AW36 D38 VSS[238] VSS[344] AP13
AJ21 VSS[73] VSS[152] AW40 D42 VSS[239] VSS[345] M14
AJ24 VSS[74] VSS[153] AW48 D8 VSS[240] VSS[346] AP3
AJ33 VSS[75] VSS[154] AV11 E18 VSS[241] VSS[347] AP1
AJ34 VSS[76] VSS[155] AY12 E26 VSS[242] VSS[348] BE16
AK12 VSS[77] VSS[156] AY22 G18 VSS[243] VSS[349] BC16
AK3 VSS[78] VSS[157] AY28 G20 VSS[244] VSS[350] BG28
VSS[79] VSS[158] G26 VSS[245] VSS[351] BJ28
PANTHER_FCBGA989 G28 VSS[246] VSS[352]
G36 VSS[247]
<BOM Structure> VSS[248]
G48
H12 VSS[249]
H18 VSS[250]
H22 VSS[251]
H24 VSS[252]
H26 VSS[253]
H30 VSS[254]
H32 VSS[255]
H34 VSS[256]
F3 VSS[257]
VSS[258]
4 4

PANTHER_FCBGA989
<BOM Structure>

Security Classification Compal Secret Data Compal Electronics, Inc.


2011/06/24 2012/07/12 Title
Issued Date Deciphered Date PCH (9/9) VSS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Sherry and Royal
Date: Thursday, February 02, 2012 Sheet 21 of 55
A B C D E
5 4 3 2 1

PEG_HTX_GRX_P[15..0] U8A PEG_GTX_HRX_P[0..15]


[5] PEG_HTX_C_GRX_P[15..0] PEG_GTX_HRX_P[0..15] [5]
U8F
PEG_HTX_GRX_N[15..0] PEG_GTX_HRX_N[0..15]
[5] PEG_HTX_C_GRX_N[15..0] PEG_GTX_HRX_N[0..15] [5]

LVDS CONTROL AB11


VARY_BL AB12
PEG_HTX_C_GRX_P15 AF30 AH30 PEG_GTX_HRX_P15 DIGON
PEG_HTX_C_GRX_N15AE31 PCIE_RX0P PCIE_TX0P AG31 PEG_GTX_HRX_N15
PCIE_RX0N PCIE_TX0N
D D
PEG_HTX_C_GRX_P14 AE29 AG29 PEG_GTX_HRX_P14 AH20
PEG_HTX_C_GRX_N14 AD28 PCIE_RX1P PCIE_TX1P AF28 PEG_GTX_HRX_N14 TXCLK_UP_DPF3P AJ19
PCIE_RX1N PCIE_TX1N TXCLK_UN_DPF3N
AL21
PEG_HTX_C_GRX_P13 AD30 AF27 PEG_GTX_HRX_P13 TXOUT_U0P_DPF2P AK20
PEG_HTX_C_GRX_N13 AC31 PCIE_RX2P PCIE_TX2P AF26 PEG_GTX_HRX_N13 TXOUT_U0N_DPF2N
PCIE_RX2N PCIE_TX2N AH22
TXOUT_U1P_DPF1P AJ21
PEG_HTX_C_GRX_P12 AC29 AD27 PEG_GTX_HRX_P12 TXOUT_U1N_DPF1N
PEG_HTX_C_GRX_N12 AB28 PCIE_RX3P PCIE_TX3P AD26 PEG_GTX_HRX_N12 AL23
PCIE_RX3N PCIE_TX3N TXOUT_U2P_DPF0P AK22
TXOUT_U2N_DPF0N

PCI EXPRESS INTERFACE


PEG_HTX_C_GRX_P11 AB30 AC25 PEG_GTX_HRX_P11 AK24
PEG_HTX_C_GRX_N11 AA31 PCIE_RX4P PCIE_TX4P AB25 PEG_GTX_HRX_N11 TXOUT_U3P AJ23
PCIE_RX4N PCIE_TX4N TXOUT_U3N

PEG_HTX_C_GRX_P10 AA29 Y23 PEG_GTX_HRX_P10 LVTMDP


PEG_HTX_C_GRX_N10 Y28 PCIE_RX5P PCIE_TX5P Y24 PEG_GTX_HRX_N10
PCIE_RX5N PCIE_TX5N AL15