Proceedings of the 2010 IEEE Students Technology Symposium

3-4 April 2010, IIT Kharagpur

Low Voltage Low Power Pipelined ADC for Video

Applications
Hameed Zohaib Samad #1, Patri Sriharirao #2, K. Sarangam #3
#Department of Electronics and Communication Engineering
National Institute of Technology Warangal, India
1
zohaibhameed007@gmail.com
2
patri@nitw.ac.in
3
sarangam.nitw@gmail.com

Abstract In todays world application of battery powered (Channel length Modulation) = 0

analog and mixed mode electronic device requires designing KP (Transconductance) = 20A/V2
analog circuit to operate at low voltage levels. There are many (Mobility) = 600cm2/V.s
issues which are involved in implementing low voltage circuits Body Effect = 0
such as reduced noise immunity, greater delay and poor
Surface Potential = 0.6V
linearity. There is a need to use certain MOSFET techniques so
that the MOSFET can be used even in sub-threshold region Vth (Threshold voltage) = 0V
without any significant change in its performance. Certain
techniques have been put forward corresponding to low voltage
analog circuits using CMOS Technology to be used in variety of
applications. Accordingly we propose to design a 10 bits
30Msample/s CMOS Analog to Digital Converter (ADC) using a
1.5-bits/stage pipeline architecture for high speed signal
processing to be used in video related applications

I. INTRODUCTION
With the growing demand for low power mixed signal
integrated circuits for portable or non-portable high
performance systems, analog circuit designers are challenged
with making analog circuit blocks with lower power
consumption with little or no performance degradation. A
possible solution to get higher dc voltage on chip is voltage
multiplication. This technique is noisy and is not compatible
with sensitive analog circuits. Circuit operation at reduced
voltage is a common practice adopted to reduce power Fig. 1. Current Mirror Circuit using N-type enhancement MOSFET
consumption. However, the circuit performance degrades and
one gets low circuit bandwidth and low voltage swings at low Fig.1 shows a current mirror circuit in which a voltage of
voltages. Scaling down the threshold voltage of MOSFETs 3V ensures the current mirror operation to take place
compensates for this performance loss to some degree, but this smoothly. The minimum required input voltage so that
result in increased static power dissipation [1]. current mirroring operation takes place can be obtained from
Low voltage analog circuit design techniques differ the following equations.
considerably from those of high voltage analog circuit design. ID = [Kn (VGS VTn)2 (1+ VDS)] / 2
This generates a need for adaptation of alternative design
techniques to suit the low voltage environments. This paper is For the above circuit shown in Fig.1
aimed at providing a comprehensive treatment of all possible VDS = VGS = VTn + 2Iref / Kn 1 VDS
Low voltage design techniques prevalent today for analog Since 0 and VTn = 0 and Kn= 20A/V2
circuits. VDS = 2.236 V
For the current to be mirrored, a voltage greater than
II. CRITICAL ISSUES 2.236V has to be applied where in Fig.1 VDS2 = 3V causes 50
There are certain issues involved when a CMOS circuit is A to appear at the output.
made to work in sub threshold conditions. This could be Considering a case where VDS2 < 2V
explained easily by considering the following analysis done in
Pspice by taking an example of Current Mirror Circuit. Some
of the parameters as defined in Pspice are as follows

TE01025 978-1-4244-5974-2/10/$26.00 2010 IEEE 161

 Proceedings of the 2010 IEEE Students Technology Symposium
3-4 April 2010, IIT Kharagpur

The real solutions to the threshold voltage problem come

from an intimate knowledge of the technology, a general
principle that has been consistent throughout the history of
electronics. Although, the technology cannot be changed,
there are ways to use existing technology that provide the
desired results on a reliable basis. For example, it is well
known that a reverse bias on the well-source junction will
cause the threshold voltage to increase. Similarly, a forward
bias on this junction will cause the threshold voltage to
decrease [3].

Fig. 2. Effect of VDS on current mirroring

From Fig.2 one can easily see that to obtain perfect current
mirroring operation a minimum amount of voltage is
necessary to be applied which is dependent upon the
magnitude of the current. Thus one can infer that for higher
value of current more amount of voltage is required to be
applied hence making it impossible for higher current to work Fig 3. Bulk-Driven MOSFET with forward bias.
at low voltages. Fig. 3 shows a Bulk Driven MOSFET with a forward bias
There is a need to employ certain low voltage analog circuit applied to the bulk-source terminal. A positive bias of 555mV
design techniques which assists in low voltage operation of will reduce the threshold voltage and will allow the circuit to
analog circuits without affecting the performance. be used in Low Voltage applications
III. METHODS OF ACHIEVING LOW VOLTAGE ANALOG D. The Channel JFET:
CIRCUITS The most significant solution to the threshold voltage
Some of the methods of achieving low voltage operation in limitation is the channel JFET. The gate-source potential is
analog circuits are as follows taken to a dc voltage that is sufficient to turn the MOSFET on.
The drain is connected normally and the signal is applied
A. The Lateral BJT: between the bulk and the source. The current flowing from the
The solution to the threshold limitation must remove or source to drain is modulated by the reverse bias on the bulk-
circumvent the requirement to provide at least Vt volts to turn channel junction. The result is a junction field-effect transistor
on the MOSFET. One possible solution is the lateral BJT. with the bulk as the signal input (gate). Consequently a high-
This solution has the added advantage of much less 1/f noise input impedance depletion device that requires no dc bulk-
because current flow is in the bulk of the material. However, source voltage for current flow result.
the lateral BJT requires turn on voltages of 0.6 to 0.7V which
do not provide that much advantage over the MOSFET. E. Cascode Technique:
However, an additional advantage of the lateral BJT is that it Owing to channel length modulation because of shrinking
has a low value of VCE(sat) which is also important for low devices the output impedance of the MOSFET is also
voltage analog circuits [2]. becoming smaller. For high gain one needs higher output
impedance and short channel MOSFETs cannot provide high
B. Subthreshold Operation: gain structure. The use of cascode structure increases the gain
A second solution is subthreshold operation of the but it decreases the output swing at the same time.
MOSFET. In this realm of operation, the MOSFET conducts To overcome the limited input common mode voltage and
currents at voltages less than the threshold voltage. In addition, possibly improve the output swing of the conventional
the value of VDS(sat) is extremely small. The primary cascode, a structure called folded cascode is used. The main
disadvantage of subthreshold operation is small currents and advantage of the folded structure is the freedom of choosing
very low frequency response. There does appear to be an the bias voltage levels since it folds the two opposite type
important area in which subthreshold operation may provide devices instead of putting one device on the top of another
an impact in low voltage and low power circuits. component.
If the conventional cascode structure is changed to bias the
C. Forward-Biased Bulk-Source:
upper MOS device in a way that has less effect on the output

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voltage swing, the output impedance of the connection may be
increased with sufficient output swing at low supply voltage
[3]. One practice is to make both of the gates of MOS driven
by the input signal and share a single bias source. This
connection provides high output impedance due to source
degeneration to give high output gains. This composite
cascode approach, which combines the regular active devices
with weak inversion devices, is promising in low voltage low
power op amp design.
At low voltage operation the dynamic range is at premium.
Every effort must be made to maximize the value which
compels the use of rail-rail input and output stages. A well
known technique for realization of rail-rail input stage is to
place complimentary differential pairs in parallel. In order to
maintain the rail-to-rail capabilities of the input stage, the
complementary input pairs have to be loaded with folded
cascode instead of current mirrors
A major drawback with the rail-to-rail input stage is that its
transconductance varies by a factor of two over the common
mode input range. This drawback can be removed by using
biasing circuit at the input stage.
Technique Available Supply Voltage Power
BW Requirement Consumption
Sub-Threshold Low 2VT Low
MOSFET
Bulk-Driven Low 2VT High
MOSFET
Self Cascode Medium >2VT High
MOSFET
Table 1. Characteristic of various Techniques for CMOS Design
Table 1 clearly shows that there are tradeoffs involved in
most of the techniques used for Low Voltage Operation
between available bandwidth and power consumption [4].
Depending on the application of the circuit one should choose
a proper CMOS design techniques.
IV. ADC DESIGNING FOR LOW VOLTAGE APPLICATIONS
Some of the specifications of ADC which must be taken
care of before choosing ADC architecture are as follows
A. Resolution
The resolution of the converter indicates the number of
discrete values it can produce over the range of analog values.
The values are usually stored electronically in binary form, so
the resolution is usually expressed in bits. In consequence, the
number of discrete values available, or "levels", is usually a
power of two. For example, an ADC with a resolution of 10
bits can encode an analog input to one in 1024 different levels,
since 210 = 1024. The values can represent the ranges from 0
to 1023 (i.e. unsigned integer) or from -512 to 511 (i.e. signed
integer), depending on the application.
A survey of recently reported ADC was done to find out the
resolutions of recent Low Voltage Low power ADCs. Most
of the ADCs has offered the resolution in the range of 1mV.
TE01025
Proceedings of the 2010 IEEE Students Technology Symposium
3-4 April 2010, IIT Kharagpur
Hence to serve a wide range of applications resolution of 1mV
is chosen.
B. Accuracy
An ADC has several sources of errors. Quantization error is
present in any analog-to-digital conversion. There is also a so-
called aperture error which is due to a clock jitter and is
revealed when digitizing a time-variant signal (not a constant
value).
These errors are measured in a unit called the LSB (Least
Significant Bit). In the above example of a 10-bit ADC, an
error of one LSB is 1/1024 of the full signal range, or about
0.1%.
C. Reference Voltage and Number of Bits
To deliver 1mV resolution a reference voltage of around
2V-3V will require 10 bits. This can be easily shown by
(2V/1024) is almost equal to 1mV. Hence depending upon the
reference voltage the number of bits can be chosen and the
resolution is decided accordingly.
D. System Energy Requirements
A figure of merit for ADCs which takes into account the
sampling rate, number of bits and power dissipation is given
by
E = Power Dissipation
2N Sampling Frequency
This figure of merit (FOM) gives energy requirements of
the system which is measured in joules per quantization levels.
For most of the low voltage ADCs the Figure of Merit
(FOM) was in the range of fJ/QL [5, 6].
E. Integral Non-Linearity
Practical value of integral non-linearity should be less than
0.5LSB
F. Differential Non-Linearity
Practical value of differential non-linearity should be less
than 0.5LSB
V. ADC ARCHITECTURE FOR LOW VOLTAGE APPLICATIONS
A. Sample and Hold Circuit
A Sample and Hold Circuit is one of the simplest ADC
that can be implemented in a variety of applications. The
purpose of this circuit is to hold the analog value steady for a
short time while the converter or other following system
performs some operation that takes a little time. In most
circuits, a capacitor is used to store the analog voltage and an
electronic switch or gate is used to alternately connect and
disconnect the capacitor from the analog input. The rate at
which this switch is operated is the sampling rate of the
system. A linear type of ADC structure can be obtained by
using a sample and hold circuit.
B. Direct Conversion ADC/Flash ADC
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Direct conversion is very fast, capabble of gigahertz
sampling rates, but usually has only 8 bitss of resolution or
fewer, since the number of comparators needed, 2N - 1,
doubles with each additional bit, requiring a large expensive
circuit. This type of ADC has various disaddvantages as well
like high input capacitance, high power dissipation, and
glitches present on the output.
C. Successive Approximation ADC
Successive approximation works by consstantly comparing consumption and simplify the desig
the input voltage to the output of an internall digital to analog be followed by DAC (Digital to Analog A
converter (DAC, fed by the current value of tthe approximation) ADC (for usage in video application
until the best approximation is achieved. Att each step in this but lower resolution), digital correcttion logic, clock generator
process, a binary value of the approximation is stored in a and on-chip CMOS current/voltage references.r
successive approximation register (SAR). T The SAR uses a
reference voltage for comparison.
Though this type of ADC offers several advantages like
higher resolution possible etc this suffers froom the most basic
disadvantage like higher clock frequency is required. For
example to sample an output of 100 kHz at 332 bit resolution a
clock frequency of over 3.2 MHz is requiired which is not
practical in most of the cases. One cannot imagine the usage
of this type ADC for video applications where the frequency
is in tens of MHz.
D. Pipeline ADC
Pipeline ADC uses two or more steps of subranging. First,
a coarse conversion is done. In a second stepp, the difference to
the input signal is determined with a ddigital to analog
converter (DAC). This difference is then connverted finer, and
the results are combined in a last step. This ccan be considered
a refinement of the successive approximatioon ADC wherein
the feedback reference signal consists of the interim
conversion of a whole range of bits (for exxample, four bits)
rather than just the next-most-significant bit. By combining
the merits of the successive approximation and flash ADCs
this type is fast, has a high resolution, andd only requires a
small die size.
One can easily conclude from the above discussion that to
use an ADC in video applications [7, 8, 9]. P Pipelined ADC is
most desirable as it offers the advantages likee (i) Extra bits per
stage optimize correction for overlapping errrors. (ii) Separate
track-and-hold (T/H) amplifiers for each sttage release each
previous T/H to process the next incoming sample, enabling
conversion of multiple samples simultaneoously in different
stages of the pipeline. (iii) Lower power consumption (iv)
Higher-speed ADCs (fCONV < 100ns, typicall) entail less cost
and less design time and effort. (v) Feewer comparators
required compared to most of the architecturee
VI. DESIGNING PIPELINE ADC FOR LOW VOLLTAGE CIRCUITS IN
VIDEO APPLICATIONS
Msample/s CMOS
We intend to design a low bit (8 bits) 30M
Analog to Digital Converter (ADC) for hhigh speed signal
processing to be used in video related applications. We
propose to use a pipelined ADC architectuure as it offers a
good figure of merit (FoM). Amongg various ADC
architectures, pipelined converters could provide a good
TE01025
Proceedings of the 2010 IEEE Students Technology Symposium
3-4 April 2010, IIT Kharagpur
tradeoff between the performance and power consumption.
Recently reported results also in ndicate that the pipeline
architecture is cost-efficient and su uitable for the deep sub-
micrometer digital CMOS technolog gies. When the input signal
frequency is relatively high, the perfformance of the ADC will
be largely depended on its front-end d. So the ADC employs a
sample-and-hold (S/H) circuit to o increase the sampling
linearity [10]. The 1.5-bits/stage pipeline architecture is a very
popular architecture because it could c reduce the power
gn of the ADC. This may
Converter), Flash
ns ie for higher frequencies
VII. PIPELINE ARC CHITECTURE
Fig 4. Pipeline A/D Converter Block Diagram
m
The pipeline converter architectu ure consists of high speed,
low resolution cascaded stages to obtain
o a final conversion.
Figure 4 shows a block diagram off a general pipeline with k
stages. The output of each stage is digitally corrected to obtain
an accurate digital output. The advaantages of breaking down
the conversion into many stages are:
1. Key advantage is high conveersion rate. There is one
complete conversion per clock cyclee.
2. Overall chip size is reduced because
b the sample rate is
not governed by the number of pipeline
p stages. Thus the
number of stages can be chosen to minimize the size of the
chip. This naturally lowers the resoluution.
3. If chip space is available addittional stages can be added
for increased resolution.
A total of 9 stages with 1.5 bits/stage architecture is
adopted for this design. Two bits area required to implement
1.5 bits thus a raw output of 18 bits is digitally corrected to 10
bits. Each stage conversion occurs during two clock phases
[11]. This means that the componentts in each stage must settle
to its final value in half of the clocck period. Since alternate
stages work in different clock cyclles, as the sample moves
from one stage to the next, the preevious stage can take in a
new sample as the old sample is prrocessed by the following
stage. This models a parallel processsing system.
Fig 5. 1.5 bits/stage architecture
164

A signal input to a stage is transferreed onto the S/H
circuitry at the front end. Once held, the siggnal is sent to the
sub-ADC and gainstage simultaneously. Thhe sample is then
converted into a low-resolution digital word by the sub-ADC.
The sub-DAC then converts this digital word into an analog
signal. This analog signal is subtracted from the initial sample
creating a residue. This residue is sent to thhe following stage
and the process is repeated. Each stage proviides a 2 bit digital
word which is sent to the digital correction bblock. The digital
correction block contains a simple shift register and digital
correction logic circuits. The 1 bit redundanccy in each stage is
usually referred to as the 0.5 bit redundanccy, thus the term
1.5bits/stage. This redundancy compensatees for component
non-idealities. When the initial sample is cloocked through all
stages then the first digital output is availablle from the digital
correction block. During this latency perriod samples are
continually taken. Individual stage outputs are stored in the
shift register. Thus a complete 10 bit digital ooutput is available
on each successive clock cycle, after the initial latency period.
Fig.6 Concept of digital correction
In pipeline converters, there are about twwice as many bits
generated through the pipeline than requireed for the output.
These bits must be digitally corrected to prroduce the correct
output. There are many ways to implementt the final output
calculation. The concept is the same regarrdless of method
used. The difference lies in the designer'ss choice of logic
circuitry to perform a particular function. T
This design breaks
down the operations into simple logic functtions. These logic
functions are built inside the correction logic circuit. The
concept behind the correction logic is repressented in figure 6.
The outputs of the earlier stages are kept inn the shift register
until stage N provides an output. The collected data bits are
then added using 1-bit overlap methodology,, shown in figure6.
VIII. CONCLUSION
The solution to the threshold limitation is to remove or
circumvent the requirement to provide at leaast Vt volts to turn
on the MOSFET. This paper has focused on circuit design
techniques that would permit the implemenntation of analog
circuits at low power supply voltages in standard CMOS
technology. The primary limitations of analoog circuits at low
voltage are a large threshold voltage, largge channel length
modulation, and poor analog modeling.. The last two
limitations are caused by short-channel technology. The
threshold voltage limitation is solved by the lateral BJT, sub-
TE01025
Proceedings of the 2010 IEEE Students Technology Symposium
3-4 April 2010, IIT Kharagpur
threshold operation, forward biasing g the bulk-source junction
and the channel JFET.
Advantages of different ADCs can be together used in
architecture (Pipeline) where paralleel processing can be used.
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