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Vacuum Discrete
Tubes Transistors
vT = VDC + vsig
iT = I DC -+Risig
Resistance and conductance and G with same
subscripts will denote reciprocal quantities. The most
convenient form will be used within expressions.
1 1
Gx = and g =
Rx r
Problem-Solving Approach
Make a clear problem statement.
List known information and given data.
Define the unknowns required to solve the problem.
List assumptions.
Develop an approach to the solution.
Perform the analysis based on the approach.
Check the results and the assumptions.
Has the problem been solved? Have all the unknowns been found?
Is the math correct? Have the assumptions been satisfied?
Evaluate the solution.
Do the results satisfy reasonableness constraints?
Are the values realizable?
Use computer-aided analysis to verify hand analysis
What are Reasonable Numbers?
If the power suppy is 10 V, a calculated DC bias value of 15 V (not within
the range of the power supply voltages) is unreasonable.
Generally, our bias current levels will be between 1 microamp and a few
hundred milliamps.
A calculated bias current of 3.2 amps is probably unreasonable and should
be reexamined.
Peak-to-peak ac voltages should be within the power supply voltage range.
A calculated component value that is unrealistic should be rechecked. For
example, a resistance equal to 0.013 ohms or 1012 ohms
Given the inherent variations in most electronic components, three
significant digits are adequate for representation of results. Three
significant digits are used throughout the text.
Circuit Theory Review: Voltage Division
v1 = ii R1 and v 2 = ii R2
Applying KVL to the loop,
v i = v1 + v 2 = ii (R1 + R2 )
vi
and ii =
R1 + R2
Combining these yields the basic voltage division formula:
R1 R2
v1 = v i v2 = vi
R1 + R2 R1 + R2
Circuit Theory Review: Voltage Division (cont.)
8 k
v1 = 10 V = 8.00 V
8 k + 2 k
2 k
v 2 = 10 V = 2.00 V
8 k + 2 k
Design Note: Voltage division only applies when both resistors are
carrying the same current.
Circuit Theory Review: Current Division
vi vi
ii = i1 + i2 where i1 = andi2 =
R1 R2
Combining and solving for vi,
1 R1 R2
v i = ii = ii = ii (R1 || R2 )
1 1 R1 + R2
+
R1 R2
Combining these yields the basic current division formula:
R2 R1
i1 = ii i2 = ii
R1 + R2 R1 + R2
Circuit Theory Review: Current
Division (cont.)
3 k
i1 = 5 ma = 3.00 mA
2 k + 3 k
2 k
i 2 = 5 ma = 2.00 mA
2 k + 3 k
Design Note: Current division only applies when the same voltage
appears across both resistors.
Circuit Theory Review: Thvenin and Norton
Equivalent Circuits
Thvenin
Norton
Circuit Theory Review: Find the Thvenin
Equivalent Voltage
G1 ( +1)v i = G1 ( +1) + GS v o
v th = 0.718v i
Circuit Theory Review: Find the Thvenin
Equivalent Resistance
Applying KCL,
i x = -i1 - i1 + G S v x
= G1v x + G1v x + G S v x
= G1 ( + 1) + G S v x
vx 1 R1
Rth = = = RS
i x G1 ( + 1) + G S +1
R1 20 k
Rth = RS = 1 k = 1 k 392 = 282
+1 50 + 1
Circuit Theory Review: Find the Norton Equivalent
Circuit
Applying KCL,
in = i1 + i1
= G1v i + G1vi
= G1 ( +1)v i
v i ( +1) Short circuit at the output
= causes zero current to flow
R1 through RS.
Rth is equal to Rth found
50 +1 vi
in = vi = = (2.55earlier.
mS)v i
20 k 392
Final Thvenin and Norton Circuits
Check of Results: Note that vth = inRth and this can be used to
check the calculations: inRth=(2.55 mS)vi(282 ) = 0.719vi,
accurate within round-off error.
In phasor notation:
v i = Vi v o = Vo( + )
v o Vo( + ) Vo
Amplifier gain is: A= = =
vi Vi Vi
Amplifier Input/Output Response
vi = sin 2000t V
Av = -5
Note: negative
gain is
equivalent to 180
degrees of
phase shift.
Ideal Operational Amplifier (Op Amp)
Assumption 1 requiring v- = v+ = 0
creates what is known as a virtual
ground at the inverting input of the
amplifier.
Ideal Op Amp Example
(Alternative Approach)
vi v- - v o -vo
From Assumption 2, i2 = ii : ii = and i2 = =
R1 R2 R2
vi -vo
i2 = ii gives =
R1 R2
Yielding: vo R2
Av = = -
vi R1
Design Note: The virtual ground is
not an actual ground. Do not short
the inverting input to ground to
simplify analysis.
Amplifier Frequency Response
Low Pass High Pass Band Pass Band Reject All Pass
Circuit Element Variations
All electronic components have manufacturing tolerances.
Resistors can be purchased with 10%, 5%, and
1% tolerance. (IC resistors are often 10%.)
Capacitors can have asymmetrical tolerances such as +20%/-50%.
Power supply voltages typically vary from 1% to 10%.
Device parameters will also vary with temperature and age.
Circuits must be designed to accommodate these variations.
We will use worst-case and Monte Carlo (statistical) analysis to
examine the effects of component parameter variations.
Tolerance Modeling
For symmetrical parameter variations
Pnom(1 - ) P Pnom(1 + )
For example, a 10 k resistor with 5% percent tolerance
could take on the following range of values:
10k(1 - 0.05) R 10k(1 + 0.05)
9500 R 10500
Circuit Analysis with Tolerances
Worst-case analysis
Parameters are manipulated to produce the worst-case min and max
values of desired quantities.
This can lead to over design since the worst-case combination of
parameters is rare.
It may be less expensive to discard a rare failure than to design for
100% yield.
Monte-Carlo analysis
Parameters are randomly varied to generate a set of statistics for
desired outputs.
The design can be optimized so that failures due to parameter
variation are less frequent than failures due to other mechanisms.
In this way, the design difficulty is better managed than a worst-case
approach.
Worst Case Analysis Example
Problem: Find the nominal and
worst-case values for output
voltage and source current.
Solution:
Known Information and Given
Data: Circuit topology and
values in figure.
Unknowns:
VO (V)
Average 4.96
Nominal 5.00
Standard Deviation 0.30
Maximum 5.70
W/C Maximum 5.87
Minimum 4.37
W/C Minimum 4.20
(e) Exposure of contact opening mask, (f) after resist development and etching of
contact openings, (g) exposure of metal mask, and (h) After etching of aluminum and
resist removal.
MOS Capacitor Structure
Accumulation Depletion
Accumulation
VG << VTN
Depletion
VG < VTN
Inversion
Inversion VG > VTN
Low-frequency C-V Characteristics for an MOS
Capacitor on p-type Substrate
4 device terminals:
Gate(G), Drain(D),
Source(S) and Body(B).
Source and drain regions
form pn junctions with
substrate.
vSB, vDS and vGS always
positive during normal
operation.
vSB always < vDS and vGS
to reverse bias pn
junctions
NMOS Transistor:
Qualitative I-V Behavior
vDS
iD = Kn vGS - VTN - v DS
2
for vGS - VTN vDS 0
Kn = Kn' W L
Kn' = mnCox" (A/V2 )
Cox" = ox Tox
ox = oxide permittivity (F/cm)
Tox = oxide thickness (cm)
NMOS Transistor:
Triode Region Characteristics (cont.)
Output characteristics
appear to be linear.
FET behaves like a
gate-source voltage-
controlled resistor
between source and
drain with
-1
i 1 1
Ron = D = =
v DS W W
v DS 0
Q -Pt Kn' (VGS - VTN - VDS ) Kn' (VGS - VTN )
L VDS 0 L
MOSFET as a
Voltage-Controlled Resistor
Kn' W
(vGS - VTN )
2
iD = for vDS vGS - VTN
2 L
iD
gm =
vGS Q - pt
Taking the derivative of the expression for the drain
current in saturation region,
W 2I D
gm = K '
n
L
(VGS - VTN ) =
VGS - VTN
Channel-Length Modulation
Kn' W
( TN ) (1+ v DS )
2
iD = vGS - V
2 L
VTN = VTO + g (v SB + 2 F - 2 F )
where
VTO = threshold voltage for vSB = 0
g = body - effect parameter ( V)
2 F = surface potential (V)
PMOS Transistors:
Enhancement-Mode Structure
p-type source and drain regions
in an n-type substrate.
vGS < 0 required to create p-type
inversion layer in channel
region
For current flow, vGS < VTP
To maintain reverse bias on
source-substrate and drain-
substrate junctions, vSB < 0 and
vDB < 0
Positive bulk-source potential
causes VTP to become more
negative
PMOS Transistors:
Output Characteristics
Cox" = Gate-channel
capacitance per unit
area(F/m2).
CGC = Total gate channel
capacitance.
CGS = Gate-source
capacitance.
CGC WL CGD = Gate-drain
CGS = + CGSOW = Cox" + CGSOW
2 2 capacitance.
C WL CGSO and CGDO = overlap
CGD = GC + CGDOW = Cox" + CGDOW
2 2 capacitances (F/m).
NMOS Transistor Capacitances:
Triode Region (cont.)
Power-Delay Product:
P PDP
PDP * = P * * = =
2 3
Cutoff Frequency:
gm mn
T = = 2 (VGS - VTN )
CGC L
Cox" W
iD =
2
(vGS - VTN )v SAT where vSAT is carrier saturation
velocity
MOS Transistor Scaling (cont.)
Sub-threshold Conduction:
iD decreases exponentially for
vGS < VTN.
Reciprocal of the slope in
mV/decade gives the turn-off
rate for the MOSFET.
VTN should be reduced if
dimensions are scaled down.
However, curve in sub-
threshold region shifts
horizontally instead of scaling
with VTN
Process-defining Factors
F=2
T = F/2 =
could be 1, 0.5, 0.25
mm, etc.
Two methods of
laying out a CMOS
inverter are shown
The PMOS
transistors lie within
the n-well, whereas
the NMOS transistors
lie in the p-substrate
Polysilicon is used to
form common gate
connections, and
metal is used to tie
the two drains
together
CMOS Inverter
Static Characteristics: vI = VL
The simulation
results show the
varying VTC of the
inverter as VDD is
changed
The theoretical
minimum voltage
supply for CMOS
technology is
VDD = 2VT ln(2) V
or only 18 mV!
CMOS Inverter
Voltage Transfer Characteristics (cont.)
Simulation results
show the varying VTC
of the inverter as KR =
KN/KP is changed
Noise margins
are defined by
the points shown
in the given figure
CMOS Inverter
Noise Margins (cont.)
KN
KR = NM L = VIL - VOL NM H = VOH - VIH
KP
2K R (VDD - VTN + VTP ) (VDD - K RVTN + VTP )
VIH = -
(K R -1) 1+ 3K R K R -1
VOL =
( K R + 1)VIH - VDD - K RVTN - VTP
2K R
2 K R (VDD - VTN + VTP ) (VDD - K RVTN + VTP )
VIL = -
(K R -1) K R + 3 K R -1
VOH =
( K R + 1)VIL + VDD - K RVTN - VTP
2
CMOS Inverter
Propagation Delay Estimate
t f = 3 PHL
t r = 3 PLH
CMOS Inverter
Design Example
Design a reference inverter to achieve a delay of 250
ps with a 0.2 pF load given the following information:
VDD = 3.3 V
C = 0.2 pF
p = 250 ps
VTN = -VTP = 0.75 V
CMOS Inverter
Design Example (cont.)
Assuming the inverter is symmetrical and using the
values given in Table 7.1:
' mA
K = 100
n
V2
' mA
K p = 40 2
V
p = PHL = PLH = 250 ps
CMOS Inverter
Design Example (cont.)
( W / L ) CL ' W W Pr ef CL '
'
P = Pr ef or =
(W / L ) ' CLref L L P CLref
PHL @ 2.4RonN C
PLH @ 2.4RonP C
t f = 2 PHL
t r = 2 PLH
CMOS Logic
Static Power Dissipation
Y = A+B
Basic CMOS logic gate CMOS NOR gate Reference
structure implementation Inverter
CMOS NOR Gate
Transistor Sizing
When sizing the transistors, we attempt to keep the
delay times the same as the reference inverter
Y = A+ B+C
CMOS Logic
NMOS and PMOS Transistor Symbols
Shorthand Notation
CMOS Logic
NAND Gates
Y = AB
Y = ABCDE
Complex CMOS Logic Gate
Design Example
Design a CMOS logic gate for (W/L)p,ref = 5/1 and for (W/L)n,ref = 2/1 that
yields the function:
Y = A + BC + BD
By inspection (knowing Y), the NMOS branch of the gate can drawn as
the following with the corresponding graph, while considering the
longest path for sizing purposes:
Complex CMOS Logic Gate
Design Example (cont.)
By placing nodes in the interior of each arc, plus two more outside
the graph for VDD (3) and the complementary output (2), the PMOS
branch can be realized as shown on the left figure
Connect all of the nodes in the manner shown in the right figure, and
the NMOS arcs that the PMOS arcs intersect have the same inputs
Complex CMOS Logic Gate
Design Example (cont.)