Este material trata a respeito da microeletrônica desde o seu início, com o desenvolvimento dos primeiros semicondutores até agora.

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Este material trata a respeito da microeletrônica desde o seu início, com o desenvolvimento dos primeiros semicondutores até agora.

© All Rights Reserved

- UT Dallas Syllabus for ee6321.501.08s taught by William Frensley (frensley)
- r05320402-vlsi-design
- Vlsi Design May2006 Rr320405
- UT Dallas Syllabus for ee6321.501.09s taught by William Frensley (frensley)
- M.Tech.Microelectronics
- Chapter 3
- Previous Papers
- datasheet
- Analog and Digital CMOS Study Notes
- 180nm-techbrief02
- Photorelay_091407
- Msc Thesis Final
- A o 23237241
- Lecture 5 Scaling II 28
- MOS Transistor Definitions
- JApplPhys_88_424calculationoftheoCV
- Chapter 10
- Electronic Components
- SYLLABUS
- MOSCAP_FTUG_v5edt.pdf

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Outline

Quantify the impact of integrated circuit

technologies.

Describe classification of electronic signals.

Review circuit notation and theory.

Introduce tolerance impacts and analysis.

Introduce CMOS Technology and Logics Circuits

The Start of the Modern Electronics Era

Bell Labs - Brattain and Bardeen transistor. Roughly 50 years later,

invented the bipolar transistor in electronics account for 10% (4

1947. trillion dollars) of the world GDP.

Electronics Milestones

1874 Braun invents the solid-state rectifier. 1958 Integrated circuits developed by Kilby

1906 DeForest invents triode vacuum tube. and Noyce

1907-1927 1961 First commercial IC from Fairchild

Semiconductor

First radio circuits developed from

diodes and triodes. 1963 IEEE formed from merger of IRE and

AIEE

1925 Lilienfeld field-effect device patent

filed. 1968 First commercial IC opamp

1947 Bardeen and Brattain at Bell 1970 One transistor DRAM cell invented by

Laboratories invent bipolar transistors. Dennard at IBM.

1952 Commercial bipolar transistor 1971 4004 Intel microprocessor introduced.

production at Texas Instruments. 1978 First commercial 1-kilobit memory.

1956 Bardeen, Brattain, and Shockley 1974 8080 microprocessor introduced.

receive Nobel prize. 1984 Megabit memory chip introduced.

2000 Alferov, Kilby, and Kromer share

Nobel prize

2009 Boyle and Smith share Nobel prize

Evolution of Electronic Devices

Vacuum Discrete

Tubes Transistors

Integrated Surface-Mount

Circuits Circuits

Microelectronics Proliferation

World transistor production has more than doubled every

year for the past twenty years.

Every year, more transistors are produced than in all

previous years combined.

Approximately 1018 transistors were produced in a recent

year.

Roughly 50 transistors for every ant in the world.

Solid-State Circuits Conference.

Device Feature Size

enabled by process

innovations.

Smaller features lead to

more transistors per unit

area and therefore higher

density.

Rapid Increase in Density of Microelectronics

versus time. versus time.

Signal Types

take on continuous values -

typically current or

voltage.

Digital signals appear at

discrete levels. Usually we

use binary signals which

utilize only two levels.

One level is referred to as

logical 1 and logical 0 is

assigned to the other level.

Analog and Digital Signals

are continuous in time - continuous analog signal

most often voltage or becomes a set of discrete

current. (Charge can also values, typically separated

be utilized as a signal

conveyor.) by fixed time intervals.

Notational Conventions

Total signal = DC bias + time varying signal

vT = VDC + vsig

iT = I DC -+Risig

Resistance and conductance and G with same

subscripts will denote reciprocal quantities. The most

convenient form will be used within expressions.

1 1

Gx = and g =

Rx r

Problem-Solving Approach

Make a clear problem statement.

List known information and given data.

Define the unknowns required to solve the problem.

List assumptions.

Develop an approach to the solution.

Perform the analysis based on the approach.

Check the results and the assumptions.

Has the problem been solved? Have all the unknowns been found?

Is the math correct? Have the assumptions been satisfied?

Evaluate the solution.

Do the results satisfy reasonableness constraints?

Are the values realizable?

Use computer-aided analysis to verify hand analysis

What are Reasonable Numbers?

If the power suppy is 10 V, a calculated DC bias value of 15 V (not within

the range of the power supply voltages) is unreasonable.

Generally, our bias current levels will be between 1 microamp and a few

hundred milliamps.

A calculated bias current of 3.2 amps is probably unreasonable and should

be reexamined.

Peak-to-peak ac voltages should be within the power supply voltage range.

A calculated component value that is unrealistic should be rechecked. For

example, a resistance equal to 0.013 ohms or 1012 ohms

Given the inherent variations in most electronic components, three

significant digits are adequate for representation of results. Three

significant digits are used throughout the text.

Circuit Theory Review: Voltage Division

v1 = ii R1 and v 2 = ii R2

Applying KVL to the loop,

v i = v1 + v 2 = ii (R1 + R2 )

vi

and ii =

R1 + R2

Combining these yields the basic voltage division formula:

R1 R2

v1 = v i v2 = vi

R1 + R2 R1 + R2

Circuit Theory Review: Voltage Division (cont.)

indicated values,

8 k

v1 = 10 V = 8.00 V

8 k + 2 k

2 k

v 2 = 10 V = 2.00 V

8 k + 2 k

Design Note: Voltage division only applies when both resistors are

carrying the same current.

Circuit Theory Review: Current Division

vi vi

ii = i1 + i2 where i1 = andi2 =

R1 R2

Combining and solving for vi,

1 R1 R2

v i = ii = ii = ii (R1 || R2 )

1 1 R1 + R2

+

R1 R2

Combining these yields the basic current division formula:

R2 R1

i1 = ii i2 = ii

R1 + R2 R1 + R2

Circuit Theory Review: Current

Division (cont.)

indicated values,

3 k

i1 = 5 ma = 3.00 mA

2 k + 3 k

2 k

i 2 = 5 ma = 2.00 mA

2 k + 3 k

Design Note: Current division only applies when the same voltage

appears across both resistors.

Circuit Theory Review: Thvenin and Norton

Equivalent Circuits

Thvenin

Norton

Circuit Theory Review: Find the Thvenin

Equivalent Voltage

equivalent voltage at the output.

Solution:

Known Information and Given

Data: Circuit topology and values

in figure.

Unknowns: Thvenin equivalent

voltage vth.

Approach: Voltage source vth is

defined as the output voltage with

no load (open-circuit voltage).

Assumptions: None.

Analysis: Next slide

Circuit Theory Review: Find the Thvenin

Equivalent Voltage

vo - vi vo

i1 = + = G1 (v o - vi )+ GS v o

R1 RS

(

Current i1 can be written i1 = G1 v o - vi )

as:

Combining the previous equations

G1 ( +1)v i = G1 ( +1) + GS v o

vo = vi = vi

G1 ( +1) + GS R1RS ( +1)RS + R1

Circuit Theory Review: Find the Thvenin

Equivalent Voltage (cont.)

vo = vi = v i = 0.718v i

( +1)RS + R1 (50 + 1)1 k +1 k

and

v th = 0.718v i

Circuit Theory Review: Find the Thvenin

Equivalent Resistance

equivalent resistance.

Solution:

Known Information and

Given Data: Circuit topology

and values in figure.

Unknowns: Thvenin

equivalent Resistance Rth.

Test voltage vx has been added to

Approach: Find Rth as the

the previous circuit. Applying vx

output equivalent resistance

and solving for ix allows us to find

with independent sources set

to zero. the

Thvenin resistance as vx/ix.

Assumptions: None.

Circuit Theory Review: Find the Thvenin

Equivalent Resistance (cont.)

Applying KCL,

i x = -i1 - i1 + G S v x

= G1v x + G1v x + G S v x

= G1 ( + 1) + G S v x

vx 1 R1

Rth = = = RS

i x G1 ( + 1) + G S +1

R1 20 k

Rth = RS = 1 k = 1 k 392 = 282

+1 50 + 1

Circuit Theory Review: Find the Norton Equivalent

Circuit

equivalent circuit.

Solution:

Known Information and

Given Data: Circuit topology

and values in figure.

Unknowns: Norton

equivalent short circuit current A short circuit has been

in. applied across the output.

Approach: Evaluate current The Norton current is the

through output short circuit. current flowing through the

Assumptions: None. short circuit at the output.

Analysis: Next slide

Circuit Theory Review: Find the Norton Equivalent

Circuit (cont.)

Applying KCL,

in = i1 + i1

= G1v i + G1vi

= G1 ( +1)v i

v i ( +1) Short circuit at the output

= causes zero current to flow

R1 through RS.

Rth is equal to Rth found

50 +1 vi

in = vi = = (2.55earlier.

mS)v i

20 k 392

Final Thvenin and Norton Circuits

Check of Results: Note that vth = inRth and this can be used to

check the calculations: inRth=(2.55 mS)vi(282 ) = 0.719vi,

accurate within round-off error.

currents at the output terminals, there is one difference between

the two circuits. With no load connected, the Norton circuit still

dissipates power!

Amplifier Basics

Analog signals are typically manipulated with linear

amplifiers.

Although signals may be comprised of several different

components, linearity permits us to use the superposition

principle.

Superposition allows us to calculate the effect of each of

the different components of a signal individually and then

add the individual contributions to create the total

resulting signal.

Amplifier Linearity

For a linear amplifier, the output is

at the same frequency, but v o = Vo sin( i t + + )

different amplitude and phase.

In phasor notation:

v i = Vi v o = Vo( + )

v o Vo( + ) Vo

Amplifier gain is: A= = =

vi Vi Vi

Amplifier Input/Output Response

vi = sin 2000t V

Av = -5

Note: negative

gain is

equivalent to 180

degrees of

phase shift.

Ideal Operational Amplifier (Op Amp)

infinite voltage gain, and

infinite input resistance.

circuits:

2. The input currents are zero.

Ideal Op Amp Example

Find the voltage gain of an op amp with resistive feedback

v i - ii R1 - i2 R2 - v o = 0

Writing a loop equation:

vi - v-

ii = i2 =

From assumption 2, we know that i- = R1

0. vi

ii =

R1

Assumption 1 requires v- = v+ = 0.

vo R2

Av = =-

Combining these equations yields: vi R1

Assumption 1 requiring v- = v+ = 0

creates what is known as a virtual

ground at the inverting input of the

amplifier.

Ideal Op Amp Example

(Alternative Approach)

vi v- - v o -vo

From Assumption 2, i2 = ii : ii = and i2 = =

R1 R2 R2

vi -vo

i2 = ii gives =

R1 R2

Yielding: vo R2

Av = = -

vi R1

Design Note: The virtual ground is

not an actual ground. Do not short

the inverting input to ground to

simplify analysis.

Amplifier Frequency Response

frequencies. Such an amplifier is known as a filter. Several filter types are

shown below:

Low Pass High Pass Band Pass Band Reject All Pass

Circuit Element Variations

All electronic components have manufacturing tolerances.

Resistors can be purchased with 10%, 5%, and

1% tolerance. (IC resistors are often 10%.)

Capacitors can have asymmetrical tolerances such as +20%/-50%.

Power supply voltages typically vary from 1% to 10%.

Device parameters will also vary with temperature and age.

Circuits must be designed to accommodate these variations.

We will use worst-case and Monte Carlo (statistical) analysis to

examine the effects of component parameter variations.

Tolerance Modeling

For symmetrical parameter variations

Pnom(1 - ) P Pnom(1 + )

For example, a 10 k resistor with 5% percent tolerance

could take on the following range of values:

10k(1 - 0.05) R 10k(1 + 0.05)

9500 R 10500

Circuit Analysis with Tolerances

Worst-case analysis

Parameters are manipulated to produce the worst-case min and max

values of desired quantities.

This can lead to over design since the worst-case combination of

parameters is rare.

It may be less expensive to discard a rare failure than to design for

100% yield.

Monte-Carlo analysis

Parameters are randomly varied to generate a set of statistics for

desired outputs.

The design can be optimized so that failures due to parameter

variation are less frequent than failures due to other mechanisms.

In this way, the design difficulty is better managed than a worst-case

approach.

Worst Case Analysis Example

Problem: Find the nominal and

worst-case values for output

voltage and source current.

Solution:

Known Information and Given

Data: Circuit topology and

values in figure.

Unknowns:

Nominal voltage solution:

Approach: Find nominal values

and then select R1, R2, and VI R1nom

values to generate extreme cases VOnom = VInom

of the unknowns. R1nom + R2nom

Assumptions: None.

Analysis: Next slides

18k

= 15V = 5V

18k + 36k

Worst-Case Analysis Example (cont.)

VI nom 15V

nom

I I = nom nom

= = 278 mA

R1 + R2 18k + 36k

VO = VI = R 2.

R1 + R2 R2

1+

R1

VO is minimized for min VI, R1, and max

15V (1.1) R 2. min 15V (0.95)

VOmax = = 5.87V VO = = 4.20V

36K(0.95) 36K(1.05)

1+ 1+

18K(1.05) 18K(0.95)

Worst-Case Analysis Example (cont.)

IImax = min min = = 322 mA

R1 + R2 18k(0.95) + 36k(0.95)

I min

I = max max = = 238 mA

R1 + R2 18k(1.05) + 36k(1.05)

percent above and below the nominal values. The sum of the

three element tolerances is 20 percent, so our calculated values

appear to be reasonable.

Monte Carlo Analysis

We use programs like MATLAB, Mathcad, SPICE, or a spreadsheet to

complete a statistically significant set of calculations.

For example, with Excel, a resistor with a nominal value Rnom and

tolerance can be expressed as:

R = Rnom (1+ 2 ( RAND() - 0.5))

returns random numbers

uniformly distributed

between 0 and 1.

Monte Carlo Analysis Results

VO (V)

Average 4.96

Nominal 5.00

Standard Deviation 0.30

Maximum 5.70

W/C Maximum 5.87

Minimum 4.37

W/C Minimum 4.20

simulation.

Monte Carlo Analysis Example

analysis and find the mean, standard

deviation, min, and max for VO, II,

and power delivered from the source.

Solution:

Known Information and Given

Data: Circuit topology and values in

figure.

Unknowns: The mean, standard

deviation, min, and max for VO, II,

and PI. Monte Carlo parameter

Approach: Use a spreadsheet to definitions:

evaluate the circuit equations with VI = 15(1+ 0.2(RAND() - 0.5))

random parameters.

Assumptions: None.

R1 = 18,000(1+ 0.1(RAND() - 0.5))

Analysis: Next slides R2 = 36,000(1+ 0.1(RAND() - 0.5))

Monte Carlo Analysis Example (cont.)

Monte Carlo parameter

definitions: VI = 15(1+ 0.2( RAND() - 0.5))

R1 = 18,000(1+ 0.1( RAND() - 0.5))

R2 = 36,000(1+ 0.1( RAND() - 0.5))

Circuit equations based on Monte Carlo parameters:

R1 VI PI = VI II

VO = VI II =

R1 + R2 R1 + R2

Results:

Avg Nom. Stdev Max WC-max Min WC-Min

Vo (V) 4.96 5.00 0.30 5.70 5.87 4.37 4.20

II (mA) 0.276 0.278 0.0173 0.310 0.322 0.242 0.238

P (mW) 4.12 4.17 0.490 5.04 -- 3.29 --

Temperature Coefficients

P = Pnom(1+1T+ 2T2) where T = T-Tnom

Pnom is defined at Tnom

Most versions of SPICE allow for the specification of

TNOM, T, TC1(1), TC2(2).

SPICE temperature model for resistor:

R(T) = R(TNOM)*[1+TC1*(T-TNOM)+TC2*(T-TNOM)2]

Many other components have similar models.

Numeric Precision

greater than 50%.

As a consequence, more than three significant digits is

meaningless.

Results in the text will be represented with three

significant digits: 2.03 mA, 5.72 V, 0.0436 A, and so

on.

However, extra guard digits are normally retained during

calculations.

Integrated Circuit Fabrication Overview

Integrated Circuit Fabrication (cont.)

(c) after SiO2 etch, and (d) after implantation/diffusion of acceptor dopant.

Integrated Circuit Fabrication (cont.)

(e) Exposure of contact opening mask, (f) after resist development and etching of

contact openings, (g) exposure of metal mask, and (h) After etching of aluminum and

resist removal.

MOS Capacitor Structure

Consists of low-resistivity

material such as metal or

doped polycrystalline silicon

Second electrode - Substrate

or Body: n-- or p-type

-type

semiconductor

Dielectric - Silicon dioxide:

stable high-quality electrical

insulator between gate and

substrate.

Substrate Conditions for Different Biases

Accumulation Depletion

Accumulation

VG << VTN

Depletion

VG < VTN

Inversion

Inversion VG > VTN

Low-frequency C-V Characteristics for an MOS

Capacitor on p-type Substrate

linear function of voltage.

Total capacitance in any

region is dictated by the

separation between

capacitor plates.

Total capacitance modeled

as series combination of

fixed oxide capacitance and

voltage-dependent

depletion-layer capacitance.

NMOS Transistor:

Structure

4 device terminals:

Gate(G), Drain(D),

Source(S) and Body(B).

Source and drain regions

form pn junctions with

substrate.

vSB, vDS and vGS always

positive during normal

operation.

vSB always < vDS and vGS

to reverse bias pn

junctions

NMOS Transistor:

Qualitative I-V Behavior

current flows.

VGS < VTN: Depletion region formed

under gate merges with source and

drain depletion regions. No current

flows between source and drain.

VGS > VTN: Channel formed between

source and drain. If vDS > 0, finite iD

flows from drain to source.

iB = 0 and iG = 0.

NMOS Transistor:

Triode Region Characteristics

vDS

iD = Kn vGS - VTN - v DS

2

for vGS - VTN vDS 0

Kn = Kn' W L

Kn' = mnCox" (A/V2 )

Cox" = ox Tox

ox = oxide permittivity (F/cm)

Tox = oxide thickness (cm)

NMOS Transistor:

Triode Region Characteristics (cont.)

Output characteristics

appear to be linear.

FET behaves like a

gate-source voltage-

controlled resistor

between source and

drain with

-1

i 1 1

Ron = D = =

v DS W W

v DS 0

Q -Pt Kn' (VGS - VTN - VDS ) Kn' (VGS - VTN )

L VDS 0 L

MOSFET as a

Voltage-Controlled Resistor

vO Ron 1

= =

vS Ron + R 1+ Kn R(VGG - VTN )

and VGG = 1.5V, then,

vO 1

= = 0.667

vS mA

1+ 500

V 2 (2000)(1.5 -1)V

To maintain triode region operation,

vDS vGS - VTN or vO VGG - VTN

0.667vS (1.5 -1)V or vS 0.750 V

MOSFET as a Voltage-Controlled Resistor (cont.)

O( )

V s s

Voltage Transfer T (s) = =

VS (s) s + o

function,

where, cut-off 1 Kn (VGS - VTN )

o = =

frequency RonC C

0.02mF and VGG = 1.5V, then,

mA

500

V

(

2

1.5 -1)V

fo = = 1.99 kHz

2 (0.02 mF )

To maintain triode region

operation, v V - V = 0.5 V

S GG TN

NMOS Transistor:

Saturation Region

channel region disappears and is said to be

pinched-off.

Current saturates at constant value, independent

of vDS.

Saturation region operation mostly used for

analog amplification.

NMOS Transistor:

Saturation Region (cont.)

Kn' W

(vGS - VTN )

2

iD = for vDS vGS - VTN

2 L

Transconductance of an MOS Device

Transconductance relates the change in drain current to a

change in gate-source voltage

iD

gm =

vGS Q - pt

Taking the derivative of the expression for the drain

current in saturation region,

W 2I D

gm = K '

n

L

(VGS - VTN ) =

VGS - VTN

Channel-Length Modulation

of the depleted channel beyond the

pinch-off point, L, increases and the

actual L decreases.

iD increases slightly with vDS instead of

being constant.

Kn' W

( TN ) (1+ v DS )

2

iD = vGS - V

2 L

parameter

Depletion-Mode MOSFETS

Ion implantation process is used to form a built-in n-

type channel in the device to connect source and drain

by a resistive channel

Non-zero drain current for vGS = 0

Negative vGS required to turn device off.

Transfer Characteristics of MOSFETS

Enhancement- & Depletion-Mode Devices

gate-source voltage for a fixed drain-source voltage

Body Effect or Substrate Sensitivity

causing substrate sensitivity modeled by

VTN = VTO + g (v SB + 2 F - 2 F )

where

VTO = threshold voltage for vSB = 0

g = body - effect parameter ( V)

2 F = surface potential (V)

PMOS Transistors:

Enhancement-Mode Structure

p-type source and drain regions

in an n-type substrate.

vGS < 0 required to create p-type

inversion layer in channel

region

For current flow, vGS < VTP

To maintain reverse bias on

source-substrate and drain-

substrate junctions, vSB < 0 and

vDB < 0

Positive bulk-source potential

causes VTP to become more

negative

PMOS Transistors:

Output Characteristics

off.

For more negative vGS, drain

current increases in

magnitude.

PMOS device is in the triode

region for small values of VDS

and in saturation for larger

values.

Remember VTP < 0 for an

enhancement mode transistor

MOSFET Circuit Symbols

(g) and(i) are the

most commonly

used symbols in

VLSI logic design.

MOS devices are

symmetric.

In NMOS, n+

region at higher

voltage is the drain.

In PMOS p+ region

at lower voltage is

the drain

Internal Capacitances in Electronic Devices

Limit high-frequency performance of the electronic device

they are associated with.

Limit switching speed of circuits in logic applications

Limit frequency at which useful amplification can be

obtained in amplifiers.

MOSFET capacitances depend on region of operation and

are non-linear functions of voltages at device terminals.

NMOS Transistor Capacitances:

Triode Region

Cox" = Gate-channel

capacitance per unit

area(F/m2).

CGC = Total gate channel

capacitance.

CGS = Gate-source

capacitance.

CGC WL CGD = Gate-drain

CGS = + CGSOW = Cox" + CGSOW

2 2 capacitance.

C WL CGSO and CGDO = overlap

CGD = GC + CGDOW = Cox" + CGDOW

2 2 capacitances (F/m).

NMOS Transistor Capacitances:

Triode Region (cont.)

CSB = CJ AS + CJSW PS

CDB = Drain-bulk capacitance.

CDB = CJ AD + CJSW PD AS and AD = Junction bottom

area capacitance of the

source and drain regions.

PS and PD = Perimeter of the

source and drain junction

regions.

NMOS Transistor Capacitances: Saturation Region

2 2

CGS = CGC + CGSOW CGD = CGDOW

3 3

NMOS Transistor Capacitances:

Cutoff Region

completely gone.

CGBO = gate-bulk

CGS = CGSOW

capacitance per unit

CGD = CGDOW width.

CGB = CGBOW

SPICE Model for NMOS Transistor

SPICE:

KP = 50 or 20 mA/V2

g=0

=0

VTO = 1 V

mn or mp = 500 or 200 cm2/V-s

2FF = 0.6 V

CGDO = CGSO = CGBO = CJSW = 0

Tox= 100 nm

MOS Transistor Scaling

Scale Factor

Drain current: ox W W

Kn* = mn = mn ox = K n

Tox L Tox L

ox W vGS VTN vDS vDS iD

i = mn

*

D - - =

Tox L 2 2

Gate Capacitance:

ox W CGC

( )

*

* " * *

CGC = C ox W L = =

Tox L

V *

=C

* *

GC =

*

iD

where is the circuit delay in a logic circuit.

MOS Transistor Scaling

Scale Factor (cont.)

VDD iD P

* *

P * = VDD iD = =

2

P* P* P 2 P

= = = extremely important result!

A* W * L* (W )(L ) A

Power-Delay Product:

P PDP

PDP * = P * * = =

2 3

Cutoff Frequency:

gm mn

T = = 2 (VGS - VTN )

CGC L

MOS Transistor Scaling (cont.)

High electric fields arise if technology is scaled down with

supply voltage constant.

Causes reduction in mobility of MOS transistor,

breakdown of linear relationship between mobility and

electric field and carrier velocity saturation.

Ultimately results in reduced long-term reliability and

breakdown of gate oxide or pn junction.

Drain current in saturation region is linearized to

Cox" W

iD =

2

(vGS - VTN )v SAT where vSAT is carrier saturation

velocity

MOS Transistor Scaling (cont.)

Sub-threshold Conduction:

iD decreases exponentially for

vGS < VTN.

Reciprocal of the slope in

mV/decade gives the turn-off

rate for the MOSFET.

VTN should be reduced if

dimensions are scaled down.

However, curve in sub-

threshold region shifts

horizontally instead of scaling

with VTN

Process-defining Factors

be reliably transferred to the wafer surface using a given generation

of lithographic manufacturing tools

Alignment Tolerance T: Maximum misalignment that can occur

between two mask levels during fabrication

Mask Sequence

Polysilicon-Gate Transistor

thin oxide region of transistor

Mask 2: Defines polysilicon gate

of transistor, aligns to mask 1

Mask 3: Delineates the contact

window, aligns to mask 2.

Mask 4: Delineates the metal

pattern, aligns to mask 3.

Channel region of transistor

formed by intersection of first

two mask layers. Source and

Drain regions formed wherever

mask 1 is not covered by mask 2

Basic Ground Rules for Layout

F=2

T = F/2 =

could be 1, 0.5, 0.25

mm, etc.

Transistor Area = 120 2

MOSFET Biasing

Bias sets the dc operating point around which the device operates.

The signal is actually comprised of relatively small changes in the

voltages and/or currents.

Remember (Total = dc + signal): vGS = VGS + vgs and iD = ID + id

Bias Analysis Approach

Assume an operation region (generally the saturation

region)

Use circuit analysis to find VGS

Use VGS to calculate ID, and ID to find VDS

Check validity of operation region assumptions

Change assumptions and analyze again if required.

always in saturation

CMOS Technology

Inverter Circuit

(b) Simplified operation model with a high input applied

(c) Simplified operation model with a low input applied

CMOS Technology

Inverter Operation

transistor is turned off, while the NMOS device is

turned on pulling the output down to VSS

transistor is turned off, while the PMOS device is

turned on pulling the output up to VDD

CMOS Technology

Inverter Fabrication

on an NMOS device, but they need to be fabricated on the

same wafer

developed as shown in this cross-section of a CMOS inverter

CMOS Technology

Inverter Layout

Two methods of

laying out a CMOS

inverter are shown

The PMOS

transistors lie within

the n-well, whereas

the NMOS transistors

lie in the p-substrate

Polysilicon is used to

form common gate

connections, and

metal is used to tie

the two drains

together

CMOS Inverter

Static Characteristics: vI = VL

= VDD, ID = 0, and there is no static power dissipation.

CMOS Inverter

Static Characteristics: vI = VH

that there is no static power dissipation

CMOS Inverter

Voltage Transfer Characteristics

CMOS inverter that is

symmetrical (Kp = Kn).

CMOS Inverter

Voltage Transfer Characteristics (cont.)

The simulation

results show the

varying VTC of the

inverter as VDD is

changed

The theoretical

minimum voltage

supply for CMOS

technology is

VDD = 2VT ln(2) V

or only 18 mV!

CMOS Inverter

Voltage Transfer Characteristics (cont.)

Simulation results

show the varying VTC

of the inverter as KR =

KN/KP is changed

current drive is

greater, and the logic

transition occurs for vI

< VDD/2

current drive is

greater, the logic

transition occurs for vI

> VDD/2

CMOS Inverter

Noise Margins

Noise margins

are defined by

the points shown

in the given figure

CMOS Inverter

Noise Margins (cont.)

KN

KR = NM L = VIL - VOL NM H = VOH - VIH

KP

2K R (VDD - VTN + VTP ) (VDD - K RVTN + VTP )

VIH = -

(K R -1) 1+ 3K R K R -1

VOL =

( K R + 1)VIH - VDD - K RVTN - VTP

2K R

2 K R (VDD - VTN + VTP ) (VDD - K RVTN + VTP )

VIL = -

(K R -1) K R + 3 K R -1

VOH =

( K R + 1)VIL + VDD - K RVTN - VTP

2

CMOS Inverter

Propagation Delay Estimate

that contribute to propagation delay

CMOS Inverter

Propagation Delay Estimate (cont.)

V - V 2V

PHL = RonN Cln4 H TN

-1 +

TN

V H + VL V H - VTN

1

RonN =

K n (V H - VTN )

PHL + PLH

p = = PHL = 1.2RonN C

2

If it is assumed the inverter in symmetrical with

(W/L)P = 2.5(W/L)N, then PLH = PHL

CMOS Inverter

Rise and Fall Times

approximate expressions:

t f = 3 PHL

t r = 3 PLH

CMOS Inverter

Design Example

Design a reference inverter to achieve a delay of 250

ps with a 0.2 pF load given the following information:

VDD = 3.3 V

C = 0.2 pF

p = 250 ps

VTN = -VTP = 0.75 V

CMOS Inverter

Design Example (cont.)

Assuming the inverter is symmetrical and using the

values given in Table 7.1:

' mA

K = 100

n

V2

' mA

K p = 40 2

V

p = PHL = PLH = 250 ps

CMOS Inverter

Design Example (cont.)

W 1 3.77

= ' =

L n K n RonN (VDD - VTN ) 1

W K n' W W 9.43

= ' = 2.5 =

L p K p L n L n 1

CMOS Inverter

Performance Scaling

State-of-the-art short gate length

technologies are hard to analyze

Scaling can be used to properly set W/L for a

given load capacitance relative to reference

gate simulation with a reference load.

( W / L ) CL ' W W Pr ef CL '

'

P = Pr ef or =

(W / L ) ' CLref L L P CLref

terms of a target load and delay.

CMOS Inverter

Performance Scaling

3.16 ns.

What is the delay if an inverter has a W/L 4x

larger than the transistors of the reference

inverter and twice the load capacitance.

(2 /1) 2 pF'

P = 3.16 ns = 1.58 ns

(8 /1)' 1pF

Scaling allows us to calculate a new geometry (W/L)' or

delay relative to a reference design.

CMOS Logic

Delay of Cascaded Inverters

An ideal step was used to derive the previous delay

equations, but this is not possible to implement

By using putting the following circuit in SPICE, it is

possible to produce more accurate equations

CMOS Logic

Delay of Cascaded Inverters (cont.)

and it can be seen that the delay for the nonideal step

input is approximately twice than the ideal case:

PHL @ 2.4RonN C

PLH @ 2.4RonP C

t f = 2 PHL

t r = 2 PLH

CMOS Logic

Static Power Dissipation

dissipation

have leakage currents associated with the reverse-

biased drain-to-substrate connections as well as sub-

threshold leakage current between the drain and

source

CMOS Logic

Dynamic Power Dissipation

components that

add to dynamic

power dissipation:

1) Capacitive load

charging at a

frequency f given

by: PD = CV2DDf

2) The current that

occurs during

switching which

can be seen in the

figure

CMOS Logic

Power-Delay Product

inverter switching waveform

CMOS Logic

NOR Gate

Y = A+B

Basic CMOS logic gate CMOS NOR gate Reference

structure implementation Inverter

CMOS NOR Gate

Transistor Sizing

When sizing the transistors, we attempt to keep the

delay times the same as the reference inverter

and NMOS branches of the NOR gate must be the

same as the reference inverter

twice as large

CMOS NOR Gate

Body Effect

Since the bottom PMOS body contact is not

connected to its source, its threshold voltage

changes as VSB changes during switching

affected by body effect, thus the total on-resistance of the

PMOS branch is the same

|VTP| being a function of time

CMOS NOR Gate

Two-Input Layout

CMOS NOR Gate

Three-Input Circuit

create multiple input NOR gates

Y = A+ B+C

CMOS Logic

NMOS and PMOS Transistor Symbols

Shorthand Notation

CMOS Logic

NAND Gates

Y = AB

implementation

CMOS NAND Gate

Transistor Sizing

devices as for the NOR gate, except now the

NMOS transistors are in series

size of that of the reference inverter

CMOS NAND Gates

Five Input NAND

Y = ABCDE

Complex CMOS Logic Gate

Design Example

Design a CMOS logic gate for (W/L)p,ref = 5/1 and for (W/L)n,ref = 2/1 that

yields the function:

Y = A + BC + BD

By inspection (knowing Y), the NMOS branch of the gate can drawn as

the following with the corresponding graph, while considering the

longest path for sizing purposes:

Complex CMOS Logic Gate

Design Example (cont.)

By placing nodes in the interior of each arc, plus two more outside

the graph for VDD (3) and the complementary output (2), the PMOS

branch can be realized as shown on the left figure

Connect all of the nodes in the manner shown in the right figure, and

the NMOS arcs that the PMOS arcs intersect have the same inputs

Complex CMOS Logic Gate

Design Example (cont.)

graph, the PMOS

network can now

be drawn for the

final CMOS logic

gate while once

again

considering the

longest PMOS

path for sizing

Two equivalent forms of the final circuit

Minimum Size Gate

Design and Performance

tradeoff that needs to be considered

devices, then the PLH will be increased compared

to the symmetrical reference inverter

Minimum Size Complex Gate

Design and Layout

size logic gate

End

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