University of Southern California

Viterbi School of Engineering

EE477L
MOS VLSI Circuit Design

Layout Design

Xue Lin

Shahin Nazarian Fall 2012

 Introduction
Layout design techniques can be learned from both design
practice and systematical study

Our lab assignments are good practice

Textbooks on layout design techniques can provide theoretical

guidance

The main reference is IC Mask Design Essential Layout

Techniques, by Christopher Saint and Judy Saint. This book
conveys layout design techniques in an enjoyable light style. Its
ebook is available at USC online library

Important techniques are extracted from this book. You are

encouraged to read related paragraphs for more details

Hope you enjoy your layout design study!

Shahin Nazarian/EE477L/Fall 2012 2

 Outline
Part 1 Digital Design Overview
Briefly goes through the flow of large digital chip design

Part 2 Standard Cell Techniques

Explains some basic layout techniques which might be
useful in our lab designs

Part 3 Parasitics
Explains the unwanted physical components, affecting the
performance of our design. Although, we may not be able
to completely eliminate them, this part explains how we
can keep them under control

Shahin Nazarian/EE477L/Fall 2012 3

 Digital Design Overview

Layout Design
Circuit Design

Partitioning
Verify the
circuitry logic
Floorplanning

Compile a netlist
Placement

Routing

A flowchart of digital design

from concept through testing and finally to a layout
Shahin Nazarian/EE477L/Fall 2012 4
 Digital Design Overview Circuit Design

Behavioral Design (verify the circuitry logic)

Circuits are described using an HDL (Hardware
Description Language) such as VHDL or Verilog
The high level HDL-based descriptions are c-like
VHDL or Verilog data files are submitted to the
simulator to verify the circuit functionality
Synthesis (compile a netlist)
Once the logic circuit passes the verification step,
a complier or logic synthesizer will translate the
high level VHDL or Verilog file into a netlist
A netlist describes which gates are used and how
to make connections between gates
Shahin Nazarian/EE477L/Fall 2012 5
 Circuit Design (Cont.)
Before synthesis, a circuit design may have some priorities
like speed, area, power, etc. These considerations could be
introduced to the synthesizer as constraints before it begins
The synthesizer uses optimization techniques such as buffer
insertion and gate size selection to meet the contraints
Driving Strength (or fan out) indicates how many devices
a gate can drive. Remember 1X, 2X and 4X gates of
Lab1. The larger the gate, the stronger the driving
strength. We should choose the gate with proper driving
strength. For example, if an INV1X could drive 2
devices, then an INV2X could drive 4 devices. It would
then be a waste of are if you used an INV4X to drive
only 2 devices
Buffers do not logically affect the circuit however they
increase the signal strength along long wires
Shahin Nazarian/EE477L/Fall 2012 6
 Circuit Design (Cont.)
Clock Network Synthesis: Most digital circuits have a
clock signal to which every function is synchronized. The
wiring nets for this clock timing signal are called clock
nets. A clock net connects to thousands of gates. Usually
a clock net is split into a branching-out pattern, called a
clock tree. For example, if a clock net needs to drive 6
devices, but with fan out limit of 3, it can be split with
buffers

Shahin Nazarian/EE477L/Fall 2012 The figure is from reference [1] 7

 Circuit Design (Cont.)
P&G (Power and Ground) Network Synthesis: Similarly
to a clock network, the digital design needs a
network of VDD and GND wires. Clock and P&G
networks are covered in EE577B

Shahin Nazarian/EE477L/Fall 2012 8

Digital Design Overview Layout Design
After circuit design, we obtain a netlist which could be
easily translated into a schematic. Now, lets start the layout
design (a.k.a. physical design)
Partitioning
Divide the chip into smaller blocks
This is done based on some goals and constraints,
e.g., to minimize the number of connections between
the blocks, but in general it is done to separate
different functional blocks and simplify their physical
design process and also to make placement and routing
easier
For example, during partitioning you may decide to
divide your design into two blocks, such that the
total number of connections between the gates in
different blocks is minimized
Shahin Nazarian/EE477L/Fall 2012 9
 Layout Design (Cont.)
Floorplanning
Create functional areas for your chip. For example, decide
where to place FPU, RAM, MPU, ROM on the chip
Place the input and output (I/O) cells of your chip
Connect functional blocks with I/O pads or with each
other
Check whether long wires would slow your design
Placement
Nail down the exact positions of all logic gates within each
block
Place I/O drivers
Similarly to other steps, placement is done based on goals
and constraints, e.g., such that the total approximate
wire length is minimized
Shahin Nazarian/EE477L/Fall 2012 10
 Layout Design (Cont.)
Routing
Route power nets and clock nets first. They are critical
nets
Route rest of the nets
Routing is typically done in two steps of global routing
and detailed routing. In global routing the resource
(channels) for the wires are selected and in detailed
routing, the wires are assigned to a specific routing
track (metal layer) in the selected channels

USC courses

Shahin Nazarian/EE477L/Fall 2012 11

 Layout Design Routing of Power Nets
Notice the highlighted cell at the far upper right corner,
farthest from the VDD input pad. As the power comes into
the circuit on the lower left, it must travel through the
existing rails. The other highlighted cell nearest the pad
would see a lot less resistance. Lets alleviate this
difference by laying straps of metal across your power
rails. Now, its like having resistors in parallel, the overall
resistivity decreases

Shahin Nazarian/EE477L/Fall 2012 The figures are from reference [1] 12

 Layout Design Routing of Clock Nets
Central Clock Trunk Approach
There is usually a clock driver cell that has enough drive
strength to drive the top level clock buffers. Place that
cell centrally within your design and create a large central
trunk that branches out to join to all the clock buffers
As the net reaches further out from the main driver, it
continually splits into more and finer branches. The wire
widths at the outer edges become smaller and smaller

Shahin Nazarian/EE477L/Fall 2012 The figure is from reference [1] 13

 Review: Layout Design Rules

Shahin Nazarian/EE477L/Fall 2012 The figure is from reference [2] 14

 Review: Layout Design Rules
Lambda Rules: One lambda = one half of the minimum mask
dimension, typically the length of a transistor channel
Lambda Rules are based on the assumption that one can scale
a design to the appropriate size before manufacturing

Shahin Nazarian/EE477L/Fall 2012 The figure is from reference [3] 15

 Standard Cell Techniques (Cont.)
Running all Metal One horizontally and running all Metal Two
vertically is a good way to avoid trapping

Shahin Nazarian/EE477L/Fall 2012 The figure is from reference [1] 16

 Standard Cell Techniques (Cont.)
Align the input and the output
Try to align the output with the input. When you place
gates next to each other, the output of one gate could
be easily connected to the input of the other gate

Shahin Nazarian/EE477L/Fall 2012 The figure is from reference [1] 17

 Standard Cell Techniques (Cont.)
Fixed height, variable width
If each gate in our library has differently sized power rails,
and each gate was a unique height, our wiring would be
messy. This figure shows how the small, medium and large
versions of our inverter cause our power rails to wander.
Thats the reason why you are asked to design cells within a
fixed height in our labs

Shahin Nazarian/EE477L/Fall 2012 The figure is from reference [1] 18

 Standard Cell Techniques (Cont.)
Common N Well
Suppose we want to place four gates next door to each other.
Typically, we want to place them as close as possible to save
area. A typical CMOS process usually has an N well spacing
rule that is very large. If we space our inverters such that
we have a minimum N well spacing between all the devices, we
would waste large amounts of space. We can create one large
single N well and save space. Now our limiting design rule is
the transistor to transistor rule, which is much smaller

Shahin Nazarian/EE477L/Fall 2012 The figure is from reference [1] 19

 Standard Cell Techniques (Cont.)
Half-Grid Cell Sizing
We will be butting cells up next to each other. However, if
we intend to butt the cells next to each other, how will that
affect the spacing between our internal components? We run
the risk of butting the internal components next to each
other as well. Here is a good solution. If we keep all internal
components far enough away from the edge of each cell, then
we are free to butt the cells next to each other

Shahin Nazarian/EE477L/Fall 2012 The figure is from reference [1] 20

 Standard Cell Techniques (Cont.)
Half Design Rule
For example, your design rule for active diffusion to active
diffusion spacing might be 1.4 microns. If you keep the edge
of your active diffusion 0.7 microns, or half the minimum
spacing, away from the edges of each cell, then two cells
placed together will provide the 1.4 micron separation needed

Shahin Nazarian/EE477L/Fall 2012 The figure is from reference [1] 21

 Standard Cell Techniques (Cont.)
Routing Channels
In your standard cell, your VDD (power) and VSS (ground)
rails might be at the extents of your cell. When you place a
bunch of these cells together in rows and columns, you have
to flip every other row. This arrangement is good for your
power net. You just connect your VDDs to each other at the
ends of the rows, so does VSSs

Shahin Nazarian/EE477L/Fall 2012 The figure is from reference [1] 22

 Standard Cell Techniques (Cont.)
Routing Channels
However, if you only have two or three metals, the previous
method gives you no room to wire metal one any more. You
can use metal one for the rails, and you can still use metal
one for the inside of the cells, if you leave some airspace
above and below the power rails, as shown in the following
figure. The air spaces are known as routing channels

Shahin Nazarian/EE477L/Fall 2012 The figure is from reference [1] 23

 Standard Cell Techniques (Cont.)
Eliminating Gaps

Shahin Nazarian/EE477L/Fall 2012 The figure is from reference [4] 24

 Standard Cell Techniques (Cont.)

Choosing a Style

Shahin Nazarian/EE477L/Fall 2012 The figure is from reference [4] 25

 Standard Cell Techniques (Cont.)

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 Parasitics

Nothing in an integrated circuit operates perfectly

Inevitably, you create extra capacitance, resistance
and inductance in your layout design just by putting
materials close to each other
Lets take a look at the three primary parasitics
capacitance, resistance, and inductance and what
can be done to alleviate their annoying presence

Shahin Nazarian/EE477L/Fall 2012 27

 Parasitics Capacitance (Cont.)
Lets look at four metal traces above two other metal traces.
Between each of these wires, there is effectively a parallel plate
capacitor. There is also a capacitance from each of the four wires
down to the lower layer, and from the lower layer to the
substrate. We also have the fringe capacitances all the way down.
Every little piece of your circuit speaks to every other little piece
of your circuit, through some kind of a capacitance. In higher
frequency and higher speed circuit, the parasitic capacitance can
kill the chip, if the designer does not pay attention to it

Shahin Nazarian/EE477L/Fall 2012 The figure is from reference [1] 28

 Parasitics Capacitance (Cont.)
Wire Length
If you are told some areas of wiring need to be low parasitic,
one of the easiest ways to accomplish that is to keep the wire
as short as possible, as mentioned above. If you reduce the
length of the wire, you are reducing the overlap between the
wire and substrate, or the wire and something else that
happens to be conducting

(a) (b)
Shahin Nazarian/EE477L/Fall 2012 The figures are from reference [4] 29
 Parasitics Capacitance (Cont.)
Metal Selection
In this figure we see two circuits, each placed in a P-
substrate. You can see that each circuit has a capacitance to
substrate. We also have the parasitic resistance of the
substrate itself. The parasitics can couple the noise from
circuit 1 to circuit 2 through substrate. This could be a real
problem if you are trying to keep circuit 2 isolated from noise

Shahin Nazarian/EE477L/Fall 2012 The figure is from reference [1] 30

 Parasitics Capacitance (Cont.)
Metal Selection
We could use the highest-level metal, the metal farthest
away from the substrate, to reduce parasitics, because the
further you get from substrate the less capacitance you have
Unfortunately, this is not always true. Confined by design
rules, the minimum width of a higher level metal is usually
larger than that of a lower level metal
Go to get the minimum width of metals and cap to
substrate/unit area of metals to calculate which layer of
metal gives the minimum cap to substrate/unit length

Shahin Nazarian/EE477L/Fall 2012 31

 Parasitics Capacitance (Cont.)
Metal over circuit
When a wire runs over the top of another circuit (foreign
circuit), parasitic capacitance develops between that wire and
everything in the underlying circuit

Shahin Nazarian/EE477L/Fall 2012 The figure is from reference [1] 32

 Parasitics Capacitance (Cont.)
Metal over Metal
Running metal over circuitry is common since we want to put
gates as close to each other as possible. But for some
critical wires, which are sensitive to noise, you need to
route them around circuitry

Shahin Nazarian/EE477L/Fall 2012 The figure is from reference [1] 33

 Parasitics Resistance
The IR drop
Know the number of squares in your wire, go to process
manual to find out the resistance of that particular wire
With the current the wire needs to carry, you could obtain
the IR drop along this wire. If the IR drop is larger than
the design requirement, making the wire wider could reduce
the IR drop
It is discussed in EE577B, how IR drop affects the VDD
and in turn the performance of the design

The figure is from reference [1]

Shahin Nazarian/EE477L/Fall 2012 34

 Parasitics Resistance (Cont.)
Wiring Options
The power supply to this array of circuits runs along from
the bond pad into each circuit as shown in the figure
Our circuit designer tells us that the current for the various
blocks are 1mA, 5mA, 10mA, 1mA, 1mA and 1mA.
Unfortunately, the block needing the most current is
farthest from the pad

Shahin Nazarian/EE477L/Fall 2012 The figure is from reference [1] 35

 Parasitics Resistance (Cont.)
Wiring Options
We could size our metal to meet the maximum IR drop. In
which case, the wire width needs to be 38 microns, as
shown in (a). It seems that we waste wire at the end,
since toward the end of the line we are merely supplying
11mA. So we could taper the width as shown in (b)

(a) (b)

Shahin Nazarian/EE477L/Fall 2012 The figures are from reference [1] 36

 Parasitics CMOS transistor
You can see a CMOS transistor has a capacitance
from the well to the substrate, a capacitance from
the gate to the well and a whole bunch of other
ancillary capacitances
The series resistance of the gate stripe, in
conjunction with the gate capacitance, forms an RC
time constant that slows the device even further

Shahin Nazarian/EE477L/Fall 2012 The figure is from reference [1] 37

 Parasitics CMOS transistor (Cont.)
The technique you can use to reduce CMOS device parasitics is to
reduce the series resistance of the gate stripe by splitting the
gate stripe into multiple fingers and wiring them in parallel. Just
by splitting a device in two for example, reduces your RC time
constant by a factor of 4. When splitting a device, source-drain
sharing is a good way to save area

Shahin Nazarian/EE477L/Fall 2012 The figures are from reference [4] 38

Parasitics CMOS transistor (Cont.)

39
Shahin Nazarian/EE477L/Fall 2012
 Reference
[1]. Christopher Saint and Judy Saint (2002), IC
Mask Design Essential Layout Techniques
McGraw-Hill
[2] Sung-Mo Kang, Yusuf Leblebici,CMOS (2003)
Digital Integrated Circuits MCGraw-Hill
[3] Neil Weste, David Harris (2011), CMOS VLSI
Design: A Circuits and Systems Perspective
[4] Spring 2009_EE577A Classnotes from Professor
Pedram

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