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EE477L

MOS VLSI Circuit Design

MOSFET

Metal Oxide Semiconductor Field Effect Transistor

(MOSFET) is a unipolar: single carrier-type device

The dominant dc current is carried by only one type:

electrons (in nMOS) and holes (in pMOS)

By contrast, a BJT (Bipolar Junction Transistor) depends

on both electrons and holes

They are called bipolar because the main flow of

electrons through them takes place in two types of

semiconductor material: P and N, as the main current

goes from emitter to collector (or vice versa). In

other words, two types of charge carriers, electrons

and holes, comprise this main current through the

transistor

MOS occupies smaller silicon area than BJT and with

fewer fabrication steps 2

Shahin Nazarian/EE477L/Fall 2012

Two-Terminal MOS Structure

np ni2 (ni 1.451010 cm 3 )

If substrate is uniformly doped @ NA (Typically 1015 to 1016 )

ni2

p p0 N A n p0

NA

3

Shahin Nazarian/EE477L/Fall 2012

Band Theory Background

the occupied molecular orbitals and is

lower in energy than conduction band.

It is generally completely full in

semi-conductors. When heated,

electrons from this band jump out

across the band gap and into the

conduction band, making the material

conductive

Conduction band: The band of

orbitals that are high in energy and

generally empty. In semiconductors,

it is the band that accepts electrons

from the valence band

4

Shahin Nazarian/EE477L/Fall 2012

Band Theory Background (Cont.)

semiconductors, the band gap

generally refers to the energy

difference btn the top of the valence

band and the bottom of the

conduction band; it is the amount of

energy required to free an outer shell

electron from its orbit about the

nucleus to the conduction band

A material with a small, positive band

gap (< 3 eV) is referred to as a

semiconductor. A material with a

large band gap is called an insulator

5

Shahin Nazarian/EE477L/Fall 2012

Band Theory Fermi Level

Each of the many distinct energies with which an electron can be

held within a solid is called an energy level. According to the

quantum mechanic laws, each energy level can accommodate only a

limited number of electrons

Fermi level: A measure of the energy of the least tightly held

electrons within a solid, named for Enrico Fermi. It is important in

determining the electrical and thermal properties of solids

The value of the Fermi level at absolute 0K (i.e., 273.15C) is a

constant for each solid and called Fermi energy. It changes as solid

is warmed & as electrons are added to or withdrawn from solid

Fermi Level

6

Shahin Nazarian/EE477L/Fall 2012

Band Theory Fermi Level (Cont.)

The Fermi level is any energy level having the probability that it is

exactly half filled with electrons. Levels of lower energy than the

Fermi level tend to be entirely filled with electrons, whereas

energy levels higher than Fermi tend to be empty

When materials with different individual Fermi levels are placed in

contact, some electrons flow from the material with the higher

Fermi level into the other material. This transfer of electrons

raises the lower Fermi level and lowers the higher Fermi level

When transfer is complete, Fermi levels of two materials are

equal. This behavior is important in electronic devices that put

different materials side by side

Fermi Level

7

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Intrinsic Valence & Conduction Bands

Band gap = 1.1 eV

are generated in pairs by thermal excitation of valence band

electrons

Leaving the valence band and entering the conduction band,

each of the thermally excited electrons generates a (mobile)

hole in the valence band

Both, the electrons lifted into the conduction band and the

defect electrons (holes) left behind the valence band will

contribute to a current flow. Generally, this kind of intrinsic

conductivity is negligible compared to the conductivity due to

ionized impurities 8

Shahin Nazarian/EE477L/Fall 2012

Doped Valence and Conduction Bands

Impurity atoms, i.e., donors or acceptors replace some

silicon atoms in the crystal lattice

Donors: a valence of five e.g., phosphorus (P) or

arsenic (As))

Acceptors: a valence of three, e.g., boron (B))

If the donors or acceptors get ionized, each donor

delivers an electron to the conduction band. Also each

acceptor will capture an electron from valence band

leaving a hole behind

Normally, at room temperature all donors (density ND)

and acceptors (concentration NA) are ionized

In an n-type semiconductor doped with donors, the

electron density is approximately n=ND where the intrinsic

concentration ni can be neglected (ni << ND)

9

Shahin Nazarian/EE477L/Fall 2012

Energy Band Diagram of P-type Substrate

Fermi Potential:

EF Ei

F volts

q

kT ni

Fp ln ( N A ni )

q NA

ni 1.45 1010 cm 3

k 1.38 1023 J / K Boltzmann

19

Constant

q 1.6 10 C kT / q 26mV@roomtemp

potential is positive:

kT N

Fn ln D ( N D ni )

q ni 10

Shahin Nazarian/EE477L/Fall 2012

Energy Band Diagram of P-type Substrate

(Cont.)

ni 1.45 1010 cm 3

Boltzmann

k 1.38 1023 J / K

Constant

19

q 1.6 10 C

kT / q 26mV@roomtemp

and vacuum (free space)

q electron affinityof Si

11

Shahin Nazarian/EE477L/Fall 2012

Energy Band Diagram of P-type

Substrate (Cont.)

ni 1.45 1010 cm 3

k 1.38 1023 J / K Boltzmann

Constant

q 1.6 1019 C

kT / q 26mV@roomtemp

electron to move from Fermi level into free space:

12

Shahin Nazarian/EE477L/Fall 2012

MOS System Energy Bands

Ec = conduction band edge = energy level of free electrons in the silicon

Ev = valence band edge = energy level of free holes in the silicon

Ei = intrinsic energy level = Fermi level for intrinsic silicon material =

approximately the center of the forbidden gap

EFP = Fermi level in the P substrate material ; FP denotes the Fermi potential

Ec-Ev = band gap of silicon = 1.1 eV

Work function = qS = q+ (Ec EFP) where is the electron affinity of silicon

qMS = qM qS = metal-to-semiconductor work function; VFB = MS = flat-

band voltage 13

Shahin Nazarian/EE477L/Fall 2012

MOS System Energy Bands (Cont.)

Eo

qMS

qS

qM

qFp

Bands necessarily bend downward at semiconductor oxide

interface due to lining up of Fermi levels and built-in

positive oxide charge (surface states and traps)

Flat Band Voltage in the presence of oxide charges VFB = MS

Qfc/Cox is the (negative) voltage that must be applied to the

gate in order to flatten the bands in the silicon; Qfc is the

built-in (fixed) oxide charge (per cm2) and Cox is the gate

oxide capacitance (per cm2)

14

Shahin Nazarian/EE477L/Fall 2012

MOS System Energy Bands (Cont.)

Eo

qMS

qS

qM

qFp

Accumulation: interface strongly p type

Depletion: interface depleted of mobile carriers

Inversion: interface strongly n type

15

Shahin Nazarian/EE477L/Fall 2012

Example: Flat Band

substrate is given: Fp = 0.2ev

Using the electron affinity for silicon and work function for

aluminum given in the Fig. calculate the built-in potential

difference across the MOS system. Assume no other charge

exists in the oxide or the oxide-silicon interface

Fp = 0.2ev , First calculate the work function for doped

silicon: qS = q+ (Ec EFP)

Electron affinity of silicon (q) is 4.15 from the Fig. 16

Shahin Nazarian/EE477L/Fall 2012

Example: Flat Band (Cont.)

= 4.15 + .55+ .2 ev= 4.9ev

Work function difference btn silicon substrate and the

aluminum gate: qM qS = 4.1ev-4.9ev = -0.8ev

If a voltage corresponding to this potential difference is

applied externally btn the gate and the substrate the

bending of the energy bands near the surface can be

compensated and becomes flat, therefore the voltage

difference M - S is called the flat-band voltage (VFB =

M - S ) 17

Shahin Nazarian/EE477L/Fall 2012

NMOS Accumulation

18

Shahin Nazarian/EE477L/Fall 2012

NMOS Depletion

19

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NMOS Inversion

20

Shahin Nazarian/EE477L/Fall 2012

NMOS Accumulation

capacitor on P substrate induces holes at the silicon-

oxide interface

VGB < 0 => Electric field direction: towards gate

Energy bands bend upward making the interface

strongly P type

21

Shahin Nazarian/EE477L/Fall 2012

NMOS Depletion

(capacitor on a P substrate) causes the silicon-oxide

interface to be depleted of mobile charge carriers

VGB (small) > 0 => Electric field direction: towards

substrate

Energy bands bend downward near the surface

22

Shahin Nazarian/EE477L/Fall 2012

NMOS Depletion (Cont.)

function of surface potential, s, by integrating Poisson

equation for sheet charge from the interface into the bulk

dQ

ds x.

si

First, assume the mobile hole charge in the thin horizontal

layer parallel to the surface is:

dQ - q.NA .dx 23

Shahin Nazarian/EE477L/Fall 2012

Deriving the Depletion Width

parallel to the Si surface, which needs to be

x qN A displaced to get depletion

d dQ x dx Change in the surface potential required

si si to displace dQ by x (Poisson eqn.)

s xd q.N A .x q.N A .xd2

F ds 0 Si

dx s F

2 Si

2 si | F s |

xd , Q qN A xd 2qN A si | F S |

qN A 24

Shahin Nazarian/EE477L/Fall 2012

Depletion Layer Change to Inversion

2 si F s

xd

qNA

Increase VG => the downward banding increases till Ei eventually

becomes smaller than EFp on the surface which means surface

become n-type (the positive gate voltage attracts minority

electrons from bulk in the thin layer at surface

Definition: Surface is inverted when density of mobile electrons on

the surface becomes equal to that of holes in the bulk => surface

potential must be equal to Fp but reverse polarity, i.e., s = - Fp

Any further increase in VG increases mobile electron concentration,

but not the depletion depth => max depletion depth, xdm

25

Shahin Nazarian/EE477L/Fall 2012

Depletion Layer Change to Inversion (Cont.)

siF

xdm 2

qN A

26

Shahin Nazarian/EE477L/Fall 2012

Structure of MOS Transistor

conduction. Now two n+ regions are added as the

current conducting terminals

Conventionally all terminal voltages are defined wrt VS

27

Shahin Nazarian/EE477L/Fall 2012

Threshold Voltage

metal-gate-oxide: increase VG and surfaces is inverted

as soon as surface potential reaches Fp. The

corresponding VGS is called threshold voltage, VT0

Note that increasing VGS beyond VT0 will not increase

the depletion region depth (xd will stay at xdm) but

increases minority carrier [electron] concentration

VDS would then allow current flow

28

Shahin Nazarian/EE477L/Fall 2012

Physical Components of VT

1) work function difference btn gate and channel, GC

GC = F (substrate) M ( for metal gate)

GC = F (substrate) F (for polysilicon gate)

This component account for part of voltage drop across MOS system

that is built in

2) gate voltage to change surface potential: -2F

3) gate voltage to offset the depletion region charge density due to fixed

acceptor ions located in the depletion region: QB0 2qNA si 2F

If substrate (body) is biased at different voltage level than source:

QB Cox Cox si tox oxide cap per unit area

Therefore the component that offsets the depletion charge:

QB 2qN A s i 2F VSB

4) gate voltage to offset the fixed positive charges in gate oxide and in

the silicon interface due to impurities/lattice imperfections at the

interface: Qox Cox

29

Shahin Nazarian/EE477L/Fall 2012

Body Effect

For zero substrate bias (VSB=0)

VT 0 GC 2F QB0 Cox Qox Cox

For nonzero substrate bias:

QB QB 0

VT VT 0

Co x

QB QB 0

Cox

2qN A Si

Cox

2F VSB 2 F

VT VT 0 2 F VSB 2 F

2qN A Si

Body effect (or substrate bias) coefficient

Cox

Shahin Nazarian/EE477L/Fall 2012 30

Threshold Voltage with Body Effect

VT VT 0 2 F VSB 2 F

2qN A Si

VT 0 GC 2F QB0 Cox Qox Cox

Cox

Threshold voltage determinants:

Gate conductor materials

Gate oxide material & thickness

Substrate doping

Impurities in Si-oxide interface

Source-bulk voltage VSB

Temperature

31

Shahin Nazarian/EE477L/Fall 2012

Signs of Key Parameters

F Negative Positive

Positive Negative

32

Shahin Nazarian/EE477L/Fall 2012

Example 3.2 VT0 (Zero Body Bias)

Calculate the threshold voltage VT0 at VSB=0, for a polysilicon

gate n-channel MOS transistor with the following parameters:

Substrate doping density:

Polysilicon doping density: N A 1016 cm3

Gate oxide thickness: ND 21020 cm3

Oxide-interface fixed charge tox 500 A

density: Nox 41010 cm2

Dielectric and oxide ox 0.34 1012 Fcm1 , si 1.06 1012 Fcm1

permittivities:

QBO QOX

VT 0 GC 2F ( sub) GC F ( sub ) F ( gate)

COX COX

kT ni 1.45 1010

F ( sub) ln 0.026ln 16 0.35V

q NA 10

kT N D 2 1020

F ( gate) ln 0.026ln 10

0.60V

q ni 1.45 10

GC F ( sub ) F ( gate ) 0.35V 0.60V 0.95V

33

Shahin Nazarian/EE477L/Fall 2012

Example 3.2 (cont.)

QBO QOX

VT 0 GC 2F ( sub)

COX COX

QB0 2qNA Si | 2F ( sub) | 2(1.6 1019 C)(1016 cm3 )(1.061012 Fcm1 ) | 2 0.35V |

4.87 108 C / cm2

COX 6.8 10 F / cm2

QOX qNox (1.6 1019 C)(4 1010 cm2 ) 6.4 109 C / cm2

0.72V 8

0.09V

COX 6.8 108 F / cm2 COX 6.8 10 F / cm 2

34

Shahin Nazarian/EE477L/Fall 2012

Threshold Voltage Adjustment

VT is increased by adding extra p-type impurities, or

decreased by implanting n-type impurities into channel

region

VT can be adjusted to become negative for nMOS,

i.e., at VGS=0 conduction exists. Remember that

this type of nMOS is called depletion-type (a

normally-ON nMOS)

Depletion-type Symbols

35

Shahin Nazarian/EE477L/Fall 2012

Example 3.3 Body Effect

Consider the n-channel MOS transistor with the following

process parameters:

Substrate doping density: N A 10 cm

16 3

20 3

Oxide-interface fixed charge density: Nox 410 cm

10 2

Dielectric and oxide permittivities: ox 0.34 1012 Fcm1 , si 1.06 1012 Fcm1

In digital circuit design, the condition VSB=0 cannot

always be guaranteed for all transistors. Plot the

threshold voltage VT as a function of VSB

VT VT 0 ( | 2F VSB | | 2F |)

2qN A si 2(1.6 1019 C )(1016 cm3 )(1.06 1012 Fcm1 )

COX 6.8 108 F / cm2

5.824 108 C / V 1/ 2cm2

0.85V 1/ 2

Shahin Nazarian/EE477L/Fall 2012

Example 3.3 (Cont.)

37

Shahin Nazarian/EE477L/Fall 2012

NMOS Modes of Operations

In linear

region:

In

saturation

region:

38

Shahin Nazarian/EE477L/Fall 2012

MOSFET I-V Characteristics

Consider the cross-sectional view of an n-MOS

transistor which is working in linear region

Coordinates system:

x direction: perpendicular to the surface pointing down

y direction: parallel to the surface originating at source (y=0)

I-V Characteristics (Cont.)

Assumptions:

No body effect: VS=VB=0

Inversion region is present between drain and source: VGS>VT0

Electric field component Ey is dominant compared to Ex;

therefore, we can only consider current flow in the y-direction

We must simplify the geometry of the channel region: Gradual

Channel Approximation (GCA)

40

Shahin Nazarian/EE477L/Fall 2012

I-V Characteristics Averaging Method

Each carrier in the channel is accelerated to an avg velocity

proportional to the lateral electrical field, i.e., the field

between source and drain: velocity: . E .V L

ds

where the proportionality constant, , is called the mobility

The time required for the carriers to cross the channel is

hence L/, therefore:

Qchannel Cg (VGC Vt ) CoxW . L(VGC Vt )

IDS CoxW (VGC Vt )

L / L / L /

Average channel voltage, Vc = (VS + VD)/2 = VS + VDS/2

therefore VGC =VGS VDS/2, therefore:

W V

ID n Cox (VGS VT DS 2 )VDS

L

or:

W VDS 2

ID n Cox (VGS VT )VDS 2

L

Shahin Nazarian/EE477L/Fall 2012 41

I-V Characteristics (Cont.)

coordinate y

Boundary conditions:

Vc ( y 0) VS 0

Vc ( y L) VDS

Entire channel region between source and drain is

inverted: V V GS T0

VG D VG S VD S VT 0

QI ( y) Cox VGS VCS ( y) VT 0

42

Shahin Nazarian/EE477L/Fall 2012

I-V Characteristics (Cont.)

Electron velocity:

n ( y) n . E( y) n . dVc dy

I D n ( y)QI ( y)W

I Ddy nCoxW (VGS Vc ( y) VT 0 )dVc

We can now integrate equation above along the

channel:

VDS

ID . L W . n . Cox 0

43

Shahin Nazarian/EE477L/Fall 2012

I-V Characteristics Linear Region

Therefore:

n .Cox W

ID 2(VGS VT 0 )VDS VDS2

2 L

The current equation may also be rewritten as:

ID

k' W

2 L

2(VG S VT 0 )VD S VD2S

k (VG S VT 0 )VD S VD2S 2

where parameters k and k are defined as:

W W

k ' n .Cox k k ' n .Cox

L L

44

Shahin Nazarian/EE477L/Fall 2012

Example 3.4

For an n-channel MOS transistor with n=600 cm2/V.s,

Cox=7x10-8 F/cm2, W=20 m, L=2 m and VT0=1.0 V, plot the

relationship between ID and the terminal voltages

20m

k 600cm2 / V .s 7 108 F / cm2 0.42 mA / V 2

2m

I D 0.21 mA / V 2 2(VGS 1)VDS VDS

2

Note the assumption we made to guarantee that the entire channel region

btn source and drain is inverted: VGS VT 0

VGD VGS VDS VT 0 VDS VGS VT 0

45

Shahin Nazarian/EE477L/Fall 2012

nMOS Cross-sectional View

saturation

46

Shahin Nazarian/EE477L/Fall 2012

Saturation Region

inversion layer connecting S to D

With VDS > 0, a positive current ID flows from D to

S but with VDS increase, inversion layer and channel

depth close to D-end start to decrease

When VDS=VDSAT the inversion at drain is reduced to

zero: this is called pinch-off

Shahin Nazarian/EE477L/Fall 2012 47

Saturation Region (Cont.)

to D, and grows twd S. Increasing VDS, reduces effective

channel while channel end voltage remains essentially constant

and equal to VDSAT

Pinch-off channel absorbs most of the excess voltage drop

(VDS-VDSAT) and high electric field region forms btn channel end

and D boundary

Electrons arriving to channel end are injected into drain

depletion and accelerated twd drain in the high field reaching

the drift velocity limit

Shahin Nazarian/EE477L/Fall 2012 48

I-V Characteristics Saturation Region

of transistor operation, i.e., VG S VT 0

VG D VG S VD S VT 0

For VDS VDSAT = VGS-VT0, the MOS transistor is in

the saturation region

function of the drain voltage, VDS, beyond the

saturation voltage, i.e. for VDS VDSAT

n Cox W

2 VGS VT 0 VGS VT 0 VGS VT 0

2

I D (sat )

2 L

n .Cox W

VGS VT 0

2

I D ( sat )

2 L 49

Shahin Nazarian/EE477L/Fall 2012

nMOS ID as a Function of VDS and VGS

Enhancement vs Depletion MOSFET

N channel enhancement mode: normally OFF

VT > 0

N channel depletion mode: normally ON

VT < 0

P channel enhancement mode: normally OFF

VT < 0

P channel depletion mode: normally ON

VT > 0

51

Shahin Nazarian/EE477L/Fall 2012

Channel Length Modulation

QI ( y 0) Cox (VGS VT 0 )

QI ( y L) Cox (VGS VT 0 VDS )

This means that under this bias condition the channel

is pinched-off at the D end

If VDS is increased further than VDSAT, a larger

portion of the channel becomes pinched-off

Thus, the effective channel length is reduced to:

L ' L L

where L is the length of the channel with QI = 0

52

Shahin Nazarian/EE477L/Fall 2012

Channel Length Modulation (Cont.)

source Vc ( y L ') VDSAT

Drain current can be found using the effective channel

length

n Cox W 1 C W

VGS VT 0 n ox VGS VT 0

2 2

I D ( sat )

2 L' L 2 L

1

L

It can be shown that: L VDS VDSAT

53

Shahin Nazarian/EE477L/Fall 2012

Channel Length Modulation (Cont.)

L

We can make the following approximation: 1 1 VDS

L

where (an empirical parameter) is the channel length

modulation coefficient

Assuming VDS << 1, we calculate the saturation

current as:

n .Cox W

VGS VT 0 1 VDS

2

I D ( sat )

2 L

Channel Length Modulation (Cont.)

linear drain-bias dependence to channel length

shortening not accurate but sufficient enough for

first-order hand calculations

Slope of I-VDS curve in saturation is determined by

n .Cox W

VGS VT 0 1 VDS

2

I D ( sat )

2 L slope

Substrate Bias Effect

Applying a substrate voltage changes the threshold

voltage

VT VSB VT 0 . 2F VSB 2F

We can simply replace the threshold voltage terms in

linear-mode and saturation-mode current equations

with VT(VSB)

n .Cox W

I D (lin) 2 VGS VT (VSB ) VDS VDS

2

2 L

n .Cox W

. . VGS VT (VSB ) . 1 .VDS

2

I D ( sat )

2 L

MOSFET Current-Voltage Equations

nMOS transistor

I D (cutoff ) 0 VGS VT

n .Cox W

I D (lin) 2 VGS VT (VSB ) VDS VDS

2

VGS VT , VDS VGS VT

2 L

n Cox W

VGS VT (VSB ) 1 VDS VGS VT , VDS VGS VT

2

I D ( sat )

2 L

pMOS transistor

I D (cutoff ) 0 VGS VT

p .Cox W

I D (lin) 2 VGS VT (VSB ) VDS VDS

2

VGS VT , VDS VGS VT

2 L

p Cox W

VGS VT (VSB ) 1 VDS VGS VT , VDS VGS VT

2

I D ( sat )

2 L

Shahin Nazarian/EE477L/Fall 2012 57

I-V Characteristics

Vgsn5

Vgsn4

Idsn

Vgsn3

-Vdsp

-VDD Vgsn2

Vgsp1 Vgsn1

Vgsp2 0 VDD

Vgsp3 Vdsn

Vgsp4 -Idsp

Vgsp5

Current vs. Vout, Vin

VDD

Idsp

Vin Vout

Idsn

Vin0 Vin5

Vin1 Vin4

Idsn, |Idsp|

Vin2 Vin3

Vin3 Vin2

Vin4 Vin1

VDD

Vout

Shahin Nazarian/EE477L/Fall 2012

Parameter Measurement: VT0,VT,,, kn)

regions were found with some approximations and

simplifications is their accuracy is limited

To get maximum accuracy, the parameters in the

equations, i.e., VT0,VT,, , and k should be

determined by experimental measurements

Consider the following test circuit, VSB is constant

and ID is measured for different values of VGS

60

Shahin Nazarian/EE477L/Fall 2012

VT0,VT,, and kn Measurement

Here since D and G of the transistor are connected

together, the saturation condition is always satisfied,

i.e., VDS > VGS-VT

Ignoring the channel length modulation effect, we can

write:

.VGS VT 0

kn

I D ( sat )

2

or:

.VGS VT 0

kn

I D ( sat )

2

VT0,VT,, and kn Measurement (Cont.)

plotted against the VGS,

the slope and the voltage-

axis intercept of the

resulting curve(s) can

determine parameters kn

and VT0

For different VSB, we can

find VT(VSB) and from

there we can calculate

VT VS B VT 0

2F VS B 2F

Shahin Nazarian/EE477L/Fall 2012 62

Measurement

We need a different experimental setup to measure

the channel length modulation coefficient,

n .Cox W

VGS VT 0 1 VDS

2

I D ( sat )

2 L

VGS is set to VT0+1, and VDS > VGS VT0 (chosen

sufficiently large) so that the transistor operates in

the saturation mode. IDSAT is then measured for two

different VDS values. is calculated as follows:

I D 2 1 .VDS 2

I D1 1 .VDS1

MOSFET Scaling

Scaling of MOS transistor is concerned with

systematic reduction of overall dimensions of the

devices as allowed by the available technology, while

preserving the geometric ratios found in the larger

devices

From the table below we observe that a new

manufacturing technology is introduced every two or

three years. Furthermore, the down scaling factor S

is from 1.2 to 1.5 from one generation to the next

for a typical CMOS gate-array process

Year 1985 1987 1989 1991 1993 1995 1997 1999

Feature 2.5 1.7 1.2 1.0 0.8 0.5 0.35 0.25

Size (m)

Full Scaling (Constant-Field Scaling)

Question? What is the average S for the 1999 to 2012

range?

Full Scaling (Constant-Field Scaling)

This scaling option attempts to preserve the magnitude of

internal electric fields in the MOSFET, while the

dimensions are scaled down by a factor of S

All potentials must be scaled down by S, including VT0

Poisson equation (relation btn charge and electric field)

dictates that charge densities scaled up by S

Therefore:

1. All dimensions, including those vertical to the

surface, 1/S

2. Device voltages, 1/S

3. Concentration densities, S

Examples: C'ox si t 'ox S. si tox S.Cox

Aspect ratio, W/L, remains unchanged so kn is

scaled up by S

Shahin Nazarian/EE477L/Fall 2012 66

MOS Full Scaling

All dimensions, including those vertical to the surface, 1/S

Device voltages, 1/S

Concentration densities, S

Full Scaling (Constant-Field Scaling)

Channel width W W=W/S

Gate oxide thickness tox tox= tox/S

Power supply voltage VDD VDD=VDD/S

ND= S.ND

Shahin Nazarian/EE477L/Fall 2012 68

Full Scaling (Cont.)

ID for linear and saturation modes:

I (lin)

'

D

k n'

2

. 2.VGS

'

VT' .VDS

'

VDS

'2

S.kn 1 I (lin )

2 S

. 2 . 2.VGS VT .VDS VDS

2

D

S

I ( sa t)

'

D

k n'

2

'

. VGS VT' S .2k

2 n

.

1

S2

.VGS VT 2

I D ( sa t)

S

For power dissipation of the transistor, we obtain:

1 P

P I .V

' '

D

'

DS 2 .I D .VDS 2

S S

Device area reduction by S2, so power density per unit

area remains unchanged for the scaled device

Cg = WLCox scales down by S, therefore faster charge-

up charge-down for the scaled device

Reduced dimensions would result in reduction of

various parasitic caps and resistances

69

Shahin Nazarian/EE477L/Fall 2012

Constant-Voltage Scaling

Power supply voltage as well as the terminal voltages

remain unchanged (may be preferred over full-scaling for

practical reasons)

Therefore

1. All dimensions including those vertical to the surface,

1/S

2. Supply voltage and threshold voltages, 1

3. The concentration densities, S2

Doping densities NA N D increased by S2 (NA=S2.NA)

Constant-Voltage Scaling (Cont.)

I (lin )

'

D

k n'

2

. 2. VGS'

VT' .VDS

'

VDS

'2

S .kn

2

. 2.VGS VT .VDS VDS

2

S . I D (lin )

I (sat)

'

D

kn'

2

'

. VGS VT' S.2k .V

2 n

GS VT S. I D (sat)

2

'

S. I D .VDS S. P

Thus, the power density (power dissipation per unit

area) is found to increase by a factor of S3

The large increase in current and power densities may

result in reliability issues such as electromagnetism,

hot-carrier degradation, oxide breakdown, and

electrical over-stress

Shahin Nazarian/EE477L/Fall 2012 71

Short-Channel Effects

Motivation: Simple GCA (Gradual Channel Approximation)

does not consider the scaling effect, so I-V equations

have to be modified, also some physical limitations may

restrict scaling amount for some device dimensions

A MOS transistor is called a short-channel device if its

effective channel length Leff is on the same order of

magnitude as the depletion region thickness of the

source and drain junctions

The short-channel effects are attributed to two

physical phenomena:

1. Limitation on the electron drift characteristics in the

channel

2. Reduction of the threshold voltage due to shortening

of the channel length

Shahin Nazarian/EE477L/Fall 2012 72

Velocity Saturation

The velocity of charge carriers in semiconductor is

under the influence of electric field

At a given electric field drift velocity is determined

by the mobility of charge carrier d = . E

However with stronger electric fields, due to the

heating of free carriers at high electric fields and

carrier scattering, drift velocity rolls off and

saturates dsat = . Esat where Esat is the electric

field value that saturation happens

Electric field at which velocity saturation occurs is

different for different semiconductors; e.g. Si:

107 cm/s, GaAs: 107 cm/s, 6H-SiC: 2x107 cm/s

which happens at channel electric fields of Ey=105

V/cm

73

Shahin Nazarian/EE477L/Fall 2012

ID Derivation for Short-Channel Devices

lateral electric field Ey along the channel increases

Velocity saturation reduces the saturation-mode

current below the current value predicted by

conventional long-channel current equations

For saturation current we have:

function of VGS and is virtually independent of the

channel length

74

Shahin Nazarian/EE477L/Fall 2012

Mobility Degradation

cause the carriers to scatter against the surface and

also reduce the carrier mobility

This effect is called mobility degradation

Mobility degradation is modeled by replacing with a

smaller eff

75

Shahin Nazarian/EE477L/Fall 2012

Mobility Degradation (Cont.)

In short-channel MOS transistor, the carrier velocity

in the channel is also a function of the vertical electric

field, Ex

Since the vertical field influences the scattering of

the carriers in the surface, the surface mobility is

reduced with respect to the bulk mobility

The surface electron mobility can be expressed as

follows: ( eff )

n 0

n 0

n

1 .E x ox

1 V Vc (y)

t ox Si GS

where n0 is the low-field surface mobility and is an

empirical factor. A simple estimation of the above

formulaeby using an empirical coefficient, , yields:

n 0

n ( eff )

1 VGS VT 76

Shahin Nazarian/EE477L/Fall 2012

Short-Channel Effect on Threshold Voltage

Long channel formula: VT VT 0 2

F VSB 2F

Previously channel depletion region was assumed to be

created only by the applied gate voltage, and depletion

regions associated with the D and S pn-junctions were

neglected

In short-channel MOS, there is a significant amount of

depletion charge around the n+ source and drain

diffusion regions, (which means a significant portion of

the total depletion region charge under gate is due to

the D and S junction depletions) hence, long channel

model overestimates depletion charge that must be

supported by gate voltage

The threshold voltage value we derived earlier is

thus larger than actual threshold voltage in short-

channel case 77

Shahin Nazarian/EE477L/Fall 2012

Simplified Channel Geometry

VT 0 (shortchannel) VT 0 VT 0

associated with the source junction and drain junction, respectively

xdS and xdD represent the depth of the pn-junction depletion regions

associated with source and drain, respectively. The edges of the

source and drain diffusion regions are represented by quarter-circular

arcs, each with a radius of xj

The vertical extent of the bulk depeltion region into the substrate is

represented by xdm

Shahin Nazarian/EE477L/Fall 2012 78

Effect on Threshold Voltage (Cont.)

due to the short-channel effect VT 0 (shortchannel) VT 0 VT 0

From the figure, we can calculate the

charge in trapezoidal region:

L LD

QB 0 1 S . 2.q. Si .N A . 2F

2L

may be approximated as:

2. Si 2. S i

xdS .0 xd D .(0 VD S )

q.N A q.N A

With the junction built-in voltage:

kT N D N A

0 ln 2

q ni

Shahin Nazarian/EE477L/Fall 2012 79

Effect on Threshold Voltage (Cont.)

( x j xdD ) 2 xdm

2

( x j LD ) 2

Solving for LD, we obtain:

2 xdD

LD x j x ( x x ) 2 x j xdD

2 2 2

x j . 1 1

j dm dD

xj

Similarly we can calculate LS:

2 x

LS x j . 1 d S

1

xj

The amount of threshold voltage reduction VT0

1 xj 1 2 xdS 2 xdD

VT 0 . 2q Si N A 2F . . . 1 1 1

Cox L 2 xj xj

Key dependency

Shahin Nazarian/EE477L/Fall 2012 80

Effect on Threshold Voltage (Cont.)

VT 0 (shortchannel) VT 0 VT 0

1 xj 1 2 xdS 2 xdD

VT 0 . 2q Si N A 2F . . . 1 1 1

Cox L 2 xj xj

asdf Key dependency

long-channel L>>xj so the shift term is negligible, however

this term becomes more prominent in short-channel that xj

is comparable to L

81

Shahin Nazarian/EE477L/Fall 2012

Short-Channel Rolloff Effect on

Threshold Voltage (Cont.)

VT Rolloff effect

82

Shahin Nazarian/EE477L/Fall 2012

Narrow-Channel Effect

MOS transistors with channel widths W on the same

order of magnitude as the maximum depletion region

thickness, xdm, are narrow-channel devices

As shown in the figure, the oxide thickness in the

channel region is tox, while the regions around the

channel are covered by a thick field oxide (FOX)

83

Shahin Nazarian/EE477L/Fall 2012

Narrow-Channel Effect (Cont.)

Since the gate electrode overlaps with this thick field

oxide, a relatively shallow depletion region forms underneath

this FOX-overlap area as well

The gate voltage must support this additional depletion

charge

The actual threshold voltage for such devices is larger than

that predicted by the conventional threshold formula

The additional contribution to the threshold voltage due to

the narrow-channel effects can be modeled as follows:

VT 0 (narrowchannel) VT 0 VT 0

where is an empirical parameter depending on the shape of

the fringe depletion region. If the depletion region edges

are modeled by quarter-circular arcs, then = /2

1 x

VT 0 2q Si N A 2F dm Key dependency

Cox W

84

Shahin Nazarian/EE477L/Fall 2012

Other Limitations of Small-Device

We used simple one-dimensional GCA (gradual channel

approximation) that assumes electric components are

parallel and perpendicular to the surface

In small-geometry MOSFETs, the potential barrier

for the electrons in the channel is controlled by both

gate-source voltage and drain-source voltage

If the drain voltage is increased, the potential

barrier in the channel decreases, leading to drain-

induced barrier lowering (DIBL) and eventually

electron flow btn source and drain even if VGS<VT0.

This flow of current is referred to as the

subthreshold current

85

Shahin Nazarian/EE477L/Fall 2012

Subthreshold Current Conduction

MOSFET results in the following

approximation for subthreshold current:

q q

( A V B V )

r GS DS

qD Wx n KT KT

I ( subthreshold ) n c 0 e e

D L

B

electron diffusion coefficient, LB length of the

barrier region in the channel, and r is a

reference potential

86

Shahin Nazarian/EE477L/Fall 2012

Punch-through

the same order of S and D depletion region

thicknesses

farther toward source and the two depletion

regions can eventually merge. This is called

punch-through

sharply when punch-through happens

87

Shahin Nazarian/EE477L/Fall 2012

Hot Carrier Effect

Lower dimensions and higher substrate doping in small geometry

technologies would result in large electric fields under gate

which in turn give rise to electrons and holes with kinetic

energies significantly higher than silicon band gap

These electrons and holes may be injected into the gate oxide

and can cause permanent changes in the oxide interface charge

distribution. This is called hot carrier effect, or sometimes

hot electron effect because this injection happens more often

for electrons due to smaller barrier height of electrons as

compared to holes

88

Shahin Nazarian/EE477L/Fall 2012

Hot carrier injection into the gate oxide

A sizeable increase in the threshold voltage of the affected

transistors and a corresponding decrease in their drain

current driving capability are undesirable results of such hot

carrier injections in the gate oxide

The hot carrier effect is exacerbated as the technology

moves toward smaller device dimensions and higher clock

frequencies

MOSFET Capacitances

used to study DC-response of MOSEFET

In order to examine the transient (AC) response of

MOSFET, we have to determine nature and amount

of parasitic caps associated with MOS transistor

There are two different types of parasitic caps:

1. Device-related capacitances

2. Metal-interconnection capacitances

capacitances

90

Shahin Nazarian/EE477L/Fall 2012

MOSFET Capacitances (Cont.)

The mask length and

actual length of the gate

are indicated by LM, and L

respectively. The extent

of both gate-source and

gate-drain overlap are LD,

and we have: L LM 2.LD

The p+ regions around the

source and drain, namely

the channel-stop implants,

are used to prevent the

formation of any unwanted

channels between two

neighboring n+ diffusion

regions

91

Shahin Nazarian/EE477L/Fall 2012

MOSFET Caps (Cont.)

are not lumped, but distributed,

and their exact calculation is complex

We will identify the parasitic caps

associated with a MOSFET as lumped equivalent

capacitances observed btn device terminals

Such a lumped representation is easily used to

analyze the dynamic transient behavior of the device

Parasitic capacitances are divided into two major

groups:

1. Oxide-related capacitances (Cgd, Cgs, Cgb)

2. Junction capacitances (Cdb, Csb)

92

Shahin Nazarian/EE477L/Fall 2012

MOSFET Capacitances (Cont.)

93

Shahin Nazarian/EE477L/Fall 2012

Oxide-Related Capacitances

Oxide-related capacitances comprise of overlap and

gate-channel capacitances

Overlap capacitances:

CGS (overlap) Cox .W . LD ox

with Cox

CGD (overlap) Cox .W . LD tox

C gs C gd 0

Cgb Cox .W . L

Oxide-Related Capacitances (Cont.)

Cgb 0

1

Cg s Cg d .Co x.W . L

2

Cgb Cgd 0

2

Cgs . Cox . W . L

3

95

Shahin Nazarian/EE477L/Fall 2012

Oxide-Related Capacitances (Cont.)

Capacitance Cut-off Linear Saturation

Cgb(total) CoxWL 0 0

Cgd(total) CoxWLD 1/2CoxWL+ CoxWLD CoxWLD

Cgs(total) CoxWLD 1/2CoxWL+ CoxWLD 2/3CoxWL+ CoxWLD

dependent (distributed)

oxide caps (Cgb+Cgs+Cgd) is

min 0.66CoxWL (in

saturation) and max CoxWL

(in cut-off & linear)

For simple hand

calculation consider a

constant worst-case gate

oxide cap of CoxW(L+LD) Variation of distributed

(gate-to-channel) oxide caps

as a function of VGS 96

Shahin Nazarian/EE477L/Fall 2012

Junction Capacitances (Cdb, Csb)

Exist due to depletion surrounding S and D diffusion regions

Calculation considers 3-dimensional shape of diffusion regions

97

Shahin Nazarian/EE477L/Fall 2012

Junction Capacitances (Cont.)

p-Substrate => NA

p+-Channel-stop => 10.NA or higher 1 W.Xj n+/p

2 Y.Xj n+/p+

3 W.Xj n+/p+

4 Y.Xj n+/p+

5 W.Y n+/p

98

Shahin Nazarian/EE477L/Fall 2012

Junction Capacitances (Cont.)

2. Si N A N D

xd . .(0 V )

q N A .N D

kT N A .N D

where built-in junction potential is: 0 . ln 2

q n i

N A.N D N A.N D

Q j A.q. . xd A 2. Si .q. .0 V

N A ND N A ND

99

Shahin Nazarian/EE477L/Fall 2012

Junction Capacitances (Cont.)

differentiating Qj

with respect to the bias voltage, V:

dQ j Si .q N A .N D 1

Cj C j (V ) A. . .

dV 2 N A N D 0 V

grading: C j (V )

A. C j 0

m

V

1

0

profile m=1/2, and for linearly graded junction profile m=1/3

zero-bias junction capacitance per

S i.q N A .N D 1

unit area (Cj=Cj0 for V=0): C j0 . .

2 N A N D 0

Shahin Nazarian/EE477L/Fall 2012 100

Equivalent Large Signal Capacitance

Cj depends on external bias across pn-junction, so Cj estimation

during transient conditions is complicated

The equivalent large-signal capacitance can be defined (to make

Cj bias-voltage independent) :

Q Q j (V2 ) Qj (V1 ) 1 V2

V2 V1 V1

Ceq . C j (V ) dV

V V2 V1

The reverse bias voltage is assumed to change between two

known values V1 and V2

A.C j 0 .0 V 1m V 1m

Ceq .1 2 1 1

(V2 V1 ).(1 m) 0 0

For the case of abrupt pn-junctions (m=1/2):

Ceq A. C j 0 . K eq

Voltage Equivalence Factor: K eq

2 0

V2 V1

. 0 V2 0 V1

101

Shahin Nazarian/EE477L/Fall 2012

Equivalent Large Signal Capacitance

The sidewalls of source of drain diffusion regions are

surrounded by p+ channel-stop implant; consequently the

sidewall zero-bias capacitance, Cj0ws as well as the sidewall

voltage equivalence factor Keq(sw) will be different from those

of the bottom junction. Assume p+ side wall doping of NA (sw)

siq N A (sw)N D 1

Ceq

2 N A (sw) N D 0sw

Since all the sidewalls have almost the same length of xj we

define the sidewalljunction cap per unit length:

C jsw C j 0 sw x j

The sidewall voltage equivalence factor Keq (sw) for a votlage

swing between V1 and V2

2 0sw

Sidewall Voltage Equivalence Factor: K eq (sw)

V2 V1

. 0sw V2 0sw V1

Equivalent large signal junction capacitance Ceq (sw) for a

sidewall length (perimeter) P: Ceq ( sw) P. C jsw . K eq ( sw) 102

Shahin Nazarian/EE477L/Fall 2012

Example 3.7

An abrupt pn-junction is reverse biased with Vbias, the

junction area is A=20 m20 m, ND=1019 cm-3,

NA=1016 cm-3. Find the equivalent large signal cap for

V1=0 to V2=-5 V

kT N .N 1016.1019

0 . ln A 2 D .026V . ln .88 V

2.110

20

q ni

103

Shahin Nazarian/EE477L/Fall 2012

Example 3.7 Solution (Cont.)

Si .q N A .N D 1

C j0 . .

2 N A N D 0

. 16

19

.

2 10 10 0.88V

3.110 8 F / cm2

K eq

2 0

V2 V1

. 0 V2 0 V1

2 0.88

5

. 0.88 (5) 0.88 0.56

Ceq A. C j 0 . K eq

400 10 8 cm 2 . 3.110 8 F / cm 2 .0.56 69 fF

104

Shahin Nazarian/EE477L/Fall 2012

Example 3.8

the figure has:

Substrate doping NA=21015 cm-3

Source/drain doping ND=1019 cm-3

Sidewall (p+) doping NA(sw)=41016 cm-3

Gate oxide thickness tox=45 nm

Junction depth xj=1.0 m

Y=

Find the avg drain-substrate

junction capacitance Cdb (drain

Voltage changes from .5 to 5V)

Example 3.8 Solution

kT N .N 2 1015.1019

0 . ln A 2 D .026V . ln .837 V

2.110

20

q ni

kT N ( sw).N D 4 1016.1019

0 sw . ln A 2 .026V . ln .915 V

2.110

20

q ni

junctions S i.q N A ( sw).N D 1

C j 0 sw . .

(2,3,4) 2 N A ( sw) N D 0 sw

.

19

.

4 10 10 0.915V

16

2

6.01 108 F / cm2

For bottom and channel side junctions (1,5)

S i.q N A .N D 1

C j0 . .

2 N A N D 0

.

19

.

2 10 10 0.837V

15

2

1.41108 F / cm2

Shahin Nazarian/EE477L/Fall 2012 106

Example 3.8 Solution (Cont.)

K eq

2 0.837

5 (0.5)

. 0.837 5 0.837 0.5 0.51

K eq (sw)

2 0.915

5 (0.5)

. 0.915 5 0.915 0.5 0.53 K eq

channel side junctions: (10 5) m 2 (5 1) m 2 55 m 2

Perimeter of the

P (10 5 10)m

sidewall junctions:

55108 cm 2 .1.4110 8

F / cm 2 .0.51

25104 cm.6.011012 F / cm.0.53 11.9 1015 F 11.9 fF

107

Shahin Nazarian/EE477L/Fall 2012

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