ISSCC 2014 / SESSION 17 / ANALOG TECHNIQUES / 17.
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17.11 A 0.65ns-Response-Time 3.01ps FOM Fully-Integrated
Low-Dropout Regulator with Full-Spectrum Power-Supply-
Rejection for Wideband Communication Systems
Yan Lu, Wing-Hung Ki, C. Patrick Yue
Hong Kong University of Science and Technology, Hong Kong, China
High performance low-dropout regulators (LDOs) are indispensable in a system-
on-a-chip (SoC) due to their low output noise, fast transient response and good
power supply rejection (PSR) characteristics. In general, differential analog
circuit loads need an LDO with high PSR, digital circuit loads need an LDO with
fast load transient response, while single-ended analog/RF circuit loads need an
LDO with both high PSR and fast transient response. Figure 17.11.1 shows an
LDO embedded in an optical receiver that helps improve the sensitivity of the
front-end system. On-chip LDOs with PSR in the GHz range are in high demand
for wideband optical communication systems because there is only one photo
detector in the optical receiver and supply voltage variations would degrade its
sensitivity severely [1].
Off-chip capacitors are conventionally connected to supplies for filtering
purposes. With a large output capacitor CL, say 1F, small ripples due to load
transients and good PSR can be achieved [2]. However, for a fully-integrated
LDO, large CL is no longer available, so both transient responses and PSR
performance will degrade significantly. Many fully-integrated LDOs with limited
on-chip capacitance (a.k.a. capacitor-less LDOs) have been proposed in the past
decade [3][6]. A figure-of-merit (FOM) of LDOs, shown in Fig. 17.11.1, is
defined in [3], where IQ is the quiescent current, and the response time, TR, is a
function of on-chip capacitance, C, load-transient of output voltage, VOUT, and
maximum load, IMAX. A considerably large current (6%) was used in [3] to move
the non-dominant poles to high frequencies. A single-transistor-control LDO
based on the flipped voltage follower (FVF) topology provided stable regulation
at various CL conditions including the capacitor-less case in [4], but it was
sensitive to PVT variations, and was not fast enough with undershoots of 160mV
observed. The FVF was also employed in [5] with a slew-rate enhancement
circuit that responded to load-transient edges of 100ns. However, its PSR
degraded to 0dB before reaching 1MHz. An ultra-fast-response comparator-
based regulator in 45nm SOI process was proposed in [6] that consumed 12mA
of IQ and required a deep-trench capacitor of 1.46nF, and its intrinsic 10mV
ripple was not suitable for RF/analog front-end circuits.
For an LDO, the largest capacitors are the output capacitor CL and the power
MOS gate capacitor CG. Hence, there are at least two low-frequency (LF) poles:
the output pole, pOUT, and the pole at the gate of the power MOS, pG. The pole
pOUT would shift to a lower frequency when RL increases and vice versa.
Basically, LDOs with an off-chip CL are designed to be pOUT dominant [2], while
all previous fully-integrated analog LDOs have an internal dominant pole [3][5].
Therefore, LDOs can be classified by the need for an off-chip CL, or by being
output-pole dominant or internal-pole dominant. Thus, there are 4 combinations
for which the pros and cons are summarized in the table of Fig. 17.11.1. An
output-pole dominant LDO puts most of the available capacitors at the output,
which could have intrinsically smaller VOUT and better PSR. The drawback is
that a relatively high IQ is needed to push the internal poles to high frequencies.
In this research, a fully-integrated tri-loop LDO designed in a 65nm GP CMOS is
proposed that achieves 0.65ns TR and full spectrum PSR. The transistor-level
schematic is shown in Fig. 17.11.2. This circuit includes an error amplifier (EA)
with VSET generation and a buffered FVF. The signal paths of each loop are
super-imposed on the schematic. Each loop has a different function: loop-1 is an
ultra-fast low-gain loop with pOUT being its dominant pole, while non-dominant
poles pA and pG are pushed to the GHz range by the buffer impedance attenuation
technique; loop-2 is composed of the EA and a diode-connected M7 and is a slow
loop that generates VMIR and VSET; and loop-3 has VOUT fed back to the EA to
improve the DC accuracy. The buffer, which consists of M9 through M11,
presents low input capacitance to VA and low output impedance to VG, pushing
pA and pG to very high frequencies. To save static current, the ratio of M7 and M8,
and that of their bias currents, is set to be 1:4, as VSET is in the low-speed path
that does not need much current, while VA is in the high-speed path and needs
a larger current. In this design, CL=130pF, I2=20A, and the buffer consumes
another 20A. All the above help pushing pA and pG to the GHz range. To increase
306 2014 IEEE International Solid-State Circuits Conference
the DC accuracy, a third loop is introduced through using a tri-input EA. The EA
compares VREF with both VMIR and VOUT, and the W/L ratios of the three input
transistors M1, M2 and M3 are 4:1:3. A bypass capacitor CB=7pF is added at the
VSET node to improve the PSR by filtering out the ripple from VMIR to VOUT.
To simulate the loop response of each loop, two simulation setups are
configured. In setup 1 loop-1 is broken between VA and the buffer input. To
isolate the influence from loop-2 and loop-3, the path from M7 to M8 is also
broken. To maintain the DC bias, a DC VSET is applied to the gate of M8, and to
account for the loading effect, a replica buffer is added to VA to mimic the buffer.
In setup 2 loop-2 and loop-3 are broken from VMIR to M2 and from VOUT to M3,
respectively. The AC response of loop-2 can be obtained at VMIR, and the
response of loop-3 can be obtained at VOUT, simultaneously. Simulation results
of these two setups at IO=10mA (the worst case) are combined in Fig. 17.11.3.
When VOUT is 1.0V, loop-1 has a DC gain of 21dB and a unity gain frequency
(UGF1) of 600MHz, with a phase margin (PM1) of 60. Loop-2 has one dominant
pole at VSET and a non-dominant pole at VEA, and PM2=80. Loop-3 has two non-
dominant poles at VEA and VOUT, respectively, and PM3 is 20. Nevertheless, the
combined loop, with loop-2 very stable and loop-3 stable but with small phase
margin, is stable. To gain more design margin for stability, the weighting of M2
and M3 could be set to 2:2 instead of 1:3 with a lower DC accuracy.
Figure 17.11.4 shows the measured transient response with on-chip load change
from 0A to 10mA within 200ps. With an IQ of 50A, the measured undershoot
was 43mV, and VOUT recovered to its steady-state value in 100ns with the help of
loop-3 regulation. The measured overshoot was 82mV, and VOUT was gradually
discharged by the bias current of M8, and then regulated by loop-3 to its steady-
state value. The well-behaved waveforms of VOUT confirmed the stability of the
proposed tri-loop LDO. The FOM achieved is 3.01ps, and the TR is 0.65ns. FOM
is expected to be improved further with process scaling. Note that FOM
improvement is not necessarily true for an internal-pole dominant LDO because
it requires a minimum load current IO,Min for stability that results in a low loop
bandwidth.
Figure 17.11.5 shows the measured PSR of the LDO up to 20GHz. For RL=100,
PSR is better than -21dB at low frequencies; and the worst case occurs at 5MHz
with -12dB rejection. Note that ripples generated by DC-DC converters could be
higher than 100MHz [7], while noise generated by digital circuits is in the GHz
range. PSR at 1GHz is -15.5dB. For frequencies higher than 1GHz, PSR would
start to be dominated by the equivalent series resistance (ESR) of the filtering
capacitor. As our design does not rely on the ESR to be zero for stability, ESR is
minimized in the layout design for good PSR.
A performance comparison with state-of-the-art LDOs is listed in Fig. 17.11.6.
Compared to previous ultra-fast response designs [3] and [6], sub-ns TR is
achieved with much smaller IQ and CL, hence resulting in a 3.01ps FOM.
Furthermore, the full-spectrum PSR characteristic is presented, while other
fully-integrated LDOs only measure PSR at specific frequencies. The chip area is
0.023mm2 including the on-chip load, as shown in Fig. 17.11.7.
References:
[1] T. Takemoto, et al., A 4x 25-to-28Gb/s 4.9mW/Gb/s -9.7dBm High-
Sensitivity Optical Receiver Based on 65nm CMOS for Board-to-Board
Interconnects, ISSCC Dig. Tech. Papers, pp. 118119, Feb. 2013.
[2] M. Al-Shyoukh, H. Lee, R. Perez, A Transient-Enhanced Low-Quiescent
Current Low-Dropout Regulator with Buffer Impedance Attenuation, IEEE J.
Solid-State Circuits, vol. 42, no. 8, pp. 17321742, Aug. 2007.
[3] P. Hazucha, et al., Area-Efficient Linear Regulator with Ultra-Fast Load
Regulation, IEEE J. Solid-State Circuits, vol. 40, no. 4, pp. 933940, Apr. 2005.
[4] T. Y. Man, et al., Development of Single-Transistor-Control LDO Based on
Flipped Voltage Follower for SoC, IEEE Trans. Circuits Syst. I: Regular Papers,
vol. 55, no. 5, pp. 13921401, May 2008.
[5] J. Guo, K. N. Leung, A 6-W Chip-Area-Efficient Output-Capacitorless LDO
in 90-nm CMOS Technology, IEEE J. Solid-State Circuits, vol. 45, no. 9, pp
18961905, Sep. 2010.
[6] J. F. Bulzacchelli, et al., Dual-Loop System of Distributed Microregulators
with High DC Accuracy, Load Response Time Below 500 ps, and 85-mV Dropout
Voltage, IEEE J. Solid-State Circuits, vol. 47, no. 4, pp. 863874, Apr. 2012.
[7] C. Huang, P. K. T. Mok, An 82.4% Efficiency Package-Bondwire-Based Four-
Phase Fully Integrated Buck Converter with Flying Capacitor for Area Reduction,
ISSCC Dig. Tech. Papers, pp. 362363, Feb. 2013.
978-1-4799-0920-9/14/$31.00 2014 IEEE
 ISSCC 2014 / February 11, 2014 / 5:00 PM

Figure 17.11.1: Block diagram of an LDO providing a clean supply for the
trans-impedance amplifier (TIA) in an optical receiver, and a table of LDO
categorization. Figure 17.11.2: Schematic of the fully-integrated tri-loop LDO.

17

Figure 17.11.3: Simulated frequency response of the three loops with Figure 17.11.4: Measured transient response with an on-chip load current
VIN=1.2V, VOUT=1.0V and RL=100. change from 0A to 10mA within 200ps.

Figure 17.11.5: Measured PSR of the proposed LDO up to 20GHz. Figure 17.11.6: Comparison of state-of-the-art LDOs.

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Figure 17.11.7: Chip micrograph of the proposed LDO.

2014 IEEE International Solid-State Circuits Conference 978-1-4799-0920-9/14/$31.00 2014 IEEE