SDHR DEGREE & P.G COLLEGE::TIRUPATI.

COURSE/SEMESTER: B.Sc-M.E.CS/III, 2016-17 SUBJECT: DIGITAL ELECTRONICS

No. of
Unit Topic Probable Dates Actual Date
Hours

Unit-I: Number systems and Codes

Number systems: Binary, Octal, Decimal and
Hexa- decimal numbers 2 20-21/7/2016
Number systems conversion 3 22, 23 & 25/7/2016
I
Digital Codes: Classification & Conversion 3 26, 27 & 28/7/2016
Error detection Codes & ASCII Code 2 29-30/7/2016
Tutorial class 1 1/8/2016
Class room Test 1 2/8/2016

Unit-II: Logic Gates & Boolean Algebra & K-Maps

Logic Gates: Basic logic gates, Universal logic
gates and logic design 3 3, 4 & 5/8/2016
Boolean Algebra: Boolean algebra, Boolean
Operations, Boolean Identities 2 6, 8 & 9/8/2016
Boolean theorem-De Morgans theorem 2 10, 11/8/2016
II Boolean Functions and their representations: Sum
of Products form functions, Product of Sums 2 16, 17/8/2016
Minimization of switching functions using K-Map
method (up to 4-variable map) 3 18, 19 & 20/8/2016
Dont care combinations/conditions 1 22/8/2016
Tutorial 1 23/8/2016
Classroom Test 1 24/8/2016
Unit-III: Combinational Circuits & Logic Families
Combinational Circuits: Arithmetic building
blocks, Design Procedure 1 26/8/2016
Half adder and Full adder 1 27/8/2016
Half Subtractor and Full Subtractor 1 29/8/2016
Serial and Parallel adder 1 30/8/2016
Multiplexers (2;1, 4:1 and 8:1) 1 31/8/2016
III
De-Multiplexers (2;1, 4:1 and 8:1) 1 1/9/2016
Encoders (Octal to Binary, Decimal to BCD) 2 2, 3/9/2016
De-Encoders ( Binary to Octal, BCD to Decimal) 2 6, 7/9/2016
Characteristics of Digital ICs-RTL, DTL, TTL and
ECL (using NAND and NOR gates) 2 8, 9/9/2016
Tutorial 1 13/9/2016
Classroom Test 1 14/9/2016
IV
Unit-IV: Sequential Circuits
Sequential Circuits: Block diagram of sequential
circuits, S-R latches, Clocked S-R 1 15/9/2016
JK, D and T flip-flops; Race around conditions 3 16/9/2016
Master slave flip-flop 1 17/9/2016
Conversion of flip-flops
2 19, 20/9/2016
 Shift registers (SISO, SIPO, PISO and PIPO) 2 21, 22/9/2016
Counters: Ripple (or) Asynchronous counters,
Synchronous counters; comparison 2 23, 24/9/2016
4-bit ripple counter, 3-bit asynchronous counter
UP/DOWN counter 1 26/9/2016
Tutorial 1 27/9/2016
Classroom Test 1 28/9/2016

Unit-V: Memory Devices

ROM Organization-types of ROMs 1 29/9/2016
PLA (Programmable Logic Array) & PAL
(Programmable Array Logic) 2 30/9/2016 & 1/10/2016
V Architecture and Logic design of combinational
logic circuits using PLAs and PALs 2 3, 4/10/2016
Realization of functions using PROM 2 5, 6/10/2016
Tutorial 1 7/10/2016
Classroom Test 1 10/10/2016

Date:

Signature of Faculty Signature of Principal

[SRINIVASULU P.] [A. USHA]