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Features Description
Switch mode controller for single switch LED drivers HV9910C is an open-loop, current-mode control, LED
Enhanced drop-in replacement to the HV9910B driver IC. This IC can be programmed to operate in
either a constant frequency or constant off-time mode.
Open loop peak current controller
It includes a 15 450V linear regulator which allows it
Internal 15 to 450V linear regulator to work with a wide range of input voltages without the
Constant frequency or constant off-time operation need for an external low voltage supply. HV9910C
Linear and PWM dimming capability includes a TTL-compatible, PWM-dimming input that
Requires few external components for operation can accept an external control signal with a duty ratio
of 0 100% and a frequency of up to a few kilohertz. It
Over-temperature protection
also includes a 0 250mV linear-dimming input which
can be used for linear dimming of the LED current.
Applications Unlike the HV9910B, the HV9910C is equipped with
DC/DC or AC/DC LED driver applications built-in thermal-shutdown protection.
RGB back-lighting LED driver HV9910C is ideally suited for buck LED drivers. Since
Back lighting of flat panel displays the HV9910C operates in open-loop current mode con-
trol, the controller achieves good output current regula-
General purpose constant current source
tion without the need for any loop compensation. Also,
Signage and decorative LED lighting being an open-loop controller, PWM-dimming
Chargers response is limited only by the rate of rise of the induc-
tor current, enabling a very fast rise and fall times of the
LED current. HV9910C requires only three external
components (apart from the power stage) to produce a
controlled LED current. This makes HV9910C an ideal
solution for low-cost LED drivers.
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
Microchips Worldwide Web site; http://www.microchip.com
Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
VIN 1 16 NC
NC 2 15 NC
NC 3 14 RT
CS 4 13 LD
CS 2 7 LD NC 6 11 NC
GND 3 6 VDD NC 7 10 NC
CIN
CO
D1
CDD L1
VIN
VDD
HV9910C
LD
GATE Q1
PWMD CS
RT GND
ROSC RCS
Input
Input DC supply voltage 3
VINDC 15 - 450 V DC input voltage
range2
Pin PWMD to VDD, no capaci-
IIN(MAX) Supply current - - 0.8 1.5 mA
tance at GATE
Shut-down mode supply
IINSD - - 0.5 1.0 mA Pin PWMD to GND
current
Internal Regulator
VIN = 15V, IDD(ext) = 0,
VDD Internally regulated voltage - 7.25 7.50 7.75 V PWMD = VDD, 500pF at GATE;
ROSC = 249k
VIN = 15 - 450V, IDD(ext) = 0,
VDD, line Line regulation of VDD - 0 - 1.0 V PWMD = VDD, 500pF at GATE;
ROSC = 249k
IDD(ext) = 0 - 1.0mA,
VDD, load Load regulation of VDD - 0 - 0.1 V PWMD = VDD, 500pF at GATE;
ROSC = 249k
VDD under voltage lockout 3
UVLO 6.45 6.70 6.95 V VDD rising
threshold
VDD under voltage lockout
UVLO - - 500 - mV VDD falling
hysteresis
4
IIN(MAX) Maximum regulator current 5.0 - - mA VDD = UVLO - UVLO
PWM Dimming
3
VEN(lo) PWMD input low voltage - - 1.0 V VIN = 15 - 450V
VEN(hi) 3
PWMD input high voltage 2.4 - - V VIN = 15 - 450V
Internal pull-down resis-
REN - 50 100 150 k VPWMD = 5.0V
tance at PWMD
Constant frequency peak current mode control has an Note: The Zener diode will increase the mini-
inherent disadvantage at duty cycles greater than mum input voltage required to turn on the
0.5, the control scheme goes into subharmonic oscilla- HV9910C to 115V.
tions. To prevent this, an artificial slope is typically
added to the current sense waveform. This slope com- The input current drawn from the VIN pin is a sum of the
pensation scheme will affect the accuracy of the LED 1.5mA (maximum) current drawn by the internal circuit
current in the present form. However, a constant off- and the current drawn by the GATE driver. The GATE
time peak current control scheme does not have this driver depends on the switching frequency and the
problem and can easily operate at duty cycles greater GATE charge of the external FET.
than 0.5. This control scheme also gives inherent input
voltage rejection, making the LED current almost I IN = 1.5mA + Q g f s
insensitive to input voltage variations. However, this
scheme leads to variable frequency operation and the
frequency range depends greatly on the input and out- In the above equation, fs is the switching frequency and
put voltage variation. Using HV9910C, it is easy to Qg is the GATE charge of the external FET, which can
switch between the two modes of operation by chang- be obtained from the data sheet of the FET.
ing one connection (see Section 3.3 Oscillator).
3.2 Current Sense
3.1 Input Voltage Regulator
The current sense input of HV9910C goes to the non-
HV9910C can be powered directly from its VIN pin and inverting inputs of two comparators. The inverting ter-
can work from 15 - 450VDC at its VIN pin. When a volt- minal of one comparator is tied to an internal 250mV
age is applied at the VIN pin, HV9910C maintains a reference, whereas the inverting terminal of the other
constant 7.5V at the VDD pin. This voltage is used to comparator is connected to the LD pin. The outputs of
power the IC and any external-resistor dividers needed both these comparators are fed into an OR GATE and
The gate output of the HV9910C is used to drive an The auto-recoverable thermal shutdown at 140C (typ.)
external FET. It is recommended that the GATE charge junction temperature with 20C hysteresis is featured
of the external FET be less than 25nC for switching fre- to avoid thermal runaway. When the junction tempera-
quencies 100kHz and less than 15nC for switching ture reaches TSD = 140C (typ.), HV9910C enters a low
frequencies > 100kHz. power consumption shut-down mode with IIN <350A.
VIN VDD
- POR
+ 1.25V
Bandgap
LD - Reference OTP
+
CS Blanking R Q GATE
+
250mV - S
Oscillator
GND RT PWMD
X = Product Code
YY = Year Sealed
WW = Week Sealed
NNN = Traceability Code
e# = JEDEC Symbol
= Pin 1 Indicator
Note: The JEDEC environmental marking symbols (e#) illustrated are
examples only, and might not reflect the actual value for the listed
package code.
D 1
Note 1
(Index Area
D/2 x E1/2)
E1 E Gauge
L2
Plane
L Seating
1 Plane
L1
Side View A
View A-A
Notes:
1. This chamfer feature is optional. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier
can be: a molded mark/identifier; an embedded metal marker; or a printed indicator.
Symbol A A1 A2 b D E E1 e h L L1 L2 1
Dimension MIN 1.35* 0.10 1.25 0.31 4.80* 5.80* 3.80* 0.25 0.40 0 5
1.27 1.04 0.25
NOM - - - - 4.90 6.00 3.90 - - - -
BSC REF BSC
(mm) MAX 1.75 0.25 1.65* 0.51 5.00* 6.20* 4.00* 0.50 1.27 8 15
JEDEC Registration MS-012, Variation AA, Issue E, Sep 2005.
* This dimension is not specified in the JEDEC drawing.
This dimension differs from the JEDEC drawing.
Drawings not to scale.
D 1
16
Note 1
(Index Area
D/2 x E1/2)
E1 E
Gauge
Plane
L2
L Seating
1 e b L1 Plane
A2
A Seating
Plane
A1
Notes:
1. This chamfer feature is optional. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier
can be: a molded mark/identifier; an embedded metal marker; or a printed indicator.
Symbol A A1 A2 b D E E1 e h L L1 L2 1
Dimension MIN 1.35* 0.10 1.25 0.31 9.80* 5.80* 3.80* 0.25 0.40 0 5
1.27 1.04 0.25
NOM - - - - 9.90 6.00 3.90 - - - -
BSC REF BSC
(mm) MAX 1.75 0.25 1.65* 0.51 10.00* 6.20* 4.00* 0.50 1.27 8 15
JEDEC Registration MS-012, Variation AC, Issue E, Sep 2005.
* This dimension is not specified in the JEDEC drawing.
This dimension differs from the JEDEC drawing.
Drawings not to scale.
8 8
Exposed
E1 E Thermal Pad Zone E2
Note 1
(Index Area
D/2 x E1/2)
1 1
View B
A Note 1
h
h
Gauge
L2
A A2 Plane
Seating
Plane
A1 L Seating
e b
L1 Plane
A
Side View View A-A View B
Notes:
1. This chamfer feature is optional. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier
can be: a molded mark/identifier; an embedded metal marker; or a printed indicator.
Symbol A A1 A2 b D D1 E E1 E2 e h L L1 L2 1
Dimension MIN 1.25* 0.00 1.25 0.31 4.80* 3.30 5.80* 3.80* 2.29 0.25 0.40 0 5
1.27 1.04 0.25
NOM - - - - 4.90 - 6.00 3.90 - - - - -
BSC REF BSC
(mm) MAX 1.70 0.15 1.55* 0.51 5.00* 3.81 6.20* 4.00* 2.79 0.50 1.27 8 15
JEDEC Registration MS-012, Variation BA, Issue E, Sep 2005.
* This dimension is not specified in the JEDEC drawing.
This dimension differs from the JEDEC drawing.
Drawings not to scale.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchips Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as unbreakable.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchips code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Authorized Distributor
Microchip:
HV9910CLG-G HV9910CNG-G HV9910CNG-G M934 HV9910CNG-G-M934