11.
The amplifier is connected in inverting mode in
1. The resolution of a DAC is stated in terms of:
a. The accuracy of the voltage reference
b. The open-loop gain of the comparator
c. The number of resistors used.
d. The number of bits used in the conversion.
2. The conversion time of a flash ADC is typically in
the range:
a. 50 ns to 1 s
b. 50 s to 1 ms
c. 50 ms to 1 s.
3. In a successive approximation ADC, the time
interval between the sc and EOC signals is:
a. The clock time
b. The cycle time
c. The conversion time.
d. End of conversion time
4. Which one of the following ADC types uses a
large number of comparators?
a. Ramp type
b. Flash type
c. Successive approximation type.
5. The conversion time of a successive
approximation ADC is typically in the range
a. 10 s to100 s.
b. 50 s to 1 ms
c. 100 s to 10 ms
6. When the output of the latch takes the binary
value 1111 (the maximum possible) the output
voltage can be (consider logic1=5v, logic0=0v)
. process is uncompleted.
a. 4.375v
b. 9.375v
c. 5.625v
7. A four-bit binary latch circuits is used for
a. Converting analog data to digital data
b. To store analog data
c. To generate bit resolution
d. To store the binary input
8. Accuracy of DAC depends on
a. Resistance values
b. Reference voltage
c. Number of bits used
d. Both (a) & (b)
9. The end of conversion signal is generated in
successive approximation ADC when
a. At the point at which the output from the
comparator reaches zero.
b. As in a &the analogue input voltage will be
the same as the analogue output from the
DAC
c. None of the above
10. The output of filter circuit is.
a. Quantized voltage levels
b. Smooth voltage levels
c. Sampled voltage levels
d. Digital voltage level
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binary weighted dac then.
a. The analogue output voltage will be negative
rather than positive.
b. The analogue output voltage will be positive.
c. The analogue input voltage will be
connected to positive terminal.
12. Consider the 4-bit binary weighted DAC,
suppose r= 2 K then which of following value
is correct ,
a. For bit 3, resistance value=1k
b. For bit 2, resistance value=2k
c. For bit 1, resistance value=6k
d. For bit 0, resistance value=16k
13. In r-2r ladder DAC,
a. Two resistance values are required
b. Four resistance values are required
c. One resistance values is required
d. Two same resistance values are required.
14. The analogue signal consists of.
a. A continuously changing voltage levels.
b. Series of discrete voltage levels.
c. Series of dis-continues voltage levels.
d. All of the above.
15. MTCS about successive approximation ADC.
a. A separate end of conversion (eoc) signal is
generated to indicate that the conversion
process is complete.
b. A separate end of conversion (eoc) signal is
generated to indicate that the conversion
c. As in (a) & a separate start of conversion
(soc) signal is generated to indicate that the
conversion process is complete
d. As in (a) & a separate start of conversion
(soc) signal is generated to indicate that the
conversion process is start.
16. The organization shall ensure that all certifying
staff and support staff receive sufficient
continuation training in each _________ period to
ensure that such staff have up-to-date
knowledge of relevant technology, organization
procedures and human factor issues
A. 2 year
B. 1 year
C. 5 year
D. 10year
17. Certifying staff shall produce their certification
authorization to any authorized person within
A. 48hrs
B. 36 hrs
C. 24 hrs
D. 72 hrs
18. The minimum age for certifying staff and support
staff is
A. 18 yrs
B. 25 yrs
C. 28 yrs
D. 21 yrs
19. When the support staff left the car-145 20. Initial traning for an permamt employee in an
organization , then their records shall be retained organization shall be given
for a period of a. Within 3 months of joining
A. 10 yrs b. Within 6 months of joining
B. 6 yrs c. Within 9 months of joining
C. 3 years d. None
D. 5 yrs

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