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Korea Advanced Institute of Science and Technology

Department of Electrical Engineering

EE 403 Spring 2013


Bae, Hyeon-Min Tu,Th 13:00-14:15

Final example

1. For MOS amplifier shown below, answer the following questions 1, through 6 using
Vthn=0.4V, Vthp=-0.4V, nCox=100A/V2, pCox=40A/V2, W/Leff=200, Cje=10fF/m2,
Cox=30fF/m2, and =0.01V-1. Assume that Rbias is adjusted to set the DC current at 0.1mA.
2.5V

M11 x20
M10
M14 M9

Rbias In- In+


M1 M3 M2
M4 Out
Cc
M7
M13 M8
M12 x20
M5 M6

GND

(1) Estimate the low frequency small signal gain of this op amp?

(2) IF the unity gain frequency of this op amp is 5MHz, what is the size of the compensation
capacitance?

(3) Estimate the input common mode range and the offset of this op amp.

(4) Estimate the maximum capacitance this op amp can drive without sacrificing more than 10
degree excess phase at the unity-gain frequency

(5) This op amp with 5MHz unity-gain bandwidth is used with a feedback factor of 1/4. What
is the 0.1% settling time if a step of 1V applied to the input?

Copyright 2013, Bae, Hyeon-Min


Korea Advanced Institute of Science and Technology
Department of Electrical Engineering

EE 403 Spring 2013


Bae, Hyeon-Min Tu,Th 13:00-14:15

2. (40 points) For the CMOS OP amp shown below, assume all NMOS and PMOS bodies are
connected to 0V and 2.5V, respectively, and the input common mode voltage is 1.25V and
the nominal output voltage is 1.25V Use vthn=0.4, vthp=-0.4, nCox=100A/V2,
pCox=50A/V2, =0.01V-1, =0.5V0.5 for hand calculations.
2.5V

M7
M8 M6
100/1 100/1 400/1

vo
100/1 100/1
M1 M2
vi 5pF
R

2pF
M3 M4 M5
100/1 100/1
0V

1. (5 points) Set the values of the resistor R so that the bias current ID8 can be 200uA
2. (5 points) Set the device size of M5 so that there may be no systematic offset. The
systematic offset is defined as an input voltage to make the output 1.25V.
3. (5 points) Estimate the small signal voltage gain
4. (5 points) Estimate the input common mode voltage range and the output swing range
5. (10 points) Estimate all poles a zero, and the unity-gain frequency
6. (5 points) Estimate the phase margin under unity gain feedback
7. (5 points) If you want to increase the phase margin without changing DC loop gain, what
will you do?

Copyright 2013, Bae, Hyeon-Min


Korea Advanced Institute of Science and Technology
Department of Electrical Engineering

EE 403 Spring 2013


Bae, Hyeon-Min Tu,Th 13:00-14:15

3. For MOS amplifier shown below, answer the following questions 1, through 6 using
Vthn=0.4V, Vthp=-0.4V, nCox=100A/V2, pCox=40A/V2, W/Leff=200, Cje=10fF/m2,
Cox=30fF/m2, and =0.01V-1. Assume that Rbias is adjusted to set the DC current at 0.1mA.
The nominal DC voltage of the input and output terminal is 1.25V for the question of 1
and 2. For the questions 3 through 7, assume this op amp is used in unity gain configuration.

2.5V

M4 M4
M3

M5 M6 M6
Vo
5pF
M8
M1 M2 M7
vi

M11 M10
M9

1. (10 points) Estimate the low frequency small signal gain of this op amp?
2. (10 points) Estimate the nominal input referred offset voltage of this op-amp. The offset
voltage is defined as the input voltage that makes the output voltage 1.25V
3. (10 points) What is the maximum peak to peak swing of this unity gain feedback
amplifier?
4. (10 points) What is the bandwidth of this amplifier in Hz?
5. (10 points) Estimate the phase margin of this unity gain feedback.
6. (10 points) What is the maximum frequency of 1V sinusoidal signal that this amplifier can
amplify without gross distortion?

Copyright 2013, Bae, Hyeon-Min