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RF Microelectronics Chip Design

EE619 Spring 2012

Shalabh Gupta (shalabh@ee.iitb.ac.in)


EE Department, IIT Bombay

Lecture #8 (30-Jan-2012)
Topics: Recap, LNAs
Representation of Noisy Circuits
For any linear two-port circuit:
<vn,in,ckt2>
1 2 1 2
~
Noisy <in,in,ckt2> Noiseless

< vn2,in ,ckt >= < vn2,in ,i >; (Obtained by taking


i
<vn,in,ckt2>
ZS = 0, and finidng input referred noise voltage) 1 2
~
< in2,in ,ckt >= < in2,in ,i >; (Obtained by taking Noiseless Assuming
i Zin =
ZS = , and finidng input referred noise current)

If ZS or YS is known : 1 2
< vn2,in ,ckt ,total >= < (vn ,in ,i + Z S in ,in ,i ) 2 > Assuming
Noiseless
i <in,in,ckt2> Zin = 0
< in2,in ,ckt ,total >= < (YS vn ,in ,i + in ,in ,i ) 2 >
i

Shalabh Gupta (IIT Bombay) EE619 RF Microelectronics Chip Design Lecture 8 (30-Jan-2012) Slide # 1
Circuit Examples For Noise Calculation
Noise at the output due to
different elements that are
part of the amplifier will be

(
< vn2.out >= < in2. R > + < in2.M > RD2
D 1
)

Ignoring channel length modulation


(i.e. ro of transistor M1 being infinite), the
input referred noise of this circuit will be

Voltage Gain ( Av ) = g m RD <v 2


>=
(<i2
n . RD
> + < in2.M > RD2
1
)
n ,in , ckt
Av2
Assuming Rs << Gate
impedance of transistor M1 =
(< i 2
n . RD
> + < in2.M > RD2
1
) =
< in2. R > + < in2.M >
D 1
2 2 2
g R
m D g m

< vn2,in , Rs >= 4kTRs


< in2. R > + < in2.M > 1
Noise Factor , F = 1 + D 1
= 1+ +
4kTRs g m2 RD Rs g m2 Rs g m

Shalabh Gupta (IIT Bombay) EE619 RF Microelectronics Chip Design Lecture 8 (30-Jan-2012) Slide # 2
Circuit Examples For Noise Calculation
Noise at the output due to different elements
that are part of the amplifier will be
Ignoring channel length modulation (i.e.
< i 2
> 2 ro of transistor M1 being infinite), the input
< vn2.out 2
>= < in. R > +
n.M 1 R referred noise of this circuit will be
D
(1 + g m Rs )
2 D
2
> 2
< i2 > +
< i n. M 1 R
n . R D (1 + g m Rs ) 2 D
Voltage Gain ( Av ) = g m RD < vn2,in ,ckt >=
2
(Input node to output) Av
< i 2
> 1 2
= < in2.R > +
n . M 1

D
(1 + g m Rs ) g m
2

< in2. R > (1 + g m Rs ) 2 + < in2.M >
= D
2 2
1

(1 + g m Rs ) g m
2
1
<v 2
>= 4kTRs .
n ,in , Rs

1 + g R
m s

< in2.R > (1 + g m Rs ) 2 + < in2.M >


Noise Factor , F = 1 + D
2
1

4kTRs g m
(1 + g m Rs ) 2
= 1+ + (ignoring 1 noise)
g m2 Rs RD g m Rs f
4
= 1+ + ( for g m Rs = 1)
g m RD
Shalabh Gupta (IIT Bombay) EE619 RF Microelectronics Chip Design Lecture 8 (30-Jan-2012) Slide # 3
Low Noise Amplifiers
LNA: Goal is to amplify the signal so that it is significantly above the
noise floor
LNA should not add significant noise of its own
As a result noise added by subsequent stages becomes insignificant

Key LNA requirements


Low Noise
Low Power
High Linearity
High Gain
<1 at all frequencies)
Stable (under all load conditions, i.e. K>1, <1;
Good reverse isolation
2 2
1 S11 S 22 + 2
K= ; = S11S 22 S12 S 21
2 S12 S 21
Shalabh Gupta (IIT Bombay) EE619 RF Microelectronics Chip Design Lecture 8 (30-Jan-2012) Slide # 4
Matching
Why is matching important

Does it have to be perfect


Tradeoff between: Gain, Stability, Noise Figure

Shalabh Gupta (IIT Bombay) EE619 RF Microelectronics Chip Design Lecture 8 (30-Jan-2012) Slide # 5
Linearity in LNAs
Linearity in LNAs etc.
In bipolar common emitter amplifier
V
1 Vbe
2

1 Vbe
3

I out = I 0 e (Vbe / VT ) = I 0 e (Vbe / VT ) = I 0 +
be
+ + L
VT 2! VT 3! VT
AIIP3 = 2 2VT IIP3 = 12.7dBm (in a 50 system)

In MOS devices (common gate configuration):


1 W
I out = nCox (VGS Vth ) 2 (1 + VDS )
2 L
No third order non-linearity in the quadratic equation?

IIP3 of cascaded stages


Linearity second stage more important

Shalabh Gupta (IIT Bombay) EE619 RF Microelectronics Chip Design Lecture 8 (30-Jan-2012) Slide # 6