C-302 (Fall 2016-17)

Practice Questions for the Final

Note: Use IEEE STD_LOGIC unless the problem specifies otherwise

Q1. It is desired to design a sequence detector for 001

a. Draw the state transition diagrams as a Moore FSM and a as a Mealy FSM
b. Write VHDL behavioral description for any one of the above.

Q2. a. Draw the FSM for a J-K flip-flop. There should be 3 states including an Undefined
initial state in which both Q and QBAR are U. It should be possible to come out of this
state by clocking the flip-flop either with (J=0 and K=1 ) or with (J=1 and K=0)
after which the flip-flop operates normally and the Undefined state is not entered again.

b.Write complete VHDL code in behavioral style for the FSM you have designed

Q3. Design a generic n-bit NOR gate by cascading n-1 OR gates and one INVERTER.
Write a complete structural description for it using generate statements.

Q4. Design a n-bit binary counter using n J-K flip-flops . Draw the circuit diagram.
Write a complete structural description for it using generate statements.
Assume JK flipflop component with asynchronous active high CLR input is available in
the work library.

Q5 State with justification what the following code segment comprising 3 sequential
assertions will report for each of the following cases:

(i) A=0, B=0

(ii) A=0, B=1
(iii) A=1, B=0
(iv) A=1, B= 1

assert(not A or B)
report Case 1
severity note;
assert (A xor B)
report Case 2
severity note;
assert (not(not A and B))
report Case 3
severity note;
Q6 Write a test bench for 2-bit comparator which has the following entity description:

entity comparator is
port(A,B:in bit_vector(1 downto 0);;
GT,EQ,LT:out bit);
end comparator;

Your test bench must run the following test cases and in each case check all the 3 outputs and
report either Correct Outputs (if all 3 outputs are correct) or Incorrect outputs.
(if one or more outputs are incorrect)

A=11, B=10
A=01 , B=01
A1=00, B=11

A template for the test bench is provided below:

Q7 Write a test bench for 3X8 decoder which has the following entity description:

entity decoder is
port(X:in bit_vector(2 downto 0);
EN: in bit;
Y: out bit_vector(7 downto 0));
end decoder;
(If EN=0, all outputs are zero regardless of X)
Your test bench must run one test case with EN=0 and 3 other test cases with EN=1 and
X=000 , 011 and 111 respectively
A template for the test bench is provided below:

Q8
Write an architecture in behavioral style to calculate the sum of all integers which are even
but not multiples of 3 out of the first n positive integers 1,2.n. Your code must use a loop
with next and exit statements (at least one next and one exit)

Q9 a. Consider the following concurrent signal assignment statements:

C <= A xor B;
D <= A or C;

Initially all signals are 0. At time T signal A changes to 1. Plot the

resultant waveforms of C and D including delta delays.

Q10 Write a complete VHDL description in dataflow style for a 4X2 priority encoder.
The entity must output UU if all the 4 inputs are 0
Q11. (a) Code a VHDL function which accepts a n-dimensional bit vector as argument
and counts the number of 1s and the number of 0s in it. It then returns an
integer which is:
- +1 if the number of 1s exceeds the number of 0s
- 0 if the number of 1s and the number of 0s are equal
- -1 if the number of 1s is less than the number of 0s

(b) Declare a package containing the above function In addition the package
should also contain:
- a J-K flip-flop as a component
- a type SPEED which can assume values SLOW, MEDIUM and FAST
- a variable c which is an integer between -5 and +5 initialized to 3.

-- ECE-C302 Template for Test bench

entity test bench is

--define no of tests
end;

architecture mixed of testbench is

component EUT -- entity under test
-- Include component under test
end component;

-- define 2D types required for the test data base

-- Using these types define signals constituting the different test inputs and expected outputs
-- define type for FSM and a signal for the next state
-- define signals to pass the test inputs from process to EUT and outputs back from EUT to
process
-- define signal for clock

-- generate clock with dataflow statement

process(clk)
-- define variable for test case no and any other count needed
begin
-- Model test bench FSM
-- On clock
case n_s is
when apply_inputs=>
-- apply test inputs
-- switch state
when check_results
-- obtain output signal from EUT
-- Check for correctness using assert statements error/note severity
-- increment test case no
-- Check if tests are complete using an assert with failure severity
-- switch state back for next test case
end process;

E1: EUT port map(----) -- instantiate entity under test connecting input/output signals

end mixed;