Fit Fast Structured Array (FFSA)

Configurable Platform
Technology

Rapid and Cost-efficient Design of ASICs/ASSPs and FPGA Replacement. Rapid and Cost-efficient Design of ASICs/ASSPs and FPGA Replacement.

CONTACT INFORMATION
REGIONAL SALES OFFICES
NORTHWEST
San Jose, CA
TEL: (408) 526-2400
FAX: (408) 526-2410
SOUTHWEST
Irvine, CA
TEL: (949) 462-7700
FAX: (949) 462-2200
El Paso, TX
TEL: 915-771-8156
FAX: 915-771-8178
MIDWEST
Wixom, MI
TEL: (248) 347-2607
FAX: (248) 347-2602
Buffalo Grove, IL
TEL: (847) 484-2400
FAX: (847) 541-7287
NORTHEAST
Choosing Toshiba Toshiba Fit Fast Structured Array (FFSA) The key features of FFSA are as follows:
As a worldwide leader in chip design and manufactur- Toshiba, a premier, world-class semiconductor manufacturer has Customization using only four metal layers
ing, Toshiba possesses the requisite design experience, provided leading companies with custom SoCs/ASICs for over 500+ core cell library
tools, design methodologies, IP libraries and manufac- three decades and now brings an innovative metal-configurable Configurable FPGA like memory with optimized size and
turing expertise needed to help its customers develop platform technology for the design of ASICs and ASSPs, and the performance
an ASIC or ASSP. FFSA can help Toshiba customers seamless replacement of FPGAs. The Toshiba FFSA technology Design of multiple SoCs from one metal-configurable platform
differentiate their products from the competition by is used to rapidly create ASICs or ASSPs by customizing metal using the same EDA tools and methodologies as for ASICs
significantly reducing design cycles, project costs and mask layers. FFSA significantly reduces time to market and Scalable technology for 28 nm and smaller geometries
power budgets while improving performance. up-front, non-recurring engineering costs while maintaining Enhanced cell architecture allowing for improved routability,
the advantages of performance, power and lower unit cost power structure and area optimization
associated with standard-cell ASICs. Configurable IOs, PLLs, DDR/LVDS PHYs and multi-protocol
transceivers
FFSA Utilizing Metal Configurable (MC) Technology
Transceiver Protocols
MC I/Os
Flexible PWR/GND/IO assignment
PCIe-G1/2/3 (2.5G/5G/8G)
MC Core SRIO (1.25G/2.5G/3.125G/5G/6.25G)
500+ Std. cell libraries Configurable I/O banks
FPGA I/O standards support Interlaken (3.12510.3125G)
OCT, Dynamic impedance XAUI/RXAUI (3.125G/6.25G)
MC Memory matching
1.2V 3.3V Support
HiGig (3.75G)

PLL

PLL

PLL
Metal Prog. I/O Metal Prog. I/O
Native DP/SP Memory
Marlboro, MA Blocks PLL PLL GigE (1.25G)
Configurable SP/DP/ 10G Ethernet

Metal Prog. I/O

Metal Prog. I/O

TEL: (508) 481-0034 SDP/ROM
CPRI (0.6144G/1.288G/2.4576G/3.072G/6.144G)
FAX: (508) 481-8828 ECC and Parity Support
MCSC CORE + MC PLL OBSAI (0.768G/1.536G/3.072G/6.144G)
FPGA Memory like PLL PLL
MEMORY Wide-Range PLL

Metal Prog. I/O

Parsippany, NJ flexibility SDH/SONET (0.62208G/2.48832G/4.97664G)

Metal Prog. I/O

(10 MHz1.6 GHz)
Cascade Capable for OIF-CEI-6G (4.976G6.375G)
TEL: (973) 541-4715 Large Memory 9 Output Processors
Frequency Synthesis & Deskew OTU-1 (2.7G)
FAX: (973) 541-4716 PLL PLL
Dynamic Frequency & Phase
Fit Fast Structured Array (FFSA) is a trademark of Toshiba Corporation. Reprogramming DisplayPort (1.62G/2.7G/5.4G)

PLL

PLL

PLL
Metal Prog. I/O Metal Prog. I/O

SOUTHEAST FFSA is based on Baysand MCSC technology. Toshiba has been granted an exclusive license to use technology.
All trademarks are of their respective manufacturer and may be registered in certain jurisdictions.
Built-In Self Test Vx1 (4G)
Duluth, GA The information contained herein is subject to change without notice. MC Transceiver
SATA/SAS (1.5G/3G/6G/12G)
MC DDR/LVDS
The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may Multi-protocol Transceiver JESD204b (0.3125G12.5G)
TEL: (770) 931-3363 result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. Soft PCS for dierent protocols
Up to 1600 Mbps
Hyper Transport (2.4G/2.8G/3.2G)
Non-DPA/DPA/Soft CDR (LVDS)
FAX: (770) 931-7602 TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability Built-in Self Test Flexible IO and Bank assignment Fiber Channel (1.0625G/2.125G/4.25G)
to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situation in which a malfunction
or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set DDR2/DDR3/LPDDR GPON (up: 1.244G, down: 2.488G)
forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the Handling Guide for Semiconductor Devices, or TOSHIBA Semiconductor Reliability Configurable Bus Width (DDR) SFI4.2 (2.5663.125G)
MCSC: Metal Configurable Standard Cell
Handbook etc. Built-in Self Test
SFI5.1 (2.4883.125G)
The Toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances,
etc.). These Toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or SPI4.2 (0.622G)
bodily injury (Unintended Usage). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instru- SPI5.1 (2.488G3.125G)
ments, medical instruments, all types of safety devices, etc. Unintended usage of Toshiba products listed in this document shall be made at the customers own risk.
The products described in this document may include products subject to foreign exchange and foreign trade laws.
The products contained herein may also be controlled under the U.S. Export Administration Regulations and/or subject to the approval of the U.S. Department of Commerce or U.S. Department of State prior to export.
Any export or re-export, directly or indirectly in contravention of any of the applicable export laws and regulations, is hereby prohibited.

www.toshiba.com/taec
Copyright 8/2014TAEC www.toshiba.com/taec
 Rapid and Cost-efficient Design of ASICs/ASSPs and FPGA Replacement.

ASIC Designs With Savings In NRE and Fast For the development of derivate ASICs, FFSAPlus offers the following FPGA Replacement with Better Performance, FFSA can provide package footprint compatibility for targeted
Time-To-Market key benefits: Lower Cost And Lower Power FPGAs on existing boards. Furthermore, BOM costs can be reduced
For the development of ASICs, FFSA offers the following key Low NRE and rapid turnaround time As an FPGA replacement product, FFSA offers the following key by eliminating the need for power management components,
benefits: Unit price similar to ASICs benefits: such as heat sinks, due to the lower power requirements of this
Three to five times lower NRE than standard-cell ASICs Mapping to multiple generations of FPGA devices technology, as shown below in the Power Comparison Chart.
Use any digital or analog IP
Power and performance that are similar to a standard-cell ASIC Faster performance than FPGAs (40 nm FFSA is faster than
FFSA offers several compelling value propositions relative to 28 nm FPGA) Power Comparison
As fast as 6 weeks from clean RTL to prototype 7.00
traditional standard-cell ASICs. Using metal mask customization Lower total system cost than an FPGA; less power and Static
Established design flow using standard tools technology, both NRE and time to market are significantly board space 6.00 Dynamic
FFSA can provide a pin/package footprint compatible solution 5.00
No FFSA specific point tools improved and design risk is minimized. Customers can take

Power (W)
4.00
FPGA-like IO flexibility advantage of current devices based on FFSA technology or they
3.00
FPGA-like memory flexibility (ROM, SP, DP RAMs) can define their own ASIC devices using FFSAPlus technology.
2.00
Packaging flexibility Short Development Lead Time 1.00
Fast time to mass production in as little as 8 weeks Synthesis DFT P&R STA PV Pkg WM Assly Test 0.00
ASIC
FPGA FFSA FFSA ASIC
28 nm 65 nm 40 nm 65 nm
25 Weeks

FFSA FFSA TAT is from clean RTL to ES sample for standard master and package FFSA Product Matrix
6 Weeks
SerDes
(Transceiver) Max. User Max. User Supported Supported
Process Data Gate Count SRAM Blocks Max. DDR Speed LVDS Speed
FFSA PLUS: Custom Master with Derivatives Series Technology Channel Rate [Gbps] [Mgate] [Mbit] User I/O [Mbps] [Mbps] Status
DDR PHY DDR PHY SA5 65 nm 0 6.5 16 13 1000 1066 1250 Available
PLL

Derivative 2 Derivative 3
FFSA (CB) SA5S 65 nm 15 6.5 6 6 1000 1066 1250 Available
MIPI DPHY

FFSA
LVDS

Fixed SA6S 40 nm 48 12.5 24 35 1000 1600 1600 Available

User Logic
PLL PLL Standard Cell
with Std. Cell
Design SA7S* 28 nm 48 28.0 45 100 1000 3200 1600 2015
Design
FFSA (CB)
HDMI PHY

USB PHY

FFSA
*Final data still to be confirmed.
Programmable Programmable
PLL

I/O I/O
Design a Customer Original Chip
Specific Platform
Derivative 1 Derivative 4
ASIC with Configurable Block (CB):
FFSA metal configurable blocks enable rapid and cost-efficient customization of derivative ASIC designs
 Rapid and Cost-efficient Design of ASICs/ASSPs and FPGA Replacement.

ASIC Designs With Savings In NRE and Fast For the development of derivate ASICs, FFSAPlus offers the following FPGA Replacement with Better Performance, FFSA can provide package footprint compatibility for targeted
Time-To-Market key benefits: Lower Cost And Lower Power FPGAs on existing boards. Furthermore, BOM costs can be reduced
For the development of ASICs, FFSA offers the following key Low NRE and rapid turnaround time As an FPGA replacement product, FFSA offers the following key by eliminating the need for power management components,
benefits: Unit price similar to ASICs benefits: such as heat sinks, due to the lower power requirements of this
Three to five times lower NRE than standard-cell ASICs Mapping to multiple generations of FPGA devices technology, as shown below in the Power Comparison Chart.
Use any digital or analog IP
Power and performance that are similar to a standard-cell ASIC Faster performance than FPGAs (40 nm FFSA is faster than
FFSA offers several compelling value propositions relative to 28 nm FPGA) Power Comparison
As fast as 6 weeks from clean RTL to prototype 7.00
traditional standard-cell ASICs. Using metal mask customization Lower total system cost than an FPGA; less power and Static
Established design flow using standard tools technology, both NRE and time to market are significantly board space 6.00 Dynamic
FFSA can provide a pin/package footprint compatible solution 5.00
No FFSA specific point tools improved and design risk is minimized. Customers can take

Power (W)
4.00
FPGA-like IO flexibility advantage of current devices based on FFSA technology or they
3.00
FPGA-like memory flexibility (ROM, SP, DP RAMs) can define their own ASIC devices using FFSAPlus technology.
2.00
Packaging flexibility Short Development Lead Time 1.00
Fast time to mass production in as little as 8 weeks Synthesis DFT P&R STA PV Pkg WM Assly Test 0.00
ASIC
FPGA FFSA FFSA ASIC
28 nm 65 nm 40 nm 65 nm
25 Weeks

FFSA FFSA TAT is from clean RTL to ES sample for standard master and package FFSA Product Matrix
6 Weeks
SerDes
(Transceiver) Max. User Max. User Supported Supported
Process Data Gate Count SRAM Blocks Max. DDR Speed LVDS Speed
FFSA PLUS: Custom Master with Derivatives Series Technology Channel Rate [Gbps] [Mgate] [Mbit] User I/O [Mbps] [Mbps] Status
DDR PHY DDR PHY SA5 65 nm 0 6.5 16 13 1000 1066 1250 Available
PLL

Derivative 2 Derivative 3
FFSA (CB) SA5S 65 nm 15 6.5 6 6 1000 1066 1250 Available
MIPI DPHY

FFSA
LVDS

Fixed SA6S 40 nm 48 12.5 24 35 1000 1600 1600 Available

User Logic
PLL PLL Standard Cell
with Std. Cell
Design SA7S* 28 nm 48 28.0 45 100 1000 3200 1600 2015
Design
FFSA (CB)
HDMI PHY

USB PHY

FFSA
*Final data still to be confirmed.
Programmable Programmable
PLL

I/O I/O
Design a Customer Original Chip
Specific Platform
Derivative 1 Derivative 4
ASIC with Configurable Block (CB):
FFSA metal configurable blocks enable rapid and cost-efficient customization of derivative ASIC designs
 Fit Fast Structured Array (FFSA)
Configurable Platform
Technology

Rapid and Cost-efficient Design of ASICs/ASSPs and FPGA Replacement. Rapid and Cost-efficient Design of ASICs/ASSPs and FPGA Replacement.

CONTACT INFORMATION
REGIONAL SALES OFFICES
NORTHWEST
San Jose, CA
TEL: (408) 526-2400
FAX: (408) 526-2410
SOUTHWEST
Irvine, CA
TEL: (949) 462-7700
FAX: (949) 462-2200
El Paso, TX
TEL: 915-771-8156
FAX: 915-771-8178
MIDWEST
Wixom, MI
TEL: (248) 347-2607
FAX: (248) 347-2602
Buffalo Grove, IL
TEL: (847) 484-2400
FAX: (847) 541-7287
NORTHEAST
Choosing Toshiba Toshiba Fit Fast Structured Array (FFSA) The key features of FFSA are as follows:
As a worldwide leader in chip design and manufactur- Toshiba, a premier, world-class semiconductor manufacturer has Customization using only four metal layers
ing, Toshiba possesses the requisite design experience, provided leading companies with custom SoCs/ASICs for over 500+ core cell library
tools, design methodologies, IP libraries and manufac- three decades and now brings an innovative metal-configurable Configurable FPGA like memory with optimized size and
turing expertise needed to help its customers develop platform technology for the design of ASICs and ASSPs, and the performance
an ASIC or ASSP. FFSA can help Toshiba customers seamless replacement of FPGAs. The Toshiba FFSA technology Design of multiple SoCs from one metal-configurable platform
differentiate their products from the competition by is used to rapidly create ASICs or ASSPs by customizing metal using the same EDA tools and methodologies as for ASICs
significantly reducing design cycles, project costs and mask layers. FFSA significantly reduces time to market and Scalable technology for 28 nm and smaller geometries
power budgets while improving performance. up-front, non-recurring engineering costs while maintaining Enhanced cell architecture allowing for improved routability,
the advantages of performance, power and lower unit cost power structure and area optimization
associated with standard-cell ASICs. Configurable IOs, PLLs, DDR/LVDS PHYs and multi-protocol
transceivers
FFSA Utilizing Metal Configurable (MC) Technology
Transceiver Protocols
MC I/Os
Flexible PWR/GND/IO assignment
PCIe-G1/2/3 (2.5G/5G/8G)
MC Core SRIO (1.25G/2.5G/3.125G/5G/6.25G)
500+ Std. cell libraries Configurable I/O banks
FPGA I/O standards support Interlaken (3.12510.3125G)
OCT, Dynamic impedance XAUI/RXAUI (3.125G/6.25G)
MC Memory matching
1.2V 3.3V Support
HiGig (3.75G)

PLL

PLL

PLL
Metal Prog. I/O Metal Prog. I/O
Native DP/SP Memory
Marlboro, MA Blocks PLL PLL GigE (1.25G)
Configurable SP/DP/ 10G Ethernet

Metal Prog. I/O

Metal Prog. I/O

TEL: (508) 481-0034 SDP/ROM
CPRI (0.6144G/1.288G/2.4576G/3.072G/6.144G)
FAX: (508) 481-8828 ECC and Parity Support
MCSC CORE + MC PLL OBSAI (0.768G/1.536G/3.072G/6.144G)
FPGA Memory like PLL PLL
MEMORY Wide-Range PLL

Metal Prog. I/O

Parsippany, NJ flexibility SDH/SONET (0.62208G/2.48832G/4.97664G)

Metal Prog. I/O

(10 MHz1.6 GHz)
Cascade Capable for OIF-CEI-6G (4.976G6.375G)
TEL: (973) 541-4715 Large Memory 9 Output Processors
Frequency Synthesis & Deskew OTU-1 (2.7G)
FAX: (973) 541-4716 PLL PLL
Dynamic Frequency & Phase
Fit Fast Structured Array (FFSA) is a trademark of Toshiba Corporation. Reprogramming DisplayPort (1.62G/2.7G/5.4G)

PLL

PLL

PLL
Metal Prog. I/O Metal Prog. I/O

SOUTHEAST FFSA is based on Baysand MCSC technology. Toshiba has been granted an exclusive license to use technology.
All trademarks are of their respective manufacturer and may be registered in certain jurisdictions.
Built-In Self Test Vx1 (4G)
Duluth, GA The information contained herein is subject to change without notice. MC Transceiver
SATA/SAS (1.5G/3G/6G/12G)
MC DDR/LVDS
The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may Multi-protocol Transceiver JESD204b (0.3125G12.5G)
TEL: (770) 931-3363 result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. Soft PCS for dierent protocols
Up to 1600 Mbps
Hyper Transport (2.4G/2.8G/3.2G)
Non-DPA/DPA/Soft CDR (LVDS)
FAX: (770) 931-7602 TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability Built-in Self Test Flexible IO and Bank assignment Fiber Channel (1.0625G/2.125G/4.25G)
to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situation in which a malfunction
or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set DDR2/DDR3/LPDDR GPON (up: 1.244G, down: 2.488G)
forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the Handling Guide for Semiconductor Devices, or TOSHIBA Semiconductor Reliability Configurable Bus Width (DDR) SFI4.2 (2.5663.125G)
MCSC: Metal Configurable Standard Cell
Handbook etc. Built-in Self Test
SFI5.1 (2.4883.125G)
The Toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances,
etc.). These Toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or SPI4.2 (0.622G)
bodily injury (Unintended Usage). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instru- SPI5.1 (2.488G3.125G)
ments, medical instruments, all types of safety devices, etc. Unintended usage of Toshiba products listed in this document shall be made at the customers own risk.
The products described in this document may include products subject to foreign exchange and foreign trade laws.
The products contained herein may also be controlled under the U.S. Export Administration Regulations and/or subject to the approval of the U.S. Department of Commerce or U.S. Department of State prior to export.
Any export or re-export, directly or indirectly in contravention of any of the applicable export laws and regulations, is hereby prohibited.

www.toshiba.com/taec
Copyright 8/2014TAEC www.toshiba.com/taec