Implementing the ALU Control Unit

A Two-Stage Approach
ALUOp Action needed by ALU

00 Addition (for load and store)

01 Subtraction (for beq)

10 Determined by funct field (R-type instruction)

11 Not used

We will let the main control (to be done later) summarize the opcode for us. From this
summary and the 6-bit funct field, we shall determine the control lines for the ALU.
Specifically, the main control will summarize the opcode as the 2-bit field ALUOp,
whose meaning is shown on the right

Controlling the ALU Given the Summary

How many entries do we have now in the truth table?

Instead of a 6-bit opcode we have a 2-bit summary.

We still have a 6-bit function (funct) field (needed for R-type).
So now we have 8 inputs (2+6) and 3 (or 4, if we want NOR) outputs.
256 rows, 11 columns; 2816 entries.
Certainly possible for automation ... but we will be clever.
Specifically, we will make great use of don't care bits.

Some Simplifications

opcode ALUOp operation funct ALU action ALU cntl

LW 00 load word xxxxxx add 0010

SW 00 store word xxxxxx add 0010

BEQ 01 branch equal xxxxxx subtract 0110

R-type 10 add 100000 add 0010

 R-type 10 subtract 100010 subtract 0110

R-type 10 AND 100100 and 0000

R-type 10 OR 100101 or 0001

R-type 10 SLT 101010 set on less than 0111

1. We will not be doing NOR so

i. We have only 8 MIPS instructions that use the ALU as shown in the
table on the right.
ii. The left bit of ALU cntl (Anegate) is always 0 and hence is not shown in
future tables.
2. The first two rows of the table above are the same. Each says that when
ALUOp=00, ALU cntl is 0010. Hence need need only one line.
3. When funct is used, its two HOBs are always 10 so are don't care inputs.
4. ALUOp=11 impossible and hence
i. 01 = x1
ii. 10 = 1x

Applying these simplifications yields the truth table:

ALUOp | Funct || Bnegate:OP
1 0 | 5 4 3 2 1 0 || B OP
------+--------------++------------
0 0 | x x x x x x || 0 10
x 1 | x x x x x x || 1 10
1 x | x x 0 0 0 0 || 0 10
1 x | x x 0 0 1 0 || 1 10
1 x | x x 0 1 0 0 || 0 00
1 x | x x 0 1 0 1 || 0 01
1 x | x x 1 0 1 0 || 1 11

How should we implement this?

We will do it PLA style (disjunctive normal form, 2-levels of logic) for each of the
three output bits separately.

Specifically, for each output, we will

1. First find the minterms, i.e., the cases in which that output bit is asserted.
2. Then produce a circuit for each miniterm (an AND of literals).
3. Finally, construct an OR of these ANDs.

Only the first part requires any real work.

BNegate

When is Bnegate (called Op2 in book) asserted?

Ans: Those rows in the table above where its bit (the leftmost output bit) is 1. That is,
rows 2, 4, and 7.

We show those three rows in the table:

ALUOp | Funct
1 0 | 5 4 3 2 1 0
------+------------
x 1 | x x x x x x
1 x | x x 0 0 1 0
1 x | x x 1 0 1 0

Looking again at the full (7-row) table, we notice that, in the 5 rows with ALUOp=1x,
F1=1 is enough to distinugish the two rows where Bnegate is asserted. This gives the
last table for BNegate:

ALUOp | Funct
1 0 | 5 4 3 2 1 0
------+-------------
x 1 | x x x x x x
1 x | x x x x 1 x

Hence Bnegate is simply ALUOp0 + (ALUOp1 F1).

Op0

Now we apply the same technique to determine when OP0 is asserted and begin by
listing on the right the rows in the full table where its bit (the rightmost output bit) is
set.
ALUOp | Funct

1 0 | 5 4 3 2 1 0

------+------------

1 x | x x 0 1 0 1

1 x | x x 1 0 1 0

As with BNegate, we look back at the full table and study all the rows where
ALUOp=1x, and, within that group of rows, those rows where OP0 is asserted (the
last two rows).
 ALUOp | Funct
1 0 | 5 4 3 2 1 0
------+------------
1 x | x x x x x 1
1 x | x x 1 x x x

We see that the rows where OP0 is asserted are characterized by just two Function
bits (3 and 0), which reduces the table to that on the right.

Hence OP0 is ALUOp1 F0 + ALUOp1 F3

Op1

Finally, we determine when is OP1 asserted using the same technique. However, we
shall see that this bit is more inspiring than the first two. Once again the procedure
begins by listing on the right those rows where the relevant bit (the middle output bit)
is one.
ALUOp | Funct

1 0 | 5 4 3 2 1 0

------+------------

0 0 | x x x x x x

x 1 | x x x x x x

1 x | x x 0 0 0 0

1 x | x x 0 0 1 0

1 x | x x 1 0 1 0

Right away we get a hint that we have more work to do as five rows pop up.

As before we study the 5 rows in the original 7-row table that have ALUOp=1x, and,
within that group, those rows where OP1 is asserted (rows 3, 4, and 7).

We again find that one Funct bit distinguishes when OP1 is asserted, namely Funct bit
2 (in this case OP1 is asserted when Funct bit 2 is false).

As a result the truth table for OP1 reduces to the 3-row version shown below:

ALUOp | Funct
1 0 | 5 4 3 2 1 0
 ------+------------
0 0 | x x x x x x
x 1 | x x x x x x
1 x | x x x 0 x x

Although this truth table would yield a fairly small circuit, we shall to simplify it
further.

Recall from the original table, that the x 1 in the second row is really 0 1.

Although x 1 gives us more freedom than 0 1 in implementing this row by itself, we

are able to simply further by undoing the don't care and noting that, with 0 1 in the
second row, rows 1 and 2 can be combined to give the table:
ALUOp | Funct
1 0 | 5 4 3 2 1 0
------+------------
0 x | x x x x x x
1 x | x x x 0 x x

Last, we can use the first row to enlarge the scope (and hence simplify the
implementation) of the last row resulting in the final table on the right.

ALUOp | Funct
1 0 | 5 4 3 2 1 0
------+------------
0 x | x x x x x x
x x | x x x 0 x x

So OP1 = (ALUOp1)' + (Funct2)'