Apple Macbook Air A1304 (MLB M96) PDF

8 7 6 5 4 3 2 1
CK ENG
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. APPD APPD
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. REV ZONE ECN DESCRIPTION OF CHANGE
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
SCHEM,MLB,M96 DATE DATE
EVT
08/01/2008
D D
(.csa) Date (.csa) Date
Page
TABLE_TABLEOFCONTENTS_HEAD
Contents Sync Page
TABLE_TABLEOFCONTENTS_HEAD
Contents Sync
1 N/A 52 02/04/2008
TABLE_TABLEOFCONTENTS_ITEM
1 Table of Contents N/A
42 M97 SMBUS CONNECTIONS BEN
2 05/11/2006 53 01/09/2007
2 System Block Diagram WFERRY-WF
43 Voltage Sensors M70
3 06/30/2005 54 02/04/2008
3 Power Block Diagram POWER
44 Current Sensing YUNWU
4 (N/A) 55 01/09/2007
4 CONFIGURATION OPTIONS (N/A)
45 TEMPERATURE SENSORS M70
5 N/A 56 01/09/2007
5 Acoustic Cap BOM Config Tables N/A
46 Fan M70
7 (MASTER) 59 01/12/2007
6 Functional Test and No-Tests (MASTER)
47 Sudden Motion Sensor (SMS) M76_MLB
8 06/15/2006 61 02/15/2008
7 Power Aliases WFERRY
48 SPI ROM CHANGZHANG
9 (MASTER) 69 01/09/2007
8 SIGNAL ALIAS /RESET (MASTER)
49 DC-In & Battery Connectors M70
10 02/04/2008 71 07/13/2005
9 CPU FSB M97
50 IMVP6 CPU VCore Regulator POWER
11 (MASTER) 72 06/24/2008
10 CPU Power & Ground (MASTER)
51 MCP CORE REGULATOR MINGJING
12 04/26/2006 73
11 CPU Decoupling & VID MSARWAR
52 1.8V LDO Supply
13 02/04/2008 74 05/21/2008
12 eXtended Debug Port (XDP) M97
53 1V05 S5 Power Supply RXU_K20
14 02/04/2008 75 01/09/2007
13 MCP CPU Interface M97
54 1.5V/0.75V Supplies M70
15 02/04/2008 76 05/21/2008
14 MCP Memory Interface M97
55 5V / 3.3V Power Supply RXU_K20
16 02/04/2008 77 02/04/2008
15 MCP Memory Misc M97 56 POWER SEQUENCING YUAN.MA
C
16
17
18
MCP PCIe Interfaces M97
02/04/2008
02/04/2008
57
78
79
POWER FETS YUAN.MA
02/04/2008
01/09/2007
C
17 MCP Ethernet & Graphics M97
58 PBUS Supply/Battery Charger M70
19 02/04/2008 90 06/23/2006
18 MCP PCI & LPC M97
59 LVDS,Camera Conn. and ALS Conn. GPU
20 02/04/2008 93 12/18/2007
19 MCP SATA & USB M97
60 DISPLAYPORT SUPPORT NMARTIN
21 02/04/2008 94 01/17/2008
20 MCP HDA & MISC M97
61 DisplayPort Connector M98_MLB
22 02/04/2008 97 (MASTER)
21 MCP Power & Ground M97
62 LED Backlight Driver (MASTER)
25 02/04/2008 98 02/04/2008
22 MCP Standard Decoupling M97
63 LCD Backlight Support M97
26 02/04/2008 99
23 MCP Graphics Support M97
64 Additional CPU/GPU Decoupling
28 02/04/2008 100 02/04/2008
24 SB Misc M97
65 CPU/FSB Constraints M97
29 01/15/2008 101 02/04/2008
25 FSB/DDR3 Vref Margining BEN
66 Memory Constraints M97
30 01/30/2008 102 02/04/2008
26 DDR3 Support T18_MLB
67 MCP Constraints 1 M97
31 (MASTER) 103 02/04/2008
27 DDR3 DRAM Channel A (0-31) (MASTER)
68 MCP Constraints 2 M97
32 106 02/04/2008
28 DDR3 DRAM Channel A (32-63)
69 SMC Constraints M97
33 (MASTER) 108 (MASTER)
29 DDR3 DRAM Channel B (0-31) (MASTER)
70 M96 Power and Ground Nets (MASTER)
34 109 02/04/2008
30 DDR3 DRAM Channel B (32-63)
71 M96 RULE DEFINITIONS M97
35 06/20/2005
31 DDR BYPASSING 1 MEMORY
36 06/20/2005
32 DDR BYPASSING 2 MEMORY
37 01/09/2007
33 Memory Active Termination
B TABLE_TABLEOFCONTENTS_ITEM
34
41
Wireless M93 Connector
M70
M70
01/09/2007 B
42 (MASTER)
35 Hatch and Audio Connectors (MASTER)
45 02/05/2008
36 SATA Connectors CHANGZHANG
46 01/09/2007
37 USB EXTERNAL CONNECTORS M70
48
38 IPD Connector
49 02/21/2008
39 SMC M97
50 01/09/2007
40 SMC SUPPORT M70
51 01/24/2008
41 LPC+SPI Debug Connector CHANGZHANG
DIMENSIONS ARE IN MILLIMETERS
METRIC APPLE INC.

XX
A X.XX
DRAFTER DESIGN CK NOTICE OF PROPRIETARY PROPERTY A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
X.XXX PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
ENG APPD MFG APPD
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
Schematic / PCB #s ANGLES II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
QA APPD DESIGNER TITLE
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
DO NOT SCALE DRAWING
051-7631 1 SCHEM,MLB,M96 SCH CRITICAL
RELEASE SCALE SCHEM,MLB,M96
820-2375 1 PCBF,MLB,M96 PCB CRITICAL NONE
DRAWING SIZE DRAWING NUMBER

TITLE=M96_MLB MATERIAL/FINISH REV.
ABBREV=DRAWING
LAST_MODIFIED=Fri Aug 1 09:54:13 2008 THIRD ANGLE PROJECTION
NOTED AS
APPLICABLE
D 051-7631
SHT 1
2.3.0
OF 71
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
U1000
CPU
1.6/1.8 GHz
J6900/80
Pg 10 J1300 DC/Batt Power

Pg 11
MINI XDP CONN Conn Supplies
PG 12 PG 51 PG 52-59
FSB
64-Bit J9000 TOP ALS PG 60
800 MHz
J4100 PG 36
MEM Active M93
J4200 FSB
Pg 14 Parallel
U3100
U3110
U3120
Term
HDMI
U1400
Display Port U3130 J4800
Main Memory
U3210 Pg 35
U3220
Pg 15/16
U3230
U3240 IPD
FLAT PANEL
PG 37 DDR3 - Dual Channel
0.75V - 64 Bits CPU/MCP T-Diode Thermal Sensor U5515 PG 47 PG 40

J9000
DDR3 RAM
1066 MHz Local TEMP near power supplies U5550 PG 47
Pg29/30
Local TEMP near Air Vent U5560 PG 47
LVDS Int Disp Local TEMP near Front Edge U5570 PG 47
Pg 18
Conn Misc
LVDS
C Camera MCP79U
Pg 21
C
PG 60 SUDDEN MOTION DETECT U5900 PG 49
7
Core
6
U3300
U3310
Pg 20
5
USB
U3320 VOLTAGE SENSORS PG 45
Ln0
U3330
4
U3410
U3420
3
U3430
U3440
2
FAN CONN J5600 PG 48
Ln1
1
PCI-E
0
DDR3 RAM
Pg31/32
Pg 24
SMB
Ln2
A B 0 BSA MGMT ADC Fan Ser

Pg 17
J5100
SMC Prt
Pg 19
LPC
FrankCard Conn
Ln3
U9600 U4900 PG 41 PG 43
U9601 U9500
NAND
NAND Flash SATA DACS LAN PCI HDA SPI
Flash Pg20 Pg18 Pg18 Pg 19 Pg 21
Controller Pg 21
PG 64 PG 63
J4500
B HDD SATA B
U6100
Conn Well Spring J4200
SPI J4800
Trackpad/Keyboard
PG 38
Boot ROM PG 40
External
PG 50 USB
PG 37
J9050
DIGITAL MIC
J4100
CONNECTOR
M93 AirPort/BT
PG 60
Pg 36
J4260
Audio
Connector
Pg 37
System Block Diagram

A SYNC_MASTER=WFERRY-WF
NOTICE OF PROPRIETARY PROPERTY

SYNC_DATE=05/11/2006
A
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
II NOT TO REPRODUCE OR COPY IT
SIZE DRAWING NUMBER REV.
D 051-7631 2.3.0
APPLE INC. SCALE SHT OF

NONE 2 71
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
DC-JACK
6A FUSE 01
M96 POWER SYSTEM ARCHITECTURE
PPDCIN_G3H_R D6901 SMC PWRGD 04
PP18V5_DCIN PP18V5_G3H_CHGR RN5VD30A-F SMC_RESET_L
02 PP3V42_G3H_SMC
PPDCIN_G3H U5000
PPVBATT_G3H_R D6901
J6980 F6900 (PAGE 42)
SMBUS_SMC_BSA_SCL ENABLE
PPBUSB_G3H PPVIN_G3H_DCIN D6901 3.425V G3HOT
03
PP3V42_G3H_REG
VIN LTC3470A DEBUG_RESET_L
SMBUS_SMC_BSA_SDA
U6900 (200 mA MAX CURRENT) 43
7A FUSE Q7853
LPC_RESET* SMC_LRESET_L
R7980 (PAGE 51)
PPVBAT_G3H_CHGR_REG FC_RESET_L
D ENABLES
VOUT
PPBUSB_G3H
PBUSA_G3H PP1V05_S0_FET 27
PCIE_RESET* PCA9557D_RESET_L D
PBUS Supply/ (0.002) 42
BATTERY CHARGER
A R7930
V 02 P1V05S0_EN 26
AIRPORT_RST_L
BKLT_PLT_RST_L
BATTERY 2S2P MCP79U
ISL6258 Q7950 Q5315 11
U7900 VIN U1400
VIN P1V05_S5_EN 1.05V PP1V05_S5_REG
(PAGE 59) 10 ENA1 VOUT1
(S5) (7 A MAX CURRENT) 40
01 CHGR_BGATE 33 MCPCORES0_EN MCPCORE PPMCPCORE_S0_REG 34 MCP_PS_PWRGD PS_PWRGD PWRBTN*
ENA2 VOUT2
(S0) (25 A MAX CURRENT)
RSMRST*
ISL6236 PG1 FSB_CPURST_L
U7200 P1V05_S5_PGOOD 12 CPU_RESET*
BATT_POS_F (PAGE 53)
PG2 MCPCORES0_PGOOD
35 CPU_PWRGD
CPU_PWRGD
41
38
02 CPUVCORE PPVCORE_S0_CPU_REG PPVCORE_S0_CPU
VOUT
VIN (30 A MAX CURRENT) U2850
PP3V3_S5_PWRCTI
IMVP_VR_ON
VR_ON
DELAY 39
Q7710
R-100K P5VS3_EN_L 16 37 ISL6261CRZ PGOOD VR_PWRGOOD_DELAY VR_PWRGOOD_DELAY CPU
C-NoStuff U7100
C 15
DELAY
R-1K P3V3S3_EN
PPBUSA_G3H
(PAGE 52) PWRGOOD
C
C-0.47uF 19 MCPCORES0_PGOOD FSB_CPURST_L
MCP79U U7770
35 RESET*
PM_SLP_S4_L
SLP_S5* DELAY
22 26 PP1V5_S0_VMON LTC2909
R-5.1K DDRREG_EN IMVP_VR_ON ADJ1 P5V3V3_PGOOD U1000
C-0.47uF (PAGE 10) 44
=PPBUSB_G3H PP1V05_S0_VMON S0PGOOD_PWROK
25 04 26 RST*
03 ADJ2 ALL_SYS_PWRGD
SLP_S3*
SMC_ADAPTER_PRESENT
SMC PP3V42_G3H_PWRCTL
(PAGE 57)
U4900
(PAGE 41) DELAY
P60 Q7700
SMC_PM_G2_EN PM_G2_P3V3S5_EN_L PP3V3S5_EN_L
R-100K
WOW_EN C-NoStuff (S5) 08
PCI_RESET0*
07 DELAY
29 P1V05_S5_EN
SMC_PM_G2_EN R-5.1K
26 C-0.47uF 10
PP3V3_S5_PWRCTL PM_WLAN_EN_L
PM_SLP_S3_L
09
P3V3S0_EN Q7840
P5VS0_EN PP5V_S0_FET
28
26
PBUSVSENS_EN
02 P5VS0_EN_L 27
DELAY
P1V05S0_EN 16 17 14
R-0 26 Q7621 VIN 22 SMC
C-0.47uF (S0) PP5V_S3_REG PP5V_S3
B DELAY
P5VS3_EN_L
(S3)
EN1 5V VO1
(? A MAX CURRENT)
U7740
ALL_SYS_PWRGD RSMRST_OUT(P15)
PM_RSMRST_L B
R-5.1k
P1V8S0_EN 31 09 09 P3V3_S5_PWRCTL TPS19918 PWRGD(P12) 99ms DLY
PP3V3_S5_REG PP3V3_S5 SENSE IMVP_VR_ON
C-0.47uF (S0) PP3V3S5_EN_L VO2 13 IMVP_VR_ON(P16) 37
EN2 3.3V (? A MAX CURRENT) PP1V5_S5_PGOOD RSMRST_PWRGD RSMRST_PWRGD
RSMRST_IN(P13)
DELAY (S5) MR RESET
12
MCPDDR_EN 08 Q7810 (PAGE 57)
R-0 26 TPS51120 SMC_ONOFF_L
C-0.47uF (S0) U7600 PP3V3_S3
PWR_BUTTON(P90) 06
21 P17(BTN_OUT)
PM_PWRBTN_L
DELAY (PAGE 60)
CPUVTTS0_EN BATTERY ONLY: 05
R-33k 36 PGOOD1,2 SMC_LRESET_L
PLT_RST*
C-0.47uF (S0) 20
P5V3V3_PGOOD 31 P1V8_S0_EN
1.8V S0
18 P3V3S3_EN_L EN TPS19918 SMC_RESET_L
DELAY RST*
MCPCORES0_EN PPVIN_S0_P1V8S0 U7360 PP1V8_S0_REG
R-22k 33 VIN VOUT 32
C-0,47uF (S0) (PAGE 54) (200 mA MAX) 15 PM_SLP_S5_L
SLP_S5_L(P95)
PM_SLP_S4_L
15 SLP_S4_L(P94)
Q7830 28 PM_SLP_S3_L
SLP_S3_L(P93)
PP3V3_S0_FET 24
U4900
(PAGE 41)
P3V3S0_EN_L 27
Q7801
27
Power Block Diagram
PP1V5_S3_P1V5S0FET =PP1V5_S0_FET
A PP0V75_S3_VTTREF
SYNC_MASTER=POWER

A
MCPDDR_EN
22 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
26 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
VIN VLDOIN AGREES TO THE FOLLOWING
23
DDRREG_EN 1.5V PP1V5_S3_REG
S5 VOUT1
(11 A MAX CURRENT)
R2870
MEM_VTT_EN_R DDRVTT_EN III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
S3 0.75V PP0V75_S0_REG
VOUT2
29 30 SIZE DRAWING NUMBER REV.
TPS51116 D 051-7631 2.3.0

U7500 DDRREG_PGOOD APPLE INC.
(PAGE 55) 24 SCALE SHT OF
NONE 3 71
8 7 6 5 4 3 2 1
PAGE_BORDER=TRUE
8 7 6 5 4 3 2 1
BOMs BOMOPTION Groups

TABLE_BOMGROUP_HEAD TABLE_BOMGROUP_HEAD
BOM NUMBER BOM NAME BOM OPTIONS BOM GROUP BOM OPTIONS
TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM
630-9734 PCBA,MLB,1.6GHZ,HY 2GB,SS CAP,M96 EEE_4DA,M96_COMMON,M96_HYNIX,M96_SS_CAP,CPU_1_6GHZ M96_COMMON ALTERNATE,COMMON,M96_COMMON1,M96_COMMON2,M96_COMMON3

630-9735 PCBA,MLB,1.6GHZ,HY 2GB,MU CAP,M96 EEE_4DB,M96_COMMON,M96_HYNIX,M96_MU_CAP,CPU_1_6GHZ M96_COMMON1 MCP_B02,BOOTROM_DEVEL,SMC_PRGRM,BOOT_MODE_USER,JTAG_ALLDEV,MEMRESET_HW,MEMRESET_MCP,VREFMRGN

630-9514 PCBA,MLB,1.6GHZ,HY 2GB,TY CAP,M96 EEE_2AL,M96_COMMON,M96_HYNIX,M96_TY_CAP,CPU_1_6GHZ M96_COMMON2 LPCPLUS,XDP,XDP_CONN

630-9738 PCBA,MLB,1.8GHZ,HY 2GB,SS CAP,M96 EEE_4DC,M96_COMMON,M96_HYNIX,M96_SS_CAP,CPU_1_8GHZ M96_COMMON3 MCP_CS1_NO

D 630-9516 PCBA,MLB,1.8GHZ,HY 2GB,MU CAP,M96 EEE_2AN,M96_COMMON,M96_HYNIX,M96_MU_CAP,CPU_1_8GHZ

TABLE_BOMGROUP_ITEM
M96_HYNIX DRAM_HYNIX
TABLE_BOMGROUP_ITEM
D
630-9517 PCBA,MLB,1.8GHZ,HY 2GB,TY CAP,M96 EEE_2AP,M96_COMMON,M96_HYNIX,M96_TY_CAP,CPU_1_8GHZ M96_MICRON DRAM_MICRON,DRAM_SPD_2
TABLE_BOMGROUP_ITEM
M96_SS_CAP SS_CAP_2_2UF,SS_CAP_10UF,SS_CAP_1UF
TABLE_BOMGROUP_ITEM
M96_MU_CAP MU_CAP_2_2UF,MU_CAP_10UF,MU_CAP_1UF
TABLE_BOMGROUP_ITEM
M96_TY_CAP TY_CAP_2_2UF,TY_CAP_10UF,TY_CAP_1UF
Module Parts
Bar Code Label / EEE #s
337S3658 1 IC,PDC,QS,1.60GHZ,17W,1066,6M U1000 CRITICAL CPU_1_6GHZ
337S3659 1 IC,PDC,QS,1.80GHZ,17W,1066,6M U1000 CRITICAL CPU_1_8GHZ
826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEE:4DA] CRITICAL EEE_4DA
338S0604 1 IC,GMCP,MCP79U-A01Q,27MMX27MM,BGA1588 U1400 CRITICAL MCP_A01Q
826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEE:4DB] CRITICAL EEE_4DB
338S0601 1 IC,GMCP,MCP79U-B01,27MMX27MM,BGA1588 U1400 CRITICAL MCP_B01
826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEE:2AL] CRITICAL EEE_2AL
338S0637 1 IC,GMCP,MCP79U-B02,27MMX27MM,BGA1588 U1400 CRITICAL MCP_B02
826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEE:4DC] CRITICAL EEE_4DC
335S0615 1 IC, 32MBIT 8-PIN SERIAL FLASH, WSON8 U6100 CRITICAL BOOTROM_BLANK_4MB
826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEE:2AN] CRITICAL EEE_2AN
341S2382 1 IC,EFI,BOOTROM DEVELOPMENT (UNLOCKED),M96 U6100 CRITICAL BOOTROM_DEVEL
826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEE:2AP] CRITICAL EEE_2AP
341S2326 1 IC,EFI,BOOTROM FINAL (LOCKED),M96 U6100 CRITICAL BOOTROM_FINAL
1 U4900 CRITICAL SMC_BLANK
C 338S0563
341S2327 1
IC,SMC,HS8/2117
IC,PRGRM,SMC (NEW),M96 U4900 CRITICAL SMC_PRGRM

C
333S0476 4 HYNIX,DDR3,128M16,9x11.5 U3100,U3110,U3120,U3130 CRITICAL DRAM_HYNIX
333S0475 4 MICRON,DDR3,128M16,9x11.5 U3100,U3110,U3120,U3130 CRITICAL DRAM_MICRON
353S1938 1 IC,ISL6258,REV2,BAT CHGR, 28P QFN U7900 CRITICAL
B B
Alternate Parts
PART NUMBER ALTERNATE FOR REFERENCE DESIGNATOR(S) DESCRIPTION BOM OPTION
PART NUMBER
128S0093 128S0092 ALL 33UF 20% 16V DCASE
376S0466 376S0410 ALL Si4413 for Si4405
740S0067 740S0028 ALL 0.5A OC FUSE
104S0023 104S0018 ALL 1206 1/4W .002 OHM
CONFIGURATION OPTIONS
152S0684 152S0421 ALL 1.0UH,22A,10MOHM SYNC_MASTER=(N/A) SYNC_DATE=(N/A)
A 376S0627 376S0723 ALL POWER NFET, 30V, 18A NOTICE OF PROPRIETARY PROPERTY
A
152S0905 152S0861 ALL IND,IHLP4040CZ,0.68uH,18A THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
D 051-7631 2.3.0

NONE 4 71
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
1UF 0402 CAPACITOR VENDOR TABLES FOR ACOUSTICS

SAMSUNG MURATA TAIYO YUDEN
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
138S0629 4 CAP, 1UF, 6.3V, 10%, 0402 C7947,C7360,C2504,C2505 CRITICAL SS_CAP_1UF 138S0628 4 CAP, 1UF, 6.3V, 10%, 0402 C7947,C7360,C2504,C2505 CRITICAL MU_CAP_1UF 138S0630 4 CAP, 1UF, 6.3V, 10%, 0402 C7947,C7360,C2504,C2505 CRITICAL TY_CAP_1UF
138S0629 7 CAP, 1UF, 6.3V, 10%, 0402 C2506,C2507,C2516,C2517,C7100,C7101,C7103 CRITICAL SS_CAP_1UF 138S0628 7 CAP, 1UF, 6.3V, 10%, 0402 C2506,C2507,C2516,C2517,C7100,C7101,C7103 CRITICAL MU_CAP_1UF 138S0630 7 CAP, 1UF, 6.3V, 10%, 0402 C2506,C2507,C2516,C2517,C7100,C7101,C7103 CRITICAL TY_CAP_1UF
D 138S0629 9 CAP, 1UF, 6.3V, 10%, 0402 C2860,C7296,C7297,C7492,C7500,C7940,C7941,C9760,C7603 CRITICAL SS_CAP_1UF 138S0628 9 CAP, 1UF, 6.3V, 10%, 0402 C2860,C7296,C7297,C7492,C7500,C7940,C7941,C9760,C7603 CRITICAL MU_CAP_1UF 138S0630 9 CAP, 1UF, 6.3V, 10%, 0402 C2860,C7296,C7297,C7492,C7500,C7940,C7941,C9760,C7603 CRITICAL TY_CAP_1UF D
2.2UF 0402 CAPACITOR VENDOR TABLES FOR ACOUSTICS

138S0632 10 CAP, 2.2UF, 6.3V, 20%, 0402 C1240,C1241,C1242,C1243,C1244,C1245,C1246,C1247,C1248,C1249 CRITICAL SS_CAP_2_2UF 138S0633 10 CAP, 2.2UF, 6.3V, 20%, 0402 C1240,C1241,C1242,C1243,C1244,C1245,C1246,C1247,C1248,C1249 CRITICAL MU_CAP_2_2UF 138S0634 10 CAP, 2.2UF, 6.3V, 20%, 0402 C1240,C1241,C1242,C1243,C1244,C1245,C1246,C1247,C1248,C1249 CRITICAL TY_CAP_2_2UF
8 CRITICAL SS_CAP_2_2UF 8 CRITICAL MU_CAP_2_2UF 8 CRITICAL TY_CAP_2_2UF
C 138S0632
138S0632 10
CAP, 2.2UF, 6.3V, 20%, 0402
CAP, 2.2UF, 6.3V, 20%, 0402

C1260,C1261,C1262,C1263,C1264,C1265,C1266,C1267
C9900,C9901,C9902,C9903,C9904,C9905,C9906,C9907,C9908,C9909 CRITICAL SS_CAP_2_2UF

138S0633
138S0633 10
CAP, 2.2UF, 6.3V, 20%, 0402
CAP, 2.2UF, 6.3V, 20%, 0402

C1260,C1261,C1262,C1263,C1264,C1265,C1266,C1267
C9900,C9901,C9902,C9903,C9904,C9905,C9906,C9907,C9908,C9909 CRITICAL MU_CAP_2_2UF

138S0634
138S0634 10
CAP, 2.2UF, 6.3V, 20%, 0402
CAP, 2.2UF, 6.3V, 20%, 0402

C1260,C1261,C1262,C1263,C1264,C1265,C1266,C1267
C9900,C9901,C9902,C9903,C9904,C9905,C9906,C9907,C9908,C9909 CRITICAL TY_CAP_2_2UF

C
138S0632 12 CAP, 2.2UF, 6.3V, 20%, 0402 C1283,C1284,C1285,C1286,C1287,C1288,C1291,C1292,C1293,C1294,C1295,C1296 CRITICAL SS_CAP_2_2UF 138S0633 12 CAP, 2.2UF, 6.3V, 20%, 0402 C1283,C1284,C1285,C1286,C1287,C1288,C1291,C1292,C1293,C1294,C1295,C1296 CRITICAL MU_CAP_2_2UF 138S0634 12 CAP, 2.2UF, 6.3V, 20%, 0402 C1283,C1284,C1285,C1286,C1287,C1288,C1291,C1292,C1293,C1294,C1295,C1296 CRITICAL TY_CAP_2_2UF
138S0632 8 CAP, 2.2UF, 6.3V, 20%, 0402 C3542,C3544,C3545,C3546,C3550,C3551,C3554,C3555 CRITICAL SS_CAP_2_2UF 138S0633 8 CAP, 2.2UF, 6.3V, 20%, 0402 C3542,C3544,C3545,C3546,C3550,C3551,C3554,C3555 CRITICAL MU_CAP_2_2UF 138S0634 8 CAP, 2.2UF, 6.3V, 20%, 0402 C3542,C3544,C3545,C3546,C3550,C3551,C3554,C3555 CRITICAL TY_CAP_2_2UF
138S0632 7 CAP, 2.2UF, 6.3V, 20%, 0402 C2530,C2531,C2532,C2533,C2534,C2535,C2536 CRITICAL SS_CAP_2_2UF 138S0633 7 CAP, 2.2UF, 6.3V, 20%, 0402 C2530,C2531,C2532,C2533,C2534,C2535,C2536 CRITICAL MU_CAP_2_2UF 138S0634 7 CAP, 2.2UF, 6.3V, 20%, 0402 C2530,C2531,C2532,C2533,C2534,C2535,C2536 CRITICAL TY_CAP_2_2UF
138S0632 3 CAP, 2.2UF, 6.3V, 20%, 0402 C4800,C7362,C7511 CRITICAL SS_CAP_2_2UF 138S0633 3 CAP, 2.2UF, 6.3V, 20%, 0402 C4800,C7362,C7511 CRITICAL MU_CAP_2_2UF 138S0634 3 CAP, 2.2UF, 6.3V, 20%, 0402 C4800,C7362,C7511 CRITICAL TY_CAP_2_2UF
B
10UF 0603 CAPACITOR VENDOR TABLES FOR ACOUSTICS B
138S0626 10 CAP, 10UF, 6.3V, 20%, 0603 C1200,C1201,C1202,C1203,C1204,C1205,C1206,C1207,C1208,C1209 CRITICAL SS_CAP_10UF 138S0625 10 CAP, 10UF, 6.3V, 20%, 0603 C1200,C1201,C1202,C1203,C1204,C1205,C1206,C1207,C1208,C1209 CRITICAL MU_CAP_10UF 138S0627 10 CAP, 10UF, 6.3V, 20%, 0603 C1200,C1201,C1202,C1203,C1204,C1205,C1206,C1207,C1208,C1209 CRITICAL TY_CAP_10UF
138S0626 3 CAP, 10UF, 6.3V, 20%, 0603 C1230,C1231,C1280 CRITICAL SS_CAP_10UF 138S0625 3 CAP, 10UF, 6.3V, 20%, 0603 C1230,C1231,C1280 CRITICAL MU_CAP_10UF 138S0627 3 CAP, 10UF, 6.3V, 20%, 0603 C1230,C1231,C1280 CRITICAL TY_CAP_10UF
138S0626 8 CAP, 10UF, 6.3V, 20%, 0603 C4109,C4613,C5066,C7502,C7541,C7650,C7690,C9012 CRITICAL SS_CAP_10UF 138S0625 8 CAP, 10UF, 6.3V, 20%, 0603 C4109,C4613,C5066,C7502,C7541,C7650,C7690,C9012 CRITICAL MU_CAP_10UF 138S0627 8 CAP, 10UF, 6.3V, 20%, 0603 C4109,C4613,C5066,C7502,C7541,C7650,C7690,C9012 CRITICAL TY_CAP_10UF
138S0626 5 CAP, 10UF, 6.3V, 20%, 0603 C7266,C7267,C7269,C7401,C7605 CRITICAL SS_CAP_10UF 138S0625 5 CAP, 10UF, 6.3V, 20%, 0603 C7266,C7267,C7269,C7401,C7605 CRITICAL MU_CAP_10UF 138S0627 5 CAP, 10UF, 6.3V, 20%, 0603 C7266,C7267,C7269,C7401,C7605 CRITICAL TY_CAP_10UF
Acoustic Cap BOM Config Tables

A SYNC_MASTER=N/A

SYNC_DATE=N/A
A
D 051-7631 2.3.0

NONE 5 71
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Functional Test Points
NB NO_TESTS
These are normally testpoints but become NC
FUNC TEST - XDP/ITP CONNECTOR
NO_TEST
I593 TRUE XDP_BPM_L<0..5> 9 12
FUNC TEST - M93 WIRELESS CONNECTOR FUNC TEST - Power Supplies 65
FUNC TEST - BATTERY CONNECTOR I595 TRUE TP_XDP_OBSFN_B0 12
x2 I647 TRUE BATT_POS 49 I470 TRUE AIRPORT_RST_L 6 24 34 I92

PPVCORE_S0_CPU 7 70 I680 TRUE TP_XDP_OBSFN_B1 12
x2 I649 TRUE GND I475 TRUE PCIE_WAKE_L 6 16 34 I454

PP0V75_S0 7 70 I681 TRUE TP_XDP_OBSDATA_B0 12
I638 TRUE SMC_BS_ALRT_L 39 40 49 I479 TRUE CK505_SRC_CLKREQ6_L 6 I455

PP1V05_S0 7 70 I683 TRUE TP_XDP_OBSDATA_B1 12
TRUE SMBUS_SMC_BSA_SCL 42 69 TRUE PCIE_CLK100M_MINI_N_F 34 PP1V5_S0 7 70 TRUE TP_XDP_OBSDATA_B2 12
D
I640
I639 TRUE SMBUS_SMC_BSA_SDA 42 69

I478
I476 TRUE PCIE_CLK100M_MINI_P_F 34

I457
I460 PP1V5_S3 7 70
I682
I684 TRUE TP_XDP_OBSDATA_B3 12 D

I477 TRUE PCIE_E_D2R_N_F 34 I459
PP1V05_S5 7 70 I685 TRUE XDP_PWRGD 12
I480 TRUE PCIE_E_D2R_P_F 34 I458 PPMCPCORE_S0 7 70 I687 TRUE XDP_OBS20 12
FUNC TEST - DC-IN CONNECTOR I483 TRUE PCIE_E_R2D_C_N_F 6 34 I461 PP5V_S0 7 70 I686 TRUE SMBUS_MCP_0_DATA 12 20 42 68
x6 I648 TRUE PP18V5_DCIN 49 70 I484 TRUE PCIE_E_R2D_C_P_F 6 34 I466

PP3V3_S0 7 70 I688 TRUE SMBUS_MCP_0_CLK 12 20 42 68
I650 TRUE ADAPTER_SENSE 49 I482 TRUE AIRPORT_RST_L 6 24 34 I463 PP3V3_S3 7 70 I689 TRUE XDP_TCK 9 12
65
x6 I706 TRUE GND I499 TRUE =SMB_AIRPORT_DATA 6 34 42 I462 PP5V_S3 7 70 I691 TRUE JTAG_MCP_TDO_CONN 12
I500 TRUE =SMB_AIRPORT_CLK 6 34 42 I467 PP3V3_S5 7 70 I690 TRUE JTAG_MCP_TRST_L 12 20

FUNC TEST - FAN CONNECTOR
I501 TRUE PCIE_E_R2D_C_N_F 6 34 I469 PP3V42_G3H 7 70 I692 TRUE MCP_DEBUG<7..0> 12 18 68
I668 TRUE =PP5V_S0_FAN 7 46
I502 TRUE PCIE_E_R2D_C_P_F 6 34 I474 PP18V5_G3H 7 70 I694 TRUE JTAG_MCP_TDI 12 20
I667 TRUE FAN_RT_PWM 46
I503 TRUE PP3V3_S3_AP_AUX 34 70 I473 PPDCIN_G3H 7 70 I695 TRUE JTAG_MCP_TMS 12 20
I669 TRUE FAN_RT_TACH 46
I472 PPBUS_G3H 7 70 I696 TRUE FSB_CLK_ITP_P 12 13 65
I714 TRUE GND
I471
PPBUS_R_G3H 7 70 I697 TRUE FSB_CLK_ITP_N 12 13 65
FUNC TEST - AIRPORT I757 PP1V8_S0 7 70 I698 TRUE XDP_CPURST_L 12 65
I741 TRUE CK505_SRC_CLKREQ6_L 6 I699 TRUE XDP_DBRESET_L 9 12

24
I742 TRUE PCIE_WAKE_L 6 16 34 I701 TRUE XDP_TDO_CONN 12
AIRPORT_RST_L FUNC TEST - SATA HDD XDP_TRST_L

I743 TRUE 6 24 34
PP3V3_S0_HDD_F I700 TRUE 9 12
I751 TRUE 36 70 65
I744 TRUE =SMB_AIRPORT_CLK 6 34 42 I702 TRUE XDP_TDI 9 12
I752 TRUE SATA_HDD_R2D_N 36 67 65
I745 TRUE =SMB_AIRPORT_DATA 6 34 42 I703 TRUE XDP_TMS 9 12
I753 TRUE SATA_HDD_R2D_P 36 67 65
I746 TRUE GND I704 TRUE =PP3V3_S0_XDP 7 12
I754 TRUE SATA_HDD_D2R_C_N 36 67
I705 TRUE =PP1V05_S0_CPU 7 9
I755 TRUE SATA_HDD_D2R_C_P 36 67 10 11 12
FUNC TEST - MIC GND
I756 TRUE
I747 TRUE PP3V3_S0_MIC_F 59 70
I748 TRUE AUD_MIC_DATA_F 59 FUNC TEST - RIO HATCH CONNECTOR

I749 TRUE AUD_MIC_CLK_F 59 I716 TRUE DP_ML_C_N<3..0> 61 67
I750 TRUE GND_MIC_F 59 I717 TRUE DP_ML_C_P<3..0> 61 67 FUNC TEST - CAMERA USB, LVDS, ALS
DP_AUX_CH_C_N PP5V_S3_CAMERA_F
C FUNC TEST - AUDIO CONNECTOR I718
I719
TRUE
TRUE DP_AUX_CH_C_P
35 60 61 67
35 60 61 67
x2 I654
I655
TRUE
TRUE USB2_CAMERA_F_P
59 70
59
C
I645 TRUE HDA_SYNC 20 35 68 I720 TRUE DP_CA_DET_Q 35 61 I656 TRUE USB2_CAMERA_F_N 59
I646 TRUE HDA_BIT_CLK 20 35 68 I721 TRUE HDMI_CEC 35 61 I657 TRUE LCDBKLT_RTN<1..6> 59 62
I735 TRUE AUD_MIC_DATA 35 59 I722 TRUE DP_HPD_Q 35 61 I658 TRUE LVDS_IG_A_DATA_N<0..2> 17 59 67
I736 TRUE HDA_SDOUT 20 35 68 I723 TRUE PP3V3_S0_DPPWR 35 61 70 I659 TRUE LVDS_IG_A_DATA_P<0..2> 17 59 67
I737 TRUE =PPVIN_S0_AUDIO 7 35 I725 TRUE USB2_EXTA_F_P 35 37 I660 TRUE PPVOUT_S0_LCDBKLT 59 62 70
I738 TRUE HDA_SDIN0 20 35 68 I726 TRUE USB2_EXTA_F_N 35 37 I661 TRUE LVDS_IG_A_CLK_F_N 59 67
I740 TRUE AUD_MIC_CLK 35 59 I727 TRUE PP5V_S3_USB2_EXTA_F 35 37 70 I662 TRUE LVDS_IG_A_CLK_F_P 59 67
I739 TRUE PM_SLP_S3_L 20 34 35 39 56 I728 TRUE GND I663 TRUE LVDS_IG_DDC_CLK 17 59
I664 TRUE LVDS_IG_DDC_DATA 17 59
I665 TRUE PP3V3_S0_LCD_F 59 70
x2 I666 TRUE PP3V3_LCDVDD_SW_F 59 70
I711 TRUE =I2C_ALS_SDA 42 59

FUNC TEST - IPD CONNECTOR =I2C_ALS_SCL
I712 TRUE 42 59
I507 TRUE SMC_LID 38 39 40
x10I713 TRUE GND
I506 TRUE PP3V42_G3H_IPD_F 38 70
I508 TRUE SMC_SYS_KBDLED 38 39
I509 TRUE SMC_SYS_LED 38 39
I510 TRUE =USB2_TPAD_N 8 38
I512 TRUE =USB2_TPAD_P 8 38
I511 TRUE SMC_ONOFF_L 6 38 39 40
I513 TRUE =USB2_IR_N 6 8 38
TRUE =USB2_IR_P
Power Supply NO_TESTs I514
I515 TRUE PP5V_S0_KBDLED_F

6 8 38
6 38 70
NO_TEST I517 TRUE PP5V_S3_TOPCASE_F 38 70
I516 TRUE =I2C_TPAD_SCL 38 42
B I518
I520
TRUE
TRUE
=I2C_TPAD_SDA
SMC_ONOFF_L
38 42
6 38 39 40
B
I519 TRUE =USB2_IR_N 6 8 38
I521 TRUE =USB2_IR_P 6 8 38
I676 TRUE PP5V_S0_KBDLED_F 6 38 70
I734 TRUE LSOC_PRESS_H_R 38
CLOCK NO_TESTS
NO_TEST TRUE
x13I522 GND
LVDS NO_TESTS REQUIRED NETS NICE2HAVE NETS

NO_TEST
Functional Test and No-Tests

A NOTICE OF PROPRIETARY PROPERTY
A
D 051-7631 2.3.0

NONE 6 71
8 7 6 5 4 3 2 . 1
8 7 6 5 4 3 2 1
"S0" RAILS "S3" RAILS "S5" RAILS "G3H" RAILS
50 =PPVCORE_S0_CPU_REG PPVCORE_S0_CPU 6 70 54 =PP0V75_S3_VTTREF PP0V75_S3 70 53 =PP1V05_S5_REG PP1V05_S5 6 70 49 24 =PP3V42_G3H_REG PP3V42_G3H 6 70

MIN_LINE_WIDTH=0.25 MM MIN_LINE_WIDTH=0.25 mm MIN_LINE_WIDTH=0.25 mm MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.20 MM MIN_NECK_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm
27 A VOLTAGE=0.9V
MAKE_BASE=TRUE
1.075 A VOLTAGE=0.75V
MAKE_BASE=TRUE
MAKE_BASE=TRUE
165 mA VOLTAGE=3.42V
MAKE_BASE=TRUE
=PPVCORE_S0_CPU 10 11 64 =PPVTT_S3_DDR_BUF 25 =PP1V05_S5_MCP_VDD_AUXC 21 22 =PP3V42_G3H_SMC 39 40
=PP1V05_S5_P1V05S0FET 57 =PP3V42_G3H_SMCVREF 40
D 51 =PPMCPCORE_S0_REG PPMCPCORE_S0
MIN_LINE_WIDTH=0.25 MM
6 70
54 =PP1V5_S3_REG PP1V5_S3 6 70
=PP1V05_RMGT_P1V05RMGTFET 57 =PP3V42_G3H_SMBUS_SMC_BSA
=PP3V42_G3H_IPD
42
38
D
MIN_NECK_WIDTH=0.20 MM MIN_LINE_WIDTH=0.6 mm
MAKE_BASE=TRUE 12.984 A MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.8V
=PP3V42_G3H_SMCUSBMUX 37
MAKE_BASE=TRUE =PP3V42_G3H_CHGR 58
=PPVCORE_S0_MCP 21 22 55 =PP3V3_S5_REG PP3V3_S5 6 70
=PP1V5_S3_MEM_A 27 28 31 33 MIN_LINE_WIDTH=0.6 mm =PP3V42_G3H_LPCPLUS 41
=PPVCORE_S0_MCP_VSENSE 43 MIN_NECK_WIDTH=0.2 mm
=PP1V5_S3_MEM_B VOLTAGE=3.3V
=PP1V5_S3_P1V5S0FET
29 30 32 33
57
4.011 A MAKE_BASE=TRUE
=PP3V3_S5_AIRPORT_AUX 34
54 =PP0V75_S0_REG PP0V75_S0 6 70 =PP1V5_S3_MEMRESET 26
MIN_LINE_WIDTH=0.25 mm =PP3V3_S5_LCD 59
MIN_NECK_WIDTH=0.2 mm
MAKE_BASE=TRUE 57 =PP3V3_S3_FET PP3V3_S3 6 70
=PP3V3_S5_MCP 21 22
MIN_LINE_WIDTH=0.25 mm =PP3V3_S5_MCPPWRGD 24 58 49 =PP18V5_G3H_CHGR PP18V5_G3H 6 70

=PPVTT_S0_VTTCLAMP 57 MIN_NECK_WIDTH=0.2 mm MIN_LINE_WIDTH=0.3 MM
VOLTAGE=3.3V =PP3V3_S5_MCP_GPIO 17 19 20 MIN_NECK_WIDTH=0.2 MM
=PP0V75_S0_MEM_VTT_A 33 315 mA MAKE_BASE=TRUE =PP3V3_S5_P1V05FET 57
VOLTAGE=18.5V
MAKE_BASE=TRUE
=PP0V75_S0_MEM_VTT_B 33 =PP3V3_S3_BT 34
=PP3V3_S5_P3V3S0FET 57
=PP3V3_S3_SMBUS_SMC_A_S3 42
=PP3V3_S5_P3V3S3FET 57
57 =PP1V05_S0_FET PP1V05_S0 6 70 =PP3V3_S3_SMC 40 49 =PPDCIN_G3H PPDCIN_G3H 6 70
MIN_LINE_WIDTH=0.2 mm =PP3V3_S5_PWRCTL 56 MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2 mm =PP3V3_S3_SMS MIN_NECK_WIDTH=0.25MM
MAKE_BASE=TRUE =PP3V3_S3_VREFMRGN
47
25
=PP3V3_S5_ROM 41 48 VOLTAGE=18.5V
MAKE_BASE=TRUE
=PP3V3_S5_SMBUS_MCP_1 42
=PP1V05_S0_CPU 6 9 10 11 12 =PP3V3_S3_SMBUS_SMC_MGMT 42 =PPVIN_G3H_P3V42G3H 49
=PP3V3_S5_MEMRESET 26
=PP1V05_S0_MCP_AVDD_UF 22 =PP3V3_S3_DDRREG 54
=PP3V3_S5_P3V3RMGTFET 57
=PP1V05_S0_MCP_FSB 8 13 21 22 =PP3V3_S3_MCPREG 51
=PP3V3_S5_P1V05RMGTFET 57 58 44 =PPBUSA_G3H PPBUS_R_G3H 6 70
=PP1V05_S0_MCP_HDMI_VDD 17 23 =PP3V3_S3_MCP_GPIO 20 MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
=PP1V05_S0_MCP_PEX_DVDD 7 22 13 A VOLTAGE=12.6V
MAKE_BASE=TRUE
=PP1V05_S0_MCP_PLL_UF 22
=PPVIN_S5_CPU_IMVP 50
=PP1V05_S0_MCP_SATA_DVDD 19 22
=PPVIN_S5_1V5S30V75S0 54
=PP1V05_S0_SMC_LS 40
=PPVIN_S0_MCPCORES0 51
=PP1V05_S0_VMON 56
=PPVIN_S5_1V05 53
55 =PP5V_S3_REG PP5V_S3 6 70
C 3.134 A
MIN_LINE_WIDTH=0.6 mm
VOLTAGE=5V
MAKE_BASE=TRUE
C
57 =PP1V5_S0_FET PP1V5_S0 6 70 =PP5V_S3_CAMERA 59
MIN_NECK_WIDTH=0.2 mm =PP5V_S3_MCPDDRFET 57 58 44 =PPBUSB_G3H PPBUS_G3H 6 70
VOLTAGE=1.5V MIN_LINE_WIDTH=0.4 mm
5.027 A MAKE_BASE=TRUE =PP5V_S3_P1V05S0FET 57
6.207 A MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V
=PP1V5_S0_CPU 10 11 =PP5V_S3_TOPCASE 38 MAKE_BASE=TRUE
=PP1V5_S0_VMON 56 =PP5V_S3_VTTCLAMP 57 =PPVIN_S3_5VS3 55
=PP1V8R1V5_S0_MCP_MEM 15 22 66 =PP5V_S3_1V5S30V75S0 54 =PPVIN_S5_3V3S5 55
=PP5V_S3_EXTUSB 37 =PPVIN_S0_AUDIO 6 35
=PP5V_S3_P5VS0FET 57 =PPVIN_G3H_DCIN 49
=PP5V_S3_MCPREG 51 =PPBUS_S0_LCDBKLT 63
52 =PP1V8_S0_REG PP1V8_S0 6 70
MIN_LINE_WIDTH=0.25 mm =PPBUS_G3HRS5 43
VOLTAGE=1.8V
19 mA MAKE_BASE=TRUE
=PP3V3R1V8_S0_MCP_IFP_VDD 17 23 "RMGT" RAILS
57 =PP3V3_S0_FET PP3V3_S0 6 70 57 =PP3V3_RMGT_FET PP3V3_RMGT 70

MIN_LINE_WIDTH=0.2 mm MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V VOLTAGE=3.3V
MAKE_BASE=TRUE MAKE_BASE=TRUE
2.046 A =PP3V3_S0_DPCONN 61 =PP3V3_ENET_MCP_RMGT 17 22
=PP3V3_S0_FAN 46
=PP3V3_S0_IMVP 50 57 =PP1V05_RMGT_FET PP1V05_RMGT 70

=PP3V3_S0_LCD 59 MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
=PP3V3_S0_LCDBKLT 62 MAKE_BASE=TRUE
=PP3V3_S0_MCP 20 21 22 =PP1V05_ENET_MCP_RMGT 17 22
=PP3V3_S0_MCP_GPIO 17 18 20
B =PP3V3_S0_MCP_PLL_UF 22
=PP1V05_ENET_MCP_PLL_MAC 22
B
=PP3V3_S0_MCP_VPLL_UF 23
=PP3V3_S0_PWRCTL 24 56
=PP3V3_S0_SMBUS_SMC_0_S0 42
=PP3V3_S0_THRM_SNR 45
=PP3V3_S0_VMON 56
=PP3V3_S0_XDP 6 12
=PPVIN_S0_P1V8S0 52
=PP3V3_S0_LPCPLUS 41
=PP3V3_S0_HDD 36
=PP3V3_S0_SMBUS_SMC_B_S0 42
=PP3V3_S0_SMBUS_MCP_0 42
=PP3V3R1V5_S0_MCP_HDA 20 22
=PP3V3_S0_SMC_LS 40
=PP3V3_S0_MIC 59
PEX & SATA AVDD/DVDD aliases

=PP1V05_S0_MCP_PEX_AVDD0 16
206 mA (A01)
Power Aliases
70 22 PP1V05_S0_MCP_PEX_AVDD =PP1V05_S0_MCP_PEX_AVDD1 16
A 57 =PP5V_S0_FET PP5V_S0
6 70
MAKE_BASE=TRUE
206 mA (A01)
=PP1V05_S0_MCP_PEX_DVDD0 16
SYNC_MASTER=WFERRY

A
VOLTAGE=5V 57 mA (A01)
562 mA MAKE_BASE=TRUE 22 7 =PP1V05_S0_MCP_PEX_DVDD =PP1V05_S0_MCP_PEX_DVDD1 16
=PP5V_S0_CPU_IMVP 50 57 mA (A01) PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
=PP5V_S0_DP_AUX_MUX 60
=PP5V_S0_FAN 6 46
=PP5V_S0_KBDLED 38
=PP5V_S0_LPCPLUS 41
D 051-7631 2.3.0

NONE 7 71
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PCI-E ALIASES CPU FSB FREQUENCY STRAPS
EMI SPRING CLIPS UNUSED GPU LANES
DACS ALIASES BSEL<2..0> FSB MHZ
UNUSED CRT & TV-OUT INTERFACE
PLACE CLIPS PER MCO ON TOPSIDE NEAR BATTERY CONNECTOR J6900 16 =PEG_D2R_N<15:0> NC_PEG_D2R_N<15:0> 0 0 0 266
NO_TEST=TRUE MAKE_BASE=TRUE 17 MCP_TV_DAC_RSET NC_MCP_TV_DAC_RSET 0 0 1 133
NO_TEST=TRUE MAKE_BASE=TRUE 65 9 IN CPU_BSEL<0:2> =MCP_BSEL<0:2>
OUT 13 0 1 0 200
CRITICAL 16 =PEG_D2R_P<15:0> NC_PEG_D2R_P<15:0> MAKE_BASE=TRUE 0 1 1 (166)
NO_TEST=TRUE MAKE_BASE=TRUE MCP_TV_DAC_VREF NC_MCP_TV_DAC_VREF 1 0 0 333
1 SC0900
EMI-SPRING 16 =PEG_R2D_C_N<15:0> NC_PEG_R2D_C_N<15:0>
17
NO_TEST=TRUE MAKE_BASE=TRUE 1
1
0
1
1
0
100
(400)
PS-25N NO_TEST=TRUE MAKE_BASE=TRUE 17 MCP_CLK27M_XTALIN NC_MCP_CLK27M_XTALIN 1 1 1 (RSVD)
NO_TEST=TRUE MAKE_BASE=TRUE
16 =PEG_R2D_C_P<15:0> NC_PEG_R2D_C_P<15:0>
16 PEG_PRSNT_L
NO_TEST=TRUE
TP_PEG_PRSNT_L
MAKE_BASE=TRUE 17 MCP_CLK27M_XTALOUT
CRT_IG_R_C_PR
NC_MCP_CLK27M_XTALOUT
NO_TEST=TRUE
NC_CRT_IG_R_C_PR
MAKE_BASE=TRUE Extra FSB Pull-ups
MAKE_BASE=TRUE 17
NO_TEST=TRUE MAKE_BASE=TRUE Exist in MRB but not Intel designs. Here for CYA.
16 PEG_CLKREQ_L TP_PEG_CLKREQ_L
D 67 16 PEG_CLK100M_P TP_PEG_CLK100M_P
MAKE_BASE=TRUE 17 CRT_IG_G_Y_Y NC_CRT_IG_G_Y_Y
If found to be necessary, will move to page14.csa
D
MAKE_BASE=TRUE 17 CRT_IG_B_COMP_PB NC_CRT_IG_B_COMP_PB
NO_TEST=TRUE MAKE_BASE=TRUE 22 21 13 7 =PP1V05_S0_MCP_FSB
67 16 PEG_CLK100M_N TP_PEG_CLK100M_N
MAKE_BASE=TRUE 17 CRT_IG_HSYNC NC_CRT_IG_HSYNC
16 EXTGPU_PWR_EN TP_EXTGPU_PWR_EN NO STUFF NO STUFF NO STUFF
MAKE_BASE=TRUE 17 CRT_IG_VSYNC NC_CRT_IG_VSYNC
BOSSES 16 EXTGPU_RESET_L TP_EXTGPU_RESET_L NO_TEST=TRUE MAKE_BASE=TRUE R0995 1 R0997 1 R0999 1
Z0900 STANDOFFS MAKE_BASE=TRUE 220
5%
200
5%
150
5%
1/20W 1/20W 1/20W
4.5OD2.0H-M1.6X0.35 Z0910
1 STDOFF-4.0OD2.4H-0.5-THNP AIRPORT CARD AND TURBOMEM PRESENT SIGNAL LVDS ALIASES MF
201
2
MF
201
2
MF
201
2
UNUSED LVDS SIGNALS
1 NO STUFF NO STUFF
PCIE_MINI_PRSNT_L 67 17 LVDS_IG_A_DATA_P<3> NC_LVDS_IG_A_DATA_P3 1 1
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE R0996 R0998
Z0901 PCIE_FC_PRSNT_L LVDS_IG_A_DATA_N<3> NC_LVDS_IG_A_DATA_N3 62 150
4.5OD2.0H-M1.6X0.35 67 17
NO_TEST=TRUE MAKE_BASE=TRUE 5% 5%
1
Z0911 LVDS_IG_B_CLK_P NC_LVDS_IG_B_CLK_P 1/20W
MF
1/20W
MF
STDOFF-4.0OD2.4H-0.5-THNP 67 17
NO_TEST=TRUE MAKE_BASE=TRUE 2 201 2 201
1 67 17 LVDS_IG_B_CLK_N NC_LVDS_IG_B_CLK_N
NO_TEST=TRUE MAKE_BASE=TRUE CPU_DPRSTP_L
Z0902 LVDS_IG_B_DATA_P<3:0> NC_LVDS_IG_B_DATA_P<3:0>
65 50 13 9 OUT
FSB_BREQ0_L
4.5OD2.0H-M1.6X0.35 67 17
65 13 9 OUT
1
Z0912
HDA PULL-DOWN
UNUSED IPHS SIGNAL(FOR IPHONE JACK)
67 17 LVDS_IG_B_DATA_N<3:0> NC_LVDS_IG_B_DATA_N<3:0>
65 13 12 9
65 13 9
OUT
OUT
FSB_CPURST_L
CPU_INTR
STDOFF-4.0OD2.4H-0.5-THNP 65 13 9 OUT CPU_NMI
AUD_IPHS_SWITCH_EN
Z0903 1
18
4.5OD2.0H-M1.6X0.35 AUD_I2C_INT_L IS PU ON MCP PAGE 1

1 R0920
100K
5%
1/20W
MF
MISC NC MCP79 ALIASES MEM ALIASES
Z0904 2 201
4.5OD2.0H-M1.6X0.35 NO_TEST
13 CPU_PECI_MCP TP_CPU_PECI_MCP
C 1
DP HOTPLUG PULL-DOWN 18
20
FW_PME_L
ODD_PWR_EN_L
TP_FW_PME_L MAKE_BASE=TRUE
MAKE_BASE=TRUE
TP_ODD_PWR_EN_L
15
15
TP_MEM_A_CLK4P
TP_MEM_A_CLK4N
NC_MEM_A_CLK4P
NC_MEM_A_CLK4N
TRUE
TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
C
MAKE_BASE=TRUE 15 TP_MEM_A_CLK3P NC_MEM_A_CLK3P TRUE
MAKE_BASE=TRUE
HPLUG_DET2 17 =DVI_HPD_GMUX_INT 15 TP_MEM_A_CLK3N NC_MEM_A_CLK3N TRUE
1 15 TP_MEM_A_CS_L<2> NC_MEM_A_CS_L<2> TRUE
SMC ALIASES R0940 15 TP_MEM_A_CS_L<3> NC_MEM_A_CS_L<3> TRUE
MAKE_BASE=TRUE
20K
NO-CONNECT UNUSED SMC INTERFACE PORTS 5%
1/20W
SATA ALIASES 15 TP_MEM_A_CKE<2> NC_MEM_A_CKE<2> TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST MF UNUSED SATA ODD SIGNALS 15 TP_MEM_A_CKE<3> NC_MEM_A_CKE<3> TRUE
39 SMC_PA0 NC_SMC_PA0 TRUE 2 201 15 TP_MEM_B_CLK4P NC_MEM_B_CLK4P TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE 19 SATA_ODD_R2D_C_P TP_SATA_ODD_R2D_C_P MAKE_BASE=TRUE

39 SMC_PA1 NC_SMC_PA1 TRUE MAKE_BASE=TRUE 15 TP_MEM_B_CLK4N NC_MEM_B_CLK4N TRUE
MAKE_BASE=TRUE 19 SATA_ODD_R2D_C_N TP_SATA_ODD_R2D_C_N MAKE_BASE=TRUE
39 ESTARLDO_EN NC_ESTARLDO_EN TRUE MAKE_BASE=TRUE 15 TP_MEM_B_CLK3P NC_MEM_B_CLK3P TRUE
MAKE_BASE=TRUE 19 SATA_ODD_D2R_P TP_SATA_ODD_D2R_P MAKE_BASE=TRUE
39 SMC_P26 NC_SMC_P26 TRUE MAKE_BASE=TRUE 15 TP_MEM_B_CLK3N NC_MEM_B_CLK3N TRUE
MAKE_BASE=TRUE 19 SATA_ODD_D2R_N TP_SATA_ODD_D2R_N MAKE_BASE=TRUE
39 SMC_P41 NC_SMC_P41 TRUE MAKE_BASE=TRUE 15 TP_MEM_B_CS_L<2> NC_MEM_B_CS_L<2> TRUE
39 SMC_BIL_BUTTON_L NC_SMC_P67 TRUE 15 TP_MEM_B_CS_L<3> NC_MEM_B_CS_L<3> TRUE
39 SMC_GFX_OVERTEMP_L NC_SMC_GFX_OVERTEMP_L TRUE LAN ALIASES 15 TP_MEM_B_ODT<2> NC_MEM_B_ODT<2> TRUE
39 SMC_EXCARD_OC_L NC_EXCARD_OC_L TRUE 15 TP_MEM_B_ODT<3> NC_MEM_B_ODT<3> TRUE
MAKE_BASE=TRUE UNUSED ETHERNET RG/MII INTERFACE MAKE_BASE=TRUE
39 SMC_P24 NC_SMC_P24 TRUE 15 TP_MEM_B_CKE<2> NC_MEM_B_CKE<2> TRUE
39 SMC_EXCARD_CP NC_SMC_EXCARD_CP TRUE 15 TP_MEM_B_CKE<3> NC_MEM_B_CKE<3> TRUE
MAKE_BASE=TRUE 17 ENET_RXD<0> 17 ENET_MDIO 17 ENET_CLK125M_RXCLK MAKE_BASE=TRUE
39 ALS_RIGHT NC_ALS_RIGHT TRUE
39 ALS_GAIN NC_ALS_GAIN MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
17 ENET_RXD<1> 17 ENET_RX_CTRL 17 ENET_INTR_L USB ALIASES
39 SMC_FAN_1_CTL NC_SMC_FAN_1_CTL TRUE UNUSED USB PORTS
MAKE_BASE=TRUE 17 ENET_RXD<2> 17 ENET_CLK125M_TXCLK
39 SMC_FAN_2_CTL NC_SMC_FAN_2_CTL TRUE
MAKE_BASE=TRUE 68 19 USB_EXTB_P TP_USB_EXTB_P
39 SMC_FAN_3_CTL NC_SMC_FAN_3_CTL TRUE 17 ENET_RXD<3> 17 MCP_MII_VREF MAKE_BASE=TRUE
MAKE_BASE=TRUE 68 19 USB_EXTB_N TP_USB_EXTB_N
39 SMC_FAN_1_TACH NC_SMC_FAN_1_TACH TRUE MAKE_BASE=TRUE
MAKE_BASE=TRUE 68 USB_EXTC_P TP_USB_EXTC_P
39 SMC_FAN_2_TACH NC_SMC_FAN_2_TACH TRUE 8 7 6 5 8 7 6 5 8 7 6 5 MAKE_BASE=TRUE
MAKE_BASE=TRUE 68 USB_EXTC_N TP_USB_EXTC_N
SMC_FAN_3_TACH NC_SMC_FAN_3_TACH TRUE MAKE_BASE=TRUE
39
SMC_EXCARD_PWR_EN NC_SMC_RSTGATE_L MAKE_BASE=TRUE

TRUE
RP0930 RP0931 RP0932 68 19 USB_EXTD_P TP_USB_EXTD_P
39
10K 10K 10K MAKE_BASE=TRUE
B 39 ISENSE_CAL_EN NC_ISENSE_CAL_EN MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
5%
1/32W
5%
1/32W
5%
1/32W
68 19
68
USB_EXTD_N
USB_EXCARD_P
TP_USB_EXTD_N
TP_USB_EXCARD_P MAKE_BASE=TRUE B
39 SMC_FWE NC_SMC_FWE TRUE 4X0201-HF 4X0201-HF 4X0201-HF MAKE_BASE=TRUE
MAKE_BASE=TRUE 68 USB_EXCARD_N TP_USB_EXCARD_N
39 SMC_ANALOG_ID NC_SMC_ANALOG_ID TRUE 1 2 3 4 1 2 3 4 1 2 3 4 MAKE_BASE=TRUE
MAKE_BASE=TRUE 68 19 USB_MINI_P TP_USB_MINI_P
39 ALS_LEFT NC_ALS_LEFT TRUE MAKE_BASE=TRUE
USB_MINI_N TP_USB_MINI_N
39 SMC_NB_DDR_ISENSE NC_SMC_NB_DDR_ISENSEMAKE_BASE=TRUE
TRUE
68 19
MAKE_BASE=TRUE
MAKE_BASE=TRUE
39 SMC_P10 NC_SMC_P10 TRUE EXTERNAL PORT A
MAKE_BASE=TRUE
39 SMC_PA5 NC_SMC_PA5 TRUE 37 =USB2_EXTA_P USB_EXTA_P 19 68
39 SMC_GPU_ISENSE NC_SMC_GPU_ISENSE TRUE 37 =USB2_EXTA_N USB_EXTA_N 19 68
37 =EXTAUSB_OC_L USB_EXTA_OC_L 19
MAKE_BASE=TRUE
CAMERA
59 =USB2_CAMERA_P USB_CAMERA_P 19 68
MAKE_BASE=TRUE
59 =USB2_CAMERA_N USB_CAMERA_N 19 68
17 ENET_RESET_L NC_ENET_RESET_L MAKE_BASE=TRUE
MAKE_BASE=TRUE
17 MCP_CLK25M_BUF0_R NC_MCP_CLK25M_BUF0_R
MAKE_BASE=TRUE TRACKPAD(WELLSPRING)
17 ENET_PWRDWN_L NC_ENET_PWRDWN_L
MAKE_BASE=TRUE 38 6 =USB2_TPAD_P USB_TPAD_P 19 68
17 ENET_MDC NC_ENET_MDC MAKE_BASE=TRUE
MAKE_BASE=TRUE 38 6 =USB2_TPAD_N USB_TPAD_N 19 68
17 ENET_TX_CTRL NC_ENEX_TX_CTRL MAKE_BASE=TRUE
MAKE_BASE=TRUE IR
17 ENET_TXD<3..0> NC_ENET_TXD<3..0>
MAKE_BASE=TRUE 38 6 =USB2_IR_P USB_IR_P 19 68
MAKE_BASE=TRUE
38 6 =USB2_IR_N USB_IR_N 19 68
MAKE_BASE=TRUE
BT (M93)
34 =USB2_BT_P USB_BT_P 19 68
MAKE_BASE=TRUE
34 =USB2_BT_N USB_BT_N 19 68
MAKE_BASE=TRUE
SIGNAL ALIAS /RESET

A SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)
A
GND
20 SMC_IG_THROTTLE_L SMC_GFX_THROTTLE_L 39 VOLTAGE=0V SIZE DRAWING NUMBER REV.
MAKE_BASE=TRUE MIN_NECK_WIDTH=0.20 MM
40 SMC_SMS_INT_L
MAKE_BASE=TRUE
=SMC_SMS_INT 39
D 051-7631 2.3.0

40 39 20 SMC_ADAPTER_EN SMC_ADAPTER_PRESENT 34
8 71
MAKE_BASE=TRUE NONE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT
FSB_A_L<3> FSB_ADS_L
65 13 BI
FSB_A_L<4>
P2
V4
A3*
A4*
U1000 ADS*
BNR*
M4
J5 FSB_BNR_L
BI 13 65
65 13 BI BGA BI 13 65
65 13 BI FSB_A_L<5> W1 A5* (1 OF 8) BPRI* L5 FSB_BPRI_L BI 13 65

=PP1V05_S0_CPU 6 7 10 11 12
PDC-Q9YM-ES1-1.86-17W-1066-CO-6M
PENRYN-SFF
65 13 BI FSB_A_L<6> T4 A6*
65 13 BI FSB_A_L<7> AA1 A7* DEFER* N5 FSB_DEFER_L BI 13 65
65 13 BI FSB_A_L<8> AB4 A8* DRDY* F38 FSB_DRDY_L BI 13 65

1
65 13 FSB_A_L<9> T2 A9* DBSY* J1 FSB_DBSY_L 13 65
R1000
BI BI
54.9
65 13 BI FSB_A_L<10> AC5 A10* 1%
1/20W
65 13 BI FSB_A_L<11> AD2 A11* BR0* M2 FSB_BREQ0_L BI 8 13 65 MF
201
FSB_A_L<12> AD4 A12* 2
65 13 BI
D 65 13
65 13
BI
BI
FSB_A_L<13>
FSB_A_L<14>
AA5
AE5
A13*
A14*
IERR*
INIT*
B40
D8
65 CPU_IERR_L
CPU_INIT_L IN 13 65
D
65 13 BI FSB_A_L<15> AB2 A15*
65 13 BI FSB_A_L<16> AC1 A16* LOCK* N1 FSB_LOCK_L BI 13 65
65 13 BI FSB_ADSTB_L<0> Y4 ADSTB0*
ADDR GROUP0
RESET* G5 FSB_CPURST_L IN 8 12 13 65
65 13 FSB_REQ_L<0> R1 REQ0* RS0* K2 FSB_RS_L<0> 13 65
CONTROL
BI IN
65 13 BI FSB_REQ_L<1> R5 REQ1* RS1* H4 FSB_RS_L<1> IN 13 65
65 13 BI FSB_REQ_L<2> U1 REQ2* RS2* K4 FSB_RS_L<2> IN 13 65
65 13 BI FSB_REQ_L<3> P4 REQ3* TRDY* L1 FSB_TRDY_L IN 13 65
65 13 BI FSB_REQ_L<4> W5 REQ4*
HIT* H2 FSB_HIT_L BI 13 65
65 13 BI FSB_A_L<17> AN1 A17* HITM* F2 FSB_HITM_L BI 13 65

OMIT
65 13 BI FSB_A_L<18>
FSB_A_L<19>
AK4 A18*
XDP_BPM_L<0>
65 13 BI FSB_D_L<0>
FSB_D_L<1>
D0* U1000 D32* FSB_D_L<32>
FSB_D_L<33>
BI 13 65
65 13 BI AG1 A19* BPM0* AY8 BI 6 12 65 65 13 BI D1* BGA D33* BI 13 65
XDP/ITP SIGNALS
65 13 FSB_A_L<20> AT4 A20* BPM1* BA7 XDP_BPM_L<1> 6 12 65
R1001 1 65 13 FSB_D_L<2> D2* (2 OF 8) D34* FSB_D_L<34> 13 65
BI BI 54.9 BI BI
PENRYN-SFF
PDC-Q9YM-ES1-1.86-17W-1066-CO-6M
FSB_A_L<21> AK2 A21* BPM2* BA5 XDP_BPM_L<2> FSB_D_L<3> D3* D35* FSB_D_L<35>
ADDR GROUP1
65 13 BI BI 6 12 65 1% 65 13 BI BI 13 65
1/20W
65 13 BI FSB_A_L<22> AT2 A22* BPM3* AY2 XDP_BPM_L<3> BI 6 12 65 MF 65 13 BI FSB_D_L<4> D4* D36* FSB_D_L<36> BI 13 65
201
FSB_A_L<23> AH2 AV10 XDP_BPM_L<4> 2 FSB_D_L<5> FSB_D_L<37>
65 13 BI A23* PRDY* BI 6 12 65 65 13 BI D5* D37* BI 13 65
65 13 BI FSB_A_L<24> AF4 A24* PREQ* AV2 XDP_BPM_L<5> BI 6 12 65 65 13 BI FSB_D_L<6> D6* D38* FSB_D_L<38> BI 13 65
65 13 BI FSB_A_L<25> AJ5 A25* TCK AV4 XDP_TCK IN 6 9 12 65 65 13 BI FSB_D_L<7> D7* D39* FSB_D_L<39> BI 13 65
65 13 BI FSB_A_L<26> AH4 A26* TDI AW7 XDP_TDI IN 6 9 12 65 65 13 BI FSB_D_L<8> D8* D40* FSB_D_L<40> BI 13 65
65 13 BI FSB_A_L<27> AM4 A27* TDO AU1 XDP_TDO OUT 9 12 65 65 13 BI FSB_D_L<9> D9* D41* FSB_D_L<41> BI 13 65
65 13 BI FSB_A_L<28> AP4 A28* TMS AW5 XDP_TMS IN 6 9 12 65 65 13 BI FSB_D_L<10> D10* D42* FSB_D_L<42> BI 13 65
65 13 BI FSB_A_L<29> AR5 A29* TRST* AV8 XDP_TRST_L IN 6 9 12 65 65 13 BI FSB_D_L<11> D11* D43* FSB_D_L<43> BI 13 65
65 13 BI FSB_A_L<30> AJ1 A30* 65 13 BI FSB_D_L<12> D12* D44* FSB_D_L<44> BI 13 65
C 65 13
65 13
BI FSB_A_L<31>
FSB_A_L<32>
AL1
AM2
A31*
A32*
R1002 1
5%
68
65 13
65 13
BI FSB_D_L<13>
FSB_D_L<14>
D13*
D14*
D45*
D46*
FSB_D_L<45>
FSB_D_L<46>
BI 13 65
13 65
C
BI THERMAL BI BI
DATA GRP 0
DATA GRP 2
1/20W
65 13 BI FSB_A_L<33> AU5 A33* MF 65 13 BI FSB_D_L<15> D15* D47* FSB_D_L<47> BI 13 65
201
FSB_A_L<34> AP2 2 FSB_DSTB_L_N<0> FSB_DSTB_L_N<2>
65 13 BI A34* 65 13 BI DSTBN0* DSTBN2* BI 13 65
65 13 BI FSB_A_L<35> AR1 A35* PROCHOT* D38 CPU_PROCHOT_L OUT 13 40 50 65 65 13 BI FSB_DSTB_L_P<0> DSTBP0* DSTBP2* FSB_DSTB_L_P<2> BI 13 65
65 13 BI FSB_ADSTB_L<1> AN5 ADSTB1* THRMDA BB34 CPU_THERMD_P OUT 45 65 13 BI FSB_DINV_L<0> DINV0* DINV2* FSB_DINV_L<2> BI 13 65
THRMDC BD34 CPU_THERMD_N OUT 45
65 13 IN CPU_A20M_L C7 A20M*
DATA GRP 3
OUT CPU_FERR_L D4 FERR* THERMTRIP* B10 PM_THRMTRIP_L FSB_D_L<16> D16* D48* FSB_D_L<48>
DATA GRP1
65 13 OUT 13 40 65 65 13 BI BI 13 65
65 13 IN CPU_IGNNE_L F10 IGNNE* 65 13 BI FSB_D_L<17> D17* D49* FSB_D_L<49> BI 13 65
ICH 65 13 BI FSB_D_L<18> D18* D50* FSB_D_L<50> BI 13 65
65 13 CPU_STPCLK_L F8 STPCLK* H CLK 65 13 FSB_D_L<19> D19* D51* FSB_D_L<51> 13 65

IN BI BI
65 13 8 IN CPU_INTR C9 LINT0 65 13 BI FSB_D_L<20> D20* D52* FSB_D_L<52> BI 13 65
65 13 8 IN CPU_NMI C5 LINT1 BCLK0 A35 FSB_CLK_CPU_P IN 13 65 65 13 BI FSB_D_L<21> D21* D53* FSB_D_L<53> BI 13 65
65 13 IN CPU_SMI_L E5 SMI* BCLK1 C35 FSB_CLK_CPU_N IN 13 65 65 13 BI FSB_D_L<22> D22* D54* FSB_D_L<54> BI 13 65
65 13 BI FSB_D_L<23> D23* D55* FSB_D_L<55> BI 13 65

24 12 6 OUT XDP_DBRESET_L J7 DBR*
RSVD7 J9 NC_CPU_RSVD_J9
9 CPU_TEST1 E37 TEST1 RSVD9 F4 NC_CPU_RSVD_F4
9 CPU_TEST2 D40 TEST2 RSVD10 H8 NC_CPU_RSVD_H8
TP_CPU_TEST3 C43 TEST3 RSVD11 V2 NC_CPU_RSVD_V2
9 CPU_TEST4 AE41 TEST4 RSVD12 Y2 NC_CPU_RSVD_Y2
TP_CPU_TEST5 AY10 TEST5 RSVD13 AG5 NC_CPU_RSVD_AG5 1
R1005 65 13 BI FSB_DSTB_L_N<1> DSTBN1* DSTBN3* FSB_DSTB_L_N<3> BI 13 65
TP_CPU_TEST6 AC43 TEST6 RSVD14 AL5 NC_CPU_RSVD_AL5 1K
1% 65 13 BI FSB_DSTB_L_P<1> DSTBP1* DSTBP3* FSB_DSTB_L_P<3> BI 13 65
1/20W
B CPU JTAG Support R1090 2
MF
201
65 13 BI FSB_DINV_L<1> DINV1* DINV3* FSB_DINV_L<3> BI 13 65
B
54.9
65 12 9 6 XDP_TMS 1 2 65 25 CPU_GTLREF GTLREF COMP0 65 CPU_COMP<0>
1% CPU_TEST1 9 MISC COMP1 65 CPU_COMP<1>
1/20W
R1091 1 CPU_TEST2 9 COMP2 CPU_COMP<2>
54.9
MF
201 R1006 65
65 12 9 6 XDP_TDI 1 2 2K COMP3 65 CPU_COMP<3>

1%
1% 1/20W CPU_TEST4 9
1/20W
MF R1092 MF
NO STUFF DPRSTP* CPU_DPRSTP_L R1023 1 R1021 1
201 54.9 2 201 IN 8 13 50 65
65 12 9 XDP_TDO 1 2 C1014 1
DPSLP* CPU_DPSLP_L IN 13 65 54.9 54.9
1% 1%
PLACEMENT_NOTE=Place R1092 near ITP connector (if present) 1% NO STUFF 0.1uF DPWR* FSB_DPWR_L 13 65 1/20W 1/20W
1/20W 10% IN
16V MF MF
MF
201 R1010 X5R 2 65 8 OUT CPU_BSEL<0> BSEL0 PWRGOOD CPU_PWRGD IN 12 13 65 201
2
201
2
402
1
0
2
65 8 OUT CPU_BSEL<1> BSEL1 SLP* FSB_CPUSLP_L IN 13 65
65 8 OUT CPU_BSEL<2> BSEL2 PSI* TP_CPU_PSI_L 1 1

NO STUFF 5% NO STUFF R1022 R1020
1/20W
R1093 R1011 1 MF
201
1
R1012 27.4
1%
27.4
1%
54.9 1K 1K PLACEMENT_NOTE=Place C1014 within 12.7mm of CPU. 1/20W 1/20W
65 12 9 6 XDP_TCK 1 2 5% 5% MF MF
1/20W 1/20W PLACEMENT_NOTE=Place R1005 within 12.7mm of CPU. 2
201
2
201
1% MF MF
R1094 1/20W 201 2 2 201 PLACEMENT_NOTE=Place R1006 within 12.7mm of CPU.
MF
649 201
65 12 9 6 XDP_TRST_L 1 2 PLACEMENT_NOTE (all 4 resistors):
1%
1/20W Place within 12.7mm of CPU
MF
201
CPU FSB
A SYNC_MASTER=M97

A
SYNC FROM M97 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

D 051-7631 2.3.0

NONE 9 71
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
64 11 10 7 =PPVCORE_S0_CPU =PP1V05_S0_CPU 6 7 9 10 11 12
Y6 OMIT AJ3 B42 OMIT AP34 E21 AE17
OMIT
=PPVCORE_S0_CPU 7 10 11 64 BD30 OMIT K20
Y8
U1000 AG3 H42 U1000 AM34 E23
U1000 AE19
(CPU CORE POWER) 27A AE37 OMIT R13 AK6 BGA AE3 F42 BGA AV36 E25 BGA AR17
BB28 U1000 M16
AP38 U1000 P12 AK8 (6 OF 8) AR3 D42 (4 OF 8) AT36 N21 (5 OF 8) AR19
PENRYN-SFF
PDC-Q9YM-ES1-1.86-17W-1066-CO-6M
BB30 BGA M18
PDC-Q9YM-ES1-1.86-17W-1066-CO-6M
PENRYN-SFF
PENRYN-SFF
PDC-Q9YM-ES1-1.86-17W-1066-CO-6M
AN37 BGA P14 AH6 AN3 D44 AY34 N23 AN17
B24 (7 OF 8) K16 (8 OF 8)
PENRYN-SFF
PDC-Q9YM-ES1-1.86-17W-1066-CO-6M
H32 OMIT AD28 AL37 AB10 AH8 AL3 F44 AW33 N25 AN19
B22 K18
PENRYN-SFF
PDC-Q9YM-ES1-1.86-17W-1066-CO-6M
G33 U1000 AD30
H22 V20
C33 AD14 AF6 AW3 M42 AW35 L21 AL17
F32 BGA AB28 B32 AC11 AF8 AU3 K42 AV34 L23 AL19
H24 T20
N33 (3 OF 8) AB30 H36 AC13 AP6 BD4 V42 AU35 L25 AW17
F22 P20
PENRYN-SFF
PDC-Q9YM-ES1-1.86-17W-1066-CO-6M
M32 Y28 F36 AB12 AP8 BC3 T42 BD36 J21 AW19
F24 V16
L33 Y30 G35 AB14 AM6 BB2 P42 BB36 J23 AU17
D24 V18
D K32
J33
AK26
AH26
D22 T16
F34
E33
AA11
AA13
AM8
AY6
BA3
G1
AD42
AB42
BC33
BA33
J25
W21
AU19
BC17
D
M22 T18
W33 AF26 E35 Y14 AW9 E1 Y42 C31 W23 BC19
M24 P16
V32 AK28 D32 AK10 AU7 AW1 AK42 C29 W25 BA17
K22 P18
U33 AK30 K36 AF10 AV6 BA1 AH42 C27 U21 BA19
K24 AD20
T32 AH28 N35 AK12 AU9 A39 AF42 G31 U23 C15
V22 AB20
R33 AH30 L35 AK14 AT6 VSS VSS A41 AP42 E31 U25 C11
V24 Y20
P32 AF28 J35 AJ11 AT8 A31 AM42 G27 R21 H10
T22 AD16
AD32 AF30 W35 AJ13 BD6 A27 AY42 G29 R23 G15
T24 AD18
AC33 AP26 V36 AH14 BC9 A29 AV42 E27 R25 E15
P22 AB16
AB32 VCC AM26 P36 AG11 BB6 A21 AT42 E29 AC21 M10
P24 AB18
AA33 AP28 U35 AG13 BA9 A23 AV44 N31 AC23 N15
AD22 Y16
Y32 AP30 R35 AF12 C3 A25 AY44 L31 AC25 L15
AD24 Y18
AK32 AM28 AB36 AF14 B4 A17 BB42 J31 AA21 J15
AB22 AK20
AJ33 AM30 AC35 AE11 G3 A19 BA43 N27 AA23 M12
AB24 AK16
AH32 AY26 AA35 AE13 E3 A15 C39 N29 AA25 T10
Y22 AK18
AG33 AV26 AK36 AP10 D2 A11 H38 L27 AJ21 W15
Y24 AH20
AF32 AT26 AF36 AR11 N3 A9 G37 L29 AJ23 U15
AK22 AF20
AE33 AY28 AJ35 AR13 L3 A5 E39 J27 AJ25 R15
AK24 AH16
AR33 AY30 AG35 AP12 J3 A7 N39 J29 AG21 T12
AH22 VCC VCC AH18
AP32 AV28 AE35 AN11 W3 M38 W31 AG23 AD10
AH24 AF16 VCCP VCCP
AN33 AV30 AP36 AN13 U3 L39 W27 AG25 Y10
AF22 AF18
AM32 AT28 AN35 AL11 R3 J39 W29 AE21 AC15
AF24 AP20
AL33 AT30 AL35 AL13 AC3 W39 U31 AE23 AA15
AP22 AM20
AY32 BD26 C13 AU11 AA3 U39 R31 AE25 AD12
AP24 AP16
AV32 BB26 B14 AU13 T38 U27 AR21 Y12
VCC AM22 AP18
AU33 BD28 B12 N7 R39 U29 AR23 AH10
C AT32
AT34 N37
(CPU IO POWER 1.05V) 2.5A
=PP1V05_S0_CPU 6 7 9 10 11 12
AM24
AY22
AM16
AM18
H12
H14
N9
L7
AD38
AC39
R27
R29
AR25
AN21
AJ15
AG15
C
AY24 AY20 VSS VSS
BD32 L37 G11 L9 AA39 VSS VSS AC31 AN23 AE15
AV22 AV20
BB32 K38 G13 W7 Y38 AA31 AN25 AH12
AV24 AT20
B26 J37 F12 W9 AJ39 AC27 AL21 AM10
AT22 AY16
B30 W37 F14 U7 AH38 AC29 AL23 AR15
AT24 AY18
B28 V38 E11 U9 AG39 AA27 AL25 AN15
BD22 AV16
H26 U37 E13 R7 AE39 AA29 AW21 AL15
BD24 AV18
F26 VCCP R37 D14 R9 AR37 AJ31 AW23 AM12
BB22 AT16
D26 P38 D12 AC7 AR39 AG31 AW25 AT10
BB24 AT18
H28 AC37 K10 AC9 AN39 AE31 AU21 AW15
B20 BD20
H30 AB38 N11 AA7 AM38 AJ27 AU23 AU15
B18 BB20
F28 AA37 N13 AA9 AL39 AJ29 AU25 AY12
B16 BD16
F30 AK38 M14 AJ7 AW37 AG27 BC21 AW11
H20 BD18
D30 AJ37 L11 AJ9 AW39 AG29 BC23 AW13
F20 BB16
D28 AG37 L13 AG7 AU37 AE27 BC25 AV12
D20 BB18
M26 AF38 K12 AG9 AU39 AE29 BA21 AT12
H16 AP14
K26 (CPU INTERNAL PLL POWER 1.5V) 0.130A VCCA=1.5 ONLY K14 AE7 AT38 AR31 BA23 BC15
H18 AM14
M28 B34 =PP1V5_S0_CPU 7 11 J11 AE9 BD38 AR27 BA25 BA15
VCCA F16 AY14
M30 D34 J13 AR7 BD40 AR29 C19 BC11
F18 AV14
K28 V10 AR9 BC41 AN31 C17
D18 AT14
K30 BD8 CPU_VID<0> OUT 11 50 65 P10 AN7 BA39 AL31 G17 BB12
D16 BD14
V26 BC7 CPU_VID<1> OUT 11 50 65 W11 AN9 B36 AN27 G19 BA11
M20 BB14
T26 BB10 CPU_VID<2> OUT 11 50 65 W13 AL7 D36 AN29 E17 BA13
P26 VID BB8 CPU_VID<3> OUT 11 50 65 V12 AL9 H34 AL27 E19 B6
=PPVCORE_S0_CPU 7 10 11 64
V28 BC5 CPU_VID<4> OUT 11 50 65 V14 A33 M36 AL29 N17 H6
B V30
T28
BB4
AY4
CPU_VID<5>
CPU_VID<6>
OUT
OUT
11 50 65
11 50 65
1
U11
U13
A13 M34
K34
AW31
AU31
N19
L17
G9
F6
B
T30 R1100 T14 T36 AW27 L19 E9
100
P28 VCCSENSE BD12 1% R11 V34 AW29 J17 D6
1/20W
P30 MF T34 AU27 J19 M6
AD26 VSSSENSE BC13 2 201 P34 AU29 W17 M8
AB26 CPU_VCCSENSE_P OUT 50 65 AD36 BC31 W19 K6
Y26 Y36 BA31 U17 K8
CPU_VCCSENSE_N OUT 50 65 AD34 BC27 U19 U5
AB34 BC29 R17 V6
1 LAYOUT NOTE: Y34 BA27 R19 V8
R1101
100 PLACE R1100 AND R1101 AK34 BA29 AC17 T6
LAYOUT NOTE: 1% WITHIN 1 INCH OF CPU W/ NO STUB
1/20W AH36 C25 AC19 T8
MF
CPU_VCCSENSE_P/CPU_VCCSENSE_N USE 201 AH34 C23 AA17 P6
2
ZO=27.4 OHM DIFFERENTIAL TRACE ROUTING. AF34 C21 AA19 P8
AR35 G21 AJ17 AD6
AM36 G23 AJ19 AD8
G25 AG17 AB6
LAYOUT NOTE: AG19 AB8
PROVIDE A TEST POINT (WITH NO STUB)
TO CONNECT A DIFFERENTIAL PROBE
BETWEEN VCCSENSE AND VSSSENSE
CPU Power & Ground


SYNC_DATE=(MASTER)
A
D 051-7631 2.3.0

NONE 10 71
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CPU VCORE HF AND BULK DECOUPLING

3x 330uF. 32x 10uF 0603, 28x 2.2uF 0402 + 40x 2.2uF 0402
64 10 7 =PPVCORE_S0_CPU
D 10UF 0603 = APN:138S0568 = MURATA,TAIYO,TDK,SAMSUNG D

LAYOUT NOTE:
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
PLACE ON OPPOSITE SIDE OF CPU
C1200 C1201 C1202 C1203 C1204 C1205 C1206 C1207 C1208 C1209
10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF
20% OMIT 20% OMIT 20% OMIT 20% OMIT 20% OMIT 20% OMIT 20% OMIT 20% OMIT 20% OMIT 20% OMIT
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R
603 603 603 603 603 603 603 603 603 603
CPU VCORE VID CONNECTIONS

65 50 10 CPU_VID<0..6> IMVP6_VID<0..6> 65
MAKE_BASE=TRUE
LAYOUT NOTE:
PLACE ON OPPOSITE SIDE OF CPU C1210 C1211 C1212 C1213 C1214 C1215 C1216 C1217 C1218 C1219
20% OMIT 20% OMIT 20% OMIT 20% OMIT 20% OMIT 20% OMIT 20% OMIT 20% OMIT 20% OMIT 20% OMIT
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R
603 603 603 603 603 603 603 603 603 603
LAYOUT NOTE:
20% OMIT 20% OMIT 20% 20% OMIT 20% OMIT 20% OMIT 20% OMIT 20% OMIT 20% OMIT 20% OMIT
C 6.3V
X5R
603
6.3V
X5R
603
6.3V OMIT
X5R
603
6.3V
X5R
603
6.3V
X5R
603
6.3V
X5R
603
6.3V
X5R
603
6.3V
X5R
603
6.3V
X5R
603
6.3V
X5R
603
C
LAYOUT NOTE:
CRITICAL CRITICAL
PLACE ON OPPOSITE SIDE OF CPU C1230 C1231
10UF 10UF
20% OMIT 20% OMIT
6.3V 6.3V
X5R X5R
603 603
VCCA (CPU AVdd) DECOUPLING

LAYOUT NOTE: 10 7 =PP1V5_S0_CPU
1x 10uF, 1x 0.01uF
C1240 C1241 C1242 C1243 C1244 C1245 C1246 C1247 C1248 C1249
2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF C1280 1 1
C1281
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 10uF 0.01UF
CERM OMIT CERM OMIT CERM OMIT CERM OMIT CERM OMIT CERM OMIT CERM OMIT CERM OMIT CERM OMIT CERM OMIT 20% 10%
402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF OMIT
6.3V 10V LAYOUT NOTE:
X5R 2 2 X5R
603 201 PLACE C1281 NEAR PIN B34 OF U1000
B B
LAYOUT NOTE:
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL 12 10 9 7 6 =PP1V05_S0_CPU VCCP (CPU I/O) DECOUPLING
PLACE ON OPPOSITE SIDE OF CPU C1250 C1251 C1252 C1253 C1254 C1255 C1256 C1257 C1258 C1259 1X 330UF, 12X 2.2UF
2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
CERM OMIT CERM OMIT CERM OMIT CERM OMIT CERM OMIT CERM OMIT CERM OMIT CERM OMIT CERM OMIT CERM OMIT 1 C1283 1 C1284 1 C1285 1 C1286 1 C1287 1 C1288
402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF
2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF
20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V
2 CERM OMIT 2 CERM OMIT 2 CERM OMIT 2 CERM OMIT 2 CERM OMIT 2 6.3V
CERM OMIT
402-LF 402-LF 402-LF 402-LF 402-LF 402-LF
LAYOUT NOTE:
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
PLACE ON OPPOSITE SIDE OF CPU C1260 C1261 C1262 C1263 C1264 C1265 C1266 C1267 CRITICAL
2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF
20% 20% 20% 20% 20% 20% 20% 20%
6.3V OMIT 6.3V OMIT 6.3V OMIT 6.3V OMIT 6.3V OMIT 6.3V OMIT 6.3V OMIT 6.3V OMIT C1290 1 1 C1291 1 C1292 1 C1293 1 C1294 1 C1295 1 C1296
CERM CERM CERM CERM CERM CERM CERM CERM 330UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF
402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V
2.5V 2 2 CERM OMIT 2 CERM OMIT 2 CERM OMIT 2 CERM OMIT 2 CERM OMIT 2 6.3V
CERM OMIT
POLY-TANT
CASE-C2-SM 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF
LAYOUT NOTE:
PLACE C1290 CLOSE TO CPU
PLACE C1283-C1288 CLOSE TO FSB ADDRESS PINS
PLACE C1291-C1296 CLOSE TO FSB DATA PINS
CPU Decoupling & VID
LAYOUT NOTE: CRITICAL CRITICAL CRITICAL
A PLACE ON SAME SIDE AS CPU 1

C1270
330UF
1
C1271
330UF
1
C1272
330UF
LAYOUT NOTE:
PLACE ON SAME SIDE AS CPU
SYNC_MASTER=MSARWAR

A
20% 20% 20%
3 2 2.0V 3 2 2.0V 3 2 2.0V
POLY-TANT POLY-TANT POLY-TANT THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
D2T-SM1 D2T-SM1 D2T-SM1 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
Intel recommends 3x220UF @ 9mOHM
D 051-7631 2.3.0

NONE 11 71
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MCP79-specific pinout
12 7 6 =PP3V3_S0_XDP
12 11 10 9 7 6 =PP1V05_S0_CPU
XDP XDP_CONN
R1305 1 CRITICAL
54.9
1%
J1300
D 1/20W
MF
201
2
LTH-030-01-G-D-NOPEGS
F-ST-SM D
2 1
65 9 6 XDP_BPM_L<5> OBSFN_A0 4 3 OBSFN_C0 JTAG_MCP_TDO_CONN 6 12

BI IN
65 9 6 XDP_BPM_L<4> OBSFN_A1 6 5 OBSFN_C1 JTAG_MCP_TRST_L 6 12 20
BI OUT
8 7
65 9 6 XDP_BPM_L<3> OBSDATA_A0 10 9 OBSDATA_C0 MCP_DEBUG<0> 6 18 68

BI BI
IN BI
14 13

IN BI
IN BI
20 19
6 TP_XDP_OBSFN_B0 OBSFN_B0 22 21 OBSFN_D0 JTAG_MCP_TDI 6 12 20

OUT
6 TP_XDP_OBSFN_B1 OBSFN_B1 24 23 OBSFN_D1 JTAG_MCP_TMS 6 12 20
OUT
26 25
6 TP_XDP_OBSDATA_B0 OBSDATA_B0 28 27 OBSDATA_D0 MCP_DEBUG<4> 6 18 68

BI
BI
32 31

BI
XDP 36 35
6 TP_XDP_OBSDATA_B3 OBSDATA_B3 OBSDATA_D3 MCP_DEBUG<7> BI 6 18 68
R1399 38 37
1K 40 39
65 13 9 IN CPU_PWRGD 1 2 6 XDP_PWRGD PWRGD/HOOK0 ITPCLK/HOOK4 FSB_CLK_ITP_P IN 6 13 65
42 41 XDP
5% 6 XDP_OBS20 HOOK1 ITPCLK#/HOOK5 FSB_CLK_ITP_N IN 6 13 65
1/20W
MF VCC_OBS_AB 44 43 VCC_OBS_CD R1303
201
46 45 1K
IN PM_LATRIGGER_L HOOK2 RESET#/HOOK6 65 6 XDP_CPURST_L 1 2 FSB_CPURST_L IN 8 9 13 65
20 12 JTAG_MCP_TCK HOOK3 48 47 DBR#/HOOK7 XDP_DBRESET_L 6 9 24 5% PLACEMENT_NOTE=Place close to CPU to minimize stub.

OUT OUT 1/20W
50 49 NOTE: XDP_DBRESET_L must be pulled-up to 3.3V. MF
C 68 42 20 6
68 42 20 6
BI SMBUS_MCP_0_DATA
SMBUS_MCP_0_CLK
SDA
SCL
52
54
51
53
TDO
TRSTn
XDP_TDO_CONN
XDP_TRST_L
IN 6 12
6 9 12 65
201
C
BI OUT
TCK1 56 55 TDI XDP_TDI
NC OUT 6 9 12 65
65 12 9 6 XDP_TCK TCK0 58 57 TMS XDP_TMS 6 9 12 65

OUT OUT
60 59 XDP_PRESENT#
XDP XDP
C1300 1 1
C1301
0.1uF 0.1UF
10% 10%
6.3V 6.3V
X5R 2 2 X5R
201 998-1571 201
From XDP connector To XDP connector

U1000 and/or level translator
12 7 6
=PP3V3_S0_XDP
=PP1V05_S0_CPU 65 12 9 6 IN XDP_TCK
CPU
12 11 10 9 7 6 XDP
65 12 9 6 IN XDP_TDI
65 12 9 6 IN XDP_TMS R1313
0
65 12 9 6 IN XDP_TRST_L 65 9 XDP_TDO 1 2 XDP_TDO_CONN OUT 6 12
5%
B 1
JTAG_ALLDEV
C1316
1/20W
MF
201
XDP connector B
0.1UF
10%
6.3V
2 X5R
201
JTAG_ALLDEV
C1311 1
JTAG_ALLDEV 0.1UF
10%
1 6.3V 2
R1311 X5R
201
11
10K
1
5%
1/20W
MF
201 2
VCCA VCCB
U1310
U1400
65 12 9 6 IN XDP_TCK 2
NLSV4T244
A1 UQFN B1 10 JTAG_MCP_TCK 12 20
MCP
XDP
3 A2 B2 9 JTAG_MCP_TDI 6 12 20
NO STUFF IN XDP_TMS 4 A3 B3 8 JTAG_MCP_TMS 6 12 20

R1314
JTAG_ALLDEV 0
R13121 6 IN XDP_TRST_L 5 A4 B4 7 JTAG_MCP_TRST_L 6 12 20 20 JTAG_MCP_TDO 1 2 JTAG_MCP_TDO_CONN OUT 6 12
9
0 12
65 5%
5%
1/20W
MF
JTAG_LVL_TRANS_EN_L 12 OE*
1/20W
MF
201
XDP connector
201 2 GND
6
eXtended Debug Port (XDP)

A SYNC_MASTER=M97

A
D 051-7631 2.3.0

NONE 12 71
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
U1400
MCP79U
BGA
(1 OF 12)
65 9 BI FSB_DSTB_L_P<0> AC61 CPU_DSTBP0# CPU_D0# AG59 FSB_D_L<0> BI 9 65
65 9 FSB_DSTB_L_N<0> AB60 CPU_DSTBN0# OMIT CPU_D1# AD58 FSB_D_L<1> 9 65

BI BI
65 9 FSB_DINV_L<0> U61 CPU_DBI0# CPU_D2# AE59 FSB_D_L<2> 9 65
BI BI
CPU_D3# AA61 FSB_D_L<3> 9 65
FSB_DSTB_L_P<1> AA57 CPU_DSTBP1# BI
65 9 BI
CPU_D4# AF58 FSB_D_L<4> 9 65
FSB_DSTB_L_N<1> AB56 CPU_DSTBN1# BI
65 9 BI
CPU_D5# AC59 FSB_D_L<5> BI 9 65
65 9 BI FSB_DINV_L<1> AE57 CPU_DBI1#
CPU_D6# AG61 FSB_D_L<6> BI 9 65
D 65 9
65 9
BI
BI
FSB_DSTB_L_P<2>
FSB_DSTB_L_N<2>
J53 CPU_DSTBP2#
H54 CPU_DSTBN2#
CPU_D7#
CPU_D8#
AF60
Y58
FSB_D_L<7>
FSB_D_L<8>
BI
BI
9 65
9 65
D
65 9 BI FSB_DINV_L<2> F56 CPU_DBI2# CPU_D9# AA59 FSB_D_L<9> BI 9 65
CPU_D10# V58 FSB_D_L<10> BI 9 65

65 9 BI FSB_DSTB_L_P<3> K60 CPU_DSTBP3#
CPU_D11# U59 FSB_D_L<11> BI 9 65
65 9 BI FSB_DSTB_L_N<3> L59 CPU_DSTBN3#
CPU_D12# V60 FSB_D_L<12> BI 9 65
65 9 BI FSB_DINV_L<3> G59 CPU_DBI3#
CPU_D13# AD60 FSB_D_L<13> BI 9 65
CPU_D14# W59 FSB_D_L<14> BI 9 65

65 9 BI FSB_A_L<3> AH60 CPU_A3#
CPU_D15# Y60 FSB_D_L<15> BI 9 65
65 9 BI FSB_A_L<4> AM60 CPU_A4#
CPU_D16# AF56 FSB_D_L<16> BI 9 65
65 9 BI FSB_A_L<5> AN59 CPU_A5#
CPU_D17# AC57 FSB_D_L<17> BI 9 65
65 9 BI FSB_A_L<6> AL59 CPU_A6#
CPU_D18# AB54 FSB_D_L<18> BI 9 65
65 9 BI FSB_A_L<7> AR59 CPU_A7#
CPU_D19# V56 FSB_D_L<19> BI 9 65
65 9 BI FSB_A_L<8> AT60 CPU_A8#
CPU_D20# AD54 FSB_D_L<20> 9 65
FSB_A_L<9> AK60 BI
65 9 BI CPU_A9# AA55
CPU_D21# FSB_D_L<21> BI 9 65
65 9 BI FSB_A_L<10> AV60 CPU_A10#
CPU_D22# AG57 FSB_D_L<22> 9 65
FSB_A_L<11> AV58 BI
65 9 BI CPU_A11# AD56
CPU_D23# FSB_D_L<23> BI 9 65
65 9 BI FSB_A_L<12> AW61 CPU_A12#
CPU_D24# V54 FSB_D_L<24> BI 9 65
65 9 BI FSB_A_L<13> AR61 CPU_A13#
CPU_D25# U55 FSB_D_L<25> BI 9 65
65 9 BI FSB_A_L<14> AW59 CPU_A14#
CPU_D26# T56 FSB_D_L<26> BI 9 65
65 9 BI FSB_A_L<15> AT58 CPU_A15#
CPU_D27# U57 FSB_D_L<27> BI 9 65
65 9 BI FSB_A_L<16> AU59 CPU_A16#
CPU_D28# W57 FSB_D_L<28> BI 9 65
65 9 BI FSB_A_L<17> AU57 CPU_A17#
CPU_D29# Y54 FSB_D_L<29> 9 65
FSB_A_L<18> AP56 BI
65 9 BI CPU_A18# Y56
CPU_D30# FSB_D_L<30> BI 9 65
65 9 BI FSB_A_L<19> AM54 CPU_A19#
CPU_D31# AC55 FSB_D_L<31> BI 9 65
65 9 BI FSB_A_L<20> AY56 CPU_A20#
CPU_D32# R55 FSB_D_L<32> 9 65
FSB_A_L<21> AP54 BI
65 9 BI CPU_A21# R57
CPU_D33# FSB_D_L<33> BI 9 65
AY54
C 65 9
65 9
BI
BI
FSB_A_L<22>
FSB_A_L<23> AM56
CPU_A22#
CPU_A23#
CPU_D34#
CPU_D35#
G57
L57
FSB_D_L<34>
FSB_D_L<35>
BI 9 65 C
FSB
BI 9 65
65 9 BI FSB_A_L<24> AK56 CPU_A24#
CPU_D36# H56 FSB_D_L<36> 9 65
FSB_A_L<25> AN55 BI
65 9 BI CPU_A25# J57
CPU_D37# FSB_D_L<37> BI 9 65
65 9 BI FSB_A_L<26> AL57 CPU_A26#
CPU_D38# K56 FSB_D_L<38> 9 65
FSB_A_L<27> AR55 BI
65 9 BI CPU_A27# E57
CPU_D39# FSB_D_L<39> BI 9 65
65 9 BI FSB_A_L<28> AV54 CPU_A28#
CPU_D40# M54 FSB_D_L<40> 9 65
FSB_A_L<29> AW55 BI
65 9 BI CPU_A29# P56
CPU_D41# FSB_D_L<41> BI 9 65
65 9 BI FSB_A_L<30> AN57 CPU_A30#
CPU_D42# N57 FSB_D_L<42> BI 9 65
65 9 BI FSB_A_L<31> AR57 CPU_A31#
CPU_D43# J55 FSB_D_L<43> BI 9 65
65 9 BI FSB_A_L<32> AT56 CPU_A32#
CPU_D44# L55 FSB_D_L<44> BI 9 65
65 9 BI FSB_A_L<33> BA57 CPU_A33#
CPU_D45# T54 FSB_D_L<45> BI 9 65
65 9 BI FSB_A_L<34> AV56 CPU_A34#
CPU_D46# P54 FSB_D_L<46> BI 9 65
65 9 BI FSB_A_L<35> AW57 CPU_A35#
CPU_D47# M56 FSB_D_L<47> BI 9 65
65 9 BI FSB_ADSTB_L<0> AP60 CPU_ADSTB0# CPU_D48# M60 FSB_D_L<48> BI 9 65
65 9 BI FSB_ADSTB_L<1> AT54 CPU_ADSTB1# CPU_D49# P58 FSB_D_L<49> BI 9 65
CPU_D50# R59 FSB_D_L<50> BI 9 65
65 9 BI FSB_REQ_L<0> AJ61 CPU_REQ0# CPU_D51# P60 FSB_D_L<51> BI 9 65
65 9 BI FSB_REQ_L<1> AK58 CPU_REQ1# CPU_D52# M58 FSB_D_L<52> BI 9 65

22 21 13 8 7 =PP1V05_S0_MCP_FSB
65 9 BI FSB_REQ_L<2> AM58 CPU_REQ2# CPU_D53# R61 FSB_D_L<53> BI 9 65
65 9 BI FSB_REQ_L<3> AJ59 CPU_REQ3# CPU_D54# H60 FSB_D_L<54> BI 9 65
65 9 BI FSB_REQ_L<4> AN61 CPU_REQ4# CPU_D55# H58 FSB_D_L<55> BI 9 65

R1410 1 R1415 1 1
R1416 CPU_D56# F60 FSB_D_L<56> 9 65
54.9 62 62 BI
1% 5% 5% 65 9 BI FSB_ADS_L AH56 CPU_ADS# CPU_D57# T60 FSB_D_L<57> BI 9 65
1/20W 1/20W 1/20W
MF MF MF 65 9 BI FSB_BNR_L AH54 CPU_BNR# CPU_D58# F58 FSB_D_L<58> BI 9 65
201 201 201
2 2 2
65 9 8 BI FSB_BREQ0_L BB60 CPU_BR0# CPU_D59# J59 FSB_D_L<59> BI 9 65
B 65 40 9 IN PM_THRMTRIP_L 65 9
65 FSB_BREQ1_L
BI FSB_DBSY_L
AV52
AK54
CPU_BR1#
CPU_DBSY#
CPU_D60#
CPU_D61#
L61
J61
FSB_D_L<60>
FSB_D_L<61>
BI
BI
9 65
9 65
B
65 9 IN CPU_FERR_L 65 9 BI FSB_DRDY_L AJ57 CPU_DRDY# CPU_D62# E61 FSB_D_L<62> BI 9 65
65 9 BI FSB_HIT_L AG55 CPU_HIT# CPU_D63# N59 FSB_D_L<63> BI 9 65
65 9 BI FSB_HITM_L AJ55 CPU_HITM#

65 9 IN FSB_LOCK_L BG59 CPU_LOCK# CPU_BPRI# AY60 FSB_BPRI_L OUT 9 65
65 9 OUT FSB_TRDY_L BD60 CPU_TRDY# CPU_DEFER# AF54 FSB_DEFER_L OUT 9 65
NO STUFF NO STUFF NO STUFF B60

8 OUT CPU_PECI_MCP CPU_PECI
R1420
1
R1421
1 1
R1422 BCLK_OUT_CPU_P BP58 FSB_CLK_CPU_P OUT 9 65
65 50 40 9 OUT CPU_PROCHOT_L BJ59 CPU_PROCHOT#
1K 1K 1K BCLK_OUT_CPU_N BN59 FSB_CLK_CPU_N OUT 9 65
5% 5% 5% BL61 CPU_THERMTRIP#
1/20W 1/20W 1/20W
MF MF MF BH60 CPU_FERR# BCLK_OUT_ITP_P BT58 FSB_CLK_ITP_P OUT 6 12 65
201 201 201
2 2 2 BCLK_OUT_ITP_N BU59 FSB_CLK_ITP_N OUT 6 12 65
8 IN =MCP_BSEL<2> (MCP_BSEL<2>) E59 CPU_BSEL2

BCLK_OUT_NB_P BN61 65 FSB_CLK_MCP_P
8 IN =MCP_BSEL<1> (MCP_BSEL<1>) C61 CPU_BSEL1
BCLK_OUT_NB_N BP60 65 FSB_CLK_MCP_N
8 IN =MCP_BSEL<0> (MCP_BSEL<0>) C59 CPU_BSEL0
Loop-back clock for delay matching.
65 9 OUT FSB_RS_L<0> BA59 CPU_RS0# BCLK_IN_N BV60
65 9 OUT FSB_RS_L<1> BA61 CPU_RS1# BCLK_IN_P BW61
65 9 OUT FSB_RS_L<2> BE61 CPU_RS2#
1 1 PP1V05_S0_MCP_PLL_FSB CPU_A20M# BG61 CPU_A20M_L =PP1V05_S0_MCP_FSB

R1430 R1435 70 22 OUT 9 65 7 8 13 21 22
49.9 49.9 270 mA (A01) 206 mAAR37 V1P1_DLLDLCELL_AVDD CPU_IGNNE# BC59 CPU_IGNNE_L 9 65 NO STUFF
OUT
1% 1%
20 mAAR39 V1P1_PLL_MCLK CPU_INIT# BK60 CPU_INIT_L 1
1/20W
MF
1/20W
MF
OUT 9 65 R1440
29 mAAR41 V1P1_PLL_FSB CPU_INTR BF60 CPU_INTR 150
201
2 2
201
15 mAAR43 V1P1_PLL_CPU CPU_NMI BB58 CPU_NMI

OUT 8 9 65
8 9 65
5%
1/20W
MCP CPU Interface
OUT
MF
CPU_SMI# BE59 CPU_SMI_L
A 65 MCP_BCLK_VML_COMP_VDD BN57 BCLK_VML_COMP_VDD
CPU_PWRGD BR59 CPU_PWRGD
OUT 9 65
2
201
9 12 65
SYNC_MASTER=M97

A
65 MCP_BCLK_VML_COMP_GND BM56 BCLK_VML_COMP_GND OUT
CPU_RESET# D60 FSB_CPURST_L OUT 8 9 12 65
BK58 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
65 MCP_CPU_COMP_VCC BU61 CPU_COMP_VCC CPU_SLP# FSB_CPUSLP_L OUT 9 65 AGREES TO THE FOLLOWING
65 MCP_CPU_COMP_GND BL59 CPU_COMP_GND CPU_DPSLP# BT60 CPU_DPSLP_L OUT 9 65 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
R1431 1
1
R1436 CPU_DPWR# BM60 FSB_DPWR_L OUT 9 65 II NOT TO REPRODUCE OR COPY IT
49.9 49.9
1% 1% CPU_STPCLK# BD58 CPU_STPCLK_L 9 65 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
OUT
1/20W 1/20W
MF MF CPU_DPRSTP# BH58 CPU_DPRSTP_L 8 9 50 65
OUT
201
2 2
201 SIZE DRAWING NUMBER REV.
D 051-7631 2.3.0

NONE 13 71
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT OMIT
U1400 U1400
MCP79U MCP79U
BGA BGA
(2 OF 12) (3 OF 12)
66 28 BI MEM_A_DQ<63> BN5 MDQ0_63 MDQS0_7_P BN7 MEM_A_DQS_P<7> BI 28 66 66 30 BI MEM_B_DQ<63> BW1 MDQ1_63 MDQS1_7_P BR3 MEM_B_DQS_P<7> BI 30 66
66 28 BI MEM_A_DQ<62> BM6 MDQ0_62 MDQS0_7_N BP8 MEM_A_DQS_N<7> BI 28 66 66 30 BI MEM_B_DQ<62> BN3 MDQ1_62 MDQS1_7_N BT2 MEM_B_DQS_N<7> BI 30 66
66 28 BI MEM_A_DQ<61> BL9 MDQ0_61 MDQS0_6_P BT8 MEM_A_DQS_P<6> BI 28 66 66 30 BI MEM_B_DQ<61> BP2 MDQ1_61 MDQS1_6_P BY8 MEM_B_DQS_P<6> BI 30 66
66 28 BI MEM_A_DQ<60> BN9 MDQ0_60 MDQS0_6_N BU9 MEM_A_DQS_N<6> BI 28 66 66 30 BI MEM_B_DQ<60> BW3 MDQ1_60 MDQS1_6_N BW7 MEM_B_DQS_N<6> BI 30 66
D 66 28
66 28
BI
BI
MEM_A_DQ<59>
MEM_A_DQ<58>
BP4
BL5
MDQ0_59
MDQ0_58
MDQS0_5_P
MDQS0_5_N
BN13
BP14
MEM_A_DQS_P<5>
MEM_A_DQS_N<5>
BI
BI
28 66
28 66
66 30
66 30
BI
BI
MEM_B_DQ<59>
MEM_B_DQ<58>
BU1
BN1
MDQ1_59
MDQ1_58
MDQS1_5_P
MDQS1_5_N
BY14
BW13
MEM_B_DQS_P<5>
MEM_B_DQS_N<5>
BI
BI
30 66
30 66
D
66 28 BI MEM_A_DQ<57> BL7 MDQ0_57 MDQS0_4_P BU17 MEM_A_DQS_P<4> BI 28 66 66 30 BI MEM_B_DQ<57> BY2 MDQ1_57 MDQS1_4_P BY22 MEM_B_DQS_P<4> BI 30 66
66 28 BI MEM_A_DQ<56> BM8 MDQ0_56 MDQS0_4_N BV18 MEM_A_DQS_N<4> BI 28 66 66 30 BI MEM_B_DQ<56> BV2 MDQ1_56 MDQS1_4_N BW21 MEM_B_DQS_N<4> BI 30 66
66 28 BI MEM_A_DQ<55> BV6 MDQ0_55 MDQS0_3_P BT36 MEM_A_DQS_P<3> BI 27 66 66 30 BI MEM_B_DQ<55> CA5 MDQ1_55 MDQS1_3_P BY30 MEM_B_DQS_P<3> BI 29 66
66 28 BI MEM_A_DQ<54> BU7 MDQ0_54 MDQS0_3_N BU37 MEM_A_DQS_N<3> BI 27 66 66 30 BI MEM_B_DQ<54> BY4 MDQ1_54 MDQS1_3_N BW29 MEM_B_DQS_N<3> BI 29 66
66 28 BI MEM_A_DQ<53> BV12 MDQ0_53 MDQS0_2_P BM44 MEM_A_DQS_P<2> BI 27 66 66 30 BI MEM_B_DQ<53> BY10 MDQ1_53 MDQS1_2_P BY40 MEM_B_DQS_P<2> BI 29 66
66 28 BI MEM_A_DQ<52> BT12 MDQ0_52 MDQS0_2_N BP44 MEM_A_DQS_N<2> BI 27 66 66 30 BI MEM_B_DQ<52> CA11 MDQ1_52 MDQS1_2_N BW39 MEM_B_DQS_N<2> BI 29 66
66 28 BI MEM_A_DQ<51> BU5 MDQ0_51 MDQS0_1_P BU47 MEM_A_DQS_P<1> BI 27 66 66 30 BI MEM_B_DQ<51> BW5 MDQ1_51 MDQS1_1_P BW49 MEM_B_DQS_P<1> BI 29 66
66 28 BI MEM_A_DQ<50> BT6 MDQ0_50 MDQS0_1_N BT46 MEM_A_DQS_N<1> BI 27 66 66 30 BI MEM_B_DQ<50> CA3 MDQ1_50 MDQS1_1_N BY50 MEM_B_DQS_N<1> BI 29 66
66 28 BI MEM_A_DQ<49> BU11 MDQ0_49 MDQS0_0_P BV54 MEM_A_DQS_P<0> BI 27 66 66 30 BI MEM_B_DQ<49> BY6 MDQ1_49 MDQS1_0_P BW55 MEM_B_DQS_P<0> BI 29 66
66 28 BI MEM_A_DQ<48> BT10 MDQ0_48 MDQS0_0_N BT54 MEM_A_DQS_N<0> BI 27 66 66 30 BI MEM_B_DQ<48> BW9 MDQ1_48 MDQS1_0_N BY56 MEM_B_DQS_N<0> BI 29 66
66 28 BI MEM_A_DQ<47> BM12 MDQ0_47 66 30 BI MEM_B_DQ<47> BY16 MDQ1_47

66 28 BI MEM_A_DQ<46> BN15 MDQ0_46 66 30 BI MEM_B_DQ<46> BY12 MDQ1_46
MEMORY PARTITION 0
MEMORY PARTITION 1
66 28 BI MEM_A_DQ<45> BN17 MDQ0_45 66 30 BI MEM_B_DQ<45> BW19 MDQ1_45
66 28 BI MEM_A_DQ<44> BL13 MDQ0_44 66 30 BI MEM_B_DQ<44> BY18 MDQ1_44
66 28 BI MEM_A_DQ<42> BP10 MDQ0_42 MRAS0# BN25 MEM_A_RAS_L OUT 27 28 33 66 66 30 BI MEM_B_DQ<42> CA15 MDQ1_42 MRAS1# BM30 MEM_B_RAS_L OUT 29 30 33 66
66 28 BI MEM_A_DQ<41> BM14 MDQ0_41 MCAS0# BP22 MEM_A_CAS_L OUT 27 28 33 66 66 30 BI MEM_B_DQ<41> BW15 MDQ1_41 MCAS1# BK30 MEM_B_CAS_L OUT 29 30 33 66
66 28 BI MEM_A_DQ<40> BP16 MDQ0_40 MWE0# BM24 MEM_A_WE_L OUT 27 28 33 66 66 30 BI MEM_B_DQ<40> BW17 MDQ1_40 MWE1# BN31 MEM_B_WE_L OUT 29 30 33 66
66 28 BI MEM_A_DQ<39> BU15 MDQ0_39 66 30 BI MEM_B_DQ<39> BY24 MDQ1_39

66 28 BI MEM_A_DQ<38> BT16 MDQ0_38 66 30 BI MEM_B_DQ<38> CA21 MDQ1_38
66 28 BI MEM_A_DQ<37> BU21 MDQ0_37 66 30 BI MEM_B_DQ<37> BW27 MDQ1_37
66 28 BI MEM_A_DQ<36> BT18 MDQ0_36 66 30 BI MEM_B_DQ<36> BW25 MDQ1_36
66 28 BI MEM_A_DQ<34> BT14 MDQ0_34 MBA0_2 BM26 MEM_A_BA<2> OUT 27 28 33 66 66 30 BI MEM_B_DQ<34> CA23 MDQ1_34 MBA1_2 BK34 MEM_B_BA<2> OUT 29 30 33 66
66 28 BI MEM_A_DQ<33> BU19 MDQ0_33 MBA0_1 BP24 MEM_A_BA<1> OUT 27 28 33 66 66 30 BI MEM_B_DQ<33> BY26 MDQ1_33 MBA1_1 BP32 MEM_B_BA<1> OUT 29 30 33 66
C 66 28
66 27
BI MEM_A_DQ<32>
MEM_A_DQ<31>
BV20
BT40
MDQ0_32
MDQ0_31
MBA0_0 BN27 MEM_A_BA<0> OUT 27 28 33 66 66 30
66 29
BI MEM_B_DQ<32>
MEM_B_DQ<31>
BW23
BW31
MDQ1_32
MDQ1_31
MBA1_0 BM32 MEM_B_BA<0> OUT 29 30 33 66 C
BI BI
66 27 BI MEM_A_DQ<30> BV36 MDQ0_30 66 29 BI MEM_B_DQ<30> BW33 MDQ1_30
66 27 BI MEM_A_DQ<29> BV42 MDQ0_29 66 29 BI MEM_B_DQ<29> BY34 MDQ1_29
66 27 BI MEM_A_DQ<28> BT42 MDQ0_28 66 29 BI MEM_B_DQ<28> CA35 MDQ1_28
66 27 BI MEM_A_DQ<27> BU35 MDQ0_27 66 29 BI MEM_B_DQ<27> CA29 MDQ1_27
MA0_14 BP28 MEM_A_A<14> OUT 27 28 33 66 MA1_14 BK36 MEM_B_A<14> OUT 29 30 33 66
66 27 BI MEM_A_DQ<26> BV38 MDQ0_26 66 29 BI MEM_B_DQ<26> BY28 MDQ1_26
MA0_13 BK26 MEM_A_A<13> OUT 27 28 33 66 MA1_13 BU31 MEM_B_A<13> OUT 29 30 33 66
MA0_12 BK24 MEM_A_A<12> OUT 27 28 33 66 MA1_12 BP36 MEM_B_A<12> OUT 29 30 33 66
MA0_11 BH28 MEM_A_A<11> OUT 27 28 33 66 MA1_11 BN33 MEM_B_A<11> OUT 29 30 33 66
66 27 BI MEM_A_DQ<23> BN41 MDQ0_23 66 29 BI MEM_B_DQ<23> BY36 MDQ1_23
MA0_10 BR23 MEM_A_A<10> OUT 27 28 33 66 MA1_10 BV32 MEM_B_A<10> OUT 29 30 33 66
66 27 BI MEM_A_DQ<22> BM42 MDQ0_22 66 29 BI MEM_B_DQ<22> BY38 MDQ1_22
MA0_9 BR27 MEM_A_A<9> OUT 27 28 33 66 MA1_9 BU33 MEM_B_A<9> OUT 29 30 33 66
MA0_8 BP26 MEM_A_A<8> OUT 27 28 33 66 MA1_8 BR35 MEM_B_A<8> OUT 29 30 33 66
66 27 BI MEM_A_DQ<20> BP46 MDQ0_20 66 29 BI MEM_B_DQ<20> BY44 MDQ1_20
MA0_7 BK28 MEM_A_A<7> OUT 27 28 33 66 MA1_7 BN35 MEM_B_A<7> OUT 29 30 33 66
66 27 BI MEM_A_DQ<19> BP42 MDQ0_19 66 29 BI MEM_B_DQ<19> BW43 MDQ1_19
MA0_6 BT26 MEM_A_A<6> OUT 27 28 33 66 MA1_6 BM36 MEM_B_A<6> OUT 29 30 33 66
66 27 BI MEM_A_DQ<18> BP40 MDQ0_18 66 29 BI MEM_B_DQ<18> BW37 MDQ1_18
MA0_5 BU27 MEM_A_A<5> OUT 27 28 33 66 MA1_5 BT34 MEM_B_A<5> OUT 29 30 33 66
66 27 BI MEM_A_DQ<17> BN45 MDQ0_17 66 29 BI MEM_B_DQ<17> CA41 MDQ1_17
MA0_4 BU23 MEM_A_A<4> OUT 27 28 33 66 MA1_4 BP34 MEM_B_A<4> OUT 29 30 33 66
66 27 BI MEM_A_DQ<16> BP48 MDQ0_16 66 29 BI MEM_B_DQ<16> BY42 MDQ1_16
MA0_3 BU25 MEM_A_A<3> OUT 27 28 33 66 MA1_3 BR33 MEM_B_A<3> OUT 29 30 33 66
66 27 BI MEM_A_DQ<15> BT44 MDQ0_15 66 29 BI MEM_B_DQ<15> BW45 MDQ1_15
MA0_2 BV24 MEM_A_A<2> OUT 27 28 33 66 MA1_2 BK32 MEM_B_A<2> OUT 29 30 33 66
MA0_1 BT24 MEM_A_A<1> OUT 27 28 33 66 MA1_1 BT32 MEM_B_A<1> OUT 29 30 33 66
66 27 BI MEM_A_DQ<13> BV48 MDQ0_13 66 29 BI MEM_B_DQ<13> BW51 MDQ1_13
MA0_0 BV26 MEM_A_A<0> OUT 27 28 33 66 MA1_0 BV30 MEM_B_A<0> OUT 29 30 33 66
66 27 BI MEM_A_DQ<12> BT48 MDQ0_12 66 29 BI MEM_B_DQ<12> BY52 MDQ1_12
66 27 BI MEM_A_DQ<10> BV44 MDQ0_10 66 29 BI MEM_B_DQ<10> CA45 MDQ1_10
MEM_A_DQ<9> BT50 MEMORY MEM_B_DQ<9> CA51 MEMORY
66 27 BI MDQ0_9 66 29 BI MDQ1_9
MEM_A_DQ<8> BV50
CONTROL MEM_B_DQ<8> CA47
CONTROL
66 27 BI MDQ0_8 66 29 BI MDQ1_8
MEM_A_DQ<7> BR51 0A MEM_B_DQ<7> CA59 1A
66 27 BI MDQ0_7 66 29 BI MDQ1_7
NC AC41 NC AD42
B 66 27
66 27
BI
BI
MEM_A_DQ<6>
MEM_A_DQ<5>
BU53
BV56
MDQ0_6
MDQ0_5
NC AC43
66 29
66 29
BI
BI
MEM_B_DQ<6>
MEM_B_DQ<5>
BW53
BY58
MDQ1_6
MDQ1_5
NC AD44 B
66 27 BI MEM_A_DQ<4> BT56 MDQ0_4 MCLK0A_1_P BH30 MEM_A_CLK_P<1> OUT 33 66 29 BI MEM_B_DQ<4> BW59 MDQ1_4 MCLK1A_1_P BJ17 MEM_B_CLK_P<1> OUT 33
66 27 BI MEM_A_DQ<3> BT52 MDQ0_3 MCLK0A_1_N BJ29 MEM_A_CLK_N<1> OUT 33 66 29 BI MEM_B_DQ<3> CA53 MDQ1_3 MCLK1A_1_N BH18 MEM_B_CLK_N<1> OUT 33

MCLK0A_0_P BJ33 MEM_A_CLK_P<0> OUT 27 28 33 66 MCLK1A_0_P BH20 MEM_B_CLK_P<0> OUT 29 30 33 66
MCLK0A_0_N BH32 MEM_A_CLK_N<0> OUT 27 28 33 66 MCLK1A_0_N BJ21 MEM_B_CLK_N<0> OUT 29 30 33 66
66 28 OUT MEM_A_DM<7> BP6 MDQM0_7 MCS0A_1# BT20 MEM_A_CS_L<1> OUT 27 28 33 66 66 30 OUT MEM_B_DM<7> BU3 MDQM1_7 MCS1A_1# BN37 MEM_B_CS_L<1> OUT 29 30 33 66
66 28 OUT MEM_A_DM<6> BV8 MDQM0_6 MCS0A_0# BN23 MEM_A_CS_L<0> OUT 27 28 33 66 66 30 OUT MEM_B_DM<6> CA9 MDQM1_6 MCS1A_0# BM38 MEM_B_CS_L<0> OUT 29 30 33 66
66 28 OUT MEM_A_DM<5> BP12 MDQM0_5 66 30 OUT MEM_B_DM<5> CA17 MDQM1_5

66 28 OUT MEM_A_DM<4> BV14 MDQM0_4 MODT0A_1 BP20 MEM_A_ODT<1> OUT 27 28 33 66 66 30 OUT MEM_B_DM<4> CA27 MDQM1_4 MODT1A_1 BN39 MEM_B_ODT<1> OUT 29 30 33 66
66 27 OUT MEM_A_DM<3> BT38 MDQM0_3 MODT0A_0 BN21 MEM_A_ODT<0> OUT 27 28 33 66 66 29 OUT MEM_B_DM<3> BY32 MDQM1_3 MODT1A_0 BH34 MEM_B_ODT<0> OUT 29 30 33 66
66 27 OUT MEM_A_DM<2> BN43 MDQM0_2 66 29 OUT MEM_B_DM<2> CA39 MDQM1_2

66 27 OUT MEM_A_DM<1> BU45 MDQM0_1 MCKE0A_1 BR21 MEM_A_CKE<1> OUT 27 28 33 66 66 29 OUT MEM_B_DM<1> BY48 MDQM1_1 MCKE1A_1 BK38 MEM_B_CKE<1> OUT 29 30 33 66
66 27 OUT MEM_A_DM<0> BR53 MDQM0_0 MCKE0A_0 BT22 MEM_A_CKE<0> OUT 27 28 33 66 66 29 OUT MEM_B_DM<0> BY60 MDQM1_0 MCKE1A_0 BP38 MEM_B_CKE<0> OUT 29 30 33 66
MCP Memory Interface

A SYNC_MASTER=M97

A
D 051-7631 2.3.0

NONE 14 71
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT
U1400
MCP79U
BGA
(4 OF 12)
AF42 NC NC AD46
MEMORY CONTROL 0B
MEMORY CONTROL 1B
AF44 NC NC AE41
D 8 TP_MEM_A_CLK4P BJ39 MCLK0B_1_P MCLK1B_1_P BJ27 TP_MEM_B_CLK4P 8
8 TP_MEM_A_CLK4N BH38 MCLK0B_1_N MCLK1B_1_N BH26 TP_MEM_B_CLK4N 8
8 TP_MEM_A_CLK3P BJ35 MCLK0B_0_P MCLK1B_0_P BH24 TP_MEM_B_CLK3P 8
8 TP_MEM_A_CLK3N BH36 MCLK0B_0_N MCLK1B_0_N BJ23 TP_MEM_B_CLK3N 8
8 TP_MEM_A_CS_L<2> BM20 MCS0B_0# MCS1B_0# BT30 TP_MEM_B_CS_L<2> 8
8 TP_MEM_A_CS_L<3> BN19 MCS0B_1# MCS1B_1# BN29 TP_MEM_B_CS_L<3> 8
TP_MEM_A_ODT<2> BK18 MODT0B_0 MODT1B_0 BP30 TP_MEM_B_ODT<2> 8
TP_MEM_A_ODT<3> BM18 MODT0B_1 MODT1B_1 BT28 TP_MEM_B_ODT<3> 8
8 TP_MEM_A_CKE<2> BK20 MCKE0B_0 MCKE1B_0 BU29 TP_MEM_B_CKE<2> 8
8 TP_MEM_A_CKE<3> BP18 MCKE0B_1 MCKE1B_1 BR29 TP_MEM_B_CKE<3> 8
70 22 PP1V05_S0_MCP_PLL_CORE
66 22 15 7 =PP1V8R1V5_S0_MCP_MEM
87 mA (A01) 17 mA Y38 V1P1_PLL_XREF_XS
12 mA W41 V1P1_PLL_DP
R1610 1 19 mA W39 V1P1_PLL_CORE
TP or NC for DDR2.
40.2 MRESET0# J27 MCP_MEM_RESET_L OUT 26
1% 39 mA V42 V1P1_PLL_V
1/20W
MF =PP1V8R1V5_S0_MCP_MEM 7 15 22 66
201
2 BD12 4771 mA (A01, DDR3)
66 MCP_MEM_COMP_VDD BP56 MEM_COMP_1P8V BD14
66 MCP_MEM_COMP_GND BR57 MEM_COMP_GND BD16
BD18
R1611 1 BD20
C 40.2
1%
1/20W
MF
A13
A19
GND1
GND2
BD24
BD26
C
201
2 A25 GND3 BD28
A31 GND4 BD30
A37 BD32
V1P8_MEM_VDDP
GND5
A43 GND6 BD34
A49 GND7 BD36
A55 GND8 BD38
A61 GND9 BD42
A7 GND10 BD44
AB10 GND11 BF12
AB4 GND12 BF14
AB52 GND13 BF18
AB58 GND14 BF20
AC19 GND15 BF24
AC21 GND16 BF26
AC23 GND17 BF30
AC25 GND18 BF32
AC27 GND19 BF36
AC29 GND20 BF38
AC31 GND21 BF42
AC33 GND22 BF44
AC35 GND23
AC37 GND24
AC39 GND25 AR23
AD16 GND26 AR25
B AD48
AE1
GND27
GND28
AR27
AR29 B
AE13 GND29 AR31
AE19 GND30 AR33
AE21 GND31 AR35
AE23 GND32 AR53
AE25 GND33 AT10
AE27 GND34 NC AT16
AE29 GND35 AT18
AE31 GND36 AT20
AE33 GND37 AT24
AE35 GND38 AT26
AE37 GND39 AT28
AE39 GND40 AT32
AE43 GND41 AT34
AE49 GND42 AT42
AE55 GND43
AE61 GND44
AE7 GND45 GND55 AG31
AF16 GND46 GND56 AG33
AF48 GND47 GND57 AG35
AG13 GND48 GND58 AG37
AG19 GND49 GND59 AG39
AG21 GND50 GND60 AH10
AG23 GND51 GND61 AH12 MCP Memory Misc
AG25 GND52 GND62 AH16
A AG27
AG29
GND53
GND54
GND63
GND64
AH4
AH46
SYNC_MASTER=M97

A
D 051-7631 2.3.0

NONE 15 71
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT
U1400
MCP79U
BGA
(5 OF 12)
8 IN =PEG_D2R_P<0> AA3 PE0_RX0_P PE0_TX0_P AA1 =PEG_R2D_C_P<0> OUT 8
8 IN =PEG_D2R_N<0> AB2 PE0_RX0_N PE0_TX0_N Y2 =PEG_R2D_C_N<0> OUT 8
8 IN =PEG_D2R_P<1> U3 PE0_RX1_P PE0_TX1_P V2 =PEG_R2D_C_P<1> OUT 8
8 IN =PEG_D2R_N<1> U1 PE0_RX1_N PE0_TX1_N W3 =PEG_R2D_C_N<1> OUT 8
8 IN =PEG_D2R_P<2> AC1 PE0_RX2_P PE0_TX2_P V4 =PEG_R2D_C_P<2> OUT 8
8 IN =PEG_D2R_N<2> AC3 PE0_RX2_N PE0_TX2_N Y4 =PEG_R2D_C_N<2> OUT 8
8 =PEG_D2R_P<3> R5 PE0_RX3_P PE0_TX3_P R3 =PEG_R2D_C_P<3> 8
D 8
IN
IN =PEG_D2R_N<3> P4 PE0_RX3_N PE0_TX3_N T2 =PEG_R2D_C_N<3>
OUT
OUT 8 D
8 IN =PEG_D2R_P<4> AM2 PE0_RX4_P PE0_TX4_P AF4 =PEG_R2D_C_P<4> OUT 8
8 IN =PEG_D2R_N<4> AN1 PE0_RX4_N PE0_TX4_N AD4 =PEG_R2D_C_N<4> OUT 8
8 IN =PEG_D2R_P<5> AJ1 PE0_RX5_P PE0_TX5_P AD2 =PEG_R2D_C_P<5> OUT 8
8 IN =PEG_D2R_N<5> AJ3 PE0_RX5_N PE0_TX5_N AE3 =PEG_R2D_C_N<5> OUT 8
8 IN =PEG_D2R_P<6> AK2 PE0_RX6_P PE0_TX6_P AH2 =PEG_R2D_C_P<6> OUT 8
8 IN =PEG_D2R_N<6> AL3 PE0_RX6_N PE0_TX6_N AG3 =PEG_R2D_C_N<6> OUT 8
8 IN =PEG_D2R_P<7> AA5 PE0_RX7_P PE0_TX7_P AG1 =PEG_R2D_C_P<7> OUT 8
PCI EXPRESS
8 IN =PEG_D2R_N<7> AB6 PE0_RX7_N PE0_TX7_N AF2 =PEG_R2D_C_N<7> OUT 8
8 IN =PEG_D2R_P<8> AU3 PE0_RX8_P PE0_TX8_P AM4 =PEG_R2D_C_P<8> OUT 8
8 IN =PEG_D2R_N<8> AT2 PE0_RX8_N PE0_TX8_N AN5 =PEG_R2D_C_N<8> OUT 8
8 IN =PEG_D2R_P<9> AJ5 PE0_RX9_P PE0_TX9_P AR1 =PEG_R2D_C_P<9> OUT 8
8 IN =PEG_D2R_N<9> AK6 PE0_RX9_N PE0_TX9_N AR3 =PEG_R2D_C_N<9> OUT 8
8 IN =PEG_D2R_P<10> AP6 PE0_RX10_P PE0_TX10_P AW1 =PEG_R2D_C_P<10> OUT 8
8 IN =PEG_D2R_N<10> AM6 PE0_RX10_N PE0_TX10_N AV2 =PEG_R2D_C_N<10> OUT 8
8 IN =PEG_D2R_P<11> AP2 PE0_RX11_P PE0_TX11_P AK4 =PEG_R2D_C_P<11> OUT 8
8 IN =PEG_D2R_N<11> AN3 PE0_RX11_N PE0_TX11_N AL5 =PEG_R2D_C_N<11> OUT 8
8 IN =PEG_D2R_P<12> AY2 PE0_RX12_P PE0_TX12_P AR7 =PEG_R2D_C_P<12> OUT 8
8 IN =PEG_D2R_N<12> AW3 PE0_RX12_N PE0_TX12_N AT6 =PEG_R2D_C_N<12> OUT 8
8 IN =PEG_D2R_P<13> AR5 PE0_RX13_P PE0_TX13_P BA1 =PEG_R2D_C_P<13> OUT 8
8 IN =PEG_D2R_N<13> AT4 PE0_RX13_N PE0_TX13_N BA3 =PEG_R2D_C_N<13> OUT 8
8 IN =PEG_D2R_P<14> AV6 PE0_RX14_P PE0_TX14_P AU5 =PEG_R2D_C_P<14> OUT 8
8 IN =PEG_D2R_N<14> AW5 PE0_RX14_N PE0_TX14_N AV4 =PEG_R2D_C_N<14> OUT 8
8 IN =PEG_D2R_P<15> BE1 PE0_RX15_P PE0_TX15_P BC3 =PEG_R2D_C_P<15> OUT 8
8 IN =PEG_D2R_N<15> BD2 PE0_RX15_N PE0_TX15_N BB2 =PEG_R2D_C_N<15> OUT 8
PE0_REFCLK_P E3
C 8 IN PEG_PRSNT_L
Int PU
M12 PE0_PRSNT_16# PE0_REFCLK_N E1
PEG_CLK100M_P
PEG_CLK100M_N
OUT
OUT
8 67
8 67
C
Int PU
34 IN MINI_CLKREQ_L C5 PEB_CLKREQ# PE1_REFCLK_P H4 PCIE_CLK100M_MINI_P OUT 34 67
AW19 NC PE1_REFCLK_N F4 PCIE_CLK100M_MINI_N OUT 34 67
Int PU
TP_FW_CLKREQ_L J9 PEC_CLKREQ# PE2_REFCLK_P J5 TP_PCIE_CLK100M_FW_P
AW21 NC PE2_REFCLK_N H6 TP_PCIE_CLK100M_FW_N
Int PU
TP_EXCARD_CLKREQ_L H8 PED_CLKREQ# PE3_REFCLK_P F6 TP_PCIE_CLK100M_EXCARD_P
TP_PCIE_EXCARD_PRSNT_L D6 PED_PRSNT# Int PU PE3_REFCLK_N G5 TP_PCIE_CLK100M_EXCARD_N
Int PU
TP_FC_CLKREQ_L E7 PEE_CLKREQ# PE4_REFCLK_P D2 TP_PCIE_CLK100M_FC_P
TP_PCIE_FC_PRSNT_L E5 PEE_PRSNT# PE4_REFCLK_N C1 TP_PCIE_CLK100M_FC_N
Int PU
Int PU
TP_MCP_GPIO_17 A3 PEF_CLKREQ# NC AW23
8 OUT EXTGPU_PWR_EN B2 PEF_PRSNT# NC AW25
Int PU
Int PU
8 IN PEG_CLKREQ_L B4 PEG_CLKREQ# NC AW27
8 OUT EXTGPU_RESET_L A5 PEG_PRSNT# NC AW29
Int PU
34 6 IN PCIE_WAKE_L J19 PE_WAKE# Int PU (S5) PEX_RST0# J17 PCIE_RESET_L OUT 24
67 34 IN PCIE_MINI_D2R_P M4 PE1_RX0_P PE1_TX0_P M2 PCIE_MINI_R2D_C_P OUT 34 67
67 34 IN PCIE_MINI_D2R_N N5 PE1_RX0_N PE1_TX0_N N3 PCIE_MINI_R2D_C_N OUT 34 67
TP_PCIE_FW_D2R_P J3 PE1_RX1_P PE1_TX1_P L1 TP_PCIE_FW_R2D_C_P
B TP_PCIE_FW_D2R_N K2 PE1_RX1_N PE1_TX1_N L3 TP_PCIE_FW_R2D_C_N

B
TP_PCIE_EXCARD_D2R_P P2 PE1_RX2_P PE1_TX2_P M6 TP_PCIE_EXCARD_R2D_C_P
TP_PCIE_EXCARD_D2R_N R1 PE1_RX2_N PE1_TX2_N P6 TP_PCIE_EXCARD_R2D_C_N
IN TP_PCIE_FC_D2R_P G3 PE1_RX3_P PE1_TX3_P J1 TP_PCIE_FC_R2D_C_P OUT

IN TP_PCIE_FC_D2R_N F2 PE1_RX3_N PE1_TX3_N H2 TP_PCIE_FC_R2D_C_N OUT
7 =PP1V05_S0_MCP_PEX_DVDD0 =PP1V05_S0_MCP_PEX_AVDD0 7
57 mA (A01) AA13 AA9 206 mA (A01)

AA7 AB8
AD14 AC13
AF14 AC9
W9 V1P1_PEX_DVDD0 AD10
Y10 AD12
Y12 AD8
V1P1_PEX_AVDD0
Y8 AE9
AF10
7 =PP1V05_S0_MCP_PEX_DVDD1
T6 V1P1_PEX_DVDD1 AF12
U7 V1P1_PEX_DVDD1 AF8
AG9
70 22 PP1V05_S0_MCP_PLL_PEX V14 V1P1_PLL_PEX =PP1V05_S0_MCP_PEX_AVDD1 7
84 mA (A01) N11
V1P1_PEX_AVDD1 N9
67 MCP_PEX_CLK_COMP C3 PEX_CLK_COMP P10 MCP PCIe Interfaces
NO STUFF
A 1
R1710
2.37K
SYNC_MASTER=M97

A
1% If PE0 interface is not used, ground DVDD0_PEX and AVDD0_PEX
1/20W
MF If PE1 interface is not used, ground DVDD1_PEX and AVDD1_PEX THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
2
201 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
PLACEMENT_NOTE=Place within 12.7mm of U1400
D 051-7631 2.3.0

NONE 16 71
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT
U1400
MCP79U
BGA
(6 OF 12) =PP3V3_ENET_MCP_RMGT 7 17 22
V3P3_DUAL_RMGT P28 83 mA (A01)

NC BA19
D
LAN
D V1P0_DUAL_RMGT V28
=PP1V05_ENET_MCP_RMGT 7 22
131 mA (A01)
V1P0_DUAL_RMGT W29
8 IN ENET_RXD<0> A33 MII_RXD0 Network Interface Select
8 IN ENET_RXD<1> J29 MII_RXD1 MII_VREF B36 MCP_MII_VREF IN 8
8 IN ENET_RXD<2> A35 MII_RXD2

E31 ENET_TXD<0>
Interface ENET_TXD<0>
MII_TXD0 8
8 IN ENET_RXD<3> C31 MII_RXD3
MII_TXD1 D32 ENET_TXD<1> 8
ENET_CLK125M_RXCLK G29 MII_RXCLK J31 ENET_TXD<2>

RGMII 1
8 IN MII_TXD2 8
8 IN ENET_RX_CTRL D30 MII_RXDV MII_TXD3 B34 ENET_TXD<3> 8

MII 0
AW31 NC MII_TXCLK F32 ENET_CLK125M_TXCLK 8
OUT
AW33 NC MII_TXEN C33 ENET_TX_CTRL 8 NOTE: All Apple products set strap to
=PP3V3_ENET_MCP_RMGT OUT
22 17 7
AW35 NC MII, RGMII products will enable
MII_MDC F28 ENET_MDC 8
feature via software. This
R1810 1 8 IN ENET_INTR_L H28 RGMII_INTR MII_MDIO E29 ENET_MDIO BI 8
avoids a leakage issue since
49.9
1% 70 22 PP1V05_ENET_MCP_PLL_MAC V30 RGMII_PWRDWN C35 ENET_PWRDWN_L 8 MCP79 requires a S5 pull-up.
1/20W V1P1_DUAL_MACPLL
MF 5 mA (A01)
201
2
BUF_25MHZ B30 MCP_CLK25M_BUF0_R 8 =PP3V3_S0_MCP_GPIO 7 18 20
MCP_MII_COMP_VDD E33 MII_COMP_VDD

MCP_MII_COMP_GND H32 MII_COMP_GND MII_RESET# B32 ENET_RESET_L 8
R1860 1
1
R1861
1
NC BA35 100K 100K
R1811 5% 5%
49.9 NC BA33 1/20W 1/20W
1%
AW39 NC MF MF
1/20W 201 201
MF
AW41 NC 2 2
201
2
DDC_CLK0 C43 MCP_DDC_CLK0
DDC_DATA0 F40 MCP_DDC_DATA0
DACS
C NC BA31 RGB DAC Disable:
C
NC BA29 Okay to float all RGB_DAC signals.
RGB ONLY
8 OUT MCP_TV_DAC_RSET H52 TV_DAC_RSET
NC BA27 DDC_CLK0/DDC_DATA0 pull-ups still required.
8 OUT MCP_TV_DAC_VREF J51 TV_DAC_VREF
NC BA25
NC BA23
TV / Component
TV DAC Disable:
20 19 7 =PP3V3_S5_MCP_GPIO C / Pr TV_DAC_RED F54 CRT_IG_R_C_PR OUT 8
Y / Y TV_DAC_GREEN E55 CRT_IG_G_Y_Y OUT 8 Okay to float all TV_DAC signals.

8 IN MCP_CLK27M_XTALIN F26 XTALIN_TV
R1820
1
E27 XTALOUT_TV Comp / Pb TV_DAC_BLUE D56 CRT_IG_B_COMP_PB OUT 8 Okay to float XTALIN_TV and XTALOUT_TV.
8 OUT MCP_CLK27M_XTALOUT
47K DDC_CLK0/DDC_DATA0 pull-ups still required.
5% TV_DAC_HSYNC A47 CRT_IG_HSYNC OUT 8
1/20W
MF TV_DAC_VSYNC E41 CRT_IG_VSYNC OUT 8
201
2
41 LPCPLUS_GPIO H18 GPIO_6 IFPA_TXC_P E49 LVDS_IG_A_CLK_P 59 67

BI OUT
60 DP_IG_CA_DET F16 GPIO_7 IFPA_TXC_N F48 LVDS_IG_A_CLK_N 59 67
IN OUT
IFPA_TXD0_P J43 LVDS_IG_A_DATA_P<0> OUT 6 59 67

63 OUT LVDS_IG_BKL_PWM J37 LCD_BKL_CTL
IFPA_TXD0_N H44 LVDS_IG_A_DATA_N<0> OUT 6 59 67
Interface Mode 63 62 OUT LVDS_IG_BKL_ON C45 LCD_BKL_ON
IFPA_TXD1_P E47 LVDS_IG_A_DATA_P<1> OUT 6 59 67
LVDS_IG_PANEL_PWR D44 LCD_PANEL_PWR
FLAT PANEL
59 OUT
MCP Signal TMDS/HDMI DisplayPort IFPA_TXD1_N F46 LVDS_IG_A_DATA_N<1> OUT 6 59 67
IFPA_TXD2_P C51 LVDS_IG_A_DATA_P<2> OUT 6 59 67

=MCP_HDMI_TXC_P/N TMDS_IG_TXC_P/N DP_IG_ML_P/N<3> 60 OUT =MCP_HDMI_TXC_P F50 HDMI_TXC_P
IFPA_TXD2_N B52 LVDS_IG_A_DATA_N<2> OUT 6 59 67
=MCP_HDMI_TXD_P/N<0> TMDS_IG_TXD_P/N<0> DP_IG_ML_P/N<2> 60 OUT =MCP_HDMI_TXC_N E51 HDMI_TXC_N
IFPA_TXD3_P J45 LVDS_IG_A_DATA_P<3> OUT 8 67
=MCP_HDMI_TXD_P/N<1> TMDS_IG_TXD_P/N<1> DP_IG_ML_P/N<1>
60 OUT =MCP_HDMI_TXD_P<0> E53 HDMI_TXD0_P IFPA_TXD3_N H46 LVDS_IG_A_DATA_N<3> OUT 8 67
=MCP_HDMI_TXD_P/N<2> TMDS_IG_TXD_P/N<2> DP_IG_ML_P/N<0>
60 OUT =MCP_HDMI_TXD_N<0> F52 HDMI_TXD0_N WF: IFP is capable of LVDS (1.8V) or TMDS (3.3V), need aliases
=MCP_HDMI_DDC_CLK TMDS_IG_DDC_CLK DP_IG_DDC_CLK
60 =MCP_HDMI_TXD_P<1> C53 HDMI_TXD1_P
B =MCP_HDMI_DDC_DATA
=MCP_HDMI_HPD
TMDS_IG_DDC_DATA
TMDS_IG_HPD
DP_IG_DDC_DATA
DP_IG_HPD
60
OUT
OUT =MCP_HDMI_TXD_N<1> B54 HDMI_TXD1_N
IFPB_TXC_P F42
IFPB_TXC_N E43
LVDS_IG_B_CLK_P
LVDS_IG_B_CLK_N
OUT
OUT
8 67
8 67
B
60 OUT =MCP_HDMI_TXD_P<2> J47 HDMI_TXD2_P
DP_IG_AUX_CH_P/N TP_DP_IG_AUX_CHP/N DP_IG_AUX_CH_P/N
60 OUT =MCP_HDMI_TXD_N<2> H48 HDMI_TXD2_N IFPB_TXD4_P J41 LVDS_IG_B_DATA_P<0> OUT 8 67
NOTE: 1M pull-down required on DP_IG_CA_DET if DP not used. IFPB_TXD4_N H42 LVDS_IG_B_DATA_N<0> OUT 8 67
NOTE: 20K pull-down required on DP_HOTPLUG_DET. 67 60 OUT DP_IG_AUX_CH_P J49 DP_AUX_CH0_P IFPB_TXD5_P E45 LVDS_IG_B_DATA_P<1> OUT 8 67
67 60 OUT DP_IG_AUX_CH_N H50 DP_AUX_CH0_N IFPB_TXD5_N F44 LVDS_IG_B_DATA_N<1> OUT 8 67

NOTE: HDMI port requires level-shifting. IFP interface can
IFPB_TXD6_P C47 LVDS_IG_B_DATA_P<2> OUT 8 67
be used to provide HDMI or dual-channel TMDS without
8 IN =DVI_HPD_GMUX_INT D42 HPLUG_DET2 IFPB_TXD6_N B48 LVDS_IG_B_DATA_N<2> OUT 8 67
level-shifters.
60 IN =MCP_HDMI_HPD B46 HPLUG_DET3 IFPB_TXD7_P J39 LVDS_IG_B_DATA_P<3> OUT 8 67
IFPB_TXD7_N H40 LVDS_IG_B_DATA_N<3> OUT 8 67

LVDS: Power +VDD_IFPx at 1.8V 23 7 =PP3V3R1V8_S0_MCP_IFP_VDD N41 VAP8_IFPA_VDD_0
Dual-channel TMDS: Power +VDD_IFPx at 3.3V 190 mA (A01, 1.8V) P38 V1P8_IFPB_VDD_1
DDC_CLK2 G39 LVDS_IG_DDC_CLK OUT 6 59
70 23 PP3V3_S0_MCP_VPLL T38 V3P3_PLL_IFPAB DDC_DATA2 H38 LVDS_IG_DDC_DATA BI 6 59
16 mA (A01) 8 mA T44 V3P3_PLL_HDMI
8 mA
DDC_CLK3 B44 =MCP_HDMI_DDC_CLK OUT 60
23 7 =PP1V05_S0_MCP_HDMI_VDD T42 V1P1_HDMI_VDD DDC_DATA3 A45 =MCP_HDMI_DDC_DATA 60

BI
95 mA (A01)
67 23 OUT MCP_HDMI_RSET A59 HDMI_RSET IFPAB_RSET A51 MCP_IFPAB_RSET OUT 23 67
67 23 OUT MCP_HDMI_VPROBE A57 HDMI_VPROBE IFPAB_VPROBE B50 MCP_IFPAB_VPROBE OUT 23 67
MCP Ethernet & Graphics

A SYNC_MASTER=M97

A
D 051-7631 2.3.0

NONE 17 71
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT
U1400 20 17 7 =PP3V3_S0_MCP_GPIO
MCP79U
BGA
(7 OF 12)
PCI_REQ0_L AJ9 PCI_REQ0# NC BE57
68 18
18 MCP_RS232_SOUT_L RP1900 8.2K 3 6
68 18 PCI_REQ1_L AD6 PCI_REQ1# NC BE9 5% 1/32W 4X0201-HF
18 OUT CRTMUX_SEL_TV_L AH6 PCI_REQ2# PCI_GNT2# AE5 TP_LVDSMUX_SEL_IG_L OUT RP1900
68 18 PCI_REQ0_L 8.2K 4 5
AUD_IPHS_SWITCH_EN AP8 PCI_REQ3# PCI_GNT3# AC7 TP_DPMUX_SEL_IG_L RP1901
8 OUT OUT
68 18 PCI_REQ1_L 8.2K 1 8 5% 1/32W 4X0201-HF
MCP_RS232_SIN_L AC5 PCI_REQ4# PCI_GNT4# AF6 MCP_RS232_SOUT_L RP1901
18 IN OUT 18
18 CRTMUX_SEL_TV_L 8.2K 2 7 5% 1/32W 4X0201-HF
D 68 12 6 BI MCP_DEBUG<0> BC5 PCI_AD0 BE53

RP1901 8.2K 4 5
5% 1/32W 4X0201-HF
D
BD8 18 MCP_RS232_SIN_L
68 12 6 BI MCP_DEBUG<1> BK4 PCI_AD1 5% 1/32W 4X0201-HF
68 12 6 MCP_DEBUG<2> BE5 PCI_AD2 BD56
BI
MCP_DEBUG<3> BH4 BD52 FIXME: ADJUST PINOUT PER LAYOUT
68 12 6 BI PCI_AD3
68 12 6 BI MCP_DEBUG<4> BE3 PCI_AD4 BD48
68 12 6 BI MCP_DEBUG<5> BA5 PCI_AD5 BC57
68 12 6 BI MCP_DEBUG<6> BJ3 PCI_AD6
NC BC9
68 12 6 BI MCP_DEBUG<7> BJ5 PCI_AD7 BD50
BC53
BD54
BB8
BD6
BB6
BE49
BB56
BE55
BB54
PCI
BA53
BB52 FIXME: USED TO BE PM_LATRIGGER_L
BB50 Int PU (S5)
BB48
BB46 PCI_RESET0# G17 MEM_VTT_EN_R 24
OUT
BB44 PCI_RESET1# G21 TP_PCI_RESET1_L
BB42
BB38
BB36
BB34 PCI_CLK0 AM10 TP_PCI_CLK0
BB32 NC NC BE7
BB30 PCI_CLK2 AG5 68 PCI_CLK33M_MCP_R
BB28
1
BB26 R1910
C BB24
BB20
22
5%
1/20W
MF
C
201
BB10 2
BA9 PLACEMENT_NOTE=Place close to pin R8

PCI_CLKIN AG7 68 PCI_CLK33M_MCP
BA7
BA55
BA49
BA43 LPC_FRAME# AJ7 41 LPC_FRAME_R_L R1960 22 1 2 LPC_FRAME_L OUT 39 41 68
BA41 5% 1/20W MF 201
LPC_PWRDWN# AL9 LPC_PWRDWN_L OUT 39 41
BA39
LPC_RESET0# E17 LPC_RESET_L OUT 24 68
41 39 IN PM_CLKRUN_L AH8 PCI_CLKRUN#

LPC LPC_AD0
LPC_AD1
AM8
AK8
LPC_AD_R<0>
LPC_AD_R<1>
R1961
R1962
22
22
1
1
2
2
5%
5%
1/20W
1/20W
MF
MF
201
201
LPC_AD<0>
LPC_AD<1>
BI
BI
39 41 68
39 41 68
LPC_AD2 AK10 LPC_AD_R<2> R1963 22 1 2 LPC_AD<2> BI 39 41 68

5% 1/20W MF 201
8 FW_PME_L AN9 LPC_DRQ1# Int PU LPC_AD3 AR9 LPC_AD_R<3> R1964 22 1 2 LPC_AD<3> BI 39 41 68
5% 1/20W MF 201
TP_LPC_DRQ0_L AN7 LPC_DRQ0# Int PU
41 39 BI LPC_SERIRQ AT8 LPC_SERIRQ Int PU LPC_CLK0 BB4 LPC_CLK33M_SMC_R OUT 24 68
1
AH48 GND65 GND98 AL7 R1965
10K
AH52 GND66 GND99 AM16 5%
1/20W
AH58 GND67 GND100 AM48 MF
201
AJ19 GND68 GND101 AN13 2
AJ21 GND69 GND102 AN19 Strap for Boot ROM Selection (See HDA_SDOUT)
AJ23 GND70 GND103 AN21
B AJ25 GND71 GND104 AN23 B
GND

AK16 GND79 GND112 AN39
AK48 GND80 GND113 AN53
AL1 GND81 GND114 AP10
AL35 GND91 GND124 AT14
MCP PCI & LPC
AL55 AU1
A AL61
GND96
GND97
GND129
GND130 AU13
SYNC_MASTER=M97

A
D 051-7631 2.3.0

NONE 18 71
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT
U1400
MCP79U
BGA
(8 OF 12) External A
67 36 OUT SATA_HDD_R2D_C_P BH2 SATA_A0_TX_P USB0_P F36 USB_EXTA_P BI 8 68
67 36 OUT SATA_HDD_R2D_C_N BG3 SATA_A0_TX_N USB0_N E37 USB_EXTA_N BI 8 68
AirPort (PCIe Mini-Card)

67 36 IN SATA_HDD_D2R_N BG1 SATA_A0_RX_N USB1_P E35 USB_MINI_P BI 8 68
67 36 IN SATA_HDD_D2R_P BF2 SATA_A0_RX_P USB1_N F34 USB_MINI_N BI 8 68
External D
D USB2_P B38 USB_EXTD_P BI 8 68 D
USB2_N C37 USB_EXTD_N BI 8 68
8 OUT SATA_ODD_R2D_C_P BL1 SATA_A1_TX_P Camera

8 OUT SATA_ODD_R2D_C_N BK2 SATA_A1_TX_N USB3_P C41 USB_CAMERA_P BI 8 68
USB3_N B42 USB_CAMERA_N BI 8 68
8 IN SATA_ODD_D2R_N BL3 SATA_A1_RX_N IR

8 IN SATA_ODD_D2R_P BM2 SATA_A1_RX_P USB4_P F38 USB_IR_P BI 8 68
USB4_N E39 USB_IR_N BI 8 68
Wellspring Trackpad/Keyboard
USB5_P J35 USB_TPAD_P BI 8 68
BK44 NC USB5_N H36 USB_TPAD_N 8 68
BI
BK16 NC Bluetooth
USB6_P B40 USB_BT_P BI 8 68
BK12 NC USB6_N C39 USB_BT_N 8 68
BI
BJ9 NC External B
SATA
USB7_P H34 USB_EXTB_P
USB
BI 8 68
USB7_N J33 USB_EXTB_N BI 8 68
BJ53 NC NC BL49 =PP3V3_S5_MCP_GPIO 7 17 20

BJ45 NC NC BK8
BJ11 NC NC BK56 1 1
R2051 R2053
BH8 NC NC BK52 8.2K 8.2K
5% 5%
1/20W 1/20W
MF MF
NC BK48 2
201
2
201
NC BK50
BH6
C BH56
NC
NC NC BK54 R2050
8.2K
1
R2052
8.2K
1
C
NC BK6 5% 5%
1/20W 1/20W
BH54 NC MF MF
201 201
BH52 NC 2 2
USB_OC0#/GPIO_25 F24 USB_EXTA_OC_L IN 8
USB_OC1#/GPIO_26 H24 USB_EXTB_OC_L IN

USB_OC2#/GPIO_27/MGPIO E25 USB_EXTC_OC_L IN
BH50 NC USB_OC3#/GPIO_28/MGPIO J23 EXCARD_OC_L IN
BH48 NC
BH46 V3P3_PLL_USB V36 PP3V3_S0_MCP_PLL_USB 22 70

NC
BH16 19 mA (A01)
NC
USB_RBIAS_GND A41 68 MCP_USB_RBIAS_GND
R2060 1
E9 SATA_LED# GND131 AU19 806
1%
GND132 AU25 1/20W
MF
70 22 PP1V05_S0_MCP_PLL_SATA AP14 V1P1_PLL_SATA GND133 AU31 201
2
84 mA (A01) GND134 AU37
BK46 GND135 AU43
BH10 GND136 AU49
BG9 NC GND137 AU55
BG7 GND138 AU61
GND139 AU7
GND140 AU9
22 7 =PP1V05_S0_MCP_SATA_DVDD AV14
GND141
B 43 mA (A01) AV12
AW13
V1P1_SATA_DVDD1
V1P1_SATA_DVDD1
GND142 AV8 B
GND143 AY10
GND144 AY4
BG53 GND145 AY52
BG5 GND146 AY58
BF8 GND147 BB12
BF6 GND148 BB14
BF56 NC GND149 BB16
BF54 GND150 BB18
BF50 GND151 BC1
BF48 GND152 BC13
BJ41 GND153 BC19
70 22 PP1V05_S0_MCP_SATA_AVDD
GND154 BC21
127 mA (A01) AR13 GND155 BC23
AT12 GND156 BC25
AV10 V1P1_SATA_AVDD1
GND157 BC27
AW9 GND158 BC29
GND159 BC31
67 MCP_SATA_TERMP AW7 SATA_TERMP GND160 BC33
1
R2010
2.49K
1%
1/20W
MF
2
201
MCP SATA & USB
A SYNC_MASTER=M97

A
D 051-7631 2.3.0

NONE 19 71
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT
U1400 =PP3V3R1V5_S0_MCP_HDA
MCP79U 7 20 22
BGA 7 mA (A01)
(9 OF 12)
V3P3_DUAL_HDA P20 1
R2160
V3P3_DUAL_HDA T20 8.2K
5%
1/20W
HDA
D 2
MF
201
R2170
22
68 35 6 IN HDA_SDIN0 F14 HDA_SDATA_IN0 HDA_SDATA_OUT H14 68 20 HDA_SDOUT_R 1 2 HDA_SDOUT OUT 6 35 68
Int PD 5%
1/20W
MF
BIOS Boot Select
R2171 201
J15 22
20 IN MLB_RAM_SIZE_0 GPIO_2 HDA_BITCLK C13 68 20 HDA_BIT_CLK_R 1 2 HDA_BIT_CLK OUT 6 35 68 I/F HDA_SDOUT LPC_FRAME#
Int PD 5%
1/20W
MF
201 R2172 LPC 0 0
B14 22
20 IN MLB_RAM_VENDOR_0 GPIO_3 HDA_RESET# A11 68 20 HDA_RST_R_L 1 2 HDA_RST_L OUT 35 68
22 20 7 =PP3V3R1V5_S0_MCP_HDA PCI 0 1
Int PD 5%
1/20W
MF
1
R2110 R2173 201 SPI0 1 0
22
49.9 HDA_SYNC E13 68 20 HDA_SYNC_R 1 2 HDA_SYNC OUT 6 35 68
1%
1/20W 5%
1/20W
SPI1 1 1
MF
201 MF
2 201
B12 HDA_PULLDN_COMP B16 SPI0 = SPI_CS0_L, SPI1 = SPI_CS1_L

68 MCP_HDA_PULLDN_COMP GPIO_4 MCP_GPIO_4 OUT 20
GPIO_5 D14 AUD_I2C_INT_L 20 R1961 and R2160 selects SPI0 ROM by

IN
70 22 PP1V05_S0_MCP_PLL_NV default, LPC+ debug card pulls
37 mA (A01) 20 mA AP20 V1P1_PLL_NV_H SLP_S3# C19 PM_SLP_S3_L 6 34 35 39 56 LPC_FRAME# high for SPI1 ROM override.
OUT
17 mA AP18 V1P1_PLL_SP_SPREF SLP_RMGT# H16 PM_SLP_RMGT_L 57
OUT
NOTE: MCP79 does not support FWH, only
SLP_S5# C17 PM_SLP_S4_L OUT 34 39 40 56
LPC ROMs. So Apple designs will
24 21 PP3V3_G3_RTC not use LPC for BootROM override.
41 =SPI_CS1_R_L_USE_MLB C21 GPIO_1
OUT
J25 THERM_DIODE_P E11 MCP_THMDIODE_P OUT 45
40 39 8 IN SMC_ADAPTER_EN GPIO_12 NOTE: MCP79 rev A01 does not support
THERM_DIODE_N G11 MCP_THMDIODE_N OUT 45
=PP3V3_S0_MCP 7 21 SPI1 option.
R2120 1 1
R2121 TP_SB_A20GATE B6 A20GATE Int PU BOOT_MODE_SAFE
22
C 49.9K
1%
1/20W
MF
49.9K
1%
1/20W
MF 39
TP_MCP_KBDRSTIN_L
SMC_WAKE_SCI_L
C7
C23
KBRDRSTIN# Int PU
SIO_PME# Int PU (S5)
GPIO_13
GPIO_14
B8
F12
MCP_VID<0>
MCP_VID<1>
OUT 20 51
20 51
1
R2180
10K BUF_SIO_CLK Frequency
C
IN OUT
201 201 5%
2 2
39 SMC_RUNTIME_SCI_L F20 EXT_SMI/GPIO_32# Int PU (S5) GPIO_15 C11 MCP_VID<2> 20 51 1/20W
IN OUT
MF Frequency
2
201 HDA_SYNC
SM_INTRUDER_L C29 INTRUDER#
SPKR H12 MCP_SPKR
24 MHz 1
A27 LID# Int PU (S5) BOOT_MODE_USER
TP_MCP_LID_L
1
39 PM_BATLOW_L B20 LLB# Int PU (S5) SMB_CLK0 A17 SMBUS_MCP_0_CLK 6 12 42 68
R2181 14.31818 MHz 0
IN OUT
10K
SMB_DATA0 B18 SMBUS_MCP_0_DATA BI 6 12 42 68 5%
MISC
1/20W
65 50 IN PM_DPRSLPVR D12 CPU_DPRSLPVR SMB_CLK1/MSMB_CLK E23 SMBUS_MCP_1_CLK OUT 42 68 MF
201
SMB_DATA1/MSMB_DATA G23 SMBUS_MCP_1_DATA BI 42 68
2
39 IN PM_PWRBTN_L F18 PWRBTN# Int PU (S5) SMB_ALERT#/GPIO_64 B24 AP_PWR_EN OUT 20 34 SPI Frequency Select
24 IN PM_SYSRST_DEBOUNCE_L D18 RSTBTN# Int PU
A9 MEM_EVENT_L
Frequency SPI_DO SPI_CLK
A29 RTC_RST# FANRPM0/GPIO_60 IN 20 39
RTC_RST_L
FANCTL0/GPIO_61 B10 ODD_PWR_EN_L 8
R2182 31 MHz 0 0
FANRPM1/GPIO_63 D8 SMC_IG_THROTTLE_L 8 20
39 IN PM_RSMRST_L G27 PWRGD_SB 0
FANCTL1/GPIO_62 C9 ARB_DETECT 20 1 2 MCP_SAFE_MODE IN 39
24 IN MCP_PS_PWRGD A23 PS_PWRGD 42 MHz 0 1
5%
1/20W
MF
24 IN MCP_CPU_VLD D20 CPU_VLD CPUVDD_EN E19 MCP_CPUVDD_EN OUT 24 201 25 MHz 1 0
MCP_SAFE_MODE SIGNAL TO SUPPORT ROM FAILURE OVERRIDE
12 6 IN JTAG_MCP_TDI J21 JTAG_TDI Int PU E15 SPI_CS0_R_L

1 MHz 1 1
B22 GPIO_10 OUT 41 68
12 OUT JTAG_MCP_TDO JTAG_TDO
GPIO_11 G15 SPI_CLK_R 41 68
JTAG_MCP_TMS F22 OUT
12 6 IN JTAG_TMS Int PU A15 NOTE: Straps not provided on this page.
GPIO_8 SPI_MISO IN 41 68
12 6 IN JTAG_MCP_TRST_L E21 JTAG_TRST#
GPIO_9 C15 SPI_MOSI_R 41 68
JTAG_MCP_TCK H22 OUT
12 IN JTAG_TCK
B 24 IN MCP_CLK25M_XTALIN B26 XTALIN SUS_CLK/GPIO_34 H20 PM_CLK32K_SUSCLK_R OUT 24 68

B
24 OUT MCP_CLK25M_XTALOUT C25 XTALOUT BUF_SIO_CLK BD4 TP_MCP_BUF_SIO_CLK
24 IN RTC_CLK32K_XTALIN B28 XTALIN_RTC TEST_MODE_EN A21 MCP_TEST_MODE_EN

24 OUT RTC_CLK32K_XTALOUT C27 XTALOUT_RTC PKG_TEST H26
R21511 R2150 1 1
R2163 1
R2190 1DRAM_4GB 1DRAM_SPD_2
100K 10K 10K 1K R2195 R2197
5% 5% 5% 1% 1K 1K
1/20W 1/20W 1/20W 1/20W 5% 5%
MF MF MF MF 1/20W 1/20W
201 201 201 201 MF MF
2 2 2 2
201
2 2 201
20 MLB_RAM_SIZE_0
7 =PP3V3_S3_MCP_GPIO 20 MLB_RAM_VENDOR_0
HDA Output Caps 1

R2140
10K
1
R2143
10K
1
R2141
10K
1
R2142
10K 1
For EMI Reduction on HDA interface
5%
1/20W
5%
1/20W
5%
1/20W
5%
1/20W
R2158
MF MF MF MF 100K
2 201 2 201 2
201
2
201 5%
1/20W
MF
HDA_SDOUT_R AUD_I2C_INT_L
20 68 20
2 201
HDA_BIT_CLK_R 20 68 MEM_EVENT_L 20 39
MCP_GPIO_4 20 34 20 AP_PWR_EN
HDA_RST_R_L 20 68
SMC_IG_THROTTLE_L
HDA_SYNC_R 20 68
8 20
MCP HDA & MISC
MCP_VID<0> 20 51
A C2170
33PF
1
C2172
10PF
1
ARB_DETECT 20
MCP_VID<1>
MCP_VID<2>
20 51
20 51
SYNC_MASTER=M97

A
5% 5%
25V 25V
NP0-C0G 2 NPO 2
201 201 1 1 1 1
R2147 R2155 R2156 R2157 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
100K 22K 22K 22K
5% 5% 5% 5% I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
1
C2171 1
C2173 1/20W 1/20W 1/20W 1/20W
33PF 10PF MF MF MF MF II NOT TO REPRODUCE OR COPY IT
201 201 201 201
5% 5% 2 2 2 2
25V 25V III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
2 NP0-C0G 2 NPO
201 201
D 051-7631 2.3.0

NONE 20 71
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT
OMIT OMIT
U1400 U1400
MCP79U U1400
BGA MCP79U BGA
(11 OF 12) BGA MCP79U
(10 OF 12) (12 OF 12)
BC35 D52 22 7 =PPVCORE_S0_MCP =PP1V05_S0_MCP_FSB 7 8 13 22
AA19 AA49 A39 G45
BC37 D58 23065 mA (A01, 1.2V) 1139 mA 1182 mA (A01)
AA21 AA53 A53 G47
BC39 G1 16996 mA (A01, 1.0V)
AA23 AC49 AA41 G51
BC41 G13
AA25 AC53 AA43 G53
BC43 G19
AA27 AD50 AF46 G9
BC49 G25
D BC55 G31
AA29
AA31
AD52
AE53
AG41
AG43
H10
H30
D
BC61 G37
AA33 AF50 AH14 J11
BC7 G43
AA35 AF52 AT44 J13
BD10 G49
AA37 AG49 AT46 J7
BD46 G55
AA39 AG53 AT52 K12
V1P2_CPU_VTT
BE13 G61
AD18 AH50 AU21 K14
BF10 G7
AD20 AJ49 AU23 K18
BF16 K10
AD24 AJ53 AU27 K20
BF28 K16
AD26 AK50 AU33 K24
BF34 K22
POWER
AD28 AK52 AU35 K26
BF4 K28
AD30 AL53 AU39 K30
BF46 K34
AD32 AM50 AU41 K32
BF52 K4
AD34 AM52 AU53 K36
BF58 K40
AD36 AN49 AV16 K38
BH12 K46
AD38 AP50 AV18 K42
BH14 K52
AF18 AR49 AV20
VDD
BH42 K58 K44
AF20 AT50 AV24 K48
BH44 M10
AF24 T50 AV26 K50
BJ1 M20
AF26 U49 AV28 K54
BJ13 M24
AF28 V50 AV30 K6
BJ19 N1
AF30 Y50 AV32 K8
BJ25 N13
AF32 Y52 AV34 L11
BJ31 N17
AF34 AV36 L13
BJ37 N19
AF36 AV38 L49
BJ43 N25 BL57 43 mA
GND
V1P2_CPUCLK_VTT
GND
AF38 AV42 L5
BJ49 N27
AH18 AV44 L51
AH42
NC
BJ55 N29
C
NC
C BJ61 N31
AH20
AH24
AH44 AV46
AV48
L53
L7
BJ7 N33 AJ13
AH26 AV50 L9
BM10 N35 AJ41
AH28 AW37 M14
BM16 N37 AJ43
AH30 AW43 M16
BM22 N43 AK12
AH32 AW49 M18
BM28 N49 AK42
AH34 AW53 M26
BM34 N55 AK44
AH36 AY6 M28
BM4 N61 AK46
AH38 AY8 M30
BM40 N7 AL41
AK18 B56 M32
BM46 P42
AK20 NC AM12
AM14 B58 M34
BM52 P50
AK24
GND
AM42 BA13 M36

BM58 P8
AK26 BA21 M38
BR1 R7 AM44
AK28 BA37 M42
BR13 R9 AM46
AK30 BG55 M44
BR19 T10 AN41
AK32 BG57 M46
BR25 T16 AN43
AK34 BJ51 M48
BR31 T18 AP24
AK36 BJ57 M50
BR37 T28 AP26
AK38 BK10 M52
BR43 T34 AP28
AM18 BK14 M8
BR49 T36 AP30
AM20 BK42 N39
BR55 T4 AP32
AM24 BL11 N45
BR61 T46 AP34
AM26 BL51 N51
BR7 T48 AP36
AM28 BL53 N53
BV10 T52 AP38
AM30 BL55 P12
BV16 T58 AR19
AM32 BM48 P14
BV22 T8 AR21
B BV28 U13
AM34
AM36
AK14
=PP3V3_S0_MCP 7 20 22
BM50
BM54
P16
P30
B
BV34 V10 450 mA (A01)
AM38 BN49 P44
BV4 V24 AU29
V3P3 P18 BN51 P46
BV40 V34
BV46 V38 P36 BN53 P48
BV52 V48 BN55 P52
BV58 V52 BP50 R53
CA1 V8 BP52 T12
CA13 W1 =PP3V3_S5_MCP 7 22
BP54 T14
N21 BR11 U5
CA19 W13 16 mA 266 mA (A01)
N23 BR15 U53
CA25 W19 V3P3_DUAL P24
CA31 W25 BR17 U9
T24 BR39 V12
CA37 W27
BR41 V16
CA43 W31
P32 BR45 V18
CA49 W37 250 mA
P34 BR47 V20
CA55 W43 V3P3_DUAL_USB T30
BR5 V32
CA61 W49
T32 BR9 V46
CA7 W53
D10 W55 BT4 V6
70 23 PP3V3_S0_MCP_DAC
D16 W61 C49 W21
V44 V3P3_TVDAC_VDD C55 W23
D22 W7 =PP1V05_S5_MCP_VDD_AUXC 7 22
D28 Y14 C57 W33
24 20 PP3V3_G3_RTC 105 mA (A01) D24 W35
D34 Y28 V1P0_VDD_AUXC T26
D4 Y42 10 uA (G3) P26 V3P3_VBAT V26 D26 W5
V1P0_VDD_AUXC
D40 Y48 80 uA (S0) D36 Y16 MCP Power & Ground
D46 Y6 D38 Y18
A D48
D50
Y20
Y24
SYNC_MASTER=M97

A
D54 Y26
F10 Y30 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
F30 Y32
F8 Y34
G33 Y36
G35 Y44
G41 Y46 SIZE DRAWING NUMBER REV.
D 051-7631 2.3.0

NONE 21 71
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MCP Core Power NV: 1x 10uF 0805, 2x 4.7uF 0402, 3x 1uF 0402, 9x 0.1uF 0402 (23.3 uF)
Apple: 4x 4.7uF 0402, 4x 1uF 0402, 6x 0.1uF 0402 (23.4 uF)
21 7 =PPVCORE_S0_MCP
23065 mA (A01, 1.2V)
16996 mA (A01, 1.0V)
1 1 1 1 1
OMIT 1
OMIT 1
OMIT 1
OMIT 1 1 1 1 1 1
C2500 C2501 C2502 C2503 C2504 C2505 C2506 C2507 C2508 C2509 C2510 C2511 C2512 C2513
(No IG vs. EG data) 4.7UF 4.7UF 4.7UF 4.7UF 1UF 1UF 1UF 1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
20% 20% 20% 20% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
4V 4V 4V 4V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
X5R 2 X5R 2 X5R 2 X5R 2 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
402 402 402 402 402-1 402-1 402-1 402-1 201 201 201 201 201 201
D MCP PCIE (DVDD) Power MCP SATA (DVDD) Power

L2570 NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 1uF 0402, 2x 0.1uF 0402 (16.9 uF) D
30-OHM-5A Apple: 5x 2.2uF 0402 (11 uF)
7 =PP1V05_S0_MCP_PEX_DVDD 19 7 =PP1V05_S0_MCP_SATA_DVDD 7 =PP1V05_S0_MCP_AVDD_UF PP1V05_S0_MCP_PEX_AVDD 7 70
1 2
57 mA (A01) 43 mA (A01) 333 mA (A01) MIN_NECK_WIDTH=0.2 MM 206 mA (A01)
VOLTAGE=1.05V
0603 OMIT OMIT OMIT OMIT OMIT
OMIT OMIT
C2515 1 1
C2516 1
C2517 C2518 C2519 C2520 1
C2521 1
C2570 1
C2571 1
C2572 1
C2573 1
C2574
4.7UF 1UF 1UF 0.1UF 0.1UF 4.7UF 0.1UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF
20% 10% 10% 10% 10% 20% 10% 20% 20% 20% 20% 20%
4V 6.3V 6.3V 6.3V 6.3V 4V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
X5R 2 2 X5R 2 X5R X5R X5R X5R 2 X5R 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
402 402-1 402-1 201 201 402 201 402-LF 402-LF 402-LF 402-LF 402-LF
NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)

MCP 1.05V AUX Power MCP 1.05V RMGT Power
L2575 Apple: 2x 2.2uF 0402 (4.4 uF)
=PP1V05_S5_MCP_VDD_AUXC =PP1V05_ENET_MCP_RMGT 30-OHM-5A PP1V05_S0_MCP_SATA_AVDD
21 7 17 7 19 70
1 2
105 mA (A01) 131 mA (A01) MIN_NECK_WIDTH=0.2 MM 127 mA (A01)
VOLTAGE=1.05V
0603 OMIT
1 1 OMIT
C2525 C2526 C2528 1
C2529 1
C2575 1
C2576
0.1UF 0.1UF 4.7uF 0.1UF 2.2UF 2.2UF
10% 10% 20% 10% 20% 20%
6.3V 6.3V 4V 6.3V 6.3V 6.3V
2 X5R 2 X5R X5R 2 X5R 2 CERM 2 CERM
201 201 402 201 402-LF 402-LF
MCP FSB (VTT) Power NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)
L2580
Apple: 7x 2.2uF 0402 (15.4 uF) 30-OHM-1.7A
21 13 8 7 =PP1V05_S0_MCP_FSB 7 =PP1V05_S0_MCP_PLL_UF PP1V05_S0_MCP_PLL_FSB 13 70
1 2
1182 mA (A01) 562 mA (A01) MIN_NECK_WIDTH=0.2 MM 270 mA (A01)
VOLTAGE=1.05V
OMIT OMIT OMIT OMIT OMIT OMIT OMIT 0402
C 1
C2530
2.2UF
1
C2531
2.2UF
1
C2532
2.2UF
1
C2533
2.2UF
1
C2534
2.2UF
1
C2535
2.2UF
1
C2536
2.2UF
C2580
4.7UF
1
C2581
0.1UF
C
20% 20% 20% 20% 20% 20% 20% 20% 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 4V 6.3V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM X5R 2 X5R
402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402 201
MCP Memory Power

L2582
=PP1V8R1V5_S0_MCP_MEM 30-OHM-1.7A PP1V05_S0_MCP_PLL_PEX
66 15 7 16 70
1 2
4771 mA (A01, DDR3) MIN_NECK_WIDTH=0.2 MM 84 mA (A01)
VOLTAGE=1.05V
0402
C2540 1
C2541 C2542 C2543 C2544 C2545 C2546 C2547 C2548 C2549 C2582 1
C2583
4.7UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 4.7UF 0.1UF
20% 10% 10% 10% 10% 10% 10% 10% 10% 10% 20% 10%
4V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 4V 6.3V
X5R 2 X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R 2 X5R
402 201 201 201 201 201 201 201 201 201 402 201
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

MCP 3.3V Power NV: 1x 4.7uF 0603, 4x 0.1uF 0402 (5.1 uF) L2584
L2555 Apple: 1x 2.2uF 0402 (2.2 uF) 30-OHM-1.7A PP1V05_S0_MCP_PLL_SATA
Apple: 4x 2.2uF 0402 (8.8 uF) 30-OHM-1.7A 19 70
21 20 7 =PP3V3_S0_MCP 7 =PP3V3_S0_MCP_PLL_UF PP3V3_S0_MCP_PLL_USB 19 70
1 2
1 2
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM 84 mA (A01)
450 mA (A01) 19 mA (A01) MIN_NECK_WIDTH=0.2 MM 19 mA (A01) 0402
VOLTAGE=1.05V
VOLTAGE=3.3V
OMIT OMIT 0402
1
C2550 1
C2551
OMIT 1
C2552 1 OMIT
C2553 1 OMIT
C2555
C2584 1
C2585
4.7UF 0.1UF
2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 20% 10%
20% 20% 20% 20% 20% 4V 6.3V
6.3V 6.3V 6.3V 6.3V 6.3V X5R 2 X5R
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 402 201
402-LF 402-LF 402-LF 402-LF 402-LF
B B
L2586
MCP 3.3V AUX/USB Power NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF) MCP 3.3V Ethernet Power NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF) 30-OHM-1.7A PP1V05_S0_MCP_PLL_CORE 15 70
Apple: 1x 2.2uF 0402 (2.2 uF) Apple: 1x 2.2uF 0402 (2.2 uF) MIN_LINE_WIDTH=0.4 MM
21 7 =PP3V3_S5_MCP 17 7 =PP3V3_ENET_MCP_RMGT 1 2
MIN_NECK_WIDTH=0.2 MM 87 mA (A01)
VOLTAGE=1.05V
266 mA (A01) OMIT 83 mA (A01) 0402
OMIT
1
C2560 1
C2564 C2586 1
C2587
2.2UF 2.2UF 4.7UF 0.1UF
20% 20% 20% 10%
6.3V 6.3V 4V 6.3V
2 CERM 2 CERM X5R 2 X5R
402-LF 402-LF 402 201
L2588
MCP 3.3V/1.5V HDA Power NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF) 30-OHM-1.7A PP1V05_S0_MCP_PLL_NV 20 70
Apple: 1x 2.2uF 0402 (2.2 uF) MIN_LINE_WIDTH=0.4 MM
20 7 =PP3V3R1V5_S0_MCP_HDA 1 2
MIN_NECK_WIDTH=0.2 MM 37 mA (A01)
VOLTAGE=1.05V
7 mA (A01) 0402
OMIT
1
C2562 C2588 1
C2589 C2590
2.2UF 4.7UF 0.1UF 0.1UF
20% 20% 10% 10%
6.3V 4V 6.3V 6.3V
2 CERM X5R 2 X5R X5R
402-LF 402 201 201
MCP Standard Decoupling

A L2595
SYNC_MASTER=M97

A
=PP1V05_ENET_MCP_PLL_MAC 30-OHM-1.7A PP1V05_ENET_MCP_PLL_MAC
7 17 70
1 2
MIN_LINE_WIDTH=0.4 MM THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
5 mA (A01) MIN_NECK_WIDTH=0.2 MM 5 mA (A01) PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
0402
VOLTAGE=1.05V AGREES TO THE FOLLOWING
1 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

C2595 1 C2596
4.7UF 0.1UF II NOT TO REPRODUCE OR COPY IT
20% 10% III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
4V 6.3V
X5R 2 2 X5R
402 201
D 051-7631 2.3.0

NONE 22 71
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
WF: Checklist says 0-ohm resistor placeholder for ferrite bead.
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

Apple: 1x 2.2uF 0402 (2.2 uF)
17 7 =PP3V3R1V8_S0_MCP_IFP_VDD PP3V3_S0_MCP_DAC 21 70
OMIT
190 mA (A01, 1.8V)
1 C2610 1
2.2UF R2650
20% 0
6.3V 5%
2 CERM 1/16W
D
402-LF MF-LF
402
2 D
17 7 =PP1V05_S0_MCP_HDMI_VDD
95 mA (A01)
C2615 1 1
C2616
4.7UF 0.1UF
20% 10%
4V 6.3V
X5R 2 2 X5R
402 201
67 17 MCP_HDMI_RSET 67 17 MCP_IFPAB_RSET
67 17 MCP_HDMI_VPROBE 67 17 MCP_IFPAB_VPROBE NO STUFF
C NO STUFF
C2620 1
1
R2620
1K
1%
NO STUFF
C2630 1
1
R2630
1K
1%
C
0.1UF 1/20W
0.1UF 1/20W
10% 10%
6.3V MF 6.3V MF
X5R 2 201 X5R 2 201
2 2
201 201
WF: Checklist says 0-ohm resistor placeholder for ferrite bead.

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
L2640 Apple: ???
=PP3V3_S0_MCP_VPLL_UF 30-OHM-1.7A PP3V3_S0_MCP_VPLL
7 17 70
1 2
16 mA (A01) MIN_NECK_WIDTH=0.2 MM 16 mA (A01)
VOLTAGE=3.3V
0402
C2640 1 1
C2641
4.7UF 0.1uF
20% 10%
6.3V 6.3V
CERM 2 2 X5R
603 201
B B
MCP Graphics Support

A SYNC_MASTER=M97

A
SYNC FROM M97 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
D 051-7631 2.3.0

NONE 23 71
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
RTC Power Sources Platform Reset Connections

LPC Reset (Unbuffered)
49 7 =PP3V42_G3H_REG PP3V3_G3_RTC 20 21
R2881
PLACEMENT_NOTE=Place close to U1400 33
OMIT 68 18 IN LPC_RESET_L 1 2 DEBUG_RESET_L OUT 41
D
1 C2860
1UF
10%
Place near MCP ball A20
5%
1/20W
MF R2883 D
6.3V
201 33
2 CERM
1 2 SMC_LRESET_L OUT 39
402 5%
PLACEMENT_NOTE=Place close to U1400
1/20W
MF
201
RTC Crystal PCIE Reset (Unbuffered)

C2810
12pF
RTC_CLK32K_XTALOUT 1 2
20 IN R2892
5%
0
1 25V 16 IN PCIE_RESET_L 1 2 BKLT_PLT_RST_L OUT 62
R2810 NP0-C0G 5%
0 201 1/20W
MF
5%
1/20W
R2891 201
MF 0
1 2 AIRPORT_RST_L
2 201 OUT 6 34
5%
RTC_CLK32K_XTALOUT_R 1/20W
MF
NO STUFF1 CRITICAL 201 R2871
R2811 0
4
1 2 PCA9557D_RESET_L
10M
5%
Y2810 5%
OUT 25
1/16W 32.768K 1/20W

MF
MF-LF 7X1.5X1.4-SM C2811
1
402 2 201
12pF
20 RTC_CLK32K_XTALIN 1 2
OUT
C
5%
25V
NP0-C0G
201
C
MCP 25MHz Crystal C2815

12PF
20 MCP_CLK25M_XTALOUT 1 2
IN
5%
25V
NP0-C0G
201 R2870
1
33
R2815 18 IN MEM_VTT_EN_R 1 2 MEM_VTT_EN
MAKE_BASE=TRUE
=DDRVTT_EN OUT 54 57
0 5%
5% 1/20W
1/20W MF
MF 201
2 201
MCP_CLK25M_XTALOUT_R
NO STUFF
1 CRITICAL
R2816
3
1M Y2815 NC
5%
2
1/16W 25.0000M NC
MF-LF SM-3.2X2.5MM
C2816
1
402 2
12pF
20 MCP_CLK25M_XTALIN 1 2
OUT
R2825
5% 33
PLACEMENT_NOTE=Place close to U1400
25V LPC_CLK33M_SMC_R 1 2 LPC_CLK33M_SMC
68 18 IN OUT 39 68
NP0-C0G
201 5%
1/20W
MF R2826
B 201
1
33
2 LPC_CLK33M_LPCPLUS OUT 41 68 B
MCP S0 PWRGD & CPU_VLD PLACEMENT_NOTE=Place close to U1400 5%
1/20W
MF
201
7 =PP3V3_S5_MCPPWRGD
R2829
22
68 20 IN PM_CLK32K_SUSCLK_R 1 2 PM_CLK32K_SUSCLK OUT 39 68
56 7 =PP3V3_S0_PWRCTL
1
C2850 PLACEMENT_NOTE=Place close to U1400 5%
1/20W
0.1UF MF
1 10% 201
R2851 2
6.3V
X5R
1.8K 201
1%
1/20W
MF
201
2
5 TC7SZ08AFEAPE
56 39 IN ALL_SYS_PWRGD 2
A
SOT665 R2853
4 0
U2850Y S0_AND_IMVP_PGOOD 1 2 MCP_PS_PWRGD OUT 20
50 VR_PWRGOOD_DELAY 1 5%
IN B
1/20W
MF
3 201
Reset Button
PM_SYSRST_L
MCP_CPU_VLD OUT 20
39 IN
XDP
SB Misc
A R2850 12 9 6 XDP_DBRESET_L
R2898
1
0
2
R2899
1
33
2
10K pull-up to 3.3V S0 inside MCP
PM_SYSRST_DEBOUNCE_L 20
SYNC_MASTER=M97

A
0 IN OUT
20 IN MCP_CPUVDD_EN 1 2 5%
1 NO STUFF 5% NO STUFF
1/20W 1/20W THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PLACEMENT_NOTE=Place close to U1400 5% MF R2890 MF 1
C2899 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
1/20W 201 0 201
1UF AGREES TO THE FOLLOWING
MF 5%
201 10%
1/16W 10V I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
MF-LF SILK_PART=SYS RST 2 X5R
402 2 402-1 II NOT TO REPRODUCE OR COPY IT
SYNC FROM M97 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

CHANGED RTC POWER SOURCE TO DIRECT CONNECTION Place R2890 on BOTTOM of board near edge
D 051-7631 2.3.0
ADDED MCPSEQ_SMC LOGIC APPLE INC. SCALE SHT

24
OF
71
NONE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes MEM A VREF DQ MEM A VREF CA MEM B VREF DQ MEM B VREF CA CPU FSB VREF
Power aliases required by this page:
- =PP3V3_S3_VREFMRGN DAC channel A B A B C
- =PP3V3_S5_VREFMRGN Min DAC code 0x00 0x00 0x00 0x00 0x00
- =PPVTT_S3_DDR_BUF Max DAC code 0x87 0x87 0x87 0x87 0x55
Max sink I -3.75 mA -3.75 mA -3.75 mA -3.75 mA -0.91 mA
Signal aliases required by this page:
Max source I 5 mA 5 mA 5 mA 5 mA 0.52 mA
- =I2C_VREFDACS_SCL
Nominal Vref 0.75 V 0.75 V 0.75 V 0.75 V 0.70 V
- =I2C_VREFDACS_SDA
Min Vref 0.375 V 0.375 V 0.375 V 0.375 V 0.091 V
- =I2C_PCA9557D_SCL
Max Vref 1.250 V 1.250 V 1.250 V 1.250 V 1.044 V
- =I2C_PCA9557D_SDA =PPVTT_S3_DDR_BUF
Vref Stepping 6.5 mV 6.5 mV 6.5 mV 6.5 mV 11.2 mV 7
D BOM options provided by this page: (per DAC LSB) 10mA max load D
VREFMRGN
R2903 VREFMRGN
200
5%
1/20W
MF PP0V75_S3_MEM_VREFDQ
201
VREFMRGN A2
B1 U2900 MIN_LINE_WIDTH=0.3 mm
27 28 29 30 70
1 C2900 V+
MAX4253
UCSP
R2904 MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.75V
0.1UF A1 1
100 2
VREFMRGN VREFMRGN_DQ_BUF
10% CRITICAL
6.3V 1%
2 X5R A3 A4
=PP3V3_S3_VREFMRGN 201 V- 1/20W
7 25 VREFMRGN_DQ_EN MF
B4 201
VREFMRGN VREFMRGN R2905 VREFMRGN
R2901
2
C2915 1 C2910 200
2.2UF 0.1UF 100K VREFMRGN
20% 10% 5% 5%
6.3V 2 6.3V 1/20W 1/20W
CERM X5R MF MF PP0V75_S3_MEM_VREFCA
1
402-LF 201 201 201
C2
B1 U2900 MIN_LINE_WIDTH=0.3 mm
27 28 29 30 70
V+
MAX4253
UCSP R2906 MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.75V
C1 100
VREFMRGN VREFMRGN VREFMRGN_CA_BUF 1 2
CRITICAL
8 U2910 C4 1%
C3 1/20W
V- VREFMRGN_CA_EN MF
VDD B4
25
201
=I2C_VREFDACS_SCL 6 SCL MSOP VOUTA 1 VREFMRGN_VREFDQ
IN
DAC5574
42
7 SDA VOUTB 2
=I2C_VREFDACS_SDA VREFMRGN_VREFCA
R2902
2
BI
100K
42
9 A0 VOUTC 4 VREFMRGN_CPUFSB VREFMRGN

5%
1/20W
ADDR=0x98(WR)/0x99(RD) 10 A1 VOUTD 5 MF
C C
1
NC 201
CRITICAL
GND
3
VREFMRGN A2
B1 U2903
NC MAX4253
1 C2903 V+ UCSP
0.1UF VREFMRGN A1
10% NC
6.3V
2 X5R CRITICAL
A3 A4
201 NC V-
B4
C2
B1 U2903
V+
MAX4253
UCSP R2907
C1 100
VREFMRGN VREFMRGN_CPUFSB_BUF 1 2 CPU_GTLREF OUT 9 65
CRITICAL 1%
C3 C4
V- 1/20W
25 VREFMRGN_CPUFSB_EN MF
B4 201
R2908
2
100K VREFMRGN
5%
1/20W
MF
1
201
B B
VREFMRGN
1 C2920 VREFMRGN
16
0.1UF
10% VCC
2 6.3V Required zero ohm resistors when no VREF margining circuit stuffed
X5R
201 U2920
PCA9557
QFN
6
P0 NC VREFMRGN_CPUFSB_EN
3 A0 P1 7 25 116S0004 1 RES,MTL FILM,0,5%,0402,SM,LF R2903 CRITICAL NO_VREFMRGN
VREFMRGN_CA_EN
4 A1 P2 9
ADDR=0x30(WR)/0x31(RD) VREFMRGN_DQ_EN
25
116S0004 1 RES,MTL FILM,0,5%,0402,SM,LF R2905 CRITICAL NO_VREFMRGN
5 A2 P3 10 25
CRITICAL P4 11
NC
P5 12
NC
=I2C_PCA9557D_SCL 1 SCL P6 13
42 IN NC
42 BI =I2C_PCA9557D_SDA 2 SDA P7 14
NC
PCA9557D_RESET_L
THRM RESET* 15 IN 24
PAD GND
17
FSB/DDR3 Vref Margining

SYNC_MASTER=BEN SYNC_DATE=01/15/2008
A
D 051-7631 2.3.0

NONE 25 71
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
DDR3 RESET Support

MCP79 cannot control this signal directly since it must be high in sleep and MCP MEM rails are not powered in sleep.
7 =PP1V5_S3_MEMRESET
3.3V input must be stable before

1
before 1.5V starts to rise to R3010
avoid glitch on MEM_RESET_L. 1K
7 =PP3V3_S5_MEMRESET 5%
1/20W
MEMRESET_HW MF
C 1
R3005
20K
2
201
MEM_RESET_L 27 28 29 30 66
C
OUT
5%
1/20W MEMRESET_MCP
MEMRESET_HW MF MEMRESET_HW 1
201 6 R3009
R3000 1 2
Q3005 0
10K MEM_RESET 2
5%
5%
MMDT3904-X-G 1/20W
SOT-363-LF
1/20W MF
MF MEMRESET_HW 1 2
201
201 3
2
5
Q3005
MEM_RESET_RC_L MMDT3904-X-G
SOT-363-LF
MEMRESET_HW
MEMRESET_HW
R3001 1
4
1
C3000
20K 0.1UF
5%
10%
1/20W 6.3V
MF 2 X5R
201 201
2
15 IN MCP_MEM_RESET_L
B B
DDR3 Support
A SYNC_MASTER=T18_MLB

A
D 051-7631 2.3.0

NONE 26 71
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
70 30 29 28 27 25 PP0V75_S3_MEM_VREFCA
70 30 29 28 27 25 PP0V75_S3_MEM_VREFCA
70 30 29 28 27 25 PP0V75_S3_MEM_VREFCA 70 30 29 28 27 25 PP0V75_S3_MEM_VREFCA
70 30 29 28 27 25 PP0V75_S3_MEM_VREFDQ =PP1V5_S3_MEM_A
70 30 29 28 27 25 PP0V75_S3_MEM_VREFDQ =PP1V5_S3_MEM_A
70 30 29 28 27 25 PP0V75_S3_MEM_VREFDQ =PP1V5_S3_MEM_A 70 30 29 28 27 25 PP0V75_S3_MEM_VREFDQ =PP1V5_S3_MEM_A
E1
J8
A2
A9
D7
G2
G8
K1
K9
M1
M9
B9
C1
E2
E9
1 C3101 1 1 C3102
E1
J8
A2
A9
D7
G2
G8
K1
K9
M1
M9
B9
C1
E2
E9
C3100 1 C3111 1 1 C3112
E1
J8
A2
A9
D7
G2
G8
K1
K9
M1
M9
B9
C1
E2
E9
E1
J8
A2
A9
D7
G2
G8
K1
K9
M1
M9
B9
C1
E2
E9
0.47UF C3110 1
C3120 C3121 1 1 C3122 C3130 1 C3131 1 1 C3132
VREFDQ
VREFCA
20% 20% VDD VDDQ 20% 0.47UF
VREFDQ
VREFCA
0.47UF 2 0.47UF 2 4V 20% 20% VDD VDDQ 20% 0.47UF 0.47UF
VREFDQ
VREFCA
VREFDQ
VREFCA
2 CERM-X5R 0.47UF 2 0.47UF 2 VDD VDDQ VDD VDDQ
CERM-X5R CERM-X5R
201 201 201 CERM-X5R CERM-X5R
2 4V
CERM-X5R
20%
0.47UF 2 0.47UF 2
20% 20%
4V
20%
0.47UF 2 0.47UF 2
20% 20%
4V
4V 4V 201 201 201 CERM-X5R CERM-X5R 2 CERM-X5R CERM-X5R CERM-X5R 2 CERM-X5R
U3100 4V 4V 201 201 201 201 201 201
FBGA
U3110 4V 4V
U3120
4V 4V
U3130
MEM_A_ODT<0> G1 FBGA
128MX8-SDRAM-1066MHZ
MT41J128M8HX-187E
66 33 28 27 14 ODT OMIT FBGA FBGA

MEM_A_ODT<0> G1
MT41J128M8HX-187E
66 33 28 27 14 ODT OMIT MEM_A_ODT<0> G1 MEM_A_ODT<0> G1
MT41J128M8HX-187E
MT41J128M8HX-187E
MEM_RESET_L N2
66 33 28 27 14 ODT OMIT 66 33 28 27 14 ODT OMIT
30 29 28 27 26 RESET* MEM_RESET_L
66 66 30 29 28 27 26 N2 RESET*
240 66 30 29 28 27 26 MEM_RESET_L N2 RESET* 66 30 29 28 27 26 MEM_RESET_L N2 RESET*
R31001 2 MEM_A_ZQ0 H8 ZQ 240
R31101 2 MEM_A_ZQ1 H8 ZQ 240 240
MF 1% 1/20W 201 R31201 2 MEM_A_ZQ2 H8 ZQ R31301 2 MEM_A_ZQ3 H8 ZQ
MF 1% 1/20W 201
66 33 28 27 14 MEM_A_A<0> K3 A0 DQ0 B3 MEM_A_DQ<7> 14 66 MF 1% 1/20W 201 MF 1% 1/20W 201
66 33 28 27 14 MEM_A_A<0> K3 A0 DQ0 B3 MEM_A_DQ<8> 14 66
66 33 28 27 14 MEM_A_A<1> L7 A1 DQ1 C7 MEM_A_DQ<1> 14 66 66 33 28 27 14 MEM_A_A<0> K3 A0 DQ0 B3 MEM_A_DQ<19> 14 66 66 33 28 27 14 MEM_A_A<0> K3 A0 DQ0 B3 MEM_A_DQ<28> 14 66
66 33 28 27 14 MEM_A_A<1> L7 A1 DQ1 C7 MEM_A_DQ<14> 14 66
66 33 28 27 14 MEM_A_A<2> L3 A2 DQ2 C2 MEM_A_DQ<0> 14 66 66 33 28 27 14 MEM_A_A<1> L7 A1 DQ1 C7 MEM_A_DQ<17> 14 66 66 33 28 27 14 MEM_A_A<1> L7 A1 DQ1 C7 MEM_A_DQ<25> 14 66
C 66 33 28 27 14
66 33 28 27 14
MEM_A_A<3>
MEM_A_A<4>
K2
L8
A3
A4
DQ3 C8 MEM_A_DQ<3>
DQ4 E3 MEM_A_DQ<4>
14 66
14 66
66 33 28 27 14
66 33 28 27 14
MEM_A_A<3>
MEM_A_A<4>
K2
L8
A3
A4
DQ3 C8 MEM_A_DQ<12>
DQ4 E3 MEM_A_DQ<10>
14 66
14 66
66 33 28 27 14
66 33 28 27 14
MEM_A_A<2>
MEM_A_A<3>
L3
K2
A2
A3
DQ2 C2 MEM_A_DQ<23>
DQ3 C8 MEM_A_DQ<20>
14 66
14 66
66 33 28 27 14
66 33 28 27 14
MEM_A_A<2>
MEM_A_A<3>
L3
K2
A2
A3
DQ2 C2 MEM_A_DQ<27>
DQ3 C8 MEM_A_DQ<26>
14 66
14 66
C
66 33 28 27 14 MEM_A_A<5> L2 A5 DQ5 E8 MEM_A_DQ<2> 14 66 66 33 28 27 14 MEM_A_A<4> L8 A4 DQ4 E3 MEM_A_DQ<22> 14 66 66 33 28 27 14 MEM_A_A<4> L8 A4 DQ4 E3 MEM_A_DQ<29> 14 66
66 33 28 27 14 MEM_A_A<5> L2 A5 DQ5 E8 MEM_A_DQ<11> 14 66
66 33 28 27 14 MEM_A_A<6> M8 A6 DQ6 D2 MEM_A_DQ<5> 14 66 66 33 28 27 14 MEM_A_A<5> L2 A5 DQ5 E8 MEM_A_DQ<16> 14 66 66 33 28 27 14 MEM_A_A<5> L2 A5 DQ5 E8 MEM_A_DQ<24> 14 66
66 33 28 27 14 MEM_A_A<6> M8 A6 DQ6 D2 MEM_A_DQ<13> 14 66
66 33 28 27 14 MEM_A_A<7> M2 A7 DQ7 E7 MEM_A_DQ<6> 14 66 66 33 28 27 14 MEM_A_A<6> M8 A6 DQ6 D2 MEM_A_DQ<18> 14 66 66 33 28 27 14 MEM_A_A<6> M8 A6 DQ6 D2 MEM_A_DQ<30> 14 66
66 33 28 27 14 MEM_A_A<7> M2 A7 DQ7 E7 MEM_A_DQ<15> 14 66
66 33 28 27 14 MEM_A_A<8> N8 A8 66 33 28 27 14 MEM_A_A<7> M2 A7 DQ7 E7 MEM_A_DQ<21> 14 66 66 33 28 27 14 MEM_A_A<7> M2 A7 DQ7 E7 MEM_A_DQ<31> 14 66
66 33 28 27 14 MEM_A_A<8> N8 A8
66 33 28 27 14 MEM_A_A<9> M3 A9 DQS C3 MEM_A_DQS_P<0> 14 66 66 33 28 27 14 MEM_A_A<8> N8 A8 66 33 28 27 14 MEM_A_A<8> N8 A8
66 33 28 27 14 MEM_A_A<9> M3 A9 DQS C3 MEM_A_DQS_P<1> 14 66
66 33 28 27 14 MEM_A_A<10> H7 A10/AP 66 33 28 27 14 MEM_A_A<9> M3 A9 DQS C3 MEM_A_DQS_P<2> 14 66 66 33 28 27 14 MEM_A_A<9> M3 A9 DQS C3 MEM_A_DQS_P<3> 14 66
DQS* D3 MEM_A_DQS_N<0> 14 66 66 33 28 27 14 MEM_A_A<10> H7 A10/AP
66 33 28 27 14 MEM_A_A<11> M7 A11 DQS* D3 MEM_A_DQS_N<1> 14 66 66 33 28 27 14 MEM_A_A<10> H7 A10/AP 66 33 28 27 14 MEM_A_A<10> H7 A10/AP
66 33 28 27 14 MEM_A_A<11> M7 A11 DQS* D3 MEM_A_DQS_N<2> 14 66 DQS* D3 MEM_A_DQS_N<3> 14 66
66 33 28 27 14 MEM_A_A<12> K7 A12/BC* 66 33 28 27 14 MEM_A_A<11> M7 A11 66 33 28 27 14 MEM_A_A<11> M7 A11
DM/TDQS B7 MEM_A_DM<0> 14 66 66 33 28 27 14 MEM_A_A<12> K7 A12/BC*
66 33 28 27 14 MEM_A_A<13> N3 A13 DM/TDQS B7 MEM_A_DM<1> 14 66 66 33 28 27 14 MEM_A_A<12> K7 A12/BC* 66 33 28 27 14 MEM_A_A<12> K7 A12/BC*
66 33 28 27 14 MEM_A_A<13> N3 A13 DM/TDQS B7 MEM_A_DM<2> 14 66 DM/TDQS B7 MEM_A_DM<3> 14 66
TDQS* A7 NC 66 33 28 27 14 MEM_A_A<13> N3 A13 66 33 28 27 14 MEM_A_A<13> N3 A13
66 33 28 27 14 MEM_A_BA<0> J2 BA0 TDQS* A7 NC
66 33 28 27 14 MEM_A_BA<0> J2 BA0 TDQS* A7 NC TDQS* A7 NC
66 33 28 27 14 MEM_A_BA<1> K8 BA1 66 33 28 27 14 MEM_A_BA<0> J2 BA0 66 33 28 27 14 MEM_A_BA<0> J2 BA0
66 33 28 27 14 MEM_A_BA<1> K8 BA1
MEM_A_BA<2> J3 BA2 A3 MEM_A_BA<1> K8 BA1 MEM_A_BA<1> K8 BA1
66 33 28 27 14 NC MEM_A_BA<2> J3 A3 66 33 28 27 14 66 33 28 27 14
66 33 28 27 14 BA2 NC A3 NC A3 NC
66 33 28 27 14 MEM_A_BA<2> J3 BA2 66 33 28 27 14 MEM_A_BA<2> J3 BA2
66 33 28 27 14 MEM_A_CKE<0> G9 CKE
66 33 28 27 14 MEM_A_CKE<0> G9 CKE
66 33 28 27 14 MEM_A_CKE<0> G9 CKE 66 33 28 27 14 MEM_A_CKE<0> G9 CKE
66 33 28 27 14 MEM_A_CLK_P<0>F7 CK
66 33 28 27 14 MEM_A_CLK_P<0>F7 CK
66 33 28 27 14 MEM_A_CLK_N<0>G7 CK* NC F1 MEM_A_ODT<1> 66 33 28 27 14 MEM_A_CLK_P<0>F7 CK 66 33 28 27 14 MEM_A_CLK_P<0>F7 CK
14 27 28 33 66 33 28 27 14 MEM_A_CLK_N<0>G7 CK* NC F1 MEM_A_ODT<1>
66 14 27 28 33 66 66 33 28 27 14 MEM_A_CLK_N<0>G7 CK* 66 33 28 27 14 MEM_A_CLK_N<0>G7 CK*
66 33 28 27 14 MEM_A_CS_L<0> H2 CS* F9 MEM_A_CKE<1> 14 27 28 33 66
NC F1 MEM_A_ODT<1> 14 27 28 33 66
NC F1 MEM_A_ODT<1> 14 27 28 33
66 33 28 27 14 MEM_A_CS_L<0> H2 CS* F9 MEM_A_CKE<1> 14 27 28 33 66 66
H9 MEM_A_ZQ0 27 66 33 28 27 14 MEM_A_CS_L<0> H2 CS* F9 MEM_A_CKE<1> 14 27 28 33 66 33 28 27 14 MEM_A_CS_L<0> H2 CS* F9 MEM_A_CKE<1> 14 27 28 33
66 33 28 27 14 MEM_A_CS_L<1> H1 NC H9 MEM_A_ZQ1 27 66 66
N7 66 33 28 27 14 MEM_A_CS_L<1> H1 NC H9 MEM_A_ZQ2 27 H9 MEM_A_ZQ3 27
N7 66 33 28 27 14 MEM_A_CS_L<1> H1 NC 66 33 28 27 14 MEM_A_CS_L<1> H1 NC
MEM_A_RAS_L F3 RAS* J7 MEM_A_A<14> N7 N7
66 33 28 27 14 NC 14 27 28 33 66
MEM_A_RAS_L F3 J7 NC MEM_A_A<14>
66 33 28 27 14 RAS* 14 27 28 33 66
J7 NC MEM_A_A<14> J7 NC MEM_A_A<14>
66 33 28 27 14 MEM_A_RAS_L F3 RAS* 14 27 28 66 33 28 27 14 MEM_A_RAS_L F3 RAS* 14 27 28 33 66
66 33 28 27 14 MEM_A_CAS_L G3 CAS* 33 66
66 33 28 27 14 MEM_A_CAS_L G3 CAS*
66 33 28 27 14 MEM_A_CAS_L G3 CAS* 66 33 28 27 14 MEM_A_CAS_L G3 CAS*
66 33 28 27 14 MEM_A_WE_L H3 WE*
66 33 28 27 14 MEM_A_WE_L H3 WE*
66 33 28 27 14 MEM_A_WE_L H3 WE* 66 33 28 27 14 MEM_A_WE_L H3 WE*
B VSS VSSQ
VSS VSSQ
VSS VSSQ VSS VSSQ B
A1
A8
B1
D8
F2
F8
J1
J9
L1
L9
N1
N9
B2
B8
C9
D1
D9
A1
A8
B1
D8
F2
F8
J1
J9
L1
L9
N1
N9
B2
B8
C9
D1
D9
A1
A8
B1
D8
F2
F8
J1
J9
L1
L9
N1
N9
B2
B8
C9
D1
D9
A1
A8
B1
D8
F2
F8
J1
J9
L1
L9
N1
N9
B2
B8
C9
D1
D9
A14/A15 FOR 2G/4G MONO ONLY
CS1 IS FOR 2G DDP RANK CONTROL
DDR3 DRAM Channel A (0-31)

SYNC_DATE=(MASTER)
A
D 051-7631 2.3.0

NONE 27 71
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
29 28 27 25 PP0V75_S3_MEM_VREFCA
70 30 70 30 29 28 27 25 PP0V75_S3_MEM_VREFCA
29 28 27 25 PP0V75_S3_MEM_VREFDQ =PP1V5_S3_MEM_A
70 30 70 30 29 28 27 25 PP0V75_S3_MEM_VREFDQ =PP1V5_S3_MEM_A
70 30 29 28 27 25 PP0V75_S3_MEM_VREFDQ =PP1V5_S3_MEM_A 70 30 29 28 27 25 PP0V75_S3_MEM_VREFDQ =PP1V5_S3_MEM_A
E1
J8
A2
A9
D7
G2
G8
K1
K9
M1
M9
B9
C1
E2
E9
1 C3201 1 1 C3202
E1
J8
A2
A9
D7
G2
G8
K1
K9
M1
M9
B9
C1
E2
E9
C3200 1 C3211 1 1 C3212
E1
J8
A2
A9
D7
G2
G8
K1
K9
M1
M9
B9
C1
E2
E9
E1
J8
A2
A9
D7
G2
G8
K1
K9
M1
M9
B9
C1
E2
E9
0.47UF C3210 1
C3220 C3221 1 1 C3222 C3230 1 C3231 1 1 C3232
VREFDQ
VREFCA
20% 20% VDD VDDQ 20% 0.47UF
VREFDQ
VREFCA
VREFDQ
VREFCA
VREFDQ
VREFCA
CERM-X5R CERM-X5R 2 CERM-X5R 0.47UF 2 0.47UF 2 4V 20% 20% VDD VDDQ 20% 20% 20% VDD VDDQ 20%
201 2 CERM-X5R 0.47UF 2 0.47UF 2 4V 0.47UF 2 0.47UF 2
201
4V
201
4V
CERM-X5R CERM-X5R
2 CERM-X5R CERM-X5R CERM-X5R
2 4V
CERM-X5R
U3200 4V 4V
U3210
201
4V
201
4V
201 201
4V
201
4V
201
MEM_A_ODT<0> G1
FBGA
FBGA
U3220 U3230
MT41J128M8HX-187E
66 33 28 27 14 ODT OMIT MEM_A_ODT<0> G1 FBGA FBGA
MT41J128M8HX-187E
66 33 28 27 14 ODT OMIT
MEM_A_ODT<0> G1 MEM_A_ODT<0> G1
MT41J128M8HX-187E
MT41J128M8HX-187E
66 33 28 27 14 ODT OMIT 66 33 28 27 14 ODT OMIT
66 30 29 28 27 26 MEM_RESET_L N2 RESET*
240 66 30 29 28 27 26
MEM_RESET_L N2 RESET* 66 30 29 28 27 26
MEM_RESET_L N2 RESET*
R32001 2 MEM_A_ZQ8H8 ZQ 240
R32101 2 MEM_A_ZQ9 H8 ZQ 240 240
MF 1% 1/20W 201 R32201 2 MEM_A_ZQ10 H8 ZQ R32301 2 MEM_A_ZQ11 H8 ZQ
MF 1% 1/20W 201
66 33 28 27 14 MEM_A_A<0> K3 A0 DQ0 B3 MEM_A_DQ<39> 14 66 MF 1% 1/20W 201 MF 1% 1/20W 201
66 33 28 27 14 MEM_A_A<0> K3 A0 DQ0 B3 MEM_A_DQ<41> 14 66
66 33 28 27 14 MEM_A_A<1> L7 A1 DQ1 C7 MEM_A_DQ<33> 14 66 66 33 28 27 14 MEM_A_A<0> K3 A0 DQ0 B3 MEM_A_DQ<50> 14 66 66 33 28 27 14 MEM_A_A<0> K3 A0 DQ0 B3 MEM_A_DQ<59> 14 66
66 33 28 27 14 MEM_A_A<2> L3 A2 DQ2 C2 MEM_A_DQ<34> 14 66 66 33 28 27 14 MEM_A_A<1> L7 A1 DQ1 C7 MEM_A_DQ<49> 14 66 66 33 28 27 14 MEM_A_A<1> L7 A1 DQ1 C7 MEM_A_DQ<57> 14 66
66 33 28 27 14 MEM_A_A<3> K2 A3 DQ3 C8 MEM_A_DQ<35> 14 66 66 33 28 27 14 MEM_A_A<2> L3 A2 DQ2 C2 MEM_A_DQ<55> 14 66 66 33 28 27 14 MEM_A_A<2> L3 A2 DQ2 C2 MEM_A_DQ<63> 14 66
C 66 33 28 27 14
66 33 28 27 14
MEM_A_A<4>
MEM_A_A<5>
L8
L2
A4
A5
DQ4 E3 MEM_A_DQ<36>
DQ5 E8 MEM_A_DQ<37>
14 66
14 66
66 33 28 27 14
66 33 28 27 14
MEM_A_A<3>
MEM_A_A<4>
K2
L8
A3
A4
DQ3 C8 MEM_A_DQ<45>
DQ4 E3 MEM_A_DQ<43>
14 66
14 66
66 33 28 27 14
66 33 28 27 14
MEM_A_A<3>
MEM_A_A<4>
K2
L8
A3
A4
DQ3 C8 MEM_A_DQ<51>
DQ4 E3 MEM_A_DQ<48>
14 66
14 66
66 33 28 27 14
66 33 28 27 14
MEM_A_A<3>
MEM_A_A<4>
K2
L8
A3
A4
DQ3 C8 MEM_A_DQ<56>
DQ4 E3 MEM_A_DQ<58>
14 66
14 66
C
66 33 28 27 14 MEM_A_A<5> L2 A5 DQ5 E8 MEM_A_DQ<40> 14 66
66 33 28 27 14 MEM_A_A<6> M8 A6 DQ6 D2 MEM_A_DQ<38> 14 66 66 33 28 27 14 MEM_A_A<5> L2 A5 DQ5 E8 MEM_A_DQ<53> 14 66 66 33 28 27 14 MEM_A_A<5> L2 A5 DQ5 E8 MEM_A_DQ<61> 14 66
66 33 28 27 14 MEM_A_A<6> M8 A6 DQ6 D2 MEM_A_DQ<47> 14 66
66 33 28 27 14 MEM_A_A<7> M2 A7 DQ7 E7 MEM_A_DQ<32> 14 66 66 33 28 27 14 MEM_A_A<6> M8 A6 DQ6 D2 MEM_A_DQ<54> 14 66 66 33 28 27 14 MEM_A_A<6> M8 A6 DQ6 D2 MEM_A_DQ<62> 14 66
66 33 28 27 14 MEM_A_A<7> M2 A7 DQ7 E7 MEM_A_DQ<42> 14 66
66 33 28 27 14 MEM_A_A<8> N8 A8 66 33 28 27 14 MEM_A_A<7> M2 A7 DQ7 E7 MEM_A_DQ<52> 14 66 66 33 28 27 14 MEM_A_A<7> M2 A7 DQ7 E7 MEM_A_DQ<60> 14 66
66 33 28 27 14 MEM_A_A<8> N8 A8
66 33 28 27 14 MEM_A_A<9> M3 A9 DQS C3 MEM_A_DQS_P<4> 14 66 66 33 28 27 14 MEM_A_A<8> N8 A8 66 33 28 27 14 MEM_A_A<8> N8 A8
66 33 28 27 14 MEM_A_A<9> M3 A9 DQS C3 MEM_A_DQS_P<5> 14 66
66 33 28 27 14 MEM_A_A<10> H7 A10/AP 66 33 28 27 14 MEM_A_A<9> M3 A9 DQS C3 MEM_A_DQS_P<6> 14 66 66 33 28 27 14 MEM_A_A<9> M3 A9 DQS C3 MEM_A_DQS_P<7> 14 66
DQS* D3 MEM_A_DQS_N<4> 14 66 66 33 28 27 14 MEM_A_A<10> H7 A10/AP
66 33 28 27 14 MEM_A_A<11> M7 A11 DQS* D3 MEM_A_DQS_N<5> 14 66 66 33 28 27 14 MEM_A_A<10> H7 A10/AP 66 33 28 27 14 MEM_A_A<10> H7 A10/AP
66 33 28 27 14 MEM_A_A<11> M7 A11 DQS* D3 MEM_A_DQS_N<6> 14 66 DQS* D3 MEM_A_DQS_N<7> 14 66
66 33 28 27 14 MEM_A_A<12> K7 A12/BC* 66 33 28 27 14 MEM_A_A<11> M7 A11 66 33 28 27 14 MEM_A_A<11> M7 A11
DM/TDQS B7 MEM_A_DM<4> 14 66 66 33 28 27 14 MEM_A_A<12> K7 A12/BC*
66 33 28 27 14 MEM_A_A<13> N3 A13 DM/TDQS B7 MEM_A_DM<5> 14 66 66 33 28 27 14 MEM_A_A<12> K7 A12/BC* 66 33 28 27 14 MEM_A_A<12> K7 A12/BC*
66 33 28 27 14 MEM_A_A<13> N3 A13 DM/TDQS B7 MEM_A_DM<6> 14 66 DM/TDQS B7 MEM_A_DM<7> 14 66
TDQS* A7 NC 66 33 28 27 14 MEM_A_A<13> N3 A13 66 33 28 27 14 MEM_A_A<13> N3 A13
66 33 28 27 14 MEM_A_BA<0> J2 BA0 TDQS* A7 NC
66 33 28 27 14 MEM_A_BA<0> J2 BA0 TDQS* A7 NC TDQS* A7 NC
66 33 28 27 14 MEM_A_BA<1> K8 BA1 NC 66 33 28 27 14 MEM_A_BA<0> J2 BA0 66 33 28 27 14 MEM_A_BA<0> J2 BA0
66 33 28 27 14 MEM_A_BA<1> K8 BA1 NC
66 33 28 27 14 MEM_A_BA<2> J3 BA2 A3 MEM_A_BA<1> K8 BA1 NC MEM_A_BA<1> K8 BA1 NC
NC MEM_A_BA<2> J3 BA2 A3 66 33 28 27 14 66 33 28 27 14
66 33 28 27 14 NC MEM_A_BA<2> J3 BA2 A3 MEM_A_BA<2> J3 BA2 A3
MEM_A_CKE<0> G9 CKE
NC 66 33 28 27 14 NC 66 33 28 27 14 NC
66 33 28 27 14
MEM_A_CKE<0> G9 NC
NC 66 33 28 27 14 CKE NC NC
NC 66 33 28 27 14 MEM_A_CKE<0> G9 CKE 66 33 28 27 14 MEM_A_CKE<0> G9 CKE
66 33 28 27 14 MEM_A_CLK_P<0>F7 CK NC NC NC
66 33 28 27 14 MEM_A_CLK_P<0>F7 CK NC
66 33 28 27 14 MEM_A_CLK_N<0>G7 CK* 66 33 28 27 14 MEM_A_CLK_P<0>F7 CK NC 66 33 28 27 14 MEM_A_CLK_P<0>F7 CK NC
NC F1 MEM_A_ODT<1> 14 27 28 33 66 33 28 27 14 MEM_A_CLK_N<0>G7 CK*
66 NC F1 MEM_A_ODT<1> 14 27 28 33 66 66 33 28 27 14 MEM_A_CLK_N<0>G7 CK* 66 33 28 27 14 MEM_A_CLK_N<0>G7 CK*
NC F1 MEM_A_ODT<1> 14 27 28 33 66
NC F1 MEM_A_ODT<1> 14 27 28 33 66
H9 MEM_A_ZQ8 28 66 33 28 27 14 MEM_A_CS_L<0> H2 CS* F9 MEM_A_CKE<1> 14 27 28 33 66 33 28 27 14 MEM_A_CS_L<0> H2 CS* F9 MEM_A_CKE<1> 14 27 28 33 66
66 33 28 27 14 MEM_A_CS_L<1> H1 NC H9 MEM_A_ZQ9 28 66
N7 66 33 28 27 14 MEM_A_CS_L<1> H1 NC H9 MEM_A_ZQ10 28 H9 MEM_A_ZQ11 28
N7 66 33 28 27 14 MEM_A_CS_L<1> H1 NC 66 33 28 27 14 MEM_A_CS_L<1> H1 NC
66 33 28 27 14 MEM_A_RAS_L F3 RAS* J7 NC N7 N7
MEM_A_RAS_L F3 RAS* J7
MEM_A_A<14>
66 33 28 27 14 NC MEM_A_RAS_L F3 J7 NC MEM_A_RAS_L F3 J7 NC
14 27 28 33 66 66 33 28 27 14 RAS* 66 33 28 27 14 RAS*
66 33 28 27 14 MEM_A_CAS_L G3 CAS* MEM_A_A<14> 14 27 28 33 66
66 33 28 27 14 MEM_A_CAS_L G3 CAS* MEM_A_A<14> 14 27 28 33 66 MEM_A_A<14> 14 27 28 33
66 33 28 27 14 MEM_A_CAS_L G3 CAS* 66 33 28 27 14 MEM_A_CAS_L G3 CAS* 66
66 33 28 27 14 MEM_A_WE_L H3 WE*
66 33 28 27 14 MEM_A_WE_L H3 WE*
VSS VSSQ 66 33 28 27 14 MEM_A_WE_L H3 WE* 66 33 28 27 14 MEM_A_WE_L H3 WE*
B VSS VSSQ
VSS VSSQ VSS VSSQ B
A1
A8
B1
D8
F2
F8
J1
J9
L1
L9
N1
N9
B2
B8
C9
D1
D9
A1
A8
B1
D8
F2
F8
J1
J9
L1
L9
N1
N9
B2
B8
C9
D1
D9
A1
A8
B1
D8
F2
F8
J1
J9
L1
L9
N1
N9
B2
B8
C9
D1
D9
A1
A8
B1
D8
F2
F8
J1
J9
L1
L9
N1
N9
B2
B8
C9
D1
D9
DDR3 DRAM Channel A (32-63)

A
D 051-7631 2.3.0

NONE 28 71
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
70 30 29 28 27 25 PP0V75_S3_MEM_VREFCA
70 30 29 28 27 25 PP0V75_S3_MEM_VREFCA
70 30 29 28 27 25 PP0V75_S3_MEM_VREFDQ =PP1V5_S3_MEM_B
70 30 29 28 27 25 PP0V75_S3_MEM_VREFDQ =PP1V5_S3_MEM_B
70 30 29 28 27 25 PP0V75_S3_MEM_VREFDQ =PP1V5_S3_MEM_B 70 30 29 28 27 25 PP0V75_S3_MEM_VREFDQ =PP1V5_S3_MEM_B
E1
J8
A2
A9
D7
G2
G8
K1
K9
M1
M9
B9
C1
E2
E9
1 C3301 1 1 C3302
E1
J8
A2
A9
D7
G2
G8
K1
K9
M1
M9
B9
C1
E2
E9
C3300 1 C3311 1 1 C3312
E1
J8
A2
A9
D7
G2
G8
K1
K9
M1
M9
B9
C1
E2
E9
E1
J8
A2
A9
D7
G2
G8
K1
K9
M1
M9
B9
C1
E2
E9
0.47UF C3310 1
C3320 C3321 1 1 C3322 C3330 1 C3331 1 1 C3332
VREFDQ
VREFCA
20% 20% VDD VDDQ 20% 0.47UF
VREFDQ
VREFCA
VREFDQ
VREFCA
VREFDQ
VREFCA
2 CERM-X5R 0.47UF 2 0.47UF 2 VDD VDDQ VDD VDDQ
CERM-X5R CERM-X5R
2 4V
CERM-X5R
20%
0.47UF 2 0.47UF 2
20% 20%
4V
20%
0.47UF 2 0.47UF 2
20% 20%
4V
4V 4V 201 201 201 CERM-X5R CERM-X5R 2 CERM-X5R CERM-X5R CERM-X5R 2 CERM-X5R
U3300 4V 4V 201 201 201 201 201 201
FBGA
U3310 4V 4V
U3320
4V 4V
U3330
MEM_B_ODT<0> G1 FBGA
MT41J128M8HX-187E
66 33 30 29 14 ODT OMIT FBGA FBGA

MEM_B_ODT<0> G1
MT41J128M8HX-187E
66 33 30 29 14 ODT OMIT MEM_B_ODT<0> G1 MEM_B_ODT<0> G1
MT41J128M8HX-187E
MT41J128M8HX-187E
MEM_RESET_L N2
66 33 30 29 14 ODT OMIT 66 33 30 29 14 ODT OMIT
30 29 28 27 26 RESET* MEM_RESET_L
66 66 30 29 28 27 26 N2 RESET*
240 66 30 29 28 27 26
R33001 2 MEM_B_ZQ0 H8 ZQ 240
R33101 2 MEM_B_ZQ1 H8 ZQ 240 240
MF 1% 1/20W 201 R33201 2 MEM_B_ZQ2 H8 ZQ R33301 2 MEM_B_ZQ3 H8 ZQ
MF 1% 1/20W 201
66 33 30 29 14 MEM_B_A<0> K3 A0 DQ0 B3 MEM_B_DQ<1> 14 66 MF 1% 1/20W 201 MF 1% 1/20W 201
66 33 30 29 14 MEM_B_A<0> K3 A0 DQ0 B3 MEM_B_DQ<14> 14 66
66 33 30 29 14 MEM_B_A<1> L7 A1 DQ1 C7 MEM_B_DQ<4> 14 66 66 33 30 29 14 MEM_B_A<0> K3 A0 DQ0 B3 MEM_B_DQ<16> 14 66 66 33 30 29 14 MEM_B_A<0> K3 A0 DQ0 B3 MEM_B_DQ<30> 14 66
66 33 30 29 14 MEM_B_A<1> L7 A1 DQ1 C7 MEM_B_DQ<9> 14 66
66 33 30 29 14 MEM_B_A<2> L3 A2 DQ2 C2 MEM_B_DQ<2> 14 66 66 33 30 29 14 MEM_B_A<1> L7 A1 DQ1 C7 MEM_B_DQ<22> 14 66 66 33 30 29 14 MEM_B_A<1> L7 A1 DQ1 C7 MEM_B_DQ<29> 14 66
C 66 33 30 29 14
66 33 30 29 14
MEM_B_A<3>
MEM_B_A<4>
K2
L8
A3
A4
DQ3 C8 MEM_B_DQ<3>
DQ4 E3 MEM_B_DQ<0>
14 66
14 66
66 33 30 29 14
66 33 30 29 14
MEM_B_A<3>
MEM_B_A<4>
K2
L8
A3
A4
DQ3 C8 MEM_B_DQ<12>
DQ4 E3 MEM_B_DQ<10>
14 66
14 66
66 33 30 29 14
66 33 30 29 14
MEM_B_A<2>
MEM_B_A<3>
L3
K2
A2
A3
DQ2 C2 MEM_B_DQ<21>
DQ3 C8 MEM_B_DQ<20>
14 66
14 66
66 33 30 29 14
66 33 30 29 14
MEM_B_A<2>
MEM_B_A<3>
L3
K2
A2
A3
DQ2 C2 MEM_B_DQ<24>
DQ3 C8 MEM_B_DQ<28>
14 66
14 66
C
66 33 30 29 14 MEM_B_A<5> L2 A5 DQ5 E8 MEM_B_DQ<5> 14 66 66 33 30 29 14 MEM_B_A<4> L8 A4 DQ4 E3 MEM_B_DQ<19> 14 66 66 33 30 29 14 MEM_B_A<4> L8 A4 DQ4 E3 MEM_B_DQ<27> 14 66
66 33 30 29 14 MEM_B_A<5> L2 A5 DQ5 E8 MEM_B_DQ<13> 14 66
66 33 30 29 14 MEM_B_A<6> M8 A6 DQ6 D2 MEM_B_DQ<6> 14 66 66 33 30 29 14 MEM_B_A<5> L2 A5 DQ5 E8 MEM_B_DQ<18> 14 66 66 33 30 29 14 MEM_B_A<5> L2 A5 DQ5 E8 MEM_B_DQ<25> 14 66
66 33 30 29 14 MEM_B_A<6> M8 A6 DQ6 D2 MEM_B_DQ<11> 14 66
66 33 30 29 14 MEM_B_A<7> M2 A7 DQ7 E7 MEM_B_DQ<7> 14 66 66 33 30 29 14 MEM_B_A<6> M8 A6 DQ6 D2 MEM_B_DQ<17> 14 66 66 33 30 29 14 MEM_B_A<6> M8 A6 DQ6 D2 MEM_B_DQ<31> 14 66
66 33 30 29 14 MEM_B_A<7> M2 A7 DQ7 E7 MEM_B_DQ<15> 14 66
66 33 30 29 14 MEM_B_A<8> N8 A8 66 33 30 29 14 MEM_B_A<7> M2 A7 DQ7 E7 MEM_B_DQ<23> 14 66 66 33 30 29 14 MEM_B_A<7> M2 A7 DQ7 E7 MEM_B_DQ<26> 14 66
66 33 30 29 14 MEM_B_A<8> N8 A8
66 33 30 29 14 MEM_B_A<9> M3 A9 DQS C3 MEM_B_DQS_P<0> 14 66 66 33 30 29 14 MEM_B_A<8> N8 A8 66 33 30 29 14 MEM_B_A<8> N8 A8
66 33 30 29 14 MEM_B_A<9> M3 A9 DQS C3 MEM_B_DQS_P<1> 14 66
66 33 30 29 14 MEM_B_A<10> H7 A10/AP 66 33 30 29 14 MEM_B_A<9> M3 A9 DQS C3 MEM_B_DQS_P<2> 14 66 66 33 30 29 14 MEM_B_A<9> M3 A9 DQS C3 MEM_B_DQS_P<3> 14 66
DQS* D3 MEM_B_DQS_N<0> 14 66 66 33 30 29 14 MEM_B_A<10> H7 A10/AP
66 33 30 29 14 MEM_B_A<11> M7 A11 DQS* D3 MEM_B_DQS_N<1> 14 66 66 33 30 29 14 MEM_B_A<10> H7 A10/AP 66 33 30 29 14 MEM_B_A<10> H7 A10/AP
66 33 30 29 14 MEM_B_A<11> M7 A11 DQS* D3 MEM_B_DQS_N<2> 14 66 DQS* D3 MEM_B_DQS_N<3> 14 66
66 33 30 29 14 MEM_B_A<12> K7 A12/BC* 66 33 30 29 14 MEM_B_A<11> M7 A11 66 33 30 29 14 MEM_B_A<11> M7 A11
DM/TDQS B7 MEM_B_DM<0> 14 66 66 33 30 29 14 MEM_B_A<12> K7 A12/BC*
66 33 30 29 14 MEM_B_A<13> N3 A13 DM/TDQS B7 MEM_B_DM<1> 14 66 66 33 30 29 14 MEM_B_A<12> K7 A12/BC* 66 33 30 29 14 MEM_B_A<12> K7 A12/BC*
66 33 30 29 14 MEM_B_A<13> N3 A13 DM/TDQS B7 MEM_B_DM<2> 14 66 DM/TDQS B7 MEM_B_DM<3> 14 66
TDQS* A7 NC 66 33 30 29 14 MEM_B_A<13> N3 A13 66 33 30 29 14 MEM_B_A<13> N3 A13
66 33 30 29 14 MEM_B_BA<0> J2 BA0 TDQS* A7 NC
66 33 30 29 14 MEM_B_BA<0> J2 BA0 TDQS* A7 NC TDQS* A7 NC
66 33 30 29 14 MEM_B_BA<1> K8 BA1 66 33 30 29 14 MEM_B_BA<0> J2 BA0 66 33 30 29 14 MEM_B_BA<0> J2 BA0
66 33 30 29 14 MEM_B_BA<1> K8 BA1
MEM_B_BA<2> J3 BA2 A3 MEM_B_BA<1> K8 BA1 MEM_B_BA<1> K8 BA1
66 33 30 29 14 NC MEM_B_BA<2> J3 BA2 A3 66 33 30 29 14 66 33 30 29 14
66 33 30 29 14 NC MEM_B_BA<2> J3 BA2 A3 NC MEM_B_BA<2> J3 BA2 A3 NC
66 33 30 29 14 66 33 30 29 14
66 33 30 29 14 MEM_B_CKE<0> G9 CKE
66 33 30 29 14 MEM_B_CKE<0> G9 CKE
66 33 30 29 14 MEM_B_CKE<0> G9 CKE 66 33 30 29 14 MEM_B_CKE<0> G9 CKE
66 33 30 29 14 MEM_B_CLK_P<0>F7 CK
66 33 30 29 14 MEM_B_CLK_P<0>F7 CK
66 33 30 29 14 MEM_B_CLK_N<0>G7 CK* NC F1 MEM_B_ODT<1> 66 33 30 29 14 MEM_B_CLK_P<0>F7 CK 66 33 30 29 14 MEM_B_CLK_P<0>F7 CK
14 29 30 33 66 33 30 29 14 MEM_B_CLK_N<0>G7 CK* NC F1 MEM_B_ODT<1>
66 14 29 30 33 66 66 33 30 29 14 MEM_B_CLK_N<0>G7 CK* 66 33 30 29 14 MEM_B_CLK_N<0>G7 CK*
66 33 30 29 14 MEM_B_CS_L<0> H2 CS* F9 MEM_B_CKE<1> 14 29 30 33 66
NC F1 MEM_B_ODT<1> 14 29 30 33 66
NC F1 MEM_B_ODT<1> 14 29 30 33
66 33 30 29 14 MEM_B_CS_L<0> H2 CS* F9 MEM_B_CKE<1> 14 29 30 33 66 66
H9 MEM_B_ZQ0 29 66 33 30 29 14 MEM_B_CS_L<0> H2 CS* F9 MEM_B_CKE<1> 14 29 30 33 66 33 30 29 14 MEM_B_CS_L<0> H2 CS* F9 MEM_B_CKE<1> 14 29 30 33
66 33 30 29 14 MEM_B_CS_L<1> H1 NC H9 MEM_B_ZQ1 29 66 66
N7 66 33 30 29 14 MEM_B_CS_L<1> H1 NC H9 MEM_B_ZQ2 29 H9 MEM_B_ZQ3 29
N7 66 33 30 29 14 MEM_B_CS_L<1> H1 NC 66 33 30 29 14 MEM_B_CS_L<1> H1 NC
MEM_B_RAS_L F3 RAS* J7 MEM_B_A<14> N7 N7
66 33 30 29 14 NC 14 29 30 33 66
MEM_B_RAS_L F3 J7 NC MEM_B_A<14>
66 33 30 29 14 RAS* 14 29 30 33 66
J7 NC MEM_B_A<14> J7 NC MEM_B_A<14>
66 33 30 29 14 MEM_B_RAS_L F3 RAS* 14 29 30 66 33 30 29 14 MEM_B_RAS_L F3 RAS* 14 29 30 33 66
66 33 30 29 14 MEM_B_CAS_L G3 CAS* 33 66
66 33 30 29 14 MEM_B_CAS_L G3 CAS*
66 33 30 29 14 MEM_B_CAS_L G3 CAS* 66 33 30 29 14 MEM_B_CAS_L G3 CAS*
66 33 30 29 14 MEM_B_WE_L H3 WE*
66 33 30 29 14 MEM_B_WE_L H3 WE*
66 33 30 29 14 MEM_B_WE_L H3 WE* 66 33 30 29 14 MEM_B_WE_L H3 WE*
B VSS VSSQ
VSS VSSQ
VSS VSSQ VSS VSSQ B
A1
A8
B1
D8
F2
F8
J1
J9
L1
L9
N1
N9
B2
B8
C9
D1
D9
A1
A8
B1
D8
F2
F8
J1
J9
L1
L9
N1
N9
B2
B8
C9
D1
D9
A1
A8
B1
D8
F2
F8
J1
J9
L1
L9
N1
N9
B2
B8
C9
D1
D9
A1
A8
B1
D8
F2
F8
J1
J9
L1
L9
N1
N9
B2
B8
C9
D1
D9
DDR3 DRAM Channel B (0-31)

SYNC_DATE=(MASTER)
A
D 051-7631 2.3.0

NONE 29 71
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
29 28 27 25 PP0V75_S3_MEM_VREFCA
70 30 70 30 29 28 27 25 PP0V75_S3_MEM_VREFCA
29 28 27 25 PP0V75_S3_MEM_VREFDQ =PP1V5_S3_MEM_B
70 30 70 30 29 28 27 25 PP0V75_S3_MEM_VREFDQ =PP1V5_S3_MEM_B
70 30 29 28 27 25 PP0V75_S3_MEM_VREFDQ =PP1V5_S3_MEM_B 70 30 29 28 27 25 PP0V75_S3_MEM_VREFDQ =PP1V5_S3_MEM_B
E1
J8
A2
A9
D7
G2
G8
K1
K9
M1
M9
B9
C1
E2
E9
1 C3401 1 1 C3402
E1
J8
A2
A9
D7
G2
G8
K1
K9
M1
M9
B9
C1
E2
E9
C3400 1 C3411 1 1 C3412
E1
J8
A2
A9
D7
G2
G8
K1
K9
M1
M9
B9
C1
E2
E9
E1
J8
A2
A9
D7
G2
G8
K1
K9
M1
M9
B9
C1
E2
E9
0.47UF C3410 1
C3420 C3421 1 1 C3422 C3430 1 C3431 1 1 C3432
VREFDQ
VREFCA
20% 20% VDD VDDQ 20% 0.47UF
VREFDQ
VREFCA
VREFDQ
VREFCA
VREFDQ
VREFCA
CERM-X5R CERM-X5R 2 CERM-X5R 0.47UF 2 0.47UF 2 4V 20% 20% VDD VDDQ 20% 20% 20% VDD VDDQ 20%
201 2 CERM-X5R 0.47UF 2 0.47UF 2 4V 0.47UF 2 0.47UF 2
201
4V
201
4V
CERM-X5R CERM-X5R
2 CERM-X5R CERM-X5R CERM-X5R
2 4V
CERM-X5R
U3400 4V 4V
U3410
201
4V
201
4V
201 201
4V
201
4V
201
MEM_B_ODT<0> G1
FBGA
FBGA
U3420 U3430
MT41J128M8HX-187E
66 33 30 29 14 ODT OMIT MEM_B_ODT<0> G1 FBGA FBGA
MT41J128M8HX-187E
66 33 30 29 14 ODT OMIT
MEM_B_ODT<0> G1 MEM_B_ODT<0> G1
MT41J128M8HX-187E
MT41J128M8HX-187E
66 33 30 29 14 ODT OMIT 66 33 30 29 14 ODT OMIT
66 30 29 28 27 26
240 66 30 29 28 27 26
R34001 2 MEM_B_ZQ8H8 ZQ 240
R34101 2 MEM_B_ZQ9 H8 ZQ 240 240
MF 1% 1/20W 201 R34201 2 MEM_B_ZQ10 H8 ZQ R34301 2 MEM_B_ZQ11 H8 ZQ
MF 1% 1/20W 201
66 33 30 29 14 MEM_B_A<0> K3 A0 DQ0 B3 MEM_B_DQ<38> 14 66 MF 1% 1/20W 201 MF 1% 1/20W 201
66 33 30 29 14 MEM_B_A<0> K3 A0 DQ0 B3 MEM_B_DQ<43> 14 66
66 33 30 29 14 MEM_B_A<1> L7 A1 DQ1 C7 MEM_B_DQ<33> 14 66 66 33 30 29 14 MEM_B_A<0> K3 A0 DQ0 B3 MEM_B_DQ<49> 14 66 66 33 30 29 14 MEM_B_A<0> K3 A0 DQ0 B3 MEM_B_DQ<61> 14 66
66 33 30 29 14 MEM_B_A<2> L3 A2 DQ2 C2 MEM_B_DQ<35> 14 66 66 33 30 29 14 MEM_B_A<1> L7 A1 DQ1 C7 MEM_B_DQ<53> 14 66 66 33 30 29 14 MEM_B_A<1> L7 A1 DQ1 C7 MEM_B_DQ<57> 14 66
66 33 30 29 14 MEM_B_A<3> K2 A3 DQ3 C8 MEM_B_DQ<32> 14 66 66 33 30 29 14 MEM_B_A<2> L3 A2 DQ2 C2 MEM_B_DQ<55> 14 66 66 33 30 29 14 MEM_B_A<2> L3 A2 DQ2 C2 MEM_B_DQ<58> 14 66
C 66 33 30 29 14
66 33 30 29 14
MEM_B_A<4>
MEM_B_A<5>
L8
L2
A4
A5
DQ4 E3 MEM_B_DQ<37>
DQ5 E8 MEM_B_DQ<36>
14 66
14 66
66 33 30 29 14
66 33 30 29 14
MEM_B_A<3>
MEM_B_A<4>
K2
L8
A3
A4
DQ3 C8 MEM_B_DQ<47>
DQ4 E3 MEM_B_DQ<44>
14 66
14 66
66 33 30 29 14
66 33 30 29 14
MEM_B_A<3>
MEM_B_A<4>
K2
L8
A3
A4
DQ3 C8 MEM_B_DQ<48>
DQ4 E3 MEM_B_DQ<50>
14 66
14 66
66 33 30 29 14
66 33 30 29 14
MEM_B_A<3>
MEM_B_A<4>
K2
L8
A3
A4
DQ3 C8 MEM_B_DQ<56>
DQ4 E3 MEM_B_DQ<59>
14 66
14 66
C
66 33 30 29 14 MEM_B_A<5> L2 A5 DQ5 E8 MEM_B_DQ<45> 14 66
66 33 30 29 14 MEM_B_A<6> M8 A6 DQ6 D2 MEM_B_DQ<34> 14 66 66 33 30 29 14 MEM_B_A<5> L2 A5 DQ5 E8 MEM_B_DQ<51> 14 66 66 33 30 29 14 MEM_B_A<5> L2 A5 DQ5 E8 MEM_B_DQ<60> 14 66
66 33 30 29 14 MEM_B_A<6> M8 A6 DQ6 D2 MEM_B_DQ<46> 14 66
66 33 30 29 14 MEM_B_A<7> M2 A7 DQ7 E7 MEM_B_DQ<39> 14 66 66 33 30 29 14 MEM_B_A<6> M8 A6 DQ6 D2 MEM_B_DQ<54> 14 66 66 33 30 29 14 MEM_B_A<6> M8 A6 DQ6 D2 MEM_B_DQ<62> 14 66
66 33 30 29 14 MEM_B_A<7> M2 A7 DQ7 E7 MEM_B_DQ<40> 14 66
66 33 30 29 14 MEM_B_A<8> N8 A8 66 33 30 29 14 MEM_B_A<7> M2 A7 DQ7 E7 MEM_B_DQ<52> 14 66 66 33 30 29 14 MEM_B_A<7> M2 A7 DQ7 E7 MEM_B_DQ<63> 14 66
66 33 30 29 14 MEM_B_A<8> N8 A8
66 33 30 29 14 MEM_B_A<9> M3 A9 DQS C3 MEM_B_DQS_P<4> 14 66 66 33 30 29 14 MEM_B_A<8> N8 A8 66 33 30 29 14 MEM_B_A<8> N8 A8
66 33 30 29 14 MEM_B_A<9> M3 A9 DQS C3 MEM_B_DQS_P<5> 14 66
66 33 30 29 14 MEM_B_A<10> H7 A10/AP 66 33 30 29 14 MEM_B_A<9> M3 A9 DQS C3 MEM_B_DQS_P<6> 14 66 66 33 30 29 14 MEM_B_A<9> M3 A9 DQS C3 MEM_B_DQS_P<7> 14 66
DQS* D3 MEM_B_DQS_N<4> 14 66 66 33 30 29 14 MEM_B_A<10> H7 A10/AP
66 33 30 29 14 MEM_B_A<11> M7 A11 DQS* D3 MEM_B_DQS_N<5> 14 66 66 33 30 29 14 MEM_B_A<10> H7 A10/AP 66 33 30 29 14 MEM_B_A<10> H7 A10/AP
66 33 30 29 14 MEM_B_A<11> M7 A11 DQS* D3 MEM_B_DQS_N<6> 14 66 DQS* D3 MEM_B_DQS_N<7> 14 66
66 33 30 29 14 MEM_B_A<12> K7 A12/BC* 66 33 30 29 14 MEM_B_A<11> M7 A11 66 33 30 29 14 MEM_B_A<11> M7 A11
DM/TDQS B7 MEM_B_DM<4> 14 66 66 33 30 29 14 MEM_B_A<12> K7 A12/BC*
66 33 30 29 14 MEM_B_A<13> N3 A13 DM/TDQS B7 MEM_B_DM<5> 14 66 66 33 30 29 14 MEM_B_A<12> K7 A12/BC* 66 33 30 29 14 MEM_B_A<12> K7 A12/BC*
66 33 30 29 14 MEM_B_A<13> N3 A13 DM/TDQS B7 MEM_B_DM<6> 14 66 DM/TDQS B7 MEM_B_DM<7> 14 66
TDQS* A7 NC 66 33 30 29 14 MEM_B_A<13> N3 A13 66 33 30 29 14 MEM_B_A<13> N3 A13
66 33 30 29 14 MEM_B_BA<0> J2 BA0 TDQS* A7 NC
66 33 30 29 14 MEM_B_BA<0> J2 BA0 TDQS* A7 NC TDQS* A7 NC
66 33 30 29 14 MEM_B_BA<1> K8 BA1 66 33 30 29 14 MEM_B_BA<0> J2 BA0 66 33 30 29 14 MEM_B_BA<0> J2 BA0
66 33 30 29 14 MEM_B_BA<1> K8 BA1
66 33 30 29 14 MEM_B_BA<2> J3 BA2 A3 MEM_B_BA<1> K8 BA1 MEM_B_BA<1> K8 BA1
NC MEM_B_BA<2> J3 A3 66 33 30 29 14 66 33 30 29 14
66 33 30 29 14 BA2 NC A3 A3
66 33 30 29 14 MEM_B_BA<2> J3 BA2 NC 66 33 30 29 14 MEM_B_BA<2> J3 BA2 NC
66 33 30 29 14 MEM_B_CKE<0> G9 CKE
66 33 30 29 14 MEM_B_CKE<0> G9 CKE
66 33 30 29 14 MEM_B_CKE<0> G9 CKE 66 33 30 29 14 MEM_B_CKE<0> G9 CKE
66 33 30 29 14 MEM_B_CLK_P<0>F7 CK
66 33 30 29 14 MEM_B_CLK_P<0>F7 CK
66 33 30 29 14 MEM_B_CLK_N<0>G7 CK* 66 33 30 29 14 MEM_B_CLK_P<0>F7 CK 66 33 30 29 14 MEM_B_CLK_P<0>F7 CK
NC F1 MEM_B_ODT<1> 14 29 30 33 66 33 30 29 14 MEM_B_CLK_N<0>G7 CK*
66 NC F1 MEM_B_ODT<1> 14 29 30 33 66 66 33 30 29 14 MEM_B_CLK_N<0>G7 CK* 66 33 30 29 14 MEM_B_CLK_N<0>G7 CK*
NC F1 MEM_B_ODT<1> 14 29 30 33 66
NC F1 MEM_B_ODT<1> 14 29 30 33 66
H9 MEM_B_ZQ8 30 66 33 30 29 14 MEM_B_CS_L<0> H2 CS* F9 MEM_B_CKE<1> 14 29 30 33 66 33 30 29 14 MEM_B_CS_L<0> H2 CS* F9 MEM_B_CKE<1> 14 29 30 33 66
66 33 30 29 14 MEM_B_CS_L<1> H1 NC H9 MEM_B_ZQ9 30 66
N7 66 33 30 29 14 MEM_B_CS_L<1> H1 NC H9 MEM_B_ZQ10 30 H9 MEM_B_ZQ11 30
N7 66 33 30 29 14 MEM_B_CS_L<1> H1 NC 66 33 30 29 14 MEM_B_CS_L<1> H1 NC
66 33 30 29 14 MEM_B_RAS_L F3 RAS* J7 NC N7 N7
MEM_B_RAS_L F3 RAS* J7
MEM_B_A<14>
66 33 30 29 14 NC MEM_B_RAS_L F3 J7 NC MEM_B_RAS_L F3 J7 NC
14 29 30 33 66 66 33 30 29 14 RAS* 66 33 30 29 14 RAS*
66 33 30 29 14 MEM_B_CAS_L G3 CAS* MEM_B_A<14> 14 29 30 33 66
66 33 30 29 14 MEM_B_CAS_L G3 CAS* MEM_B_A<14> 14 29 30 33 66 MEM_B_A<14> 14 29 30 33
66 33 30 29 14 MEM_B_CAS_L G3 CAS* 66 33 30 29 14 MEM_B_CAS_L G3 CAS* 66
66 33 30 29 14 MEM_B_WE_L H3 WE*
66 33 30 29 14 MEM_B_WE_L H3 WE*
VSS VSSQ 66 33 30 29 14 MEM_B_WE_L H3 WE* 66 33 30 29 14 MEM_B_WE_L H3 WE*
B VSS VSSQ
VSS VSSQ VSS VSSQ B
A1
A8
B1
D8
F2
F8
J1
J9
L1
L9
N1
N9
B2
B8
C9
D1
D9
A1
A8
B1
D8
F2
F8
J1
J9
L1
L9
N1
N9
B2
B8
C9
D1
D9
A1
A8
B1
D8
F2
F8
J1
J9
L1
L9
N1
N9
B2
B8
C9
D1
D9
A1
A8
B1
D8
F2
F8
J1
J9
L1
L9
N1
N9
B2
B8
C9
D1
D9
DDR3 DRAM Channel B (32-63)

A
D 051-7631 2.3.0

NONE 30 71
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D 33 31 28 27 7 =PP1V5_S3_MEM_A 33 31 28 27 7 =PP1V5_S3_MEM_A D
OMIT OMIT
OMIT OMIT OMIT OMIT
1 C3500 1 C3510 1 C3520 1 C3530 1 C3540 1 C3550
2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF
20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
402-LF 402-LF 402-LF 402-LF 402-LF 402-LF
OMIT OMIT OMIT OMIT OMIT OMIT

1 C3501 1 C3511 1 C3521 1 C3531 1 C3541 1 C3551
2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF
20% 20% 20% 20% 20% 20%
6.3V
2 CERM 6.3V
2 CERM 6.3V
2 CERM 6.3V
2 CERM 6.3V
2 CERM 6.3V
2 CERM
402-LF 402-LF 402-LF 402-LF 402-LF 402-LF
OMIT OMIT
1 C3512 1 C3542
2.2UF 2.2UF
2 CAPS ALONG PACKAGE EDGE 20% 20% 2 CAPS ALONG PACKAGE EDGE
2 6.3V
CERM 2 6.3V
CERM
402-LF 402-LF
C C
OMIT
OMIT OMIT OMIT OMIT OMIT
1 C3504 1 C3514 1 C3524 1 C3534 1 C3544 1 C3554
2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF
20% 20% 20% 20% 20% 20%
2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
402-LF 402-LF 402-LF 402-LF 402-LF 402-LF
OMIT
OMIT OMIT OMIT OMIT OMIT
1 C3505 1 C3515 1 C3525 1 C3535 1 C3545 1 C3555
2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF
20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
402-LF 402-LF 402-LF 402-LF 402-LF 402-LF
OMIT OMIT
1 C3516 1 C3546
2.2UF 2.2UF
20% 20%
6.3V 6.3V
2 CERM 2 CERM
402-LF 402-LF
COLUMN OF THREE CAPS BETWEEN PACKAGES COLUMN OF THREE CAPS BETWEEN PACKAGES
B B
APPROXIMATE CAP ARRANGEMENT
TWO 0402 CAPS ALONG PACKAGE EDGE
DDR BYPASSING 1
A SYNC_MASTER=MEMORY

A
COLUMN OF THREE 0402 CAPS BETWEEN PACKAGES D 051-7631 2.3.0

NONE 31 71
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D 33 32 30 29 7 =PP1V5_S3_MEM_B 33 32 30 29 7 =PP1V5_S3_MEM_B D
C3600 1 C3610 1 C3620 1 C3630 1 C3640 1 C3650
2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF
20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
402-LF 402-LF 402-LF 402-LF 402-LF 402-LF

1 C3601 1 C3611 1 C3621 1 C3631 1 C3641 1 C3651
2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF
20% 20% 20% 20% 20% 20%
6.3V
2 CERM 6.3V
2 CERM 6.3V
2 CERM 6.3V
2 CERM 6.3V
2 CERM 6.3V
2 CERM
402-LF 402-LF 402-LF 402-LF 402-LF 402-LF
OMIT OMIT
1 C3612 1 C3642
2.2UF 2.2UF
2 CAPS ALONG PACKAGE EDGE 20% 20% 2 CAPS ALONG PACKAGE EDGE
2 6.3V
CERM 2 6.3V
CERM
402-LF 402-LF
C C
1 C3604 1 C3614 1 C3624 1 C3634 1 C3644 1 C3654
2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF
20% 20% 20% 20% 20% 20%
2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
402-LF 402-LF 402-LF 402-LF 402-LF 402-LF

1 C3605 1 C3615 1 C3625 1 C3635 1 C3645 1 C3655
2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF
20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
402-LF 402-LF 402-LF 402-LF 402-LF 402-LF
OMIT OMIT
1 C3616 1 C3646
2.2UF 2.2UF
20% 20%
6.3V 6.3V
2 CERM 2 CERM
402-LF 402-LF
COLUMN OF THREE CAPS BETWEEN PACKAGES COLUMN OF THREE CAPS BETWEEN PACKAGES
B APPROXIMATE CAP ARRANGEMENT

B
TWO 0402 CAPS ALONG PACKAGE EDGE
DDR BYPASSING 2
A SYNC_MASTER=MEMORY

A
COLUMN OF THREE 0402 CAPS BETWEEN PACKAGES SIZE DRAWING NUMBER REV.
D 051-7631 2.3.0

NONE 32 71
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
JEDEC recommends 30 Ohm term to VTT for CS,CKE,ODT and 36 Ohm for BA,A,RAS,CAS,WE
MEM CLOCK TERMINATION
Place RC end termination after last DRAM 7 =PP0V75_S0_MEM_VTT_A
Place Source Cterm at neckdown at first DRAM
MEM_A_WE_L RP3702 36 1 8
R3700 C3700 66 28 27 14 IN
RP3702 36 5% 1/32W 4X0201
30 66 28 27 14 IN MEM_A_BA<0> 2 7 1 C3710
2
MEM_A_CLK_N<0> 1 2 MEM_A_CLK_TERM_R =PP1V5_S3_MEM_A RP3706 5% 1/32W 4X0201
66 28 27 14
VOLTAGE=0V
7 27 28 31
66 28 27 14 IN MEM_A_BA<1> 36 4 5 0.47UF
20%
5%
1/20W 0.1UF 66 28 27 14 MEM_A_BA<2> RP3702 36 3 6 5% 1/32W 4X0201
2 4V
C3704 1 MF
201
10%
X5R
IN
MEM_A_RAS_L RP3701 36 1 8 5% 1/32W 4X0201
CERM-X5R
201
3.3PF 66 28 27 14
D 5%
25V
CERM 2 R3701
201
6.3V 66 28 27 14
IN
IN MEM_A_CAS_L RP3701 36 3 6 5% 1/32W
5% 1/32W
4X0201
4X0201
D
201 30
66 28 27 14 MEM_A_CLK_P<0> 1 2
MEM_A_A<0> RP3702 36 4 5
1 C3712 1 C3713
5%
66 28 27 14 IN
RP3707 5% 1/32W 4X0201
0.47UF 0.47UF
1/20W 66 28 27 14 IN MEM_A_A<1> 36 3 6 20% 20%
MF RP3704 5% 1/32W 4X0201 2 4V 2 4V
201 66 28 27 14 IN MEM_A_A<2> 36 1 8 CERM-X5R
201
CERM-X5R
201
66 28 27 14 IN MEM_A_A<3> R3792 36 1 2
5% 1/32W 4X0201
66 28 27 14 MEM_A_A<4>
RP3707 36 2 7 5% 1/20W 201
IN
R3704 C3702 66 28 27 14 IN MEM_A_A<5> R3793 36 1 2
5% 1/32W 4X0201 1 C3714 1 C3715
30 RP3703 36 5% 1/20W 201 0.47UF 0.47UF
2
66 30 29 14 MEM_B_CLK_N<0> 1 2 MEM_B_CLK_TERM_R =PP1V5_S3_MEM_B 7 29 30 32 66 28 27 14 MEM_A_A<6> 2 7
IN 20% 20%
5%
VOLTAGE=0V
66 28 27 14 MEM_A_A<7>
RP3704 36 3 6 5% 1/32W 4X0201 4V
2 CERM-X5R
4V
2 CERM-X5R
0.1UF IN
C3706 1 1/20W
MF 10% 66 28 27 14 MEM_A_A<8>
RP3703 36 4 5 5% 1/32W 4X0201 201 201
X5R IN
3.3PF 201
201 66 28 27 14 MEM_A_A<9>
RP3704 36 2 7 5% 1/32W 4X0201
5% 6.3V IN
25V RP3706 36 3 6 5% 1/32W 4X0201
CERM 2 R3705 66 28 27 14 IN MEM_A_A<10>
RP3703 5% 1/32W 4X0201
MEM_B_CLK_P<0>
201
1
30 2
66 28 27 14 IN MEM_A_A<11>
RP3703
36 3 6
5% 1/32W 4X0201
1 C3716 1 C3717
66 30 29 14
66 28 27 14 IN MEM_A_A<12> 36 1 8 0.47UF 0.47UF
20% 20%
5%
1/20W 66 28 27 14 MEM_A_A<13>
RP3704 36 4 5 5% 1/32W 4X0201 4V
2 CERM-X5R
4V
2 CERM-X5R
MF IN
5% 1/32W 4X0201 201 201
201
66 28 27 14 MEM_A_CS_L<0> R3790 36 1 2 1 C3718

IN
Unused Clock Termination MEM_A_CS_L<1> R3791 36 1 2
5% 1/20W 201 0.47UF
IN 20%
66 28 27 14 MEM_A_CKE<0>
RP3706 36 2 7 5% 1/20W 201
2 4V
IN CERM-X5R
14 MEM_A_CLK_N<1>
66 28 27 14 MEM_A_CKE<1>
RP3706 36 1 8 5% 1/32W 4X0201 201
IN
66 28 27 14 MEM_A_ODT<0>
RP3701 36 4 5 5% 1/32W 4X0201
1 IN
R3706 66 28 27 14 IN MEM_A_ODT<1>
RP3701 36 2 7 5% 1/32W 4X0201
75 RP3707 36 5% 1/32W 4X0201
5% 66 28 27 14 IN MEM_A_A<14> 1 8 1 C3720
C 1/20W
MF
2 201
5% 1/32W 4X0201 0.47UF
20%
2 4V
C
CERM-X5R
MEM_A_CLK_P<1> 201
14
14 MEM_B_CLK_N<1>
1
R3707
75
5%
1/20W
MF
2 201 =PP0V75_S0_MEM_VTT_B
7
14 MEM_B_CLK_P<1>
66 30 29 14 MEM_B_WE_L RP3715 36 3 6
IN
66 30 29 14 MEM_B_BA<0> RP3715 36 4 5 5% 1/32W 4X0201 1 C3722
IN
66 30 29 14 MEM_B_BA<1> RP3711 36 1 8 5% 1/32W 4X0201 0.47UF
IN 20%
66 30 29 14 MEM_B_BA<2> RP3709 36 1 8 5% 1/32W 4X0201 4V
2 CERM-X5R
IN
66 30 29 14 MEM_B_RAS_L RP3715 36 2 7 5% 1/32W 4X0201 201
IN
66 30 29 14 MEM_B_CAS_L RP3715 36 1 8 5% 1/32W 4X0201
IN
5% 1/32W 4X0201
MEM_B_A<0> RP3709 36 3 6
1 C3724
66 30 29 14 IN
RP3710 5% 1/32W 4X0201
0.47UF
66 30 29 14 IN MEM_B_A<1> 36 3 6 20%
4V
66 30 29 14 MEM_B_A<2>
RP3708 36 1 8 5% 1/32W 4X0201 2 CERM-X5R
IN 201
66 30 29 14 MEM_B_A<3>
RP3709 36 2 7 5% 1/32W 4X0201
IN
66 30 29 14 MEM_B_A<4>
RP3711 36 2 7 5% 1/32W 4X0201
IN
66 30 29 14 MEM_B_A<5>
RP3709 36 4 5 5% 1/32W 4X0201
IN
66 30 29 14 MEM_B_A<6>
RP3711 36 3 6 5% 1/32W 4X0201 1 C3726 1 C3727
B 66 30 29 14
IN
IN MEM_B_A<7>
RP3708
RP3711
36
36
2
4
7
5
5% 1/32W
5% 1/32W
4X0201
4X0201
0.47UF
20%
4V
0.47UF
20%
4V
B
66 30 29 14 IN MEM_B_A<8> 2 CERM-X5R 2 CERM-X5R
66 30 29 14 MEM_B_A<9>
RP3708 36 3 6 5% 1/32W 4X0201 201 201
IN
66 30 29 14 MEM_B_A<10>
RP3713 36 4 5 5% 1/32W 4X0201
IN
66 30 29 14 MEM_B_A<11>
RP3710 36 2 7 5% 1/32W 4X0201
IN
66 30 29 14 MEM_B_A<12>
RP3710 36 4 5 5% 1/32W 4X0201 1 C3728 1 C3729
IN
66 30 29 14 MEM_B_A<13>
RP3708 36 4 5 5% 1/32W 4X0201 0.47UF 0.47UF
IN 20% 20%
66 30 29 14 MEM_B_A<14>
RP3710 36 1 8 5% 1/32W 4X0201 4V
2 CERM-X5R
4V
2 CERM-X5R
IN
5% 1/32W 4X0201 201 201
MEM_B_CS_L<0>
RP3714 36 1 8
66 30 29 14 IN
MEM_B_CS_L<1>
RP3714 36 2 7 5% 1/32W 4X0201
1 C3730
66 30 29 14 IN
RP3713 5% 1/32W 4X0201 0.47UF
66 30 29 14 IN MEM_B_CKE<0> 36 3 6 20%
RP3713 5% 1/32W 4X0201 2 4V
66 30 29 14 IN MEM_B_CKE<1> 36 2 7 CERM-X5R
201
66 30 29 14 MEM_B_ODT<0>
RP3714 36 3 6 5% 1/32W 4X0201
IN
66 30 29 14 MEM_B_ODT<1>
RP3714 36 4 5 5% 1/32W 4X0201
IN
5% 1/32W 4X0201 1 C3732 1 C3733
0.47UF 0.47UF
20% 20%
4V 4V
2 CERM-X5R 2 CERM-X5R
201 201
Memory Active Termination

A
D 051-7631 2.3.0

NONE 33 71
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
CRITICAL
Q4101
FDC638P_G
SM
M93 WIRELESS
L4104
AIRPORT & BT CONNECTOR
6 FERR-120-OHM-1.5A
0402-LF
5
34 7 =PP3V3_S5_AIRPORT_AUX
4
2 70 6 PP3V3_S3_AP_AUX 2 1 70 PP3V3_S3_AP_AUX_F
34 7 =PP3V3_S5_AIRPORT_AUX 1 MIN_NECK_WIDTH=0.2MM MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.2MM MIN_LINE_WIDTH=0.2MM
R4104
1 C4108 1 C4107 1 C4109 1 C4110

100K 2
1/20W
1 C4111 3 0.1UF 0.1UF 10UF 0.1UF

201
10% 10% 20% 10%

5%
MF
33NF 2 6.3V 2 6.3V 2 6.3V 2 6.3V

10% X5R X5R X5R X5R
2 25V 201 201 603 201
7 =PP3V3_S3_BT
1
CERM
R4105 402 C4112 OMIT
PM_WLAN_EN_L 2 100K 1 PM_WLAN_EN_L_SS
2
5%
0.01UF
C Q4102 D 6 Q4102 D 3
1/20W
MF
201
10V
201
10%
C
X5R
SSM6N15FEAPE SSM6N15FEAPE
SOT563 SOT563
CRITICAL
PM_SLP_S3_L
2 G S 1 5 G S 4 L4101
90-OHM-100MA
56 39 35 20 6
DLP11S
PM_WLAN_EN_L2 4 3
OUT PCIE_E_D2R_N
SYM_VER-2
8
SMC_ADAPTER_PRESENT 34 CRITICAL
J4100
D 6 CPB6330-0101F
Q4103 34 OUT PCIE_E_D2R_P 1 2
F-ST-SM
SSM6N15FEAPE 31 32
SOT563
CRITICAL 1 2
2 G S 1
L4100
90-OHM-100MA
6 PCIE_E_D2R_N_F 3 4 MINI_CLKREQ_L OUT 16
DLP11S 6 PCIE_E_D2R_P_F 5 6 PCIE_WAKE_L 6 16
PCIE_CLK100M_MINI_P 4 SYM_VER-2 3 IN
67 16 IN 7 8 AIRPORT_RST_L 6 24
PM_WLAN_EN_L1 IN
6 PCIE_CLK100M_MINI_P_F 9 10
20
AP_PWR_EN 67 16 PCIE_CLK100M_MINI_N 1 2 6 PCIE_CLK100M_MINI_N_F 11 12 =SMB_AIRPORT_CLK 6 42
IN BI
13 14 =SMB_AIRPORT_DATA
Q4103 D 3 BI 6 42
15 16
SSM6N15FEAPE CRITICAL
SOT563 L4103 17 18
90-OHM-100MA 19 20
DLP11S
8 =USB2_BT_P 4 SYM_VER-2 3 USB2_BT_P_F 21 22
BI
5 G S 4 23 24
25 26
8 =USB2_BT_N 1 2 USB2_BT_N_F
BI 27 28
B PM_SLP_S4_L
29 30 B
56 40 39 20
CRITICAL 33 34
L4102
90-OHM-100MA
C4100 DLP11S
34 PCIE_E_R2D_C_N 1 2 0.1UF PCIE_E_R2D_N 4 SYM_VER-2 36 PCIE_E_R2D_C_N_F
IN X5R 201
10% 6.3V
C4101 PCIE_E_R2D_P 1 26 PCIE_E_R2D_C_P_F

34 PCIE_E_R2D_C_P 1 2 0.1UF
IN X5R 201
10% 6.3V
PLACE FILTERS NEAR CONNECTOR
67 16 PCIE_MINI_D2R_N PCIE_E_D2R_N 34
PLACE C4100,C4101 < 250 MILS FROM MCP
MAKE_BASE=TRUE
67 16 PCIE_MINI_D2R_P
67 16 PCIE_MINI_R2D_C_N
PCIE_E_D2R_P
PCIE_E_R2D_C_N MAKE_BASE=TRUE
34
34
MAKE_BASE=TRUE
APN:516S0580
67 16
PCIE_MINI_R2D_C_P PCIE_E_R2D_C_P 34
MAKE_BASE=TRUE
Wireless M93 Connector

A
D 051-7631 2.3.0

NONE 34 71
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
Micro-DisplayPort / USB to RIO Hatch Assembly

CRITICAL
J4200
54102-8640
F-ST-SM
1 2
C 67 61
67 61
DP_ML_F_P<0>
DP_ML_F_N<0>
3
5
7
4
6
8
Audio Connector C
DP_CA_DET_Q 6 61
67 61 DP_ML_F_P<3> 9 10
67 61 DP_ML_F_N<3> 11 12 7 6 =PPVIN_S0_AUDIO CRITICAL
13 14 HDMI_CEC 6 61 J4260
67 61 DP_ML_F_P<1> 15 16 QT500166-L020
M-ST-SM
67 61 DP_ML_F_N<1> 17 18
68 20 6 HDA_SYNC 1 2 HDA_SDIN0 6 20 68
19 20 DP_HPD_Q 6 IN OUT
61
3 4
67 61 DP_ML_F_P<2> 21 22
68 20 6 HDA_SDOUT 5 6 AUD_MIC_CLK 6 59
DP_ML_F_N<2> 23 24 IN IN
67 61
68 20 HDA_RST_L 7 8
25 26 PP3V3_S0_DPPWR 6 IN
61 70
56 39 34 20 6 PM_SLP_S3_L 9 10 AUD_MIC_DATA 6 59
DP_AUX_CH_C_P 27 28 IN OUT
67 61 60 6
11 12
67 61 60 6 DP_AUX_CH_C_N 29 30
13 14 HDA_BIT_CLK 6 20 68
31 32 IN
15 16
33 34 PP5V_S3_USB2_EXTA_F 6 37 70
37 6 USB2_EXTA_F_P 35 36
37 6 USB2_EXTA_F_N 37 38
39 40
516S0350
B B
516S0710
Hatch and Audio Connectors


SYNC_DATE=(MASTER)
A
D 051-7631 2.3.0

NONE 35 71
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
SATA HDD PORT

CRITICAL
L4500
FERR-120-OHM-1.5A
70 6 PP3V3_S0_HDD_F 1 2 =PP3V3_S0_HDD 7
MIN_LINE_WIDTH=0.25 MM 0402-LF
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=3.3V PLACEMENT_NOTE=PLACE L4500 CLOSE TO J4501
PLACEMENT_NOTE=PLACE C4501 CLOSE TO J4500

1 C4501 1 C4502 PLACEMENT_NOTE=PLACE C4502 CLOSE TO J4500
0.1UF 0.1UF
10% 10%
2 6.3V
X5R 2 6.3V
X5R
201 201
C CRITICAL C
FL4501 PLACEMENT_NOTE=Place C4510 close to MCP79
PLACEMENT_NOTE=Place C4511 next to C4510
90-OHM-100MA
DLP11S
3 SYM_VER-2 4 67 SATA_HDD_R2D_UF_P C4510 1 2 SATA_HDD_R2D_C_P IN 19 67
4700PF 10% 10V X7R 201

CRITICAL
J4500 2 1 67 SATA_HDD_R2D_UF_N C4511 1 2 SATA_HDD_R2D_C_N IN 19 67
10% 10V X7R 201
54167-0201 PLACEMENT_NOTE=Place FL4501 close to J4501 4700PF
F-ST-SM
2 1
4 3
6 5
8 7 67 6 SATA_HDD_R2D_P
10 9 67 6 SATA_HDD_R2D_N
12 11
14 13
16 15 67 6 SATA_HDD_D2R_C_N
18 17 67 6 SATA_HDD_D2R_C_P
20 19
CRITICAL
FL4502
90-OHM-100MA
DLP11S
C4515 1 2 67 SATA_HDD_D2R_UF_N 4 SYM_VER-2 3 SATA_HDD_D2R_N OUT 19 67
4700PF 10% 10V X7R 201
C4516 1 2 67 SATA_HDD_D2R_UF_P 1 2 SATA_HDD_D2R_P OUT 19 67
B 4700PF 10% 10V
PLACEMENT_NOTE=Place C4515 next to C4516

X7R 201 PLACEMENT_NOTE=Place FL4502 close to MCP79
B
PLACEMENT_NOTE=Place C4516 close to J4501
516S0678
SATA Connectors
A SYNC_MASTER=CHANGZHANG

A
D 051-7631 2.3.0

NONE 36 71
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
USB 2.0 CONNECTOR
CRITICAL
L4602
FERR-120-OHM-3A
PP5V_S3_USB2_EXTA_F
MIN_LINE_WIDTH=0.6MM
CONNECT TO 5V S5 or S3 PER LAYOUT 0603 MIN_NECK_WIDTH=0.2MM
VOLTAGE=5V
CRITICAL
C4610 1 ROUTE USB DATA LINES AS DIFFERENTIAL PAIRS
100UF CRITICAL
20%
6.3V 2
POLY-TANT
L4600
90-OHM-100MA
CASE-B2-SM DLP11S
SYM_VER-1 PP5V_S3_USB2_EXTA_F 6 635 37 70
35 37 70
7 =PP5V_S3_EXTUSB 68 37 USB_EXTA_MUXED_N USB2_EXTA_F_N 6 35
OMIT USB2_EXTA_F_P 6
CONNECT TO RIO CONNECTOR J4200
35
1 C4613 1 C4612 CRITICAL
68 37 USB_EXTA_MUXED_P
10uF 0.1UF
20%
2 6.3V
10%
6.3V U4600 70 PP5V_S3_USB2_EXTA
X5R 2 X5R TPS2052B
603 201 2 IN 7 MIN_NECK_WIDTH=0.2MM
VOLTAGE=5V
MSOP
OUT1 1 C4602
8 CRITICAL 0.01UF
1
OC1* 10%
3 EN1 OUT2 6 D4600 10V
2 X5R
5 OC2* SC-75 201
4 EN2 RCLAMP0502B
DUAL SWITCH HAS GANGED OUTPUT
3
GND TPAD
LAYOUT NOTE:C4602 IS AN EMC BY-PASS CAP FOR J4200
C 1 9 BOTH SWITCHES WILL TRIP TOGETHER AT 1.5A-2.2A C
56 =USBPWR_EN
R4650
2
1K 1 =EXTAUSB_OC_L
EXTAUSB_OC_F_L 8
5%
1/16W
MF-LF
C4650 1
402 0.47UF
10%
6.3V
CERM-X5R 2
402
B USB/SMC MUX USB_EXTA_MUXED_P 37 68

B
USB_EXTA_MUXED_N 37 68
7 =PP3V42_G3H_SMCUSBMUX
R4675
1
100 2 70 PP3V42_G3H_SMCUSBMUX_R
5% MIN_NECK_WIDTH=0.2 mm
1/20W
MF
1 C4675 VOLTAGE=3.42V
1
201 0.1UF R4677
10%
6.3V 10K
2 X5R 5%
PLACE C4675 NEAR U4675 201 1/20W
MF
9
2 201
VCC
41 40 39 SMC_RX_L 5 M+ CRITICAL Y+ 1
40 39 SMC_TX_L
4 M- Y- 2
41
U4675
PI3USB102ZLE
8 =USB2_EXTA_P 7 D+ TQFN
8 =USB2_EXTA_N 6 D-
8 OE* SEL 10 USB_DEBUGPRT_EN_L 39

GND SEL=0 CHOOSE SMC
3
SEL=1 CHOOSE USB
USB EXTERNAL CONNECTORS

A SYNC_MASTER=M70

A
NOSTUFF
R4678 PLACE NEAR U4675 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
0 2
5% I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
1/20W NOSTUFF
MF II NOT TO REPRODUCE OR COPY IT
201
SIGNAL_MODEL=EMPTY
R4679 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
1
0 2
5%
1/20W
MF
201
SIGNAL_MODEL=EMPTY
D 051-7631 2.3.0

NONE 37 71
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D IPD Connector D
PP5V_S3_TOPCASE_F 6 38 70
OMIT
1 C4801 1 C4800
0.1UF 2.2UF
10% 20%
6.3V 6.3V
2 X5R 2 CERM
6 PP3V42_G3H_IPD_F
201 402-LF
70 38
CRITICAL
70 38 6 PP5V_S0_KBDLED_F J4800
51338-0249
F-ST-SM
25 26
1 2 SMC_LID 6 39 40
39 6 SMC_SYS_LED 3 4
5 6
42 6 BI =I2C_TPAD_SCL 7 8
42 6 BI =I2C_TPAD_SDA 9 10 SMC_SYS_KBDLED 6 39
11 12
13 14 =USB2_IR_N BI 6 8
C R4831
15
17
16
18
=USB2_IR_P BI 6 8 C
10K
49 40 LSOC_PRESS_H 2 1 6 LSOC_PRESS_H_R 19 20 =USB2_TPAD_N BI 6 8
5% 40 39 38 6 SMC_ONOFF_L 21 22 =USB2_TPAD_P BI 6 8
1/20W
MF 23 24
201
27 28
1 C4831
0.1UF
10%
6.3V
2 X5R
201 516S0591
PLACE R4800,R4801 UNDER L4800

NO STUFF TPAD_GND_F 38
R4800
1
0 2
5%
1/10W
MF-LF
603
CRITICAL
L4800
470UH-0.3A-80V
ZCYS9480-SM-HF
SYM_VER-1
7 =PP5V_S3_TOPCASE 1 4 PP5V_S3_TOPCASE_F 6 38 70
MIN_LINE_WIDTH=0.3mm
2 3
1 C4810
MIN_NECK_WIDTH=0.2mm
VOLTAGE=5V Power Button Inverter
0.01UF
B 10%
2 10V
X5R
201
38 7 =PP3V42_G3H_IPD B
NO STUFF
R4801 TPAD_GND_F 38
0
MIN_LINE_WIDTH=0.2mm
MIN_NECK_WIDTH=0.2mm R4830 1
1 2 VOLTAGE=0V 1M
5%
5% 1/20W
1/10W MF
MF-LF 201 2
603
SMC_ONOFF_H 40 49
Q4830
SSM3K15FV D 3 Inverted to drive SMC_RESET logic
CRITICAL SOD-VESM-HF
L4812
600-OHM-300MA
7 =PP5V_S0_KBDLED 1 2 PP5V_S0_KBDLED_F 6 38 70
0402
MIN_LINE_WIDTH=0.30 MM 1 G S 2
VOLTAGE=5V
1 C4812
0.01UF 40 39 38 6 SMC_ONOFF_L
10%
10V
2 X5R
201
CRITICAL
L4813
600-OHM-300MA
7 =PP3V42_G3H_IPD PP3V42_G3H_IPD_F 6
1 2
38
0402
38 70
IPD Connector
VOLTAGE=3.42V
A 1 C4813
0.01UF NOTICE OF PROPRIETARY PROPERTY
A
10%
10V
2 X5R
201 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
D 051-7631 2.3.0

NONE 38 71
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NOTE: Unused pins have "SMC_Pxx" names. Unused
pins designed as outputs can be left floating,
those designated as inputs require pull-ups.
70 40 PP3V3_S5_AVREF_SMC
40 7 =PP3V42_G3H_SMC
D D
C4902 1 1 C4903 1 C4904 1 C4905 1 C4906
22UF 0.1UF 0.1UF 0.1UF 0.1UF
20% 10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V 6.3V
X5R-CERM 2 2 X5R 2 X5R 2 X5R 2 X5R
603 201 201 201 201
U4900 PLACEMENT_NOTE=Place C4907 close to U4900 pin F1
8 SMC_P10 B12 P10 P60 L13 SMC_PM_G2_EN 56
HS82117 OUT
8 OUT SMC_EXCARD_PWR_EN A13 P11 LGA-HF P61 K12
NC SMC_VCL
ALL_SYS_PWRGD A12 P12 (1 OF 3) P62 K11 R4999
56 24 IN NC 4.7
56 IN RSMRST_PWRGD B13 P13 OMIT P63 J12
NC 1 2 70 PP3V3_S5_SMC_AVCC
SMC_ADAPTER_EN
MIN_LINE_WIDTH=0.25 MM C4907 1
NC D11 P14 P64 K13 8 20 40 5% MIN_NECK_WIDTH=0.20 MM
M12
H10
L11
OUT 1/16W 0.47UF
B1
M1
E1
VOLTAGE=3.3V
20 OUT PM_RSMRST_L C13 P15 P65 J10
NC MF-LF
402
C4920 1 10%
6.3V
0.1UF CERM-X5R 2
50 OUT IMVP_VR_ON C12 P16 P66 J11 SMC_PROCHOT_3_3_L IN 40 402
10%
PM_PWRBTN_L SMC_BIL_BUTTON_L 6.3V AVCC VCC VCL AVREF
20 OUT D10 P17 P67 H12 IN 8 X5R 2
R4909 1
1
201 R4901
8 OUT ESTARLDO_EN D13 P20 P70 N10 SMC_CPU_ISENSE IN 50
U4900 NC E5
NC 10K 10K
PLACEMENT_NOTE=Place R4999 close to U4900 pins N14,N15 HS82117 5% 5%
NC E11 P21 P71 M11 SMC_ACIN_VSENSE IN 43
LGA-HF
1/20W 1/20W
PLACEMENT_NOTE=Place C4920 close to U4900 pins N14,N15 MF MF
D12 P22 P72 L10 SMC_GPU_ISENSE 201 2
NC IN 8
(3 OF 3) 2 201
F11 P23 P73 N11 SMC_GPU_VSENSE
NC IN 43
OMIT MD1 D1 SMC_MD1 IN 41
8 SMC_P24 E13 P24 P74 N12 SMC_DCIN_ISENSE IN 58
MD2 H1 SMC_KBC_MDE
E12 P25 P75 M13 SMC_PBUS_VSENSE SMC_RESET_L D3 RES*
NC IN 43 41 40 IN
8 SMC_P26 F13 P26 P76 N13 SMC_BATT_ISENSE IN 58
40 SMC_XTAL A3 XTAL
E10 P27 P77 L12 SMC_PBUS_ISENSE 44
NC IN
40 SMC_EXTAL A2 EXTAL NMI E3 SMC_NMI IN 41
68 41 18 BI LPC_AD<0> A9 P30 P80 A7 SMC_WAKE_SCI_L OUT 20
68 41 18 BI LPC_AD<1> D9 P31 P81 B6

NC
68 41 18 BI LPC_AD<2> C8 P32 P82 C7 PM_CLKRUN_L OUT 18 41
ETRST H3 SMC_TRST_L IN 41
C 68 41 18
68 41 18
BI
IN
LPC_AD<3>
LPC_FRAME_L
B7
A8
P33
P34
P83
P84
D5
A6
LPC_PWRDWN_L
SMC_TX_L
IN
OUT
18 41
37 39 40 41 AVSS L9
1 1 1
NO STUFF C
24 SMC_LRESET_L D8 P35 P85 B5 SMC_RX_L 37 39 40 41 VSS R4902 R4998 R4903
IN IN 10K 10K 0
68 24 IN LPC_CLK33M_SMC D7 P36 P86 C6 (OC) SMB_MGMT_CLK BI 42 5% 5% 5%
1/20W 1/20W 1/20W
D2
L3
F10
B11
C5
41 18 BI LPC_SERIRQ D6 P37 XW4900 MF MF MF
P90 J4 SMC_ONOFF_L IN 6 38 40 SM
2 201 2 201 2 201
NC D4 P40 P91 G3 SMC_BC_ACOK IN 40 49 58 2 1
8 SMC_P41 A5 P41 P92 H2 SMC_BS_ALRT_L IN 6 40 49
42 BI SMB_MGMT_DATA (OC) B4 P42 P93 G1 PM_SLP_S3_L IN 6 20 34 35 56
47 OUT SMS_PWRDN A1 P43 P94 H4 PM_SLP_S4_L IN 20 34 40 56
C2 P44 P95 G4 PM_SLP_S5_L NOTE: P94 and P95 are shorted, P95 could be spare.
NC IN 40
GND_SMC_AVSS 40 43 44 58
NC B2 P45 P96 F4 PM_CLK32K_SUSCLK IN 24 68
8 OUT SMC_GFX_THROTTLE_L C1 P46 P97 F1 (OC) SMB_0_S0_DATA BI 42
38 6 OUT SMC_SYS_KBDLED C3 P47
41 40 39 37 OUT SMC_TX_L G2 P50

41 40 39 37 IN SMC_RX_L F3 P51
42 BI SMB_0_S0_CLK (OC) E4 P52
U4900
(DEBUG_SW_1) 8 SMC_PA0 N3 PA0 HS82117 PE0 K1 SMC_CASE_OPEN IN 40
(DEBUG_SW_2) 8 SMC_PA1 N1 PA1 LGA-HF PE1 J3 SMC_TCK IN 40 41
24 OUT PM_SYSRST_L (OC) M3 PA2 (2 OF 3) PE2 K2 SMC_TDI IN 40 41
37 OUT USB_DEBUGPRT_EN_L (OC) M2 PA3 OMIT PE3 J1 SMC_TDO OUT 40 41
20 BI MEM_EVENT_L (OC) N2 PA4 PE4 K4 SMC_TMS IN 40 41
B 49 40 BI
8 SMC_PA5
SYS_ONEWIRE
(OC)
(OC)
L1
K3
PA5
PA6
PF0 K5
NC B
PF1 N5 SMC_SYS_LED OUT 6 38
20 OUT PM_BATLOW_L (OC) L2 PA7
PF2 M6 SMC_LID IN 6 38 40
NC B8 PB0 PF3 L5
NC
20 OUT SMC_RUNTIME_SCI_L C9 PB1 PF4 M5
NC
40 IN SMC_ODD_DETECT B9 PB2 PF5 N4 MCP_SAFE_MODE OUT 20
ISENSE_CAL_EN A10 PB3 PF6 L4

8 OUT NC
SMC_EXCARD_CP C10 PB4 PF7 M4
8 IN NC
NC B10 PB5
PG0 M8
NC
8 IN SMC_EXCARD_OC_L C11 PB6
PG1 N7 =SMC_SMS_INT IN 8 NOTE: SMS Interrupt can be active high or low, rename net accordingly.
8 IN SMC_GFX_OVERTEMP_L A11 PB7
PG2 K8 (OC) SMB_BSA_DATA BI 42 If SMS interrupt is not used, pull up to SMC rail.
46 OUT SMC_FAN_0_CTL G11 PC0 PG3 K7 (OC) SMB_BSA_CLK BI 42
8 OUT SMC_FAN_1_CTL G13 PC1 PG4 K6 (OC) SMB_A_S3_DATA BI 42
8 OUT SMC_FAN_2_CTL F12 PC2 PG5 N6 (OC) SMB_A_S3_CLK BI 42
8 OUT SMC_FAN_3_CTL H13 PC3 PG6 M7 (OC) SMB_B_S0_DATA BI 42
46 IN SMC_FAN_0_TACH G10 PC4 PG7 L6 (OC) SMB_B_S0_CLK BI 42
8 IN SMC_FAN_1_TACH G12 PC5

PH0 E2 SMC_PROCHOT OUT 40
8 IN SMC_FAN_2_TACH H11 PC6
PH1 F2 SMC_THRMTRIP OUT 40
8 IN SMC_FAN_3_TACH J13 PC7
PH2 J2 SMC_FWE IN 8
47 IN SMS_X_AXIS M10 PD0 PH3 A4 ALS_GAIN OUT 8
47 IN SMS_Y_AXIS N9 PD1 PH4 B3

NC
47 IN SMS_Z_AXIS K10 PD2 PH5 C4
NC
SMC_ANALOG_ID L8 PD3
8
44
IN
SMC_NB_CORE_ISENSE M9 PD4
SMC
IN
SMC_NB_DDR_ISENSE
A 8
8
IN
IN ALS_LEFT
N8
K9
PD5
PD6
SYNC_MASTER=M97

A
8 IN ALS_RIGHT L7 PD7
D 051-7631 2.3.0

NONE 39 71
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SMC Reset Button / Brownout Detect SMC 1.05V to 3.3V Level Shifting
40 39 7 =PP3V42_G3H_SMC
7 =PP3V3_S0_SMC_LS
C5000 1 1
R5000 =PP1V05_S0_SMC_LS
0.1UF 1K =PP3V42_G3H_SMC 7 39 40
7
1
R5078
10%
6.3V 2 U5000 5%
1/20W 470
D
D X5R
201 NCP303LSN
SOT23-5-HF
MF
2 201 1
R5070
5%
1/20W
MF
SMC_MANUAL_RST_L CRITICAL SMC_RESET_L 2 201
5 CD OUT 1
OUT 39 41 3.3K
NOSTUFF NC 4 NC IN 2 8 SMC_SMS_INT_L R5098 1 2 10K =PP3V3_S3_SMC 7
5%
1/20W 39
1 GND MF
R5001 2 201
SMC_PROCHOT_3_3_L
Silk: "SMC RST" 0 C5001 1 3
5% 0.01UF 3
Place R5001 on bottom side 1/10W
MF-LF
10%
10V 2 40 39 38 6 SMC_ONOFF_L R5095 1 2 100K Q5077
near board edge 2 603
X5R
201 CPU_PROCHOT_BUF 5 BC847BV-X-F
41 39 37 SMC_TX_L R5080 1 2 10K SOT563-HF
41 39 37 SMC_RX_L R5081 1 2 100K 4
Q5030 D 6
SSM6N15FEAPE 41 39 SMC_TMS R5097 1 2 10K R5071 6
Q5077
SMC_TDO R5085 CPU_PROCHOT_L 3.3K 2 2
SOT563 41 39 1 2 10K 65 50 40 13 9 1 BC847BV-X-F
41 39 SMC_TDI R5086 1 2 10K 5% CPU_PROCHOT_L_R SOT563-HF
R5087 1/20W
41 39 SMC_TCK 1 2 10K MF 1
2 G S 1 201
49 38 LSOC_PRESS_H SMC_MANUAL_RST_L1
Q5030 D 3
SSM6N15FEAPE 49 39 SYS_ONEWIRE R5082 1 2 2.0K
SOT563
49 39 6 SMC_BS_ALRT_L R5083 1 2 470K
39 SMC_ODD_DETECT R5049 1 2 10K
5 G S 4
Q5030 will pull down SMC_BC_ACOK R50841 2 10K
58 49 39
SMC_ONOFF_H SMC_MANUAL_RST_L in the event

49 38
of a keyboard SMC Reset
generated when left shift,option,and control SMC_LID R5073 1 2 100K
C and the power button is depressed.
39 38 6
C
R5092 1 2 10K SMC_CASE_OPEN 39
R5096 1 2 10K SMC_ADAPTER_EN 8 20 39
SMC Crystal Circuit

Debug Power Button C5020
15PF
39 SMC_XTAL 1 2
SMC_ONOFF_L OUT 6 38 39 40 39 PM_SLP_S5_L PM_SLP_S4_L 20 34 39 56
MAKE_BASE=TRUE
NOSTUFF NOSTUFF 5%
25V
3
1 1 CRITICAL NPO
2 4
R5010 R5011 Y5020 201

0 0 20MHZ
5% 5%
Silk: "PWR BTN" SM-2.5X2.0MM C5021
1
1/8W 1/16W
MF-LF MF-LF 15PF
2 805 2 402 SMC_EXTAL 1 2
39
5%
SMC 3.3V to 1.05V Level Shifting
APN: 197S0231 25V
Place R5011 on top side NPO
201 CPU_PROCHOT_L 9 13 40 50 65 PM_THRMTRIP_L 9 13 65
Place R5010 on bottom side

Place both near board edge Q5001 D 6 Q5001 D 3
B SOT563 SOT563
B
2 G S 1 5 G S 4
39 SMC_THRMTRIP
39 SMC_PROCHOT
SMC AVREF Supply

VR5065
7 =PP3V42_G3H_SMCVREF REF3333 PP3V3_S5_AVREF_SMC 39 70
SOT23-3 MIN_LINE_WIDTH=0.4 MM
1 IN OUT 2 MIN_NECK_WIDTH=0.2 MM
CRITICAL VOLTAGE=3.3V
GND
3 1 C5067
0.01UF
10%
OMIT 2 10V
X5R
1 C5065 C5066 1 201
0.47UF 10uF
10%
2 6.3V
CERM-X5R
402
20%
6.3V 2
X5R
603
SMC SUPPORT
GND_SMC_AVSS SYNC_MASTER=M70 SYNC_DATE=01/09/2007
A MIN_LINE_WIDTH=0.4 MM
VOLTAGE=0V
39 43 44 58

A
D 051-7631 2.3.0

NONE 40 71
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
LPC+SPI Connector
CRITICAL
LPCPLUS
MCP79 SPI Frequency Select J5100
55909-0374
M-ST-SM
D Frequency SPI_MOSI SPI_CLK 41 7 =PP3V42_G3H_LPCPLUS 31 32 D

7 =PP5V_S0_LPCPLUS
31 MHz 0 0 1 2 LPC_CLK33M_LPCPLUS IN 24 68
68 39 18 BI LPC_AD<0> 3 4 LPC_AD<2> BI 18 39 68
42 MHz 0 1 68 39 18 BI LPC_AD<1> 5 6 LPC_AD<3> BI 18 39 68

7 8
25 MHz 1 0 41 IN SPI_ALT_MOSI 9 10 SPIROM_USE_MLB OUT 41
41 OUT SPI_ALT_MISO 11 12 SPI_ALT_CLK IN 41
1 MHz 1 1 68 39 18 IN LPC_FRAME_L 13 14 SPI_ALT_CS_L IN 41
39 18 OUT PM_CLKRUN_L 15 16 LPC_SERIRQ BI 18 39
40 39 OUT SMC_TMS 17 18 LPC_PWRDWN_L IN 18 39
25MHz is selected with R5190 and R5191 24 IN DEBUG_RESET_L 19 20 SMC_TDI OUT 39 40
40 39 OUT SMC_TDO 21 22 SMC_TCK OUT 39 40

Any of the 4 frequencies can be 39 SMC_TRST_L 23 24 SMC_RESET_L 39 40
IN OUT
selected w/ R5190,R5191,R5192,R5193 39 OUT SMC_MD1 25 26 SMC_NMI OUT 39
40 39 37 IN SMC_TX_L 27 28 SMC_RX_L OUT 37 39 40

29 30 LPCPLUS_GPIO OUT 17
41 7 =PP3V42_G3H_LPCPLUS 33 34
48 41 7 =PP3V3_S5_ROM LPCPLUS
NO STUFF1
1 C5114
R5192 R5190 1 0.1UF
10%
2 6.3V
10K 10K X5R 516S0573 MCP79 Internal SPI MUX Support
9
5% 5% 201
1/20W 1/20W
MF MF VCC
201 2 201 2 Not supported in Rev A01 MCP79 silicon
68 41 20 IN SPI_CLK_R 1 Y+ LPCPLUS M+ 5 SPI_ALT_CLK OUT 41
2 Y- M- 4 SPI_ALT_MOSI
C 68 41 20 IN SPI_MOSI_R
NO STUFF1
U5110
PI3USB102ZLE
TQFN D+ 7 SPI_CLK_MUX
OUT
OUT
41
41 48 68
MCP SPI Override Options =PP3V3_S0_LPCPLUS
=PP3V42_G3H_LPCPLUS C
R51911 R5193 D- 6 SPI_MOSI_MUX OUT 41 48 68
R5140 1
MCP_CS1_YES
10K 10K CRITICAL
5% 5% Internal MUX in rev B01 does not work as intended. 100K 2 3 LPC_FRAME_PU
1/20W 1/20W 5%
MF MF 10 SEL OE* 8 Now MCP_CS1_YES and MCP_CS1_NO determines external MUX option. 1/20W
D
201 2 201 2 MF MCP_CS1_YES
GND 201 2
R5141 1
SPIROM_USE_MLB Q5140
3
G
41 470
5%
1 SSM3J16FV 1/20W
MF
SOD-VESM-HF 201 2
MCP_CS1_NO
LPC_FRAME_R_L OUT 18
7 =PP3V42_G3H_LPCPLUS R5142
SPIROM_USE_MLB
41 41 LPCPLUS
From Frank Card 0
SEL HIGH WILL OUTPUT TO D (ON BOARD ROM) 1 C5124 1 2
SEL LOW WILL OUTPUT TO M (FRANKCARD ROM) 0.1UF 5% PLACEMENT_NOTE=Place near J5100
10% 1/20W
2 6.3V
X5R MF
201
9
201 SPI_ALT_MISO 41
IN SPI_CS1_R_L_USE_MLB =SPI_CS1_R_L_USE_MLB
VCC BI 20
MAKE_BASE=TRUE
LPCPLUS MCP_CS1_NO MCP_CS1_YES
68 41 20 OUT SPI_MISO 1 Y+ M+ 5 Pull-up on debug card
SPI_CS0_R_L 2 Y- 0 R5127 SPI_ALT_CS_L OUT 41 R5143
68 20 IN U5120 M- 4 1
SPI_ALT_CS_L_MUX 2
1/20W
5%
201
1
02
PI3USB102ZLE MF
TQFN D+ 7 SPI_MISO_MUX 41 48 68 To Frank Card 5% PLACEMENT_NOTE=PLACE NEAR R5147
IN 1/20W
D- 6 SPI_MLB_CS_L_MUX MF
MCP_CS1_NO 201
CRITICAL 0
10 SEL OE* 8 1 2 R5126 SPI_MLB_CS_L OUT 48 68
1/20W 201
GND 5%
MF MCP_CS1_NO
1
R5144 =PP3V3_S5_ROM 7 41 48
3
B MCP_CS1_YES&LPCPLUS_NOT
5%
1/20W
20K
B
MF
R5146 201 2
1
0 2
5% PLACEMENT_NOTE=PLACE NEXT TO U1400
1/20W
MF
201
SPI MUX BYPASS

LPCPLUS_NOT
R5156
0
68 48 41 OUT SPI_CLK_MUX 1 2 SPI_CLK_R IN 20 41 68
5%
1/20W LPCPLUS_NOT
MF
201 R5157
0
68 48 41 OUT SPI_MOSI_MUX 1 2 SPI_MOSI_R IN 20 41 68
5%
LPCPLUS_NOT 1/20W
MF
R5158 201
0
SPI_MISO_MUX 1 2 SPI_MISO
68 48 41 IN
5%
OUT 20 41 68
LPC+SPI Debug Connector
1/20W
A MF
201
SYNC_MASTER=CHANGZHANG

A
D 051-7631 2.3.0

NONE 41 71
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SMC "A" SMBus Connections SMC "0" SMBus Connections SMC "Management" SMBus Connections
NOTE: SMC RMT bus remains powered and may be active in S3 state The bus formerly known as "Battery B"
7 =PP3V3_S3_SMBUS_SMC_MGMT
7 =PP3V3_S3_SMBUS_SMC_A_S3 7 =PP3V3_S0_SMBUS_SMC_0_S0
R5240 1
1
1 1 1 1
SMC R5241 Vref DACs
SMC R5200 R5201 TRACKPAD SMC R5220 R5221 CPU Temp 2.2K 2.2K
4.7K 4.7K 4.7K 4.7K U4900 5% 5% U2900
U4900 5% 5% J4800 U4900 5% 5% EMC1403-5: U5515 1/20W 1/20W
1/20W 1/20W 1/20W 1/20W (MASTER) MF MF (Write: 0x98 Read: 0x99)
(MASTER) MF MF (Write: 0x92 Read: 0x93) (MASTER) MF MF (Write: 0x98 Read: 0x99) 201
2 2
201
201 201 201 201
2 2 2 2
39 SMB_MGMT_CLK 69 SMBUS_SMC_MGMT_SCL =I2C_VREFDACS_SCL 25
D 39 SMB_A_S3_CLK 69 SMBUS_SMC_A_S3_SCL
MAKE_BASE=TRUE
=I2C_TPAD_SCL 6 38 39 SMB_0_S0_CLK 69 SMBUS_SMC_0_S0_SCL
MAKE_BASE=TRUE
=I2C_CPUTHMSNS_SCL 45
39 SMB_MGMT_DATA
MAKE_BASE=TRUE
69 SMBUS_SMC_MGMT_SDA =I2C_VREFDACS_SDA 25
D
39 SMB_A_S3_DATA 69 SMBUS_SMC_A_S3_SDA =I2C_TPAD_SDA 6 38 39 SMB_0_S0_DATA 69 SMBUS_SMC_0_S0_SDA =I2C_CPUTHMSNS_SDA 45 MAKE_BASE=TRUE
M93 Wireless Card Front Edge Temp Margin Control

TMP102: U5570 U2901
J4100 (Write: 0x92 Read: 0x93) (Write: 0x30 Read: 0x31)
(Write: 0x90 Read: 0x91)
THRM_FRONT_SMB_CLK 45 =I2C_PCA9557D_SCL 25
=SMB_AIRPORT_CLK 6 34
THRM_FRONT_SMB_DATA 45 =I2C_PCA9557D_SDA 25
=SMB_AIRPORT_DATA 6 34
ALS
J9000
SMC "B" SMBus Connections SMC "Battery A" SMBus Connections (Write: 0x72 Read: 0x73)
=I2C_ALS_SCL 6 59
7 =PP3V3_S0_SMBUS_SMC_B_S0 7 =PP3V42_G3H_SMBUS_SMC_BSA
=I2C_ALS_SDA 6 59
R5210 1
1
R5230 1
1
SMC R5211 Air Vent Temp SMC R5231 Battery
4.7K 4.7K 2.2K 2.2K
U4900 5% 5% TMP102: U5560 U4900 5% 5% J6950
1/20W 1/20W 1/16W 1/16W
(MASTER) MF
201
2 2
MF
201
(Write: 0x92 Read: 0x93) (MASTER) MF-LF
402
2 2
MF-LF
402
(See Table)
MCP79 SMBUS "0" CONNECTIONS
C 39
39
SMB_B_S0_CLK
SMB_B_S0_DATA
69
69
SMBUS_SMC_B_S0_SCL
MAKE_BASE=TRUE
SMBUS_SMC_B_S0_SDA
THRM_VENT_SMB_CLK
THRM_VENT_SMB_DATA
45
45
39
39
SMB_BSA_CLK
SMB_BSA_DATA
SMBUS_SMC_BSA_SCL
MAKE_BASE=TRUE
SMBUS_SMC_BSA_SDA
=SMBUS_BATT_SCL
=SMBUS_BATT_SDA
49
49
7 =PP3V3_S0_SMBUS_MCP_0 C
MCP79 R5250 1 1
R5251
10K 10K
Power Supply Temp Battery Charger U1400 5%
1/20W
5%
1/20W
TMP102: U5550 ISL6258A - U7900 (MASTER) MF MF
201 2
2 201
(Write: 0x90 Read: 0x91) Battery (Write: 0x12 Read: 0x13)
68 20 12 6 SMBUS_MCP_0_CLK
Battery Manager - (Write: 0x?? Read: 0x??) MAKE_BASE=TRUE
THRM_PS_SMB_CLK 45 =SMBUS_CHGR_SCL 58
Battery Temp - (Write: 0x?? Read: 0x??) 68 20 12 6 SMBUS_MCP_0_DATA
MAKE_BASE=TRUE
THRM_PS_SMB_DATA 45 =SMBUS_CHGR_SDA 58
MCP79 SMBUS "1" CONNECTIONS

7 =PP3V3_S5_SMBUS_MCP_1
MCP79 R5260 1 1
R5261
10K 10K
U1400 5% 5%
1/20W 1/20W
(MASTER?) MF MF
201 2
2 201
B 68 20 SMBUS_MCP_1_CLK
MAKE_BASE=TRUE B
68 20 SMBUS_MCP_1_DATA
MAKE_BASE=TRUE
M97 SMBUS CONNECTIONS

A SYNC_MASTER=BEN

A
D 051-7631 2.3.0

NONE 42 71
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
ACIN VOLTAGE SENSE
D 70 58 PPVDCIN_G3H_PRE MAX 16.5V + 10% ACIN = 3.0V SMC_ACIN_VSENSE D

R5300 and R5301 VALUES CHOSEN FOR RC FILTER @ 4.53KOHM THEVENIN RESISTANCE
1
R5300
27.4K
1%
1/20W
MF
2 201
SMC_ACIN_VSENSE 39
1
R5301 1 C5300
5.36K 0.22UF
1% 10%
1/20W
MF 2 6.3V
CERM-X5R
2 201 402
GND_SMC_AVSS 39 40 43 44 58
PLACE C5300 NEAR SMC
C MCP VOLTAGE SENSE C
R5310
4.53K2
7 =PPVCORE_S0_MCP_VSENSE 1 SMC_GPU_VSENSE 39
1%
1/20W
MF
201 1 C5310
0.22UF
10%
2 6.3V
CERM-X5R
402
GND_SMC_AVSS 39 40 43 44 58
PLACE R5310.C5310 NEAR SMC
PBUS VOLTAGE SENSE

B B
Q5315
NTUD3127CXXG PBUSISENSE_EN_L OUT TO PBUS CURRENT SENSOR
SOT-963
N-CHANNEL 6 PBUSVSENS_EN_L
D
R5316 1
100K
56 =PBUSVSENS_EN 2 G 1%
IN
S 1/20W
MF
Enables PBUS VSense 201
2
1
divider when high.
3 70 PPBUS_G3HRS5_VSENSE
D VOLTAGE=18.5V
R5385 1
12.7K
5 G 1%
S 1/20W
7 =PPBUS_G3HRS5 MF
4
201
2
RTHEVENIN = 4573 OHMS
P-CHANNEL SMC_PBUS_VSENSE 39
OUT
R53151
100K 1
1%
R5386 1
C5385
1/16W 6.98K 0.22UF
MF-LF 1%
20%
402 1/20W
2 MF 2
6.3V
X5R
201 402
PBUSVSENS_EN_L_DIV 2
GND_SMC_AVSS 39 40 43 44 58
Voltage Sensors
Place RC close to SMC
A SYNC_MASTER=M70

A
D 051-7631 2.3.0

NONE 43 71
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
MCP VCore Current Sense
MCP VCore Current Sense Filter

R5416
4.53K
51 IN MCPCORE_IOUT 1 2 SMC_NB_CORE_ISENSE OUT 39
1%
1/20W
MF
201
1
C5472
0.22UF
20%
6.3V
2 X5R
402
GND_SMC_AVSS 39 40 43 44 58
Place RC close to SMC
C C
PBUS Current Sense

58 7 =PPBUSB_G3H
R5481 1 1 C5480
7
21 0.1UF
1% 10%
1/16W V+ 16V
2 X5R
MF-LF
402 2 U5480
LTC6102AP
402
DFN
B 2 -INF VREG 6 PBUS_ISENSE_VREG
PLACE C CLOSE TO SMC
B
PBUS_ISENSE_IN_NEG 1 CRITICAL 4 SMC_PBUS_ISENSE
-INS OUT 39
58 7 =PPBUSA_G3H 8 +IN SHDN 3

1
1 C5489
R5489 0.22UF
THM 4.53K 20%
6.3V
V- PAD 1% 2 X5R
1/20W 402
5 MF
9
2 201 GND_SMC_AVSS 39 40 43 44 58
43 PBUSISENSE_EN_L
LTC6102 DISABLED WHEN SHDN=1
LTC6102 ENABLED WHEN SHDN=0
Current Sensing
A SYNC_MASTER=YUNWU

A
D 051-7631 2.3.0

NONE 44 71
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CPU/MCP T-Diode Thermal Sensor LOCAL TEMP NEAR FRONT EDGE

INTERNAL DIODE IN U5515 DETECTS CPU PROXIMITY TEMPERATURE
45 7 =PP3V3_S0_THRM_SNR R5515
47 =PP3V3_S0_THRM_SNR 7 45
1 2 70 PP3V3_S0_CPUTHMSNS_R
D 5%
1/20W
VOLTAGE=3.3V
D
MF
201 1 C5515 R5516 1 1
R5517 C5570 1
VDD 10K 10K
0.1uF 5% 5% 0.1UF
10% 1/20W 1/20W 10%
9 CPU_THERMD_P U5515 2
6.3V MF MF
6.3V 2
BI X5R X5R
201 201
SIGNAL_MODEL=EMPTY
EMC1403-1 201 2 2 201
1 DFN 5
C5521 DP1 THERM* CPUTHMSNS_THERM_L
DETECT CPU DIE TEMPERATURE 2.2NF V+
10% CPUTHMSNS_ALERT_L
10V
X5R 2
DN1 ALERT* U5570
201
DP2 SMDATA =I2C_CPUTHMSNS_SDA 42
HPA00330AI
CPU_THERMD_N BI SOT563
9 BI
CRITICAL 42 BI
THRM_FRONT_SMB_DATA 6 SDA ADD0
4
DN2 SMCLK =I2C_CPUTHMSNS_SCL BI 42
GND THRM_PAD THRM_FRONT_SMB_CLK 1 CRITICAL 3

42 BI SCL ALERT
GND
2
20 BI MCP_THMDIODE_P
SIGNAL_MODEL=EMPTY
PLACEMENT NOTE: PLACE U5515 NEAR CPU
C5520 1
DETECT MCP DIE TEMPERATURE 2.2NF

10%
10V
X5R 2
201
20 BI MCP_THMDIODE_N
C C
LOCAL TEMP NEAR AIR VENT
=PP3V3_S0_THRM_SNR 7 45
C5560 1
0.1UF
10%
6.3V 2
X5R
201
5
V+
U5560
HPA00330AI
SOT563
42 BI THRM_VENT_SMB_DATA 6 SDA ADD0
4
42 BI
THRM_VENT_SMB_CLK 1 SCL CRITICAL
ALERT
3
GND
2
B B
LOCAL TEMP NEAR POWER SUPPLIES

=PP3V3_S0_THRM_SNR 7 45
C5550 1
0.1UF
10%
6.3V 2
X5R
201
5
V+
U5550
HPA00330AI
SOT563
42 BI THRM_PS_SMB_DATA6 SDA ADD0
4
THRM_PS_SMB_CLK 1 CRITICAL 3
42 BI SCL ALERT
GND
TEMPERATURE SENSORS
A 2
SYNC_MASTER=M70

A
D 051-7631 2.3.0

NONE 45 71
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
C
FAN CONNECTOR C
7 6 =PP5V_S0_FAN
7 =PP3V3_S0_FAN
CRITICAL
R5660SM04B-SURKHF-GAN-TF-LF-SN
1 J5600
47K
5% NC
F-RT-SM
5
1/20W
R5665 MF
201 2
1 5V DC
39 SMC_FAN_0_TACH 1 47K2 6 FAN_RT_TACH 2 TACH
5% 3
1/20W
MF 4 MOTOR CONTROL
201 GND
NC 6
R5661 1
100K 518S0658
5% Q5660
1
1/20W
MF SSM3K15FV
G
201 2 SOD-VESM-HF
FAN_RT_PWM
D
6
3
2
39 SMC_FAN_0_CTL
B B
Fan
SYNC_MASTER=M70 SYNC_DATE=01/09/2007
A
D 051-7631 2.3.0

NONE 46 71
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
SUDDEN MOTION SENSOR
C 7 =PP3V3_S3_SMS C
R59211 1 C5922 1 C5900
14
10K 0.1UF 10UF
5% 10% 20% Desired orientation when
6.3V 4V
1/20W VDD 2 X5R 2 X5R
MF 201 603
201 2 U5900 placed on board top-side:
AP344ALH
LGA
1 FS VOUTX 12 SMS_X_AXIS OUT 39
39 IN SMS_PWRDN 5 PD
2 ST VOUTY 10 SMS_Y_AXIS OUT 39 +Y
SMS_SELFTEST
CRITICAL
VOUTZ 8 SMS_Z_AXIS OUT 39 Front of system
+X
15 RES
4 RES
+Z (up)
NC
1
R5922 NC 3 NC NC 11 NC
10K
5% NC 6 NC NC 13 NC
1/20W
MF NC 9 NC NC 16 NC 1 C5923 1 C5924 1 C5925
201 GND 0.01UF 0.01UF 0.01UF
2
10% 10% 10% Circle indicates pin 1 location when placed
7
10V 10V 10V
2 X5R 2 X5R 2 X5R in correct orientation
201 201 201
B B
Sudden Motion Sensor (SMS)

A SYNC_MASTER=M76_MLB

A
D 051-7631 2.3.0

NONE 47 71
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
41 7 =PP3V3_S5_ROM
R61001 1
R6101 C6100 1
C 3.3K
5%
1/20W
5%
3.3K
1/20W
0.1UF
10%
C
MF MF 6.3V 2
201 2 X5R
2 201 201
R6152
SPI_MOSI_MUX 1
0 2 68 SPI_MOSI
68 41 IN 8
PLACEMENT_NOTE=Place close to U6100 5%
1/20W
VCC
CRITICAL R6105
MF 0
201
R6150 5 D
U6100 Q2 68 SPI_MISO_R 1 2 SPI_MISO_MUX OUT 41 68
0 M25P32 5%
68 41 IN SPI_CLK_MUX 1 2 68 SPI_CLK 6 C 1/16W
MF-LF
PLACEMENT_NOTE=Place close to U6100 5% VFQFPN 402
1/20W 1 S*
MF OMIT
201
SPI_WP_L 3 W*/VPP
SPI_HOLD_L 7 HOLD*
68 41 IN SPI_MLB_CS_L
VSS THM
PAD
4 9
B B
SPI ROM
A SYNC_MASTER=CHANGZHANG

A
D 051-7631 2.3.0

NONE 48 71
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
DC-JACK INTERFACE CRITICAL

D6901
R6905 HN2S02FUAPE
SOT-363
47
5%
7 =PPVIN_G3H_DCIN
1/8W
CRITICAL 70 6 PP18V5_DCIN
VOLTAGE=18.5V
MF-LF
805
6 1 =PPDCIN_G3H 7
J6980 MIN_LINE_WIDTH=0.6 MM 1 2 PPDCIN_G3H_R
D WTB-PWR-M82
M-RT-SM
1 C6902
VOLTAGE=18.5V
5 2
D
1 0.01UF 58 49 BATT_POS_F1 2 PPVBATT_G3H_R 4 3
10%
2 25V
2 X7R CRITICAL R6940
3 402 F6900 10 VOLTAGE=18.5V
4
6AMP-24V 5%
1/8W
1206-1
MF-LF
5 1 2 805 =PP18V5_G3H_CHGR 7 58
D6900
SC-75
518S0507 1
1 R6902 ONEWIRE_PWR_EN_L1 2
1K R6904
NO STUFF 3 5% Q6910 47K
2
1/16W
MF-LF
SSM6N15FEAPE
SOT563
R6911
D 3 100K 5%
2 402 2 1/16W
MF-LF S
SMC_BC_ACOK1 2 SMC_BC_ACOK_ONEWIRE_R 5% 402
58 40 39 1/16W SOT-723-HF
MF-LF SSM3J15FVAPZE
RCLAMP2402B
CRITICAL 1 C6907 402 ONEWIRE_PWR_EN_L_DIV 1 Q6940
0.001UF
10%
G
6 ADAPTER_SENSE 50V 5 G S 4
2 CERM D
402
3
SYS_ONEWIRE6 SYS_ONEWIRE_BILAT
4 S
1
3 D
40 39
D
70 PP18V5_DCIN_ONEWIRE
Q6920
G
G 5
VOLTAGE=18.5V
SSM6N15FEAPE 2 MIN_LINE_WIDTH=0.25 MM
SOT563
Q6920 1
R6932
1
R6901 1
R6933
OneWire OVP
SSM6N15FEAPE
SOT563 1%
24.3K
1/16W
MF-LF
2 402
1
R6903
200K 1 C6930
1%
1/16W
MF-LF
2 402
24.3K 100K
5%
1/20W
MF
201
BATTERY INTERFACE
C 5%
1/16W
MF-LF
0.1UF
10% 5
ONEWIRE_DCIN_DIV
2
C
ONEWIRE_EN 2 25V 1
2 402 X5R
402 V+
Q6980 ONEWIRE_OV 4
SSM3K15FV 3 D
SOD-VESM-HF ONEWIRE_ESD
1
R6931 CRITICAL
CRITICAL V- 3 100K
1
R6906 U6990 2
5%
1/20W J6900 CRITICAL
1 200K MF WTB-PWR-M82 L6900
R6900 1 C6903 5%
LM397
SOT23-5-HF
2 201 M-RT-SM FERR-50-OHM
100K 0.001UF 1/16W 1 BATT_POS 1 2 BATT_POS_F
5% 10% 2 S G 1 MF-LF 6 49 58
1/16W 2 402
MF-LF 2 50V
CERM
2 2 SM-LF
2 402 402 3
C6900
0.01UF
4 10%
1 25V
5 X7R
402
6
7 SMC_BS_ALRT_L 6 39 40
8 =SMBUS_BATT_SDA 42
9 =SMBUS_BATT_SCL 42
518S0540
B 3.425V "G3Hot" Supply B

Supply needs to guarantee 3.31V delivered to SMC VRef generator
7 =PPVIN_G3H_P3V42G3H P3V42G3H_BOOST
R69901
6
1 C6994
100K VIN BOOST 0.22UF CRITICAL
5% CRITICAL 10% =PP3V42_G3H_REG
1/20W
MF U6900
DFN
2 6.3V
CERM-X5R L6995 7 24
201 2 402 33UH

LTC3470A
P3V42G3H_SHDN_L 8 SHDN* SW 4 PP3V42G3H_SW 1 2

Q6990 will pull down 70
MIN_LINE_WIDTH=0.5 mm Vout = 3.425V
P3V42G3H_SHDN_L in the event BIAS 2 MIN_NECK_WIDTH=0.2 mm CDPH4D19FHF-SM
D 6 VOLTAGE=3.42V
of a keyboard SMC Reset Q6990 C6991 1
NC
7 NC
(PP3V42_G3H_REG)
200mA max output
generated when left shift,option,and controlSSM6N15FEAPE
SOT563
0.22UF
10% FB 1 (Switcher limit)
and the power button is depressed. 6.3V
2 THRM <Ra>
GND
R69951
CERM-X5R PAD
402
5
1 C6995 348K
2 G S 1 22PF 1%
5% 1/20W
MF
40 38 LSOC_PRESS_H 2 50V 201 1 C6999
P3V42G3H_SHDN_L1
CERM 2
201 22UF
CRITICAL P3V42G3H_FB 20%
6.3V
D 3 2 CERM
Q6990 C6990 <Rb>
DC-In & Battery Connectors
R69961
805
SSM6N15FEAPE 5.6UF
SOT563 20% 200K
25V SYNC_MASTER=M70 SYNC_DATE=01/09/2007
A POLY-TANT
CASE-B2-SM
1%
1/20W
MF
201 2 NOTICE OF PROPRIETARY PROPERTY
A
5 G S 4
Vout = 1.25V * (1 + Ra / Rb) I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
40 38 SMC_ONOFF_H
D 051-7631 2.3.0

NONE 49 71
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
1 2 50 IMVP6_PVCC
VOLTAGE=5V OMIT
1 C7100
R7100 1UF
0 10%
7 =PP5V_S0_CPU_IMVP 5% 6.3V
CERM
1/16W 2
MF-LF 402
402
1 2 70 PP5V_S0_IMVP6_VDD
OMIT MIN_LINE_WIDTH=0.25 MM
C7101
IMVP6 CPU VCORE REGULATOR

1
R7101 1UF VOLTAGE=5V
0 10%
5% 6.3V
1/16W CERM
2 402
MF-LF
D
402
D
50 7 =PPVIN_S5_CPU_IMVP 1 2 70 PPVIN_S5_IMVP6_VIN
R7102 1 C7102 VOLTAGE=18.5V
0 0.22UF
5% 10%
1/16W 16V
MF-LF X7R
2 603
65 20 IN
PM_DPRSLPVR 402
VOLTAGE=3.3V
7 =PP3V3_S0_IMVP 1 2 70 PP3V3_S0_IMVP6_3V3
OMIT
R7103 1
C7103
0 1UF 50 7 =PPVIN_S5_CPU_IMVP
5% 10%
1/20W 6.3V
X5R
MF 2 402-1 CRITICAL CRITICAL
18
20
27
201
1 1 1 C7152 1 C7153
50 GND_IMVP6_SGND C7150 C7151 1UF 1UF
VIN VDD VCCP 47UF 47UF 10%
25V
10%
25V
20% 20%
X5R X5R
CRITICAL 2 10V 2 10V 2 603-1 2 603-1
65 11 10 CPU_VID<6> 34 VID6 POLY-TANT POLY-TANT
CASE-B2-SM CASE-B2-SM
65 11 10 CPU_VID<5> 33 VID5 BOOT 50 22 IMVP6_BOOT 1 2 IMVP6_BOOT_RC 5
65 11 10 CPU_VID<4> 32 VID4
U7100
QFN C7104
CPU_VID<3> 31 R7104 1
ISL6261A
1 1 65 11 10 VID3 0.22UF
PLACE R7110 WITH NO STUB R7111 R7110 30
2.2 10%
65 11 10 CPU_VID<2> VID2 5%
16V
ON PM_DPRSLPVR 499 499 1/16W 4
CPU_VID<1> 29 X7R
1% 1% 65 11 10 VID1 MF-LF 2 603
1/20W 1/20W 402
MF MF 65 11 10 CPU_VID<0> 28 VID0 LGATE 50 26 IMVP6_LGATE CRITICAL
2 201 2 201
Q7100
65 13 9 8 IN CPU_DPRSTP_L 37 DPRSTP* RJK0305DPB
VSSP 25
(GND)
65 IMVP_DPRSLPVR 36 DPRSLPVR 1 2 3 LFPAK-HF
CRITICAL
1
C NO STUFF
R7115
FDE
UGATE 50 23 IMVP6_UGATE
L7100
0.36UH-30A-1.05M-OHM
=PPVCORE_S0_CPU_REG
C
7
0 (IMVP6_PHASE) 1 2
5% PHASE 50 24 IMVP6_PHASE
1/20W 39 3V3
65 MF PCMB103T
40 CPU_PROCHOT_L 201 NC 38 CLK_EN* PMON 2 IMVP6_CPU_ISENSE 1 2 SMC_CPU_ISENSE 39
13 1 2
9
39 FROM SMC IMVP_VR_ON 35 VR_ON C7190
IN
40 R7190
1
0.22UF PWM FREQ. = 300kHz
OUT VR_PWRGOOD_DELAY PGOOD
1 2
24
IMVP6_VR_TT 4 VR_TT*
4.53K
1%
20%
6.3V
5
MAX CURRENT = 30A
1/20W X5R
R7116 2 201
C7111 NC 5 NTC MF
147K 201 CRITICAL
0.015uF 1%
1/20W VSUM 50 17 IMVP6_VSUM
Q7151
10% MF 50 IMVP6_SOFT 6 SOFT
16V
X7R
201 OCSET 7 50 IMVP6_OCSET 4 RJK0328DPB
402 1 2 50 IMVP6_RBIAS 3 RBIAS VO 50 16 IMVP6_VO (IMVP6_VO) NO STUFF LFPAK-HF
1
DROOP 50 14 IMVP6_DROOP
C7141
50 IMVP6_VDIFF 11 VDIFF 1000PF
R7141 2
DFB 50 15 IMVP6_DFB 10%
16V 1 2 3
1
8.66K X7R
50 IMVP6_FB 10 FB VSEN 12 R7140 1/20W 1 C7140 201
806 MF 330PF
50 IMVP6_COMP 9 COMP RTN 13 1% 201 1
R7142
1% 10%
1/20W
50 IMVP6_VW 8 VW MF 2 16V 20K
1
C7120 1 2 2
201 X7R 1%
IMVP6_VSEN_N
IMVP6_VSEN_P
1/20W
180PF 201
MF
5% R7124 21 NC 201
50V 2
CERM
1K C7130
2 1% (IMVP6_VO)
402 1/20W VSS TPAD 1000PF
MF 1
R7146
41
201 10%
19
16V 1 7.68K
IMVP6_VDIFF_RC 50 50 IMVP6_COMP_R 1 2 X7R R7143 1%
65 201 65
1 1 2
3.57K 1/16W
R7120 1
1% MF-LF
2.21K R7122 1/20W

MF
2
402
B 1%
1/20W
MF
15K
1%
1/20W
1 C7124
0.01UF
10%
C7131
1000PF 1
C7142
0.12UF
1
C7143
0.01UF
1
R7145
2
201
IMVP6_VO_R
B
2
201 MF 10V 10% 10% 10%
4.53K
201 X5R 50 GND_IMVP6_SGND 1%
2 16V 10.0V 10V 1
(IMVP6_FB) 2 201 VOLTAGE=0 V
X7R CERM-X5R X5R 1/20W
2 402 2 201 MF
201
1 2
201 CRITICAL
R7130 R7144
1
100 10KOHM-5%
R7121 1 2
1%
1/20W 0603-LF
374K MF
1% (IMVP6_VW) 2 201 2
1/20W
MF
C7132 ERT-J1VR103J
2
201 330PF (IMVP6_VSUM)
10%
1 16V
IMVP6_FB_RC 1
C7122 1
C7123 R7123 R7134 X7R
(IMVP6_VO)
50
56PF 1000PF 6.04K 100 2 201
5% 10% 1
25V 16V 1%
NP0-C0G X7R 1/20W
1 C7121 2 201 2 201 MF 1%
1/20W 1 2
R1100/R1101 **ON THE CPU PAGE** PROTECT THE IMVP6 IF THE CPU IS NOT INSTALLED
201
270PF 2 MF
10% 201
50V 1 1
2
X7R-CERM 2
C7133 R7131 R7132
402 OMIT 0.1UF 0 0
XW7100 10%
5%
1/20W
5%
1/20W
SM 6.3V
MF MF
X5R
NOTE 1: C7132,C7133 = 27.4 OHM FOR VALIDATING CPU ONLY. 1
201 2
201
2 201
CPU_VCCSENSE_P 10 65 MIN_LINE_WIDTH MIN_NECK_WIDTH
CPU_VCCSENSE_N 10 65 50
IMVP6_OCSET 0.25 MM 0.20 MM
50
IMVP6_VSUM 0.25 MM 0.20 MM
50
GND_IMVP6_SGND 0.50 MM 0.20 MM
50
IMVP6_VO 0.25 MM 0.20 MM
IMVP6_DROOP
50
50
IMVP6_DFB
0.25 MM
0.25 MM
0.20 MM
0.20 MM
IMVP6 CPU VCore Regulator
IMVP6_SOFT
A 50
50
IMVP6_RBIAS
0.25 MM
0.25 MM
0.20 MM
0.20 MM
SYNC_MASTER=POWER

A
50
IMVP6_VDIFF 0.25 MM 0.20 MM
MIN_LINE_WIDTH MIN_NECK_WIDTH
50
IMVP6_FB 0.25 MM 0.20 MM THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
50
IMVP6_PHASE 1.5 MM 0.20 MM PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
50
IMVP6_COMP 0.25 MM 0.20 MM AGREES TO THE FOLLOWING
50
IMVP6_BOOT 0.25 MM 0.20 MM
50
IMVP6_VW 0.25 MM 0.20 MM I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
50
IMVP6_UGATE 1.5 MM 0.20 MM
50
IMVP6_PVCC 0.25 MM 0.20 MM II NOT TO REPRODUCE OR COPY IT
50
IMVP6_LGATE 1.5 MM 0.20 MM
50
IMVP6_COMP_R 0.25 MM 0.20 MM III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
50
IMVP6_FB_RC 0.25 MM 0.20 MM
50
IMVP6_VDIFF_RC 0.25 MM 0.20 MM
D 051-7631 2.3.0

NONE 50 71
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MCP CORE POWER SUPPLY

D R7260
2.2
7 =PPVIN_S0_MCPCORES0
=PPMCPCORE_S0_REG 7 51
D
1 2 CRITICAL CRITICAL
Vout = See below
=PP5V_S3_MCPREG
5%
1/10W 5V_S3_MCPREG_VIN C7262 1
C7260 1 1 C7261
7
MF-LF VOLTAGE=5V 47UF 47UF 1UF MAX CURRENT: 20A
OMIT 603 0.6 mm OMIT 20% 20% 10%
C7297 1 0.2 MM 1 C7296
1 C7255 1 C7272 10V
POLY-TANT 2
10V
POLY-TANT 2 2 25V
X5R F = 300 KHZ
0.1UF 1UF CASE-B2-SM CASE-B2-SM 603-1
7 =PP3V3_S3_MCPREG 1UF 1UF 10% 10%
10%
16V 2
10% 2 25V 2 25V
X5R 2 16V
X5R
X5R
402
X5R
603-1 5
402 402 PLACE AT U7200.14
16
22
1 CRITICAL
R7261 51 GND_MCPCORES0_AGND
Q7260
20 VDD PVCC 4 CRITICAL
1% (MCPCORES0_UGATE) RJK0305DPB 1
R7290
1/20W
MF
CRITICAL MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM LFPAK-HF C7268
330UF
MCP_VID<0> 1
0 2
2 201
MCPCORES0_RBIAS 1 RBIAS
U7200 VIN 14
GATE_NODE=TRUE
20%
2 2.5V
20 IN
5%
QFN
R7274 C7264
0.22UF
POLY-TANT
CASE-C2-SM
ISL6263D
1/20W R7291 MCPCORES0_SOFT 2 SOFT 0
2 MCPCORES0_BOOT_R 1 2 OMIT CRITICAL OMIT OMIT
MF UGATE 18 MCPCORES0_UGATE 1 1 2 3 CRITICAL
MCP_VID<1>
201
1
0 2 5%
0.25 MM
0.2 MM
C7266 1 1
C7265 C7267 1 C7269 1
20 IN
5%
44 OUT MCPCORE_IOUT 28 IMON BOOT 17 MCPCORES0_BOOT 1/10W
0.2 MM MF-LF
CERM-X7R
10V L7200 10UF
20%
330UF
20%
10UF
20%
10UF
20%
R7292 1/20W 0.25 MM 603 603
5%
0.68UH-3.9MOHM 4V
X5R 2 2 2.5V 4V
X5R 2
4V
X5R 2
0 MF 56 OUT MCPCORES0_PGOOD 31 PGOOD PHASE 19 2 1 603 POLY-TANT 603 603
20 IN MCP_VID<2> 1 2 201 MCPCORES0_PHASE (MCPCORES0_PHASE) (=PPMCPCORE_S0_REG) CASE-C2-SM
MCP_VID0_R 25 VID0 MIN_LINE_WIDTH=0.5 MM SWITCHNODE
5% MIN_NECK_WIDTH=0.2 MM IHLP4040CZ-SM
1/20W MCP_VID1_R 26 VID1 SWITCH_NODE=TRUE
MF
201 MCP_VID2_R 27 VID2
2 OMIT
MCPCORES0_OFFSET0 23 OFFSET0 2 OMIT
CONNET OFFSET0 TO 3V3 FOR +12.5MV
CONNET OFFSET1 TO 3V3 FOR +25.0MV MCPCORES0_OFFSET1 24 OFFSET1
5
XW7260 SM
XW7202
56 =MCPCORES0_EN 29 VR_ON CRITICAL SM
1 IN
R7293 MCPCORES0_FDE 30 AF_EN LGATE 21 MCPCORES0_LGATE Q7265 1
1
0 32
5% FDE (MCPCORES0_LGATE) 4 RJK0328DPB
C 1/20W
MF
2 201
1
R7294
0
MCPCORES0_VSEN
MCPCORES0_RTN
8
9
VSEN
RTN
GATE_NODE=TRUE
LFPAK-HF
MCPCORES0_ISP_R
C
5%
1/20W 4 VW
MF MCPCORES0_VW
2 201 1 2 3
51 7 =PPMCPCORE_S0_REG
VO 12 MCPCORES0_VO R72641 CRITICAL
1
R7263 GND_MCPCORES0_AGND 51
11.3K
1%
R7265
100 MCPCORES0_COMP 5 COMP OCSET 3 MCPCORES0_OCSET 1/20W 0603-LF
1% MF
1/20W 201 2
MF
XW7262
SM R7266 2 201 MCPCORES0_FB 6 FB ISP 13 MCPCORES0_ISP 1 2 MCPCORES0_ISN_R
20 ISN 11 MCPCORES0_ISN
=PPMCPCORE_S0_REG 1 2 MCPCORES0_RSEN_H 1 2 MCPCORES0_VDIFF 7 VDIFF
PLACE XW NEAR THE MCP, OMIT 1% ICOMP 10 MCPCORES0_ICOMP 10KOHM-5%
CONNECT SENSE LINES TO CLOSEST 1/20W 1 C7270 C7298 1 1 1 C7273
1
R7270 1
R7267
MCPCORE AND GND BALL
OF MCP
MF
201 1000PF 1000PF PGND VSS THRM_PAD R7269 10K 1K
XW7263 R7268 10%
2 16V
10%
16V 2 4.99K 0.047UF
10% 1% 1%
20
15
33
SM X7R X7R 1% 1/20W 1/20W
20 1/20W 2 16V MF MF
1 2 MCPCORES0_RSEN_L 1 2 201 201 C7276 1 1
R7272 MF X7R
402 2 201 2 201
OMIT 1% 0.015UF 150K 2 201
1/20W 10% 1% (MCPCORES0_VO)
MF 16V 2 1/20W
201
1
1 C7299 X7R
402 MF 1
R7271 1000PF
10%
2 201 R7273 1 C7277 1 C7278
100 10K 0.1UF 0.1UF
1% 2 16V 1%
1/20W
MF
X7R
201 XW7261
SM
1/20W
MF
10%
2 6.3V
10%
2 6.3V
X5R X5R
2 201 51 GND_MCPCORES0_AGND 1 2 (MCPCORES0_ISP) 2 201 201 201
VOLTAGE=0V OMIT (MCPCORES0_ISN)
1
R7275
10K
1%
B 1/20W
MF
2 201
B
(MCPCORES0_ICOMP)
C7279 1
1000PF
C7280 10%
25V 2
68PF X7R 1
1 2 402 R7276
6.98K
5% 1%
25V 1/20W
CERM MF
201 2 201
R7277 C7281
1
374K 2 MCPCORES0_COMP_C180PF
1 2
1% 5%
1/20W
MF 50V
201 CERM NEED NEW TABLE?
402
C7282 Rev A01 Rev A01P Production

R7278
1
4.99K2 MCPCORES0_VDIF_C 560PF
1 2 VID<2:0> Voltage Voltage Voltage
1% 10%
1/20W
MF 50V 000 +1.224V +1.355V +1.060V
201 CERM
R7279 402 001 +1.158V +1.243V +0.994V
1
2.21K2
1%
010 +1.101V +1.216V +0.937V
1/20W
MF 011 +1.047V +1.124V +0.885V
201 MCP CORE REGULATOR
100 +0.996V +1.065V +0.830V
A 101 +0.952V +0.994V +0.789V
SYNC_MASTER=MINGJING

A
110 +0.913V +0.977V +0.752V
111 +0.876V +0.917V +0.719V AGREES TO THE FOLLOWING
(Also A01Q)
D 051-7631 2.3.0

NONE 51 71
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
C 1.8V S0 LDO C
U7360
TPS79918
7 =PPVIN_S0_P1V8S0 6 IN SON OUT 1 =PP1V8_S0_REG 7
CRITICAL MAX CURRENT = 200MA

56 =P1V8S0_EN 4 EN NR 2 P1V8S0_NR
OMIT OMIT
1 C7360 5 NC
THRML 1 C7361
1 C7362
1UF GND PAD 2.2UF
10% 0.01UF 20%
2 6.3V 3 7 10% 2 6.3V
CERM 2 10V CERM
402 X5R 402-LF
201
B B
1.8V LDO Supply

SYNC_MASTER= SYNC_DATE=
A
D 051-7631 2.3.0

NONE 52 71
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D
1V05 S5 POWER SUPPLY D
supply for MCP1V05 AUX, FSB (CPU & MCP) VTT, 1V05 S0
53 7 =PPVIN_S5_1V05
(1V05S5_VLDO)
VOLTAGE=5V
CRITICAL
3
C7450 1 C7451 1
V5V
47UF 1UF
20%
10V 10%
POLY-TANT 2 25V
CASE-B2-SM X5R 2
603-1 CRITICAL
CRITICAL
C 1 FB
U7400 VIN0 6 L7400 C
SC417 1.0UH-22A-10M-OHM
VIN1 9
1V05S5_TON 31 TON
MLPQ
VIN2 10 R7421 C7420 1 2 =PP1V05_S5_REG 7
11 0 0.22UF MIN_LINE_WIDTH=0.5 MM
SM-IHLP
VIN3 5% 10% MIN_NECK_WIDTH=0.2 MM
5 35 1/16W 10V
VOUT VIN4 MF-LF CERM
402 402
R7440 1 BST 8 1V05S5_VBST 1 2
1V05S5_VBST_R2 1
1V05S5_VLDO7 VLDO
130K 12 NC CRITICAL OMIT
1% DH
1/20W
MF 1V05S5_FBL 2 FBL
1
C7400 1 C7401 1 C7402
201 2 LX0 13 1V05S5_LL 330UF 10UF 0.01UF
20% 20% 10%
R7490
2
23 2 2.5V 2 4V 2 10V
LX1 XW7400
2
1V05S5_EN 29 EN/PSV POLY-TANT X5R X5R
63.4K 24 603 201
SM
SM
LX2 NO STUFF CASE-C2-SM
1%
OMIT 1/20W 26 LX3 25 R7420 1 C7410
MF 12.1K
1
PGOOD 180PF
C7492 1 201 1 LX4 28 1%
1/20W XW7401 5%
1UF LX5 33 MF 2 50V
CERM
10% 201
10V 2 402
X5R R7491 27 1V05S5_ILIM 1 2 1
R7410
2
402 ILIM
11K 14 NC
12.1K
1% DL 1V05S5_LL_XW PP1V05_S5_REG_XW 1%
1/20W 1/20W
MF MF
201 ENL 32 1V05S5_ENL 1 2 201
10K
1
AGND PGND R7412 1%

1 C7411
1/20W 0.01UF
MF 10%
201 2 10V
XW7402 2 X5R
4
30
34
15
16
17
18
19
20
21
22
1V05S5_FB_C 201 MAX CURRENT = 12A
1
SM
2
1 R7411
11.5K
1%
C7430 1
1 C7412 1/20W
MF PWM FREQ = 400KHZ
330PF 201
0.47UF
B 20%
4V
CERM-X5R 2
10%
16V
2 X7R
201
2
B
201 1V05S5_FB
GND_1V05S5_SGND
R7432
2
1K
5%
1/20W
MF
201
1
R7430
1 2
0 5%
1/20W
MF
201
5V LDO ENABLE EITHER FROM S5 CONTROL OR PBUS POWER
NO STUFF
=PPVIN_S5_1V05
R7431
1 2
53 7
100K 5%
1/20W
MF
201
1V05 S5 Power Supply

A 56 IN =P1V05_S5_EN
SYNC_MASTER=RXU_K20

A
56 OUT P1V05_S5_PGOOD THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
D 051-7631 2.3.0

NONE 53 71
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
1.5V/0.75V POWER SUPPLY
State PM_S4_STATE_L PM_SLP_S3_L PP1V5_S3 PP0V75_S0
S0 HIGH HIGH 1.5V 0.75V
S3 HIGH LOW 1.5V 0.0V
S5/G3Hot LOW LOW 0.0V 0.0V
Vout = 0.75V * (1 + Ra / Rb)
<Rb> NO STUFF
1 2 1V5S3_VDDQSET 1 2
R7522 <Ra> C7503

20K
1%
1/20W R7521 100PF
MF 20K 5%
25V
C 201 1%
1/20W
MF
201
CERM
201 C
1 2
1 2 MEMVTT_VREF
C7540
0.033UF
10%
16V
X5R
402 OMIT
1 2 1V5S3_V5FILT 1 2 =PP5V_S3_1V5S30V75S0 7
OMIT
C7500 R7507 1 C7502 PLACE XW7502 NEAR L7520
4.7 10UF
1UF 5%
1/16W 20% XW7502
SM
10% MF-LF 2 6.3V
10V 402 X5R 1V5S3_VDDQSNS 1 2
X5R 603
402-1
7 =PP0V75_S3_VTTREF
7 =PP0V75_S0_REG R7500
1V5S3_VBST 1 2
7 =PPVIN_S5_1V5S30V75S0
0
1V5S3_VBST_RC
5% CRITICAL CRITICAL
1/16W 1 1
1 C7531
MF-LF
OMIT 402 C7530 C7532 1UF
47UF 47UF 10%
1 1 C7511 2 25V PWM FREQ. = 400 kHz
23
24
14
22
15
R7510 20% 20% X5R
9
2
2.2UF 2 10V 2 10V 603-1
9.76K 5 CRITICAL POLY-TANT POLY-TANT
1%
1/20W
MF
VDDQSET VTTREF VLDOIN VTT V5FILT VBST V5IN VDDQSNS VTTSNS
20%
2 6.3V
CERM Q7520
CASE-B2-SM CASE-B2-SM
MAX CURRENT = 11A
2 201
402-LF C7509 1 SI7110DN (inductor limited)
B Routing Note: 0.1uF
10%
16V
D
PWRPK-1212-8-HF B
CONNECT VTTSNS TO C7507 PIN1 X5R 2 4
using separate trace. 402 G CRITICAL
57 24 =DDRVTT_EN 10 S3 PGOOD 13
S
56 =DDRREG_EN 11 S5
CRITICAL MIN_LINE_WIDTH=0.6 mm
L7520
DRVH 21 1V5S3_DRVH MIN_NECK_WIDTH=0.2 mm 1 2 3 1.0UH-22A-10M-OHM VOLTAGE=1.8V
U7500
SYM (1 OF 2) LL 20 1V5S3_LL MIN_LINE_WIDTH=0.6 mm 1 2 MIN_NECK_WIDTH=0.2 mm =PP1V5_S3_REG 7
SM-IHLP
6 COMP TPS51116 5
QFN MIN_LINE_WIDTH=0.6 mm CRITICAL
DRVL 19 1V5S3_DRVL MIN_NECK_WIDTH=0.2 mm
1
1V5S3_CS 16 CS CRITICAL OMIT C7543
Routing Note:
MODE 4 (1V5S3_VDDQSNS) D CRITICAL 1
C7542 1 C7541 330UF
20%
Q7521 330UF 10UF 2 2.5V
Connect CS_GND to NC0 7 NC 20% 20% POLY-TANT
Q7521 PIN1,2.3 4 G SI7108DN 2 2.5V 2 6.3V
X5R CASE-C2-SM1
using Kelvin connection. NC1 12 NC PWRPK-1212-8-HF POLY-TANT
CASE-C2-SM1 603
S
THRM_PAD CS_GND GND PGND VTTGND
Placement Note:
1 C7507 1 C7508 1 2 3
Placement Note:
22UF 22UF
25
17
18
PLACE C7507,C7508 GND NEAR PIN 1 20% 20% PLACE C7543 NEAR NB
2 6.3V
X5R-CERM 2 6.3V
X5R-CERM
603 603 (GND)
GND_1V5S3_SGND 1 2 DDRREG_PGOOD 56
Routing Note: XW7500
put 6 vias under the thermal pad Placement Note:
SM R7599 1.5V/0.75V Supplies
100K
PLACE XW7500, NEAR C7542 PIN 2 1%
1/20W SYNC_MASTER=M70 SYNC_DATE=01/09/2007
A GND_1V5S3_CSGND
1 2
1
MF
201
2 =PP3V3_S3_DDRREG 7 NOTICE OF PROPRIETARY PROPERTY
A
XW7501
SM THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
D 051-7631 2.3.0

NONE 54 71
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
5V_S3 / 3V3_S5 POWER SUPPLY D

D
55 7 =PP5V_S3_REG
2
XW7608
SM
PLACEMENT_NOTE=PLACE XW7608 NEXT TO C7691.
1
=PPVIN_S3_5VS3 P5VP3V3_V5SW =PPVIN_S5_3V3S5

7 7
P5VP3V3_VREG5
P5VP3V3_VREG3 CRITICAL
CRITICAL 55
1 C7681 C7640 1 1 C7641

C7680 1 1UF 47UF 1UF
47UF 20% 10%
20%
10V 2
10%
2 25V
C7600 1 P5VP3V3_VREF2
10V 2
POLY-TANT
25V
2 X5R
POLY-TANT X5R 1UF 55
CASE-B2-SM 603-1
CASE-B2-SM 603-1 10% OMIT OMIT
25V 2
23
29
22
13
X5R C7603 1 C7605
2
1
603-1
CRITICAL 1UF 10UF
V5SW
VIN
VREG5
VREG3
VREF2
Q7660 C7624 1
10%
6.3V 2
20%
2 6.3V
C7664 1 CRITICAL
CERM X5R 0.1UF Q7620
SI7904BDN 0.1UF 1 C7601 402 603 10%
SI7904BDN
6
PWRPK-1212-8 10% 16V 2
6
F=300KHZ D 16V 2
X5R
6 SKIPSEL1 CRITICAL 0.22UF X5R
402
PWRPK-1212-8 F=300KHZ
10% D
402 19 SKIPSEL2 2 10V
=PP5V_S3_REG CERM =PP3V3_S5_REG
55 7
14 TRIP U7600 402 7
C Vout = 5.0V
G 2 LLP
EN 12
2 G Vout = 3.3V
C
TPS51220
S
CRITICAL P5VS3_VBST 31 VBST1 VBST2 26 P3V3S5_VBST S CRITICAL
1
4A MAX OUTPUT MIN_LINE_WIDTH=0.6 mm MIN_LINE_WIDTH=0.6 mm 4A MAX OUTPUT
1
L7660 MIN_NECK_WIDTH=0.2 mm
P5VS3_DRVH 1 DRVH1 DRVH2 24 P3V3S5_DRVH MIN_NECK_WIDTH=0.2 mm L7620
(Q7660 limit) 3.3UH MIN_LINE_WIDTH=0.6 mm GATE_NODE=TRUE GATE_NODE=TRUE MIN_LINE_WIDTH=0.6 mm 3.3UH (Q7620 limit)
1 2 MIN_NECK_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm 1 2
P5VS3_LL 32 SW1 SW2 25 P3V3S5_LL
IHLP SWITCH_NODE=TRUE SWITCH_NODE=TRUE MIN_LINE_WIDTH=0.6 mm IHLP
NO STUFF CRITICAL
P5VS3_DRVL 30 DRVL1 P3V3S5_DRVL MIN_NECK_WIDTH=0.2 mm CRITICAL
CRITICAL CRITICAL OMIT DRVL2 27 2
C7690 1 Q7660 MIN_LINE_WIDTH=0.6 mm GATE_NODE=TRUE GATE_NODE=TRUE MIN_LINE_WIDTH=0.6 mm Q7620 OMIT CRITICAL CRITICAL
C7692 1 C7691 1 2 SI7904BDN MIN_NECK_WIDTH=0.2 mm
P5VS3_CSP1 7 CSP1 CSP2 18 P3V3S5_CSP2 MIN_NECK_WIDTH=0.2 mm SI7904BDN XW7605 1 C7650 1
C7652 1
C7651
5
10UF
5
150UF 150UF XW7602 PWRPK-1212-8 PWRPK-1212-8 SM

10UF
20% 20% 20%
6.3V 2 SM D
C7618 P5VS3_CSN1 8 CSN1 CSN2 17 P3V3S5_CSN2 D
20%
150UF 150UF
6.3V 2
POLY-TANT
6.3V 2
POLY-TANT X5R
603 0.1UF C7688 1
PLACEMENT_NOTE=PLACE XW7605 AND XW7606 NEXT TO L7620 . 2 6.3V
X5R
20%
2 6.3V
20%
2 6.3V
CASE-B2-SM CASE-B2-SM 1 2 1 2 55 P5VP3V3_VREG3 11 FUNC RF 3 P3V3S5_RF 0.1UF 603
POLY-TANT
CASE-B2-SM
POLY-TANT
CASE-B2-SM
XW7607 G 4 P5VS3_VFB1 9 VFB1 VFB2 16 P3V3S5_VFB2 1 2 4 G 2
SM 10% P5VS3_COMP1 10 P3V3S5_COMP2
S
16V COMP1 COMP2 15 10%
S
XW7606
3
3
PLACEMENT_NOTE=PLACE XW7602 AND XW7607 NEXT TO L7660.

1 X5R 25V SM
2 402 4 EN1 EN2 21 X5R
1 402
XW7603 R7647 P5VS3_PGOOD1 5 PGOOD1 PGOOD2 20 P5VS3_PGOOD2 R7637 1
2
SM 1.24K2 6.04K R7646
PLACEMENT_NOTE=PLACE XW7603 NEXT TO L7660
1
R76361 GND THRM_PAD 1%
1/20W 1.24K2 XW7604
SM
1 1% MF 1
R76561 6.04K
28
33
1/20W
XW7601 1 2 201
4.87K
MF
201
1%
1/20W SM R7606 1%
1/20W 1
R7616
1 PLACEMENT_NOTE=PLACE XW7604 NEXT TO L7620
1% MF 332K MF
P5VS3_VFB1-R 1/20W 201 2 1
1 2
R76981 1% 201 4.87K
MF
201 2 R7699 0 1/20W
MF
1%
1/20W P3V3S5_VFB2-R
0 5% 2 201 MF
5% 1/20W 2 201
R76201 P5VS3_CSP1-R 1/20W
MF
MF
201 2
1
R7660
40.2K 2 201 PLACEMENT_NOTE=Place XW7601 between U7600 pins 28 and 33. P3V3S5_CSP2-R 23.2K
1% 1%
1/20W 1/20W
MF MF
201 2 2 201
B 1
R7661
B
R76211 10K
10K 1%
1% 55 P5VP3V3_VREF2 P5VP3V3_VREF2 55 1/20W
1/20W MF
MF 2 201
201 2
GND_P5VP3V3_SGND
VOLTAGE=0V
One master PGOOD for both 5V and 3V3

56 OUT P5V3V3_PGOOD
56 IN =P5VS3_EN
56 IN =P3V3S5_EN
5V / 3.3V Power Supply
A SYNC_MASTER=RXU_K20

A
.
D 051-7631 2.3.0

NONE 55 71
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
S5 ENABLE
2
R7702
10K
1 P3V3S5_EN
MAKE_BASE=TRUE
=P3V3S5_EN
OUT 55
Power Control Signals
5%
1/20W
MF NO STUFF
201 1 C7702
0.068UF
D 2
10%
10V
CERM
402
D
SMC_PM_G2_EN
39 IN
S0 ENABLE
1
R7700
100K
5%
1/20W
MF
R7701 56 7 =PP3V3_S5_PWRCTL
C7758
201
2 5.1K 0.1UF
2 1 PM_G2_P1V05S5_EN =P1V05_S5_EN 53
MAKE_BASE=TRUE OUT 2 1
5%
1/20W
MF 1 C7701 10%
201 6.3V
0.47UF X5R
20% 201
2
4V 5 TC7SZ08AFEAPE
CERM-X5R 2 SOT665
201 A
4 (PM_SLP_S3_L_BUF) PM_SLP_S3_L_BUF =P5VS0_EN 57
U7759 Y MAKE_BASE=TRUE
OUT
39 35 34 20 6 PM_SLP_S3_L (PM_SLP_S3_L) 1
IN B
2
2 R7785 2 R7780 2 R7782 2 R7783 2 R7784 R7781
5% 5% 5% 5% 5% 5%
1/20W 1/20W 1/20W 1/20W 1/20W 1/20W
MF MF MF MF MF MF
S3 ENABLE R7779
1
1
201
22K 1
201
22K 1
201
0 1
201
5.1K 1
201 201
1
100K 0 4.7K
5%
1/20W
P5VS3_EN =P5VS3_EN 55 MF P3V3S0_EN =P3V3S0_EN OUT 57
MAKE_BASE=TRUE OUT
201 MAKE_BASE=TRUE
2
NO STUFF =PBUSVSENS_EN 43
OUT
C7712
R7712 0.47UF P1V05S0_EN OUT 57
1K 1 2
1 2
P1V8S0_EN =P1V8S0_EN OUT 52
5% MAKE_BASE=TRUE
C 1/20W
MF
201
10%
6.3V
CERM-X5R
402
MCPDDR_EN
MAKE_BASE=TRUE
=MCPDDR_EN OUT 57 C
MCPCORES0_EN =MCPCORES0_EN OUT 51
40 39 34 20 IN PM_SLP_S4_L MAKE_BASE=TRUE
MAKE_BASE=TRUE P3V3S3_EN =P3V3S3_EN
OUT 57
MAKE_BASE=TRUE DPPWR_EN =DPPWR_EN 61
OUT
MAKE_BASE=TRUE
1
R7710 C7713
R7713 0.47UF
100K
1K NO STUFF NO STUFF
5% 1 2 1 2
1/20W 1
C7785 1
C7780 1
C7782 1
C7783 1 C7784 1 C7781
MF 5%
201 10% 0.47UF 0.47UF 0.47UF 0.47UF 0.47UF 0.47UF
2 1/20W
6.3V 10% 10% 10% 10% 10% 10%
MF
CERM-X5R 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
201
402
2 CERM-X5R
2 CERM-X5R
2 CERM-X5R
2 CERM-X5R 2 CERM-X5R
2 CERM-X5R
402 402 402 402 402 402
C7711
R7711 0.47UF
5.1K
1 2 1 2
5%
1/20W 10%
MF 6.3V
201 CERM-X5R
402
DDRREG_EN =DDRREG_EN OUT 54

MAKE_BASE=TRUE
C7714
R7714 0.47UF
5.1K 1 2
1 2
5%
1/20W 10%
MF 6.3V
201 CERM-X5R
402
USBPWR_EN =USBPWR_EN 56 7 =PP3V3_S5_PWRCTL

OUT 37
MAKE_BASE=TRUE
C7740 1
0.1uF 1
B 10%
6.3V
X5R
2
R7740
100K
5%
B
201
1/20W
MF
6
201
2
VDD
5 SENSE RESET* 1 RSMRST_PWRGD
U7740 39
TPS3808G33DBVRG4
SOT23-6
CT 4 CT MR* 3 P1V05_S5_PGOOD 53
3.3V 1.05V AND 1.5V S0 RAILS MONITOR CIRCUIT CRITICAL
TPS3808 MR* HAS INTERNAL PULLUP
GND
2
C7741 1
7 =PP3V3_S0_VMON
1000PF
10%
16V
X7R 2
C7770 1 201
0.1uF
10%
6.3V
2
OTHER S0 RAILS PGOOD
X5R
3
201
24 7 =PP3V3_S0_PWRCTL
VCC 1
R7720
10K
5%
LTC2909 TIE TMR TO GND 1/20W
1 2 TRST = 200MS MF
SEL DFN TMR 201
2
7
=PP1V5_S0_VMON 8 ADJ1 4 S0PGOOD_PWROK
7 ADJ2 U7770 RST*
NC
6 REF CRITICAL R7721 Unused PGOOD signal POWER SEQUENCING
0
1 2
A 7 =PP1V05_S0_VMON
GND THRM_PAD
51 IN MCPCORES0_PGOOD
5%
1/20W
TP_DDRREG_PGOOD
MAKE_BASE=TRUE
DDRREG_PGOOD 54 SYNC_MASTER=YUAN.MA

A
5
MF
201
R7722 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

0 AGREES TO THE FOLLOWING
LTC2909 THRESHOLD IS 95% (3.136V) 55 IN P5V3V3_PGOOD 1 2
1.5V 1.05V COMPARED TO 0.5V I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
5%
1/20W ALL_SYS_PWRGD 24 39 II NOT TO REPRODUCE OR COPY IT
MF
OUT
MAKE_BASE=TRUE
201 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
R7723
0 SIZE DRAWING NUMBER REV.
1 2
5%
1/20W
D 051-7631 2.3.0
MF
201 APPLE INC. SCALE SHT OF
NONE 56 71
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
1.5V S0 FET
(1.5V S0 FET FOR DDR3 MEM, MCP79 AND CPU)
7 =PP1V5_S3_P1V5S0FET
CRITICAL
3.3V S3 FET Q7810
5
FDC638P_G
SM
C7802 1
0.1UF
6
3.3V S3 FET 10%
6.3V CRITICAL
2 D
4
5 =PP3V3_S3_FET 7
7 =PP5V_S3_MCPDDRFET R7801 X5R
201 Q7801
2
MOSFET FDC638P 10K SI7108DN
1 2 MCPDDR_SS 4 G PWRPK-1212-8-HF
1
CHANNEL P-TYPE
R7812 1
C7811 1 5%
1/20W S
D 10K
5%
33000PF
10%
6.3V 3
RDS(ON) 48 mOhm @4.5V
R7803 1
MF
201
SSM6N15FEAPE
Q7871 D 6
1 2 3
D
1/20W
X5R
2
LOADING 0.315 A (EDP) 100K
MF
201 5% SOT563 =PP1V5_S0_FET 7
201
2
R7810 C7810 1/20W
MF
0.01UF
47K 201
2
P3V3S3_EN_L 1 2 P3V3S3_SS 1 2
R7871 2 G S 1
1
C7803
5%
1/20W 10% 47K 0.068UF 1.5V S0 FET
10V MCPDDR_EN_L 1 2 10%
Q7803 MF
201
X5R
5%
2
10V
CERM MOSFET SI7108DNS
201
SSM3K15FV D 3 1/20W 402
MF
SOD-VESM-HF
Q7871 D 3
201 CHANNEL N-TYPE
MCPDDR_EN_L_RC
SSM6N15FEAPE
SOT563 RDS(ON) 6 MOHM @3.5V VGS
LOADING 5.027A (EDP)

1 G S 2
56 IN =P3V3S3_EN 5 G S 4
56 IN =MCPDDR_EN
CRITICAL
5V S0 FET Q7840 3.3V RMGT FET
FDC606P_G
SOT-6
5V S0 FET
5 6
@ 2.5V Vgs: CRITICAL
=PP5V_S0_FET 7
7 =PP5V_S3_P5VS0FET Rds(on) = 90mOhm max Q7820
MOSFET FDC606P
D
4
2
I(max) = 1.7A (85C) NTR4101P
1
SOT-23-HF
CHANNEL P-TYPE
R7842 1
C7841 1
7 =PP3V3_S5_P3V3RMGTFET =PP3V3_RMGT_FET 7
G
33000PF RDS(ON) 26 MOHM @4.5V S D
100K 2 3
3
10%
5%
6.3V
1/20W
X5R
2 LOADING 0.562 A (EDP)
MF
201
2
201
C7840 R7820 1 1 C7821 G
R7840 0.01UF 10K 0.033UF
C P5VS0_EN_L 1
33K 2 P5VS0_SS 1 2
5%
1/20W
MF
2
10%
16V
X5R
402
1
C7820
C
5%
1/20W
10%
201
2 R7821 0.01UF
MF 10V
100K
Q7845 201 X5R
201
P3V3RMGT_EN_L 1 2 P3V3RMGT_SS 2 1
SSM3K15FV D 3 5%
SOD-VESM-HF 1/20W 10%
MF 16V
Q7821 D 3
201 CERM
402
SSM6N15FEAPE
SOT563
1 G S 2
56 =P5VS0_EN
IN
G S
CRITICAL
PM_SLP_RMGT_L
5
4
1.05V RMGT FET
3.3V S0 FET Q7830 57 20 IN
7 =PP1V05_RMGT_P1V05RMGTFET
FDC606P_G
SOT-6
3.3V S0 FET @ 1.8V Vgs:
5 6
=PP3V3_S0_FET 7
7 =PP3V3_S5_P3V3S0FET Rds(on) = 47mOhm max
C7860 1
MOSFET FDC606P 3 I(max) = 3.1A (70C)
S
0.1UF
4
20%
D CRITICAL
1
10V
CHANNEL P-TYPE CERM 2
R7832 1
C7831 1
7 =PP3V3_S5_P1V05RMGTFET R7860 402 Q7860
G
100K 33000PF RDS(ON) 26 MOHM @4.5V 10K 1 G SI2312BDS

5% 1 2 P1V05RMGT_SS
SOT23
3
10%
1/20W
MF
6.3V
2 LOADING 2.046 A (EDP) 1% S
X5R
201
2
R7830 201 C7830 1/20W
MF
D 6 2
47K
0.01UF R7864 1 201 Q7861 =PP1V05_RMGT_FET 7
P3V3S0_EN_L 1 2 P3V3S0_SS 1 2
69.8K SSM6N15FEAPE
1% SOT563
5% 1/20W
1/20W 10%
MF
10V
Q7805 MF
201 X5R
201
2
SSM3K15FV D 3
201
R7861 2 G S 1
1
C7861
SOD-VESM-HF 15K 0.068UF
B P1V05RMGT_EN_L 1
1%
2
2
10%
10V
CERM
B
MCP79 DDRVTT FET D 3
1/20W
MF
402
Q7861 201 P1V05RMGT_EN_L_RC

1 G S 2
56 IN =P3V3S0_EN 1.05V S0 FET MCP79 DDR PAD LEAKAGE IS HIGH ENOUGH THAT
SSM6N15FEAPE
SOT563
NVIDIA RECOMMENDS UNPOWERING DURING SLEEP.

IN ORDER TO SUPPORT UNPOWERING RAIL, HARDWARE 5 G S 4
MUST GUARANTEE MEM_CKE SIGNALS ARE LOW
57 20 IN PM_SLP_RMGT_L
7 =PP5V_S3_P1V05S0FET R7852 1.05V S0 FET
BEFORE RAIL IS TURNED OFF, AND REMAINS LOW
220K 2 UNTIL AFTER RAIL TURNS BACK ON OR DIMMS
1 P1V05S0_SS
MOSFET SI7108DN WILL EXIT SELF-REFRESH PREMATURELY.
5% 5
1/20W MEM_VTT_EN OUTPUT FROM MCP79 USED TO ENABLE CLAMP
MF
CHANNEL N-TYPE
201 ON VTT RAIL, WHICH PULLS ALL CKE SIGNALS
D CRITICAL
NO STUFF RDS(ON) 6.1 MOHM @4.5V VGS LOW THROUGH VTT TERMINATION RESISTORS.
C7852 NO STUFF Q7853
0.1UF R7854 4
SI7108DN LOADING 8.25A (EDP)
R7875
7 =PP3V3_S5_P1V05FET 510 G PWRPK-1212-8-HF 10
2 1 P1V05S0_RC 1 2 7 =PPVTT_S0_VTTCLAMP 2 1 VTTCLAMP_L 90mA max load @ 0.9V
5% S 5% 81mW max power
10% 1/20W 1/10W
6.3V MF MF-LF
X5R 201 1 2 3 603
201
Q7851 D 6 CKT FROM T18
R7853 1 SSM6N15FEAPE
7 =PP5V_S3_VTTCLAMP
D
10K
5%
SOT563 =PP1V05_S0_FET 7
Q7875 6
SSM6N15FEAPE
1/20W
MF
R7876 1 SOT563
201
2
100K
5%
R7851 2 G S 1
1
C7853 1/20W
MF POWER FETS
100K 2 0.068UF 201 2 G S
P1V05_EN_L 1 10% 2 1
10V
SYNC_MASTER=YUAN.MA SYNC_DATE=02/04/2008
A 5%
1/20W
MF
2 CERM
402
VTTCLAMP_EN
A
Q7851 D 3 201
P1V05_EN_L_RC D NO STUFF
SSM6N15FEAPE
SOT563
Q7875 3
C7876 1
SSM6N15FEAPE AGREES TO THE FOLLOWING
SOT563 1000PF
10%
16V I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
X7R 2
5 G S 201 II NOT TO REPRODUCE OR COPY IT
4
P1V05S0_EN
5 G S 4
56 IN
54 24 IN =DDRVTT_EN SIZE DRAWING NUMBER REV.
D 051-7631 2.3.0

NONE 57 71
8 7 6 5 4 3 2 . 1
8 7 6 5 4 3 2 1
CRITICAL
PBUS SUPPLY / BATTERY CHARGER CRITICAL
Q7900 Q7901
HAT1127H HAT1127H
LFPAK-SM LFPAK-SM
7 =PP18V5_G3H_CHGR PPVDCIN_G3H_PRE
3
49 70 43
S
PPVDCIN_G3H_PRE2
2
70
D CRITICAL MIN_LINE_WIDTH=0.2 MM
D
1
1
D7910
SOD-323
G
B0530WS-X-G
C7900 1 R79001
4
2 R7999
0.1UF 100K 100K
5% CHGR_SGATE_DIV 2 1
10% 1/20W
25V 2 MF
5%
X5R =PP3V42_G3H_CHGR 1 MIN_NECK_WIDTH=0.2 MM 1/20W
402 201 2 58 7 R7962 MF
1
62K 201
C7960 5%
R79601 0.1UF 1/20W
MF
57.6K 10% 201 2
1% 5 2 25V
X5R
1/20W CHGR_AMON 1 402
MF VCC
201 2 4 CHGR_LOWCURRENT_GATE
3 GND
CHGR_LOWCURRENT_REF
CRITICAL
R79611
2 U7960
58 CHGR_DCIN TL331
1.82K SOT23-5
1%
1/20W
C7910 1 MF
201
0.1UF 2 XW7920
10%
25V 2
R7923 SM
X5R R7901 2
10 1 1 2
402 62K 70 PPVDCIN_G3H_PRE_0 CRITICAL
CHGR_SGATE 2 1 C7924 5% MIN_LINE_WIDTH=0.2MM
1
MIN_LINE_WIDTH=0.2 MM 5% 0.047UF 1 1/20W MIN_NECK_WIDTH=0.2MM
MF R7920
1/20W 10%
16V R7921 201 0.02
MF 10 0.5%
58 1 2CHGR_VDD 1 2 CHGR_VDDP 201 CERM
5% 1W
1 402
R7910 OMIT R7940
OMIT 2 1/20W
MF
XW7921
SM
MF
2 0612
30.1K
1% C7941 4.7
5%
1 C7940 1
201
2 1
PPVDCIN_G3H_PRE_R 2
1/20W 58 7 =PP3V42_G3H_CHGR 1UF 1/16W 1UF
MF 10% MF-LF 10% MIN_LINE_WIDTH=0.2MM
2 10V
10V 402
C 201 2
(CHGR_ACIN) C7947 1 X5R
402-1
X5R
402-1 C
44
1UF KELVIN CONNECTION
10%
7
6.3V 2 MIN_LINE_WIDTH=0.6 MM
R79111 OMIT TO CURRENT SENSOR U5480
19
20
X5R C7995 C7996 MIN_NECK_WIDTH=0.2 MM 70 PP18V5_S5_CHGR_SW_R
9.76K 402-1
1% 0.1UF 1 1 0.1UF CRITICAL CRITICAL
1/20W VDD VDDP 10% 10%
MF
201 2 12 VHST CRITICAL
AGATE 1 CHGR_AGATE
25V
X5R
25V
X5R
1
C7920 1
C7921 1 C7922 1 C7923
402 402 22UF 22UF 1UF 1UF CRITICAL
58 CHGR_SCL 11 SCL U7900 CSIP 28 CHGR_CSIP 2 2
20% 20% 10%
25V
10%
25V
pullups offpage QFN 2 25V 2 25V 2 X5R 2 X5R R7980
CHGR_SDA 10 SDA CSIN 27 CHGR_CSIN POLY-TANT POLY-TANT
ISL6258
58 603-1 603-1
CASE-D2-SM CASE-D2-SM 0.0022
OMIT GND_CHGR_SGND 58 1 =PPBUSA_G3H 7 44
4 VREF BGATE
58 16 CHGR_BGATE
1%
NC DCIN 2 CHGR_DCIN 58 D CRITICAL 1/4W
CHGR_ACIN 3 ACIN MF-LF
BOOT 25 CHGR_BOOT Q7920
FDMC8296
CRITICAL
1206
TO SYSTEM
CHGR_ICOMP 5 ICOMP UGATE 24 CHGR_UGATE G
POWER33 1 2 =PPBUSB_G3H
CHGR_VCOMP 7 VCOMP PHASE 23 CHGR_PHASE S
C7925
C7942 1 CHGR_VNEG 8 VNEG
LGATE 21 CHGR_LGATE 0.1UF
1
CRITICAL F7900 CRITICAL
33000PF CHGR_CSOP 18 CSOP 10% 7AMP-24V R7930
10% TRKL* 13 NC 25V 1206 0.01
6.3V
X5R 2 1
CHGR_CSON 17 CSON
AMON 9 CHGR_AMON 58
X5R
402 2 L7900 0.5%
201 R7945 C7943
4.7UH-7.5A MIN_LINE_WIDTH=0.6 MM 1W
MF MIN_LINE_WIDTH=0.6 MM
29 THRM_PAD
56.2K CHGR_BMON 58 MIN_NECK_WIDTH=0.2 MM 0612 MIN_NECK_WIDTH=0.2 MM
BMON 15 2 1 PPVBAT_G3H_CHGR_REG 1 2 PPVBAT_G3H_CHGR_OUT
1% 0.1UF CHGR_ACOK 58
70 58 70
1/16W ACOK 14 MIN_LINE_WIDTH=0.6 MM
1 C7944 1 2 IHLP4040CZ-SM
6 AGND
PGND
MF-LF MIN_NECK_WIDTH=0.2 MM
0.01UF 402 2 CRITICAL CRITICAL 1 C7935
10% CHGR_VCOMP_R 10% CRITICAL 1
C7930 1
C7931 1UF
10V
2 X5R 16V D 10%
47UF 47UF 2 25V
26
22
X5R
201 C7945 1 402
Q7921 20%
2 10V
20%
10V
X5R
603-1
0.001UF FDMC8296 POLY-TANT 2 POLY-TANT
10% G CASE-B2-SM CASE-B2-SM 2
GND_CHGR_SGND 50V POWER33
58
CERM 2 XW7930
402 S 2
1 2 SM
XW7931
B XW7900
1 C7926
1000PF
1 SM
B
R79461
3.01K
SM 10%
16V
2 X7R
PWM FREQ. = 400 kHz PPVBAT_G3H_CHRGR_REG_0 70
1
1%
1/16W 201
MAX CURRENT = 5.35A?? R79311 70 PPVBAT_G3H_CHRGR_REG_R
MF-LF 10 MIN_LINE_WIDTH=0.2MM
402 2 5% MIN_NECK_WIDTH=0.2MM
CHGR_VNEG_R 58 GND_CHGR_SGND (AC adapter limited?) 1/20W

MF R79471
201 2
10
C7946 1 5%
1/20W
470PF MF
10% (CHGR_CSOP) (CHGR_CSOP) 201 2
50V
CERM 2
402 (CHGR_CSON)
42 =SMBUS_CHGR_SCL CHGR_SCL 58
42 =SMBUS_CHGR_SDA CHGR_SDA 58
ACOK pullup/down on SMC page

SMC_BC_ACOK
49 40 39
MAKE_BASE=TRUE
CHGR_ACOK 58
AMON PULLDOWN LOGIC
CHGR_AMON 58
BATTERY CHARGING
PLACE RC CLOSE TO SMC CRITICAL
58
CHGR_BMON 1 2 SMC_BATT_ISENSE 39 Q7950
1NO STUFF FDS6681Z
R7971
0
1
58 7 =PP3V42_G3H_CHGR R7975
1M SO-8 TO BATTERY
5%
1/16W C7972 5% MIN_LINE_WIDTH=0.6 MM
MF-LF 0.68UF 1/20W MIN_NECK_WIDTH=0.2 MM
402 10%
6.3V R7974 1 Q7970 MF
PPVBAT_G3H_CHGR_OUT
BATT_POS_F 49
2 201
70 58
2 CERM 1MSSM6N15FEAPE
SOT563
D 6
PBUS Supply/Battery Charger
402 5%
GND_SMC_AVSS 1/20W 1 C7950 1 C7951
A 39 40 43 44 58 MF
201 2 0.01UF
10%
2 10V
0.1UF
10%
2 16V
SYNC_MASTER=M70

A
PLACE RC CLOSE TO SMC
58 CHGR_VDD
X5R X5R
58
CHGR_AMON 1 2 SMC_DCIN_ISENSE 39 2 G S 1 201 402
R7970 1 C7971 Q7970 D 3 CHGR_VDD_L AGREES TO THE FOLLOWING
0
5%
1/16W
0.68UF
10% R79731SSM6N15FEAPE I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
MF-LF
2 6.3V 100K SOT563 II NOT TO REPRODUCE OR COPY IT
402 CERM 5% CHGR_BGATE 58
402 1/20W III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
MF
GND_SMC_AVSS 39 40 43 44 58 201 2
5 G S 4 SIZE DRAWING NUMBER REV.
CHGR_VDD_R
D 051-7631 2.3.0

NONE 58 71
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
7 =PP3V3_S5_LCD CRITICAL
1 Q9003
R9002 FDC638P_G
5%
100K
1/20W
SM
6 PP3V3_LCDVDD_SW
LCD + CAMERA CONNECTOR
MF 70
2 201 5 VOLTAGE=3.3V
R9023 4
2 OMIT
CRITICAL
D LCDVDD_PWREN_L
10K 1 1 C9011 1 C9012 L9007 D
2
C9040 1
5% 0.1UF 10UF 90-OHM-100MA
0.1UF Q9004 1/20W 10% 20% 1210-4SM1
SYM_VER-1
10% SSM3K15FV D MF 2 6.3V 2 6.3V
6.3V 2
X5R SOD-VESM-HF
3 201
LCDVDD_PWREN_L_R
3 X5R
201
X5R
603 8 BI =USB2_CAMERA_N 1 4 L9052
201 240-OHM-0.2A-0.8-OHM
C9013 2 3 42 6 =I2C_ALS_SDA 1 2 I2C_ALS_SDA_F
3300PF 8 BI =USB2_CAMERA_P 0201
1 2 CRITICAL
1 G S 2
L9005 L9051
10% 240-OHM-0.2A-0.8-OHM
10V FERR-120-OHM-1.5A
17 LVDS_IG_PANEL_PWR X5R 42 6 =I2C_ALS_SCL 1 2 I2C_ALS_SCL_F
IN 201 =PP5V_S3_CAMERA 1 2
7
0201
0402-LF
1
R9014 C9016 1 1 C9052 CRITICAL
100K 1000PF 10PF C9051 1
5%
1/20W 10%
16V
5%
25V 10PF
J9000
MF X7R 2 2 NPO 20347-130E-11
2 201 CRITICAL 201 201
5%
25V F-RT-SM
2
L9004 NPO
201
38
FERR-120-OHM-1.5A
1 2 1
0402-LF 2
C9015 1 3
1000PF VOLTAGE=5V MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM 70 6 PP5V_S3_CAMERA_F 4
10%
PLACE FILTERS AND CAPS NEAR PINS ON CONNECTOR 16V 2 6 USB2_CAMERA_F_P 5
X7R
201 6 USB2_CAMERA_F_N 6 CAMERA I/F
7
L9008 VOLTAGE=3.3V MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM 70 6 PP3V3_LCDVDD_SW_F 8
120-OHM-0.3A-EMI 9 LCD I/F
7 =PP3V3_S0_LCD 1 2 (LVDS DDC POWER) VOLTAGE=3.3V MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM 70 6 PP3V3_S0_LCD_F 10
C 0402-LF 11
12
C
C9010 1
67 LVDS_IG_A_DATA_F_N<0> 13
1000PF
10% 67 LVDS_IG_A_DATA_F_P<0> 14
16V 2
X7R 67 LVDS_IG_A_DATA_F_N<1> 15
201
67 LVDS_IG_A_DATA_F_P<1> 16
67 LVDS_IG_A_DATA_F_N<2> 17
67 LVDS_IG_A_DATA_F_P<2> 18
67 6 LVDS_IG_A_CLK_F_N 19
67 6 LVDS_IG_A_CLK_F_P 20
21
62 6 LCDBKLT_RTN<1> 22
1 LCDBKLT_RTN<2> 23
R9008 R9009
62 6
1
10K 62 6 LCDBKLT_RTN<3> 24
10K 5%
LCDBKLT_RTN<4> 25
5% 1/20W 62 6
1/20W MF 26
MF 2 201 62 6 LCDBKLT_RTN<5>
17 6 LVDS_IG_DDC_CLK 2 201 62 6 LCDBKLT_RTN<6> 27
BI
17 6 LVDS_IG_DDC_DATA 28
BI
62 6 PPVOUT_S0_LCDBKLT 29
70
30
31
32
CRITICAL
33
67 17 6 LVDS_IG_A_DATA_N<0>
L9010 34
BI 2 3
67 17 6 LVDS_IG_A_DATA_P<0> 35
BI
B 1
1210-4SM1
SYM_VER-2
4
36
37 B
90-OHM-100MA
39
CRITICAL
LVDS_IG_A_DATA_N<1>
L9011
67 17 6
67 17 6
BI
BI LVDS_IG_A_DATA_P<1>
2 3 518S0433
1 SYM_VER-2
4
1210-4SM1
90-OHM-100MA
MIC CONNECTOR CRITICAL
67 17 6 LVDS_IG_A_DATA_N<2>
L9012
BI 2 3
CRITICAL LVDS_IG_A_DATA_P<2>
CRITICAL L9050 67 17 6 BI
J9050 600-OHM-300MA
1 4
GS03067-11131-7F 1 2 =PP3V3_S0_MIC 7
1210-4SM1
SYM_VER-2
F-RT-SM MIN_LINE_WIDTH=0.20MM 90-OHM-100MA
7 MIN_NECK_WIDTH=0.20MM 0402
VOLTAGE=3.3V
CRITICAL
1 PP3V3_S0_MIC_F CRITICAL L9006
2 NC L9030 90-OHM-100MA
1210-4SM1
3 NC 600-OHM-300MA 67 17 LVDS_IG_A_CLK_N 1 SYM_VER-2 4
BI
4 6 AUD_MIC_DATA_F 1 2 AUD_MIC_DATA 6 35 67 17 BI LVDS_IG_A_CLK_P
5 6 AUD_MIC_CLK_F CRITICAL
0402
2 3
6 6 GND_MIC_F L9031 LVDS,Camera Conn. and ALS Conn.
600-OHM-300MA
8 CRITICAL 1 2 AUD_MIC_CLK SYNC_MASTER=GPU SYNC_DATE=06/23/2006
A L9053
600-OHM-300MA 0402
6 35

A
1 2
MIN_LINE_WIDTH=0.20MM THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
MIN_NECK_WIDTH=0.20MM 0402 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
C9050 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
0.01UF
10%
APN:518S0536 16V
CERM
402
2
C9053 1
NO STUFF 1
C9030
10PF
1 NO STUFF
C9031
10PF
0.01UF 5% 5% SIZE DRAWING NUMBER REV.

10% 25V 25V
16V NPO 2 2 NPO
CERM
402
2 201 201
D 051-7631 2.3.0

NONE 59 71
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
17 =MCP_HDMI_TXC_P DP_ML_P<3> 61 67
MAKE_BASE=TRUE
17 =MCP_HDMI_TXC_N DP_ML_N<3> 61 67
MAKE_BASE=TRUE
17 =MCP_HDMI_TXD_P<0> DP_ML_P<2> 61 67
MAKE_BASE=TRUE
17 =MCP_HDMI_TXD_N<0> DP_ML_N<2> 61 67
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
17 =MCP_HDMI_HPD DP_HPD 61
D 17 =MCP_HDMI_DDC_CLK DP_IG_DDC_CLK
MAKE_BASE=TRUE
MAKE_BASE=TRUE
60 D
17 =MCP_HDMI_DDC_DATA DP_IG_DDC_DATA 60
MAKE_BASE=TRUE
DP_AUX_CH_C_N 6 35 61 67
BI
R9300 C9300
0.1UF
60 DP_IG_DDC_DATA 1
33 2 1 2 67 DP_AUX_CH_SW_N
BI
5%
1/20W 10%
MF 6.3V
201 X5R
201
DP_AUX_CH_C_P 6 35 61 67
BI
R9301 C9301
0.1UF
60
DP_IG_DDC_CLK 1
33 2 1 2 67 DP_AUX_CH_SW_P
BI
5%
1/20W 10%
MF 6.3V
201 X5R
201
C 3 D Q9300 Q9300 D 6
C
SOT563 SOT563
4 S G 5 2 G S 1
67 17
DP_IG_AUX_CH_P
BI
67 17
DP_IG_AUX_CH_N
BI
=PP5V_S0_DP_AUX_MUX
7
1
R9306
1K
5%
1/20W 1
MF
2 201
R9302
100K
5%
1/20W
MF
2 201
DDC_CA_DET_LS5V_L
B B
Q9301
3 D SSM3K15FV
SOD-VESM-HF
2 S G 1
61
DP_CA_DET
IN
DP_IG_CA_DET 17
OUT
DISPLAYPORT SUPPORT
SYNC_MASTER=NMARTIN SYNC_DATE=12/18/2007
A
D 051-7631 2.3.0

NONE 60 71
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CRITICAL
61 7 =PP3V3_S0_DPCONN
1
U9450
C9451 TPS2051
0.1UF MSOP
10%
6.3V
2 IN OUT 8
X5R 2
D
201 3 IN OUT 7
6
D
OUT
56 IN =DPPWR_EN 4 EN OC* 5 NC L9400
FERR-120-OHM-3A
THRML
GND PAD 70 PP3V3_S0_DPFUSE
70
35 6 PP3V3_S0_DPPWR
1 9 MIN_LINE_WIDTH=0.38 MM MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM 0603 MIN_NECK_WIDTH=0.20 MM
NO STUFF1 VOLTAGE=3.3V VOLTAGE=3.3V
C9450 DP_ESD 1
C9400
22UF CRITICAL 0.01UF
20% 10%
6.3V
2
D9411 2
10V
X5R-CERM X5R
603 RCLAMP0524P 201
SLP2510P8 DP_ESD
CRITICAL
D9410
5 IO
RCLAMP0524P
IO 4
SLP2510P8
6 NC NC 7
GND
5 IO IO 4
6 NC NC 7
R9420 1 3
100K
GND
5%
1/20W
FL9400
12-OHM-100MA
MF
201 3
2
TCM1210-4SM
67 60 IN DP_ML_P<0> C9410 1 2 67 6 DP_ML_C_P<0> 1 SYM_VER-2 4
0.1uF
10% 6.3V X5R 201 FL9410
12-OHM-100MA
TCM1210-4SM
67 60 IN DP_ML_N<0> C9411 1 2 DP_ML_C_N<0> 2 3 1 SYM_VER-2 4 DP_ML_C_P<1> C9412 1 2 DP_ML_P<1> IN 60 67
10% 6.3V X5R 201 10% 6.3V X5R 201
0.1uF 0.1uF
2 3 C9413
C FL9420 DP_ML_F_P<0> 35 67
DP_ML_C_N<1>
0.1uF
1 2
10%
DP_ML_N<1>
6.3V X5R 201
IN 60 67
C
12-OHM-100MA
TCM1210-4SM DP_ML_F_N<0> 35 67 67 35 DP_ML_F_P<1> FL9430
67 60 IN DP_ML_P<2> C9414 1 2 DP_ML_C_P<2> 1 SYM_VER-2 4 12-OHM-100MA
TCM1210-4SM
10% 6.3V X5R 201 67 35 DP_ML_F_N<1>
0.1uF 1 SYM_VER-2 4 67 6 DP_ML_C_P<3> C9416 1 2 DP_ML_P<3> IN 60 67
DP_ML_F_P<2> 35 67 10% 6.3V X5R 201
0.1uF
67 60 IN DP_ML_N<2> C9415 1 2 DP_ML_C_N<2> 2 3 DP_ML_F_N<2> 35 67 67 35 DP_ML_F_P<3>
10% 6.3V X5R 201
0.1uF 67 35 DP_ML_F_N<3> 2 3 67 6 DP_ML_C_N<3> C9417 1 2 DP_ML_N<3> IN 60 67
10% 6.3V X5R 201
DP_CA_DET_Q 6 35 35 6 HDMI_CEC 0.1uF
67 60 35 6 BI DP_AUX_CH_C_P
67 60 35 6 BI DP_AUX_CH_C_N 35 6 DP_HPD_Q 1
R9425
61 7 =PP3V3_S0_DPCONN 1M
These nets connect to 5%
1/20W
1 RIO connector @ J4200
R9440 MF
100K R9421 1 DP_ESD

CRITICAL
DP_ESD
CRITICAL 2
201
5% 100K
1/20W
MF
5%
1/20W
D9410 D9411
201 2 1 MF RCLAMP0524P RCLAMP0524P
60 OUT DP_CA_DET R9441 201
2 SLP2510P8 SLP2510P8
100K
5%
6 1/20W
MF
Q9440 D 201 2 2 IO IO 1 2 IO IO 1
2N7002DW-X-G 9 NC NC 10 9 NC NC 10
SOT-363 2 DP_CA_DET_L
S G
GND
GND
3 DP_ESD
1 CRITICAL
Q9440 must have Drain to Gate leakage of <500nA
D Q9440 3
D9400
3
2N7002DW-X-G
and Gate to Source resistance of >5MOhm SOT-363 RCLAMP0504F
G 5 (DP_CA_DET_Q) SC70-6-1
S
B 4
1
6 B
1
R9422 DP to DVI/HDMI 2 5
1M
5% Cable Adapter
1/20W
MF (CA) has 100k 4
201 3
2
pullup to DP_PWR.
61 7 =PP3V3_S0_DPCONN
R94451
10K
5%
1/20W
MF
201 2
60 OUT DP_HPD R94441

10K
6 5%
1/20W
R94461 MF
100K Q9441 D 201 2
1% 2N7002DW-X-G
1/20W SOT-363
MF S G 2DP_HPD_DET_L
201 2 DisplayPort Connector
1 3
A Q9441 SYNC_MASTER=M98_MLB SYNC_DATE=01/17/2008

D
2N7002DW-X-G
SOT-363 NOTICE OF PROPRIETARY PROPERTY
A
G 5 (DP_HPD_Q)
MCP requires pull S
down HPD input with PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
100K if DP_HPD is used. R94231 DP Source must pull I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
100K
1% down HPD input with II NOT TO REPRODUCE OR COPY IT
1/20W
MF greater than or equal III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
201 2
to 100K (DPv1.1a).
D 051-7631 2.3.0

NONE 61 71
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
LED Backlight Driver

D D
CRITICAL
CRITICAL
L9750 D9750
70 63 PPBUS_S0_LCDBKLT_PWR 22UH-1.7A SM PPVOUT_S0_LCDBKLT 6 59 70
70 PPVOUT_S0_LCDBKLT_SW 1 2 MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.5 mm VOLTAGE=35V
7 =PP3V3_S0_LCDBKLT IHLP2020CZ11-SM MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE PD3S140XF 1
C9755 1
C9756 1
C9757 1
C9758
4.7UF 4.7UF 4.7UF 4.7UF
10% 10% 10% 10%
50V 50V 50V 50V
5 TC7SZ08AFEAPE 2 X7R-CERM 2 X7R-CERM 2 X7R-CERM 2 X7R-CERM
63 17 IN LVDS_IG_BKL_ON 2
A
SOT665 R9741 1206 1206 1206 1206
4
10K
U9740Y 63 LCDBKLT_ENA 1 2
24 BKLT_PLT_RST_L 1 5%
IN B
1/20W
MF
3 1 NO STUFF C9741 1 1 C9751 1 C9750
C9740 R9740 201
4
1
100K 0.1UF 1UF 10UF
0.1UF 5% 10% 10% 10%
10% 16V 25V 25V VIN
6.3V 2 1/20W
MF
X5R 2 2 X5R 2 X5R
CRITICAL
X5R 402 603-1 1206-1
201 2 201
U9750 R97551
OZ9956ALN f=500KHz 1M
1%
C LCDBKLT_ENA_RC
>2V = ON, <1V = OFF
1 ENA
QFN
SW 18
1/20W
MF
201 2 R9771
C
1
63 IN BKLT_PWM 20 PWM ISEN1 10 LCDBKLT_RTN_RC<1> 1 2 LCDBKLT_RTN<1> 6 59
MIN_LINE_WIDTH=0.25 mm MIN_LINE_WIDTH=0.25 mm
100Hz - 20KHz MIN_NECK_WIDTH=0.2 mm 5%
1/20W
LCDBKLT_ISET 8 ISET ISEN2 11 LCDBKLT_RTN_RC<2> MF
MIN_LINE_WIDTH=0.25 mm 201
ILED[A] = 1500/R9766 MIN_NECK_WIDTH=0.2 mm
LCDBKLT_RT 5 RT ISEN3 12 LCDBKLT_RTN_RC<3> R9772
FOP[Mhz] = 50000/R9764 MIN_NECK_WIDTH=0.2 mm
1
1 2 LCDBKLT_RTN<2> 6 59
LCDBKLT_SSTCMP 9 SSTCMP ISEN4 14 LCDBKLT_RTN_RC<4> MIN_LINE_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.25 mm 5% MIN_NECK_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm 1/20W
MF
R97661 1
R9762 LCDBKLT_VREF 3 VREF ISEN5 15 LCDBKLT_RTN_RC<5> 201
75K 10K
C9763 1 MIN_LINE_WIDTH=0.25 mm
0.001UF MIN_NECK_WIDTH=0.2 mm
1%
1/20W
1%
1/20W 10%
50V NC 2 NC1 ISEN6 16 LCDBKLT_RTN_RC<6> R9773
MF MF CERM 2 MIN_LINE_WIDTH=0.25 mm 1
201 2 2 201 402 NC 7 NC2 MIN_NECK_WIDTH=0.2 mm 1 2 LCDBKLT_RTN<3> 6 59
NC 17 NC3 OVP 6 LCDBKLT_OVP 5% MIN_NECK_WIDTH=0.2 mm
LCDBKLT_SSTCMP_RC 1/20W
OMIT NC 19 NC4 OVP Threshold: 37.9V MF
1
THRML 201
R9764 C9762 1 1 C9760 GNDA PAD R97561
100K 78.7K R9774
13
21
1% 0.01UF 1UF 1%
1/20W 20% 10% 1/20W 1
16V 10V 1 2 LCDBKLT_RTN<4>
MF CERM 2 2 X5R MF 6 59
2 201 402 402-1 201 2 MIN_LINE_WIDTH=0.25 mm
1/20W
GND_LCDBKLT_GNDA XW9750 MF
201
MIN_LINE_WIDTH=0.5 mm SM
VOLTAGE=0V 1 2
R9775
1
1/20W
B MF
201 B
R9776
1
1/20W
MF
201
C9771 1 C9772 1 C9773 1 C9774 1 C9775 1 C9776 1

1000PF 1000PF 1000PF 1000PF 1000PF 1000PF
10% 10% 10% 10% 10% 10%
16V 16V 16V 16V 16V 16V
X7R 2 X7R 2 X7R 2 X7R 2 X7R 2 X7R 2
201 201 201 201 201 201
Place R9771-R9776,C9771-C9776 close to J9000
LED Backlight Driver

SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)
A
D 051-7631 2.3.0

NONE 62 71
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CRITICAL
Q9806
FDC638APZ_SBMS001
SSOT6-HF
CRITICAL
F9800
6
2AMP-32V
2 5
4
=PPBUS_S0_LCDBKLT 1 2 70 PPBUS_S0_LCDBKLT_FUSED
7
D
IN
MIN_NECK_WIDTH=0.25 mm D
1
1
0402-HF
R9808 1
C9802
301K
1%
0.1UF
3
10%
1/16W
16V
MF-LF 2 X5R
402
2 402
70 PPBUS_S0_LCDBKLT_EN_DIV
1
R9809
147K
1%
1/16W
MF-LF
402
70 PPBUS_S0_LCDBKLT_EN_L 2
Q9807
SSM3K15FV D 3
SOD-VESM-HF
1 G S 2 PPBUS_S0_LCDBKLT_PWR 62 70
OUT
VOLTAGE=12.6V
62 LCDBKLT_ENA
IN
C 63 17 IN LVDS_IG_BKL_PWM
MAKE_BASE=TRUE
BKLT_PWM
OUT 62 C
LVDS_IG_BKL_ON 17 62
LVDS_IG_BKL_PWM 17 63
B 1
R9840
1
R9841 B
100K 100K
5% 5%
1/20W 1/20W
MF MF
2 201 2 201
LCD Backlight Support
A SYNC_MASTER=M97

A
D 051-7631 2.3.0

NONE 63 71
8 7 6 5 4 3 2 . 1
8 7 6 5 4 3 2 1
ADDITIONAL CPU VCORE HF DECOUPLING

40x 2.2uF 0402
11 10 7 =PPVCORE_S0_CPU
D LAYOUT NOTE:
D
C9900 C9901 C9902 C9903 C9904 C9905 C9906 C9907 C9908 C9909
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
CERM OMIT CERM OMIT CERM OMIT CERM OMIT CERM OMIT CERM OMIT CERM OMIT CERM OMIT CERM OMIT CERM OMIT
LAYOUT NOTE:
C9910 C9911 C9912 C9913 C9914 C9915 C9916 C9917 C9918 C9919
PLACE ON OPPOSITE SIDE OF CPU 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
LAYOUT NOTE:
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
C C
LAYOUT NOTE:
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
B B
Additional CPU/GPU Decoupling

A SYNC_MASTER=

SYNC_DATE=
A
D 051-7631 2.3.0

NONE 64 71
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
FSB (Front-Side Bus) Constraints CPU / FSB Net Properties
TABLE_PHYSICAL_RULE_HEAD
NET_TYPE
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER? ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING
TABLE_PHYSICAL_RULE_ITEM
FSB_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD

FSB_DATA_GROUP0 FSB_50S FSB_DATA FSB_D_L<15..0> 9 13
FSB_DSTB_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =1:1_DIFFPAIR =1:1_DIFFPAIR FSB_DATA_GROUP0 FSB_50S FSB_DATA FSB_DINV_L<0> 9 13
FSB_DSTB0 FSB_DSTB_50S FSB_DSTB FSB_DSTB_L_P<0> 9 13

TABLE_SPACING_RULE_HEAD TABLE_SPACING_RULE_HEAD
FSB_DSTB0 FSB_DSTB_50S FSB_DSTB FSB_DSTB_L_N<0> 9 13

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
FSB 4X Signal Groups

TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM

FSB_DATA * =2x_DIELECTRIC ? FSB_DATA TOP,BOTTOM =4x_DIELECTRIC ?
FSB_DATA_GROUP1 FSB_50S FSB_DATA FSB_DINV_L<1> 9 13
FSB_DSTB * =3x_DIELECTRIC ? FSB_DSTB TOP,BOTTOM =5x_DIELECTRIC ? FSB_DSTB1 FSB_DSTB_50S FSB_DSTB FSB_DSTB_L_P<1> 9 13
D FSB_ADDR * =STANDARD ?
TABLE_SPACING_RULE_ITEM
FSB_ADDR TOP,BOTTOM =3x_DIELECTRIC ?


D

FSB_ADSTB * =2x_DIELECTRIC ? FSB_ADSTB TOP,BOTTOM =4x_DIELECTRIC ?
FSB_1X * =STANDARD ? FSB_1X TOP,BOTTOM =3x_DIELECTRIC ? FSB_DSTB2 FSB_DSTB_50S FSB_DSTB FSB_DSTB_L_P<2> 9 13

All 4x/2x/1x FSB signals with impedance requirements are 50-ohm single-ended.
FSB 4X signals / groups shown in signal table on right.
Signals within each 4x group should be matched within 5 ps of strobe.
FSB_DSTB3 FSB_DSTB_50S FSB_DSTB FSB_DSTB_L_P<3> 9 13
DSTB# complementary pairs should be matched within 1 ps of each other, all DSTB#s matched to +/- 300 ps.
Spacing is 2x dielectric between DATA#, DINV# signals, with 3x dielectric spacing to the DSTB#s.
DSTB# complementary pairs are spaced normally and are NOT routed as differential pairs. FSB_ADDR_GROUP0 FSB_50S FSB_ADDR FSB_A_L<16..3> 9 13
Signals
FSB_REQ_L<4..0>
FSB 2X
FSB_ADDR_GROUP0 FSB_50S FSB_ADDR 9 13
FSB 2X signals / groups shown in signal table on right.
FSB_ADSTB0 FSB_50S FSB_ADSTB FSB_ADSTB_L<0> 9 13
Signals within each 2x group should be matched within 20 ps. ADTSB#s should be matched +/- 300 ps.
Spacing is 1x dielectric between ADDR#, REQ# signals, with 2x dielectric spacing to ADSTB#. FSB_ADDR_GROUP1 FSB_50S FSB_ADDR FSB_A_L<35..17> 9 13
FSB_ADSTB1 FSB_50S FSB_ADSTB FSB_ADSTB_L<1> 9 13

FSB 1X signals shown in signal table on right.
Signals within each 1x group should be matched to CPU clock, +0/-1000 mils. FSB_1X FSB_50S FSB_1X FSB_ADS_L 9 13
FSB_BREQ0_L FSB_50S FSB_1X FSB_BREQ0_L 8 9 13

Design Guide recommends each strobe/signal group is routed on the same layer.
FSB_BREQ1_L FSB_50S FSB_1X FSB_BREQ1_L 13
Intel Design Guide recommends FSB signals be routed only on internal layers.
FSB 1X Signals
FSB_1X FSB_50S FSB_1X FSB_BNR_L 9 13
NOTE: Intel Design Guide allows closer spacing if signal lengths can be shortened. FSB_1X FSB_50S FSB_1X FSB_BPRI_L 9 13
FSB_1X FSB_50S FSB_1X FSB_DBSY_L 9 13

SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2
FSB_1X FSB_50S FSB_1X FSB_DEFER_L 9 13
SOURCE: Santa Rosa Platform DG, Rev 1.5 (#22294), Sections 4.2 & 4.3
FSB_1X FSB_50S FSB_1X FSB_DRDY_L 9 13
FSB_1X FSB_50S FSB_1X FSB_HIT_L

CPU Signal Constraints FSB_1X FSB_50S FSB_1X FSB_HITM_L
9 13
9 13
ALLOW ROUTE
C PHYSICAL_RULE_SET
CPU_50S
LAYER
*
ON LAYER?
=50_OHM_SE
MINIMUM LINE WIDTH
=50_OHM_SE
MINIMUM NECK WIDTH
=50_OHM_SE
MAXIMUM NECK LENGTH
=50_OHM_SE
DIFFPAIR PRIMARY GAP
=STANDARD
DIFFPAIR NECK GAP
=STANDARD
FSB_1X
FSB_CPURST_L
FSB_50S
FSB_50S
FSB_1X
FSB_1X
FSB_LOCK_L
FSB_CPURST_L
9 13
8 9 12 13
C
FSB_1X FSB_50S FSB_1X FSB_RS_L<2..0> 9 13
CPU_27P4S * =27P4_OHM_SE =27P4_OHM_SE =27P4_OHM_SE =27P4_OHM_SE 7 MIL 7 MIL FSB_1X FSB_50S FSB_1X FSB_TRDY_L 9 13
NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance. CPU_ASYNC CPU_50S CPU_AGTL CPU_A20M_L 9 13
CPU_BSEL CPU_50S CPU_AGTL CPU_BSEL<2..0> 8 9
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT CPU_FERR_L CPU_50S CPU_8MIL CPU_FERR_L 9 13
CPU_ASYNC CPU_50S CPU_AGTL CPU_IGNNE_L 9 13

CPU_AGTL * =STANDARD ? CPU_AGTL TOP,BOTTOM =2x_DIELECTRIC ?
CPU_INIT_L CPU_50S CPU_AGTL CPU_INIT_L 9 13
CPU_8MIL * 8 MIL ? CPU_ASYNC_R CPU_50S CPU_AGTL CPU_INTR 8 9 13

CPU_ASYNC_R CPU_50S CPU_AGTL CPU_NMI 8 9 13

CPU_COMP * 25 MIL ?
CPU_PROCHOT_L CPU_50S CPU_AGTL CPU_PROCHOT_L 9 13 40 50
CPU_GTLREF * 25 MIL ? SR DG recommends at least 25 mils, >50 mils preferred CPU_PWRGD CPU_50S CPU_AGTL CPU_PWRGD 9 12 13
CPU_ASYNC CPU_50S CPU_AGTL CPU_SMI_L 9 13

CPU_ITP * =2:1_SPACING ?
CPU_ASYNC CPU_50S CPU_AGTL CPU_STPCLK_L 9 13
CPU_VCCSENSE * 25 MIL ? PM_THRMTRIP_L CPU_50S CPU_8MIL PM_THRMTRIP_L 9 13 40
FSB_CPUSLP_L CPU_50S CPU_AGTL FSB_CPUSLP_L 9 13

Most CPU signals with impedance requirements are 55-ohm single-ended.
CPU_FROM_SB CPU_50S CPU_AGTL CPU_DPSLP_L 9 13
Some signals require 27.4-ohm single-ended impedance.
CPU_DPRSTP_L CPU_50S CPU_AGTL CPU_DPRSTP_L 8 9 13 50
SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2 CPU_ASYNC CPU_50S CPU_AGTL FSB_DPWR_L 9 13
SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.4 & 5.8.2.4 MCP_CPU_COMP MCP_50S MCP_FSB_COMP MCP_BCLK_VML_COMP_VDD 13
MCP_CPU_COMP MCP_50S MCP_FSB_COMP MCP_BCLK_VML_COMP_GND 13
MCP FSB COMP Signal Constraints MCP_CPU_COMP MCP_50S MCP_FSB_COMP MCP_CPU_COMP_VCC 13
ALLOW ROUTE
MCP_CPU_COMP MCP_50S MCP_FSB_COMP MCP_CPU_COMP_GND 13

PHYSICAL_RULE_SET LAYER ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
FSB_CLK_CPU CLK_FSB_100D CLK_FSB FSB_CLK_CPU_P 9 13

MCP_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD
FSB_CLK_CPU CLK_FSB_100D CLK_FSB FSB_CLK_CPU_N 9 13
B TABLE_SPACING_RULE_HEAD
FSB_CLK_ITP CLK_FSB_100D CLK_FSB FSB_CLK_ITP_P 6 12 13 B
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT FSB_CLK_ITP CLK_FSB_100D CLK_FSB FSB_CLK_ITP_N 6 12 13
FSB_CLK_MCP CLK_FSB_100D CLK_FSB FSB_CLK_MCP_P 13

MCP_FSB_COMP * 8 MIL ?
FSB_CLK_MCP CLK_FSB_100D CLK_FSB FSB_CLK_MCP_N 13
SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.4

CPU_IERR_L CPU_50S CPU_IERR_L 9
FSB Clock Constraints PM_DPRSLPVR CPU_50S CPU_AGTL PM_DPRSLPVR 20 50
ALLOW ROUTE
(See above) CPU_50S CPU_AGTL IMVP_DPRSLPVR 50

CPU_GTLREF CPU_50S CPU_GTLREF CPU_GTLREF 9 25

CLK_FSB_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF
CPU_COMP CPU_50S CPU_COMP CPU_COMP<3> 9
CPU_COMP CPU_27P4S CPU_COMP CPU_COMP<2> 9
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT CPU_COMP CPU_50S CPU_COMP CPU_COMP<1> 9
CPU_COMP CPU_27P4S CPU_COMP CPU_COMP<0> 9

CLK_FSB * =3x_DIELECTRIC ? CLK_FSB TOP,BOTTOM =4x_DIELECTRIC ?
XDP_TDI CPU_50S CPU_ITP XDP_TDI 6 9 12
SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.5
XDP_TDO CPU_50S CPU_ITP XDP_TDO 9 12
XDP_TMS CPU_50S CPU_ITP XDP_TMS 6 9 12
XDP_TCK CPU_50S CPU_ITP XDP_TCK 6 9 12
XDP_TRST_L CPU_50S CPU_ITP XDP_TRST_L 6 9 12
XDP_BPM_L CPU_50S CPU_ITP XDP_BPM_L<4..0> 6 9 12
XDP_BPM_L5 CPU_50S CPU_ITP XDP_BPM_L<5> 6 9 12
(FSB_CPURST_L) CPU_50S CPU_ITP XDP_CPURST_L 6 12
CPU_50S CPU_8MIL CPU_VID<6..0> 10 11 50
CPU_50S CPU_8MIL IMVP6_VID<6..0> 11 CPU/FSB Constraints

CPU_VCCSENSE CPU_27P4S CPU_VCCSENSE CPU_VCCSENSE_P 10 50
A CPU_VCCSENSE
(CPU_VCCSENSE)
CPU_27P4S
CPU_27P4S
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE_N
IMVP6_VSEN_P
10 50
50
SYNC_MASTER=M97

A
(CPU_VCCSENSE) CPU_27P4S CPU_VCCSENSE IMVP6_VSEN_N 50
D 051-7631 2.3.0

NONE 65 71
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Memory Bus Constraints
Memory Net Properties

ON LAYER? NET_TYPE
MEM_50S * =50_OHM_SE =50_OHM_SE 0.110 MM =50_OHM_SE =STANDARD =STANDARD ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING
MEM_50S_VDD * =50_OHM_SE =50_OHM_SE 0.110 MM =50_OHM_SE =STANDARD =STANDARD MEM_A_CLK MEM_90D MEM_CLK MEM_A_CLK_P<0> 14 27 28 33
MEM_A_CLK MEM_90D MEM_CLK MEM_A_CLK_N<0> 14 27 28 33

MEM_90D * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF
MEM_A_CNTL MEM_50S MEM_CTRL MEM_A_CKE<1..0> 14 27 28 33

MEM_90D_VDD * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF
MEM_A_CNTL MEM_50S MEM_CTRL MEM_A_CS_L<1..0> 14 27 28 33
TABLE_SPACING_RULE_HEAD
MEM_A_CNTL MEM_50S MEM_CTRL MEM_A_ODT<1..0> 14 27 28 33
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT

MEM_A_CMD MEM_50S MEM_CMD MEM_A_A<14..0> 14 27 28 33
D MEM_CLK2MEM * =2.28:1_SPACING ?
MEM_A_CMD MEM_50S MEM_CMD MEM_A_BA<2..0> 14 27 28 33 D

MEM_A_CMD MEM_50S MEM_CMD MEM_A_RAS_L 14 27 28 33

MEM_CTRL2CTRL * =1.1:1_SPACING ?
MEM_A_CMD MEM_50S MEM_CMD MEM_A_CAS_L 14 27 28 33
MEM_CTRL2MEM * =2.28:1_SPACING ? MEM_A_CMD MEM_50S MEM_CMD MEM_A_WE_L 14 27 28 33

MEM_CMD2CMD * =1.1:1_SPACING ? MEM_A_DQ_BYTE0 MEM_50S MEM_DATA MEM_A_DQ<7..0> 14 27

MEM_A_DQ_BYTE1 MEM_50S MEM_DATA MEM_A_DQ<15..8> 14 27

MEM_CMD2MEM * =2.28:1_SPACING ?
MEM_DATA2DATA * =1.1:1_SPACING ? MEM_A_DQ_BYTE3 MEM_50S MEM_DATA MEM_A_DQ<31..24> 14 27


MEM_DATA2MEM * =2.28:1_SPACING ?
MEM_DQS2MEM * =2.28:1_SPACING ? MEM_A_DQ_BYTE6 MEM_50S MEM_DATA MEM_A_DQ<55..48> 14 28


MEM_2OTHER * 25 MIL ?
MEM_A_DQ_BYTE0 MEM_50S MEM_DATA MEM_A_DM<0> 14 27
MEM_A_DQ_BYTE1 MEM_50S MEM_DATA MEM_A_DM<1>

Memory Bus Spacing Group Assignments MEM_A_DQ_BYTE2 MEM_50S MEM_DATA MEM_A_DM<2>
14 27
14 27
TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_A_DQ_BYTE3 MEM_50S MEM_DATA MEM_A_DM<3> 14 27
TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

MEM_CLK MEM_CLK * MEM_CLK2MEM MEM_CMD MEM_CLK * MEM_CMD2MEM
MEM_CLK MEM_CTRL * MEM_CLK2MEM MEM_CMD MEM_CTRL * MEM_CMD2MEM MEM_A_DQ_BYTE6 MEM_50S MEM_DATA MEM_A_DM<6> 14 28

MEM_CLK MEM_CMD * MEM_CLK2MEM MEM_CMD MEM_CMD * MEM_CMD2CMD
MEM_A_DQS0 MEM_90D MEM_DQS MEM_A_DQS_P<0> 14 27

MEM_CLK MEM_DATA * MEM_CLK2MEM MEM_CMD MEM_DATA * MEM_CMD2MEM
MEM_A_DQS0 MEM_90D MEM_DQS MEM_A_DQS_N<0> 14 27
MEM_CLK MEM_DQS * MEM_CLK2MEM MEM_CMD MEM_DQS * MEM_CMD2MEM MEM_A_DQS1 MEM_90D MEM_DQS MEM_A_DQS_P<1> 14 27

C NET_SPACING_TYPE1
MEM_CTRL
NET_SPACING_TYPE2
MEM_CLK
AREA_TYPE
*
SPACING_RULE_SET
MEM_CTRL2MEM
TABLE_SPACING_ASSIGNMENT_ITEM
NET_SPACING_TYPE1
MEM_DATA
NET_SPACING_TYPE2
MEM_CLK
AREA_TYPE
*
SPACING_RULE_SET
MEM_DATA2MEM
MEM_A_DQS2
MEM_A_DQS3
MEM_90D
MEM_90D
MEM_DQS
MEM_DQS
MEM_A_DQS_N<2>
MEM_A_DQS_P<3>
14 27
14 27
C

MEM_CTRL MEM_CTRL * MEM_CTRL2CTRL MEM_DATA MEM_CTRL * MEM_DATA2MEM
MEM_CTRL MEM_CMD * MEM_CTRL2MEM MEM_DATA MEM_CMD * MEM_DATA2MEM MEM_A_DQS4 MEM_90D MEM_DQS MEM_A_DQS_N<4> 14 28

MEM_CTRL MEM_DATA * MEM_CTRL2MEM MEM_DATA MEM_DATA * MEM_DATA2DATA
MEM_CTRL MEM_DQS * MEM_CTRL2MEM MEM_DATA MEM_DQS * MEM_DATA2MEM MEM_A_DQS6 MEM_90D MEM_DQS MEM_A_DQS_P<6> 14 28


NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET
MEM_DQS MEM_CLK * MEM_DQS2MEM MEM_CLK * * MEM_2OTHER

MEM_B_CLK MEM_90D MEM_CLK MEM_B_CLK_P<0> 14 29 30 33
MEM_DQS MEM_CTRL * MEM_DQS2MEM MEM_CTRL * * MEM_2OTHER MEM_B_CLK MEM_90D MEM_CLK MEM_B_CLK_N<0> 14 29 30 33

MEM_DQS MEM_CMD * MEM_DQS2MEM MEM_CMD * * MEM_2OTHER MEM_B_CNTL MEM_50S MEM_CTRL MEM_B_CKE<1..0> 14 29 30 33

MEM_B_CNTL MEM_50S MEM_CTRL MEM_B_CS_L<1..0> 14 29 30 33

MEM_DQS MEM_DATA * MEM_DQS2MEM MEM_DATA * * MEM_2OTHER
MEM_B_CNTL MEM_50S MEM_CTRL MEM_B_ODT<1..0> 14 29 30 33
MEM_DQS MEM_DQS * MEM_DQS2MEM MEM_DQS * * MEM_2OTHER

MEM_B_CMD MEM_50S MEM_CMD MEM_B_A<14..0> 14 29 30 33
MEM_B_CMD MEM_50S MEM_CMD MEM_B_BA<2..0> 14 29 30 33
NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_B_CMD MEM_50S MEM_CMD MEM_B_RAS_L 14 29 30 33
MEM_B_CMD MEM_50S MEM_CMD MEM_B_CAS_L 14 29 30 33

MEM_CLK GND * GND_P2MM MEM_CLK PWR * BUS2PWR_GND
MEM_B_CMD MEM_50S MEM_CMD MEM_B_WE_L 14 29 30 33
MEM_CMD GND * GND_P2MM MEM_CLK GND * BUS2PWR_GND

MEM_B_DQ_BYTE0 MEM_50S MEM_DATA MEM_B_DQ<7..0> 14 29
MEM_CTRL GND * GND_P2MM MEM_CTRL PWR * BUS2PWR_GND MEM_B_DQ_BYTE1 MEM_50S MEM_DATA MEM_B_DQ<15..8> 14 29

MEM_DATA GND * GND_P2MM MEM_CTRL GND * BUS2PWR_GND
B MEM_DQS GND * GND_P2MM
MEM_CMD PWR *
BUS2PWR_GND
MEM_B_DQ_BYTE3
MEM_B_DQ_BYTE4
MEM_50S
MEM_50S
MEM_DATA
MEM_DATA
MEM_B_DQ<31..24>
MEM_B_DQ<39..32>
14 29
14 30
B

MEM_CLK PP1V5_MEM * PWR_P2MM MEM_CMD GND * BUS2PWR_GND
MEM_CTRL PP1V5_MEM * PWR_P2MM MEM_DATA PWR * BUS2PWR_GND MEM_B_DQ_BYTE7 MEM_50S MEM_DATA MEM_B_DQ<63..56> 14 30
MEM_DATA PP1V5_MEM * PWR_P2MM MEM_DATA GND * BUS2PWR_GND MEM_B_DQ_BYTE0 MEM_50S MEM_DATA MEM_B_DM<0> 14 29
MEM_B_DQ_BYTE1 MEM_50S MEM_DATA MEM_B_DM<1> 14 29

MEM_DQS PP1V5_MEM * PWR_P2MM MEM_DQS PWR * BUS2PWR_GND
MEM_CMD PP1V5_MEM * PWR_P2MM MEM_DQS GND * BUS2PWR_GND MEM_B_DQ_BYTE3 MEM_50S MEM_DATA MEM_B_DM<3> 14 29
MEM_B_DQS0 MEM_90D MEM_DQS MEM_B_DQS_P<0> 14 29
MEM_B_DQS0 MEM_90D MEM_DQS MEM_B_DQS_N<0> 14 29

DDR3: MEM_B_DQS_P<2>
MEM_B_DQS2 MEM_90D MEM_DQS 14 29
DQ signals should be matched within 5 ps of associated DQS pair.
DQS intra-pair matching should be within 1 ps, inter-pair matching shoulw be within 180 ps
No DQS to clock matching requirement.
CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 2 ps.
A/BA/cmd signals should be matched within 5 ps of CLK pairs.
All memory signals maximum length is 1.005 ps. CLK minimum length is 594 ps (lengths include substrate).
DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric.
MEM_B_DQS5 MEM_90D MEM_DQS MEM_B_DQS_P<5> 14
30
Memory Constraints
A SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3

SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 6.2
MEM_B_DQS6
MEM_B_DQS6
MEM_90D
MEM_90D
MEM_DQS
MEM_DQS
MEM_B_DQS_P<6>
MEM_B_DQS_N<6>
14 30
14 30
SYNC_MASTER=M97

A
MCP MEM COMP Signal Constraints MEM_B_DQS7 MEM_90D MEM_DQS MEM_B_DQS_N<7> 14 30 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP_VDD 15 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
ON LAYER? VOLTAGE=0V
MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP_GND 15 II NOT TO REPRODUCE OR COPY IT

MCP_MEM_COMP * Y 7 MIL 7 MIL =STANDARD =STANDARD =STANDARD VOLTAGE=1.5V
30 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
MEM_CLK MEM_RESET_L 26 27
28 29

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =PP1V8R1V5_S0_MCP_MEM NET_SPACING_TYPE=PP1V5_MEM 22
7
MCP_MEM_COMP * 8 MIL ?
GND NET_SPACING_TYPE=GND
15
D 051-7631 2.3.0

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3.4 66 71
NONE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NET_TYPE
PCI-Express ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING

PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP PCIE_90D PCIE PEG_R2D_P<15..0>
ON LAYER?
PCIE_90D PCIE PEG_R2D_N<15..0>

PCIE_90D * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF
PEG_R2D PCIE_90D PCIE PEG_R2D_C_P<15..0>
CLK_PCIE_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF PCIE_90D PCIE PEG_R2D_C_N<15..0>
PEG_D2R PCIE_90D PCIE PEG_D2R_P<15..0>
PCIE_90D PCIE PEG_D2R_N<15..0>

PCIE_90D PCIE PEG_D2R_C_P<15..0>
PCIE * =3X_DIELECTRIC ? PCIE TOP,BOTTOM =4X_DIELECTRIC ? PCIE_90D PCIE PEG_D2R_C_N<15..0>
PCIE_90D PCIE PCIE_MINI_R2D_P

CLK_PCIE * 20 MIL ?
PCIE_90D PCIE PCIE_MINI_R2D_N
D MCP_PEX_COMP * 8 MIL ?
PCIE_MINI_R2D PCIE_90D PCIE PCIE_MINI_R2D_C_P 16 34 D

PCIE_90D PCIE PCIE_MINI_R2D_C_N 16 34
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.4
PCIE_MINI_D2R PCIE_90D PCIE PCIE_MINI_D2R_P 16 34
PCIE_90D PCIE PCIE_MINI_D2R_N

Analog Video Signal Constraints PCIE_90D PCIE PCIE_FW_R2D_P
16 34
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP PCIE_90D PCIE PCIE_FW_R2D_N
ON LAYER?
PCIE_FW_R2D PCIE_90D PCIE PCIE_FW_R2D_C_P

CRT_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD
PCIE_90D PCIE PCIE_FW_R2D_C_N
PCIE_FW_D2R PCIE_90D PCIE PCIE_FW_D2R_P
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT PCIE_90D PCIE PCIE_FW_D2R_N
PCIE_90D PCIE PCIE_FW_D2R_C_P

CRT * =4:1_SPACING ?
PCIE_90D PCIE PCIE_FW_D2R_C_N
CRT_2CRT * =STANDARD ? PCIE_90D PCIE PCIE_EXCARD_R2D_P
PCIE_90D PCIE PCIE_EXCARD_R2D_N

CRT_2CLK * 50 MIL ?
PCIE_EXCARD_R2D PCIE_90D PCIE PCIE_EXCARD_R2D_C_P
CRT_2SWITCHER * 250 MIL ? PCIE_90D PCIE PCIE_EXCARD_R2D_C_N
PCIE_EXCARD_D2R PCIE_90D PCIE PCIE_EXCARD_D2R_P

CRT_SYNC * 16 MIL ?
PCIE_90D PCIE PCIE_EXCARD_D2R_N
MCP_DAC_COMP * =2:1_SPACING ? PCIE_90D PCIE PCIE_FC_R2D_P
PCIE_90D PCIE PCIE_FC_R2D_N
CRT signal single-ended impedence varies by location:
PCIE_FC_R2D PCIE_90D PCIE PCIE_FC_R2D_C_P
- 37.5-ohm from MCP to first termination resistor.
PCIE_90D PCIE PCIE_FC_R2D_C_N
- 50-ohm from first to second termination resistor.
PCIE_FC_D2R PCIE_90D PCIE PCIE_FC_D2R_P
- 75-ohm from output of three-pole filter to connector (if possible).
PCIE_90D PCIE PCIE_FC_D2R_N
R/G/B signals should be matched as close as possible and < 10 inches.
MCP_PE0_REFCLK CLK_PCIE_100D CLK_PCIE PEG_CLK100M_P 8 16
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.1 & 2.5.2.
CLK_PCIE_100D CLK_PCIE PEG_CLK100M_N 8 16
C Digital Video Signal Constraints

MCP_PE1_REFCLK CLK_PCIE_100D
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE
PCIE_CLK100M_MINI_P
PCIE_CLK100M_MINI_N
16 34
16 34
C
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP MCP_PE4_REFCLK CLK_PCIE_100D CLK_PCIE PCIE_CLK100M_FC_P
ON LAYER?
CLK_PCIE_100D CLK_PCIE PCIE_CLK100M_FC_N

DP_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF
MCP_PE2_REFCLK CLK_PCIE_100D CLK_PCIE PCIE_CLK100M_FW_P
LVDS_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF CLK_PCIE_100D CLK_PCIE PCIE_CLK100M_FW_N
MCP_PE3_REFCLK CLK_PCIE_100D CLK_PCIE PCIE_CLK100M_EXCARD_P

MCP_DV_COMP * Y 20 MIL 20 MIL =STANDARD =STANDARD =STANDARD
CLK_PCIE_100D CLK_PCIE PCIE_CLK100M_EXCARD_N
MCP_PEX_CLK_COMP MCP_PEX_COMP MCP_PEX_CLK_COMP 16
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TMDS_IG_TXC DP_100D DISPLAYPORT TMDS_IG_TXC_P
TMDS_IG_TXC DP_100D DISPLAYPORT TMDS_IG_TXC_N

DISPLAYPORT * =3x_DIELECTRIC ? DISPLAYPORT TOP,BOTTOM =4x_DIELECTRIC ?
TMDS_IG_TXD DP_100D DISPLAYPORT TMDS_IG_TXD_P<2..0>
LVDS * =3x_DIELECTRIC ? LVDS TOP,BOTTOM =4x_DIELECTRIC ? TMDS_IG_TXD DP_100D DISPLAYPORT TMDS_IG_TXD_N<2..0>
LVDS intra-pair matching should be 5 mils. Pairs should be within 100 mils of clock length. DP_ML DP_100D DISPLAYPORT DP_ML_C_P<3..0> 6 61
DisplayPort/TMDS intra-pair matching should be 5 ps. Inter-pair matching should be within 150 ps. DP_ML DP_100D DISPLAYPORT DP_ML_C_N<3..0> 6 61
DIsplayPort AUX CH intra-pair matching should be 5 ps. No relationship to other signals. DP_ML DP_100D DISPLAYPORT DP_ML_F_P<3..0> 35 61
Max length of LVDS/DisplayPort/TMDS traces: 12 inches. DP_ML DP_100D DISPLAYPORT DP_ML_F_N<3..0> 35 61
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.3 & 2.5.4. DP_ML DP_100D DISPLAYPORT DP_ML_P<3..0> 60 61
DP_ML DP_100D DISPLAYPORT DP_ML_N<3..0> 60 61
SATA Interface Constraints DP_AUX_CH DP_100D DISPLAYPORT DP_IG_AUX_CH_P 17 60

DP_AUX_CH DP_100D DISPLAYPORT DP_IG_AUX_CH_N 17 60

ON LAYER? DP_AUX_CH DP_100D DISPLAYPORT DP_AUX_CH_C_P 6 35 60 61
SATA_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF DP_AUX_CH DP_100D DISPLAYPORT DP_AUX_CH_C_N 6 35 60 61
DP_AUX_CH DP_100D DISPLAYPORT DP_AUX_CH_SW_P 60

SATA_100D_HDD * =100_OHM_DIFF_HDD =100_OHM_DIFF_HDD =100_OHM_DIFF_HDD =100_OHM_DIFF_HDD =100_OHM_DIFF_HDD =100_OHM_DIFF_HDD
DP_AUX_CH DP_100D DISPLAYPORT DP_AUX_CH_SW_N 60
MCP_HDMI_RSET MCP_DV_COMP MCP_HDMI_RSET 17 23
B SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT

MCP_HDMI_VPROBE MCP_DV_COMP MCP_HDMI_VPROBE 17 23 B
SATA * =4x_DIELECTRIC ? SATA TOP,BOTTOM =3x_DIELECTRIC ? LVDS_IG_A_CLK LVDS_100D LVDS LVDS_IG_A_CLK_F_P 6 59
LVDS_IG_A_CLK LVDS_100D LVDS LVDS_IG_A_CLK_F_N 6 59

SATA_TERMP * 8 MIL ?
LVDS_IG_A_CLK LVDS_100D LVDS LVDS_IG_A_CLK_P 17 59
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.7.1. LVDS_IG_A_CLK LVDS_100D LVDS LVDS_IG_A_CLK_N 17 59
LVDS_IG_A_DATA LVDS_100D LVDS LVDS_IG_A_DATA_F_P<2..0> 59
LVDS_IG_A_DATA LVDS_100D LVDS LVDS_IG_A_DATA_F_N<2..0> 59
LVDS_IG_A_DATA LVDS_100D LVDS LVDS_IG_A_DATA_P<2..0> 6 17 59
LVDS_IG_A_DATA LVDS_100D LVDS LVDS_IG_A_DATA_N<2..0> 6 17 59
LVDS_IG_A_DATA3 LVDS_100D LVDS LVDS_IG_A_DATA_P<3> 8 17
LVDS_IG_A_DATA3 LVDS_100D LVDS LVDS_IG_A_DATA_N<3> 8 17
LVDS_IG_B_CLK LVDS_100D LVDS LVDS_IG_B_CLK_P 8 17
LVDS_IG_B_CLK LVDS_100D LVDS LVDS_IG_B_CLK_N 8 17
LVDS_IG_B_DATA LVDS_100D LVDS LVDS_IG_B_DATA_P<2..0> 8 17
LVDS_IG_B_DATA LVDS_100D LVDS LVDS_IG_B_DATA_N<2..0> 8 17
LVDS_IG_B_DATA3 LVDS_100D LVDS LVDS_IG_B_DATA_P<3> 8 17
LVDS_IG_B_DATA3 LVDS_100D LVDS LVDS_IG_B_DATA_N<3> 8 17
MCP_IFPAB_RSET MCP_DV_COMP MCP_IFPAB_RSET 17 23
MCP_IFPAB_VPROBE MCP_IFPAB_VPROBE 17 23
SATA_HDD_R2D SATA_100D_HDD SATA SATA_HDD_R2D_C_P 19 36
SATA_100D_HDD SATA SATA_HDD_R2D_C_N 19 36
SATA_100D_HDD SATA SATA_HDD_R2D_P 6 36
SATA_100D_HDD SATA SATA_HDD_R2D_N

SATA_100D_HDD SATA SATA_HDD_R2D_UF_P
6 36
36
MCP Constraints 1
SATA_HDD_R2D_UF_N
A SATA_HDD_D2R
SATA_100D_HDD
SATA_100D_HDD
SATA
SATA SATA_HDD_D2R_P
36
19 36
SYNC_MASTER=M97

A
SATA_100D_HDD SATA SATA_HDD_D2R_N 19 36
SATA_100D_HDD SATA SATA_HDD_D2R_C_P 6 36 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

SATA_100D_HDD SATA SATA_HDD_D2R_C_N 6 36 AGREES TO THE FOLLOWING
SATA_100D_HDD SATA SATA_HDD_D2R_UF_P 36 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
SATA_100D_HDD SATA SATA_HDD_D2R_UF_N 36 II NOT TO REPRODUCE OR COPY IT
MCP_SATA_TERMP SATA_TERMP MCP_SATA_TERMP 19 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
D 051-7631 2.3.0

NONE 67 71
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PCI Bus Constraints
NET_TYPE
PCI_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD

MCP_DEBUG PCI_55S PCI MCP_DEBUG<7..0> 6 12 18
CLK_PCI_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD PCI_AD PCI_55S PCI PCI_AD<23..8>
PCI_AD24 PCI_55S PCI PCI_AD<24>
PCI_AD PCI_55S PCI PCI_AD<31..25>

PCI_AD PCI_55S PCI PCI_PAR
PCI * =STANDARD ? PCI_C_BE_L PCI_55S PCI PCI_C_BE_L<3..0>
PCI_CNTL PCI_55S PCI PCI_IRDY_L

CLK_PCI * 8 MIL ?
PCI_CNTL PCI_55S PCI PCI_DEVSEL_L
D SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.8.

PCI_CNTL PCI_55S PCI PCI_PERR_L D
PCI_CNTL PCI_55S PCI PCI_SERR_L
PCI_CNTL PCI_55S PCI PCI_STOP_L
LPC Bus Constraints PCI_CNTL PCI_55S PCI PCI_TRDY_L
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP PCI_CNTL PCI_55S PCI PCI_FRAME_L
ON LAYER?
PCI_REQ0_L PCI_55S PCI PCI_REQ0_L 18

LPC_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD
PCI_GNT0_L PCI_55S PCI PCI_GNT0_L
CLK_LPC_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD PCI_REQ1_L PCI_55S PCI PCI_REQ1_L 18
PCI_GNT1_L PCI_55S PCI PCI_GNT1_L

PCI_INTW_L PCI_55S PCI PCI_INTW_L

PCI_INTX_L PCI_55S PCI PCI_INTX_L
LPC * 6 MIL ? PCI_INTY_L PCI_55S PCI PCI_INTY_L
PCI_INTZ_L PCI_55S PCI PCI_INTZ_L

CLK_LPC * 8 MIL ?
MCP_PCI_CLK2 CLK_PCI_55S CLK_PCI PCI_CLK33M_MCP_R 18
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.9.1. CLK_PCI_55S CLK_PCI PCI_CLK33M_MCP 18
LPC_AD LPC_55S LPC LPC_AD<3..0>

USB 2.0 Interface Constraints LPC_FRAME_L LPC_55S LPC LPC_FRAME_L
18 39 41
18 39 41
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP LPC_RESET_L LPC_55S LPC LPC_RESET_L 18 24
ON LAYER?
MCP_USB_RBIAS * =STANDARD 8 MIL 8 MIL =STANDARD =STANDARD =STANDARD MCP_LPC_CLK0 CLK_LPC_55S CLK_LPC LPC_CLK33M_SMC_R 18 24
CLK_LPC_55S CLK_LPC LPC_CLK33M_SMC 24 39

USB_90D * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF
CLK_LPC_55S CLK_LPC LPC_CLK33M_LPCPLUS 24 41
USB_EXTA USB_90D USB USB_EXTA_P 8 19

USB_90D USB USB_EXTA_N 8 19
USB * =2x_DIELECTRIC ? USB TOP,BOTTOM =4x_DIELECTRIC ? USB_90D USB USB_EXTA_MUXED_P 37
C SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.10.1.

USB_90D
USB_90D
USB
USB
USB_EXTA_MUXED_N
CONN_USB_EXTA_P
37
C
USB_90D USB CONN_USB_EXTA_N
SMBus Interface Constraints USB_MINI USB_90D USB USB_MINI_P 8 19
ALLOW ROUTE
USB_90D USB USB_MINI_N 8 19

USB_EXTD USB_90D USB USB_EXTD_P 8 19
SMB_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD USB_90D USB USB_EXTD_N 8 19
USB_CAMERA USB_90D USB USB_CAMERA_P 8 19

USB_90D USB USB_CAMERA_N 8 19

USB_90D USB USB_CAMERA_CONN_P
SMB * =2x_DIELECTRIC ? USB_90D USB USB_CAMERA_CONN_N
USB_BT USB_90D USB USB_BT_P 8 19
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.11.1. USB_90D USB USB_BT_N 8 19
USB_90D USB CONN_USB2_BT_P

HD Audio Interface Constraints USB_90D USB CONN_USB2_BT_N
USB_TPAD USB_90D USB USB_TPAD_P 8 19

ON LAYER? USB_90D USB USB_TPAD_N 8 19
HDA_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD USB_90D USB CONN_TPAD_USB_P
USB_90D USB CONN_TPAD_USB_N
USB_IR USB_90D USB USB_IR_P 8 19

USB_90D USB USB_IR_N 8 19
HDA * =2x_DIELECTRIC ? USB_EXTB USB_90D USB USB_EXTB_P 8 19

USB_90D USB USB_EXTB_N 8 19

MCP_HDA_COMP * 8 MIL ?
USB_90D USB CONN_USB_EXTB_P
USB_90D USB CONN_USB_EXTB_N
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.12.1.
USB_EXCARD USB_90D USB USB_EXCARD_P 8
USB_90D USB USB_EXCARD_N

B SIO Signal Constraints USB_EXTC USB_90D USB USB_EXTC_P
8
8 B
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP USB_90D USB USB_EXTC_N 8
ON LAYER?
CLK_SLOW_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD MCP_USB_RBIAS MCP_USB_RBIAS MCP_USB_RBIAS_GND 19
SMBUS_MCP_0_CLK SMB_55S SMB SMBUS_MCP_0_CLK 6 12 20 42
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT SMBUS_MCP_0_DATA SMB_55S SMB SMBUS_MCP_0_DATA 6 12 20 42

SMBUS_MCP_1_CLK SMB_55S SMB SMBUS_MCP_1_CLK 20 42

CLK_SLOW * 8 MIL ?
SMBUS_MCP_1_DATA SMB_55S SMB SMBUS_MCP_1_DATA 20 42
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.13. HDA_BIT_CLK HDA_55S HDA HDA_BIT_CLK 6 20 35
HDA_55S HDA HDA_BIT_CLK_R 20
SPI Interface Constraints HDA_SYNC HDA_55S HDA HDA_SYNC 6 20 35
ALLOW ROUTE
HDA_55S HDA HDA_SYNC_R 20

HDA_RST_L HDA_55S HDA HDA_RST_R_L 20
SPI_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD HDA_55S HDA HDA_RST_L 20 35
HDA_SDIN0 HDA_55S HDA HDA_SDIN0 6 20 35

HDA_55S HDA HDA_SDIN_CODEC

HDA_SDOUT HDA_55S HDA HDA_SDOUT 6 20 35
SPI * 8 MIL ? HDA_55S HDA HDA_SDOUT_R 20
MCP_HDA_PULLDN_COMP MCP_HDA_COMP MCP_HDA_PULLDN_COMP 20

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.14.
MCP_SUS_CLK CLK_SLOW_55S CLK_SLOW PM_CLK32K_SUSCLK_R 20 24
CLK_SLOW_55S CLK_SLOW PM_CLK32K_SUSCLK 24 39
SPI_CLK SPI_55S SPI SPI_CLK_R

SPI_55S SPI SPI_CLK
20 41
48
MCP Constraints 2
SPI_MOSI_R
A SPI_MOSI SPI_55S
SPI_55S
SPI
SPI SPI_MOSI
20 41
48
SYNC_MASTER=M97

A
SPI_MISO SPI_55S SPI SPI_MISO 20 41
SPI_55S SPI SPI_MISO_R 48 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

SPI_CS0 SPI_55S SPI SPI_CS0_R_L 20 41 AGREES TO THE FOLLOWING
SPI_55S SPI SPI_CS0_L I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
SPI_CLK SPI_55S SPI SPI_CLK_MUX 41 48 II NOT TO REPRODUCE OR COPY IT
SPI_MOSI SPI_55S SPI SPI_MOSI_MUX 41 48 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SPI_MISO SPI_55S SPI SPI_MISO_MUX 41 48
SPI_CS0 SPI_55S SPI SPI_MLB_CS_L 41 48
D 051-7631 2.3.0

NONE 68 71
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SMC SMBus Net Properties
NET_TYPE
1TO1_DIFFPAIR * =STANDARD =STANDARD =STANDARD =STANDARD 0.1 MM 0.1 MM

SMBUS_SMC_A_S3_SCL SMB_55S SMB SMBUS_SMC_A_S3_SCL 42
SMBUS_SMC_A_S3_SDA SMB_55S SMB SMBUS_SMC_A_S3_SDA 42
SMBUS_SMC_B_S0_SCL SMB_55S SMB SMBUS_SMC_B_S0_SCL 42
SMBUS_SMC_B_S0_SDA SMB_55S SMB SMBUS_SMC_B_S0_SDA 42
SMBUS_SMC_0_S0_SCL SMB_55S SMB SMBUS_SMC_0_S0_SCL 42
SMBUS_SMC_0_S0_SDA SMB_55S SMB SMBUS_SMC_0_S0_SDA 42
SMBUS_SMC_BSA_SCL SMB_55S SMB SMBUS_SMC_BSA_SCL 6 42
SMBUS_SMC_BSA_SDA SMB_55S SMB SMBUS_SMC_BSA_SDA 6 42
D SMBUS_SMC_MGMT_SCL SMB_55S SMB SMBUS_SMC_MGMT_SCL 42 D

SMBUS_SMC_MGMT_SDA SMB_55S SMB SMBUS_SMC_MGMT_SDA 42
SMBus Charger Net Properties

NET_TYPE
ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING
CHGR_CSI 1TO1_DIFFPAIR CHGR_CSI_P

1TO1_DIFFPAIR CHGR_CSI_N
CHGR_CSO 1TO1_DIFFPAIR CHGR_CSO_P

1TO1_DIFFPAIR CHGR_CSO_N
C C
B B
SMC Constraints
A SYNC_MASTER=M97

A
D 051-7631 2.3.0

NONE 69 71
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
I1
PP0V75_S0 NET_SPACING_TYPE=PWR 6 7
I2 PP0V75_S3 NET_SPACING_TYPE=PWR 7
I3
PP0V75_S3_MEM_VREFCA NET_SPACING_TYPE=PWR 25 27 28 29 30
I4
PP0V75_S3_MEM_VREFDQ NET_SPACING_TYPE=PWR 25 27 28 29 30
I5
PP18V5_DCIN NET_SPACING_TYPE=PWR 6 49
I6
PP18V5_DCIN_ONEWIRE NET_SPACING_TYPE=PWR 49
I7 PP18V5_G3H NET_SPACING_TYPE=PWR 6 7
I8 PP18V5_S5_CHGR_SW_R NET_SPACING_TYPE=PWR 58
I10 PP1V05_ENET_MCP_PLL_MAC NET_SPACING_TYPE=PWR 17 22
I9
PP1V05_RMGT NET_SPACING_TYPE=PWR 7
I12
PP1V05_S0_MCP_PEX_AVDD NET_SPACING_TYPE=PWR 7 22
D
I11
I13 PP1V05_S0_MCP_PEX_AVDD_R NET_SPACING_TYPE=PWR D

I14
PP1V05_S0_MCP_PEX_DVDD_R NET_SPACING_TYPE=PWR
I16 PP1V05_S0_MCP_PLL_CORE NET_SPACING_TYPE=PWR 15 22
I15 PP1V05_S0_MCP_PLL_FSB NET_SPACING_TYPE=PWR 13 22
I18
PP1V05_S0_MCP_PLL_NV NET_SPACING_TYPE=PWR 20 22
I17
PP1V05_S0_MCP_PLL_PEX NET_SPACING_TYPE=PWR 16 22
I19
PP1V05_S0_MCP_PLL_SATA NET_SPACING_TYPE=PWR 19 22
I21 PP1V05_S0_MCP_SATA_AVDD NET_SPACING_TYPE=PWR 19 22 TABLE_SPACING_RULE_HEAD

I20
PP1V05_S5 NET_SPACING_TYPE=PWR 6 7 TABLE_SPACING_RULE_ITEM
I23
PP1V2_S0_FC_VDD NET_SPACING_TYPE=PWR PWR * =STANDARD ?
I100 PP1V5_S0 NET_SPACING_TYPE=PP1V5_MEM 6 7 TABLE_SPACING_RULE_ITEM
BUS2PWR_GND * 0.228 MM ?
I101 PP1V5_S0_FC_AVDDL_F NET_SPACING_TYPE=PWR
I22
PP1V5_S0_FC_AVDDT_F NET_SPACING_TYPE=PWR
I24
PP1V5_S3 NET_SPACING_TYPE=PP1V5_MEM 6 7
I25 PP1V8_S0 NET_SPACING_TYPE=PWR 6 7
I26
PP2V_S0_MCPREG_REF NET_SPACING_TYPE=PWR
I28
PP3V3_LCDVDD_SW NET_SPACING_TYPE=PWR 59
I27
PP3V3_LCDVDD_SW_F NET_SPACING_TYPE=PWR 6 59
I30 PP3V3_RMGT NET_SPACING_TYPE=PWR 7
I29
I31
PP3V3_S0_CPUTHMSNS_R NET_SPACING_TYPE=PWR 45
I33 PP3V3_S0_DPFUSE NET_SPACING_TYPE=PWR 61
I32
PP3V3_S0_DPPWR NET_SPACING_TYPE=PWR 6 35 61
I35
PP3V3_S0_FC_AVDD_F NET_SPACING_TYPE=PWR
I34
PP3V3_S0_HDD_F NET_SPACING_TYPE=PWR 6 36
I36 PP3V3_S0_IMVP6_3V3 NET_SPACING_TYPE=PWR 50
C I38
I37
PP3V3_S0_LCD_F
PP3V3_S0_MCPREG_VREF3
NET_SPACING_TYPE=PWR 6 59
NET_SPACING_TYPE=PWR
C
I39
PP3V3_S0_MCP_DAC NET_SPACING_TYPE=GND 21 23
I41
PP3V3_S0_MCP_PLL_USB NET_SPACING_TYPE=PWR 19 22
I40
PP3V3_S0_MCP_VPLL NET_SPACING_TYPE=PWR 17 23
I43
I42 PP3V3_S3_AP_AUX NET_SPACING_TYPE=PWR 6 34
I44
PP3V3_S3_AP_AUX_F NET_SPACING_TYPE=PWR 34
I46
PP3V3_S0_MIC_F NET_SPACING_TYPE=PWR 6 59
I45
I48
PP3V3_S5_AVREF_SMC NET_SPACING_TYPE=PWR 39 40
I47
PP3V3_S5_MCP NET_SPACING_TYPE=PWR
I49
PP3V3_S5_SMC_AVCC NET_SPACING_TYPE=PWR 39
I50 PP3V42G3H_SW NET_SPACING_TYPE=PWR 49
I52
PP3V42_G3H NET_SPACING_TYPE=PWR 6 7
I51
PP3V42_G3H_IPD_F NET_SPACING_TYPE=PWR 6 38
I54
PP3V42_G3H_SMCUSBMUX_R NET_SPACING_TYPE=PWR 37
I53
PP5V_S0 NET_SPACING_TYPE=PWR 6 7
I55
PP5V_S0_IMVP6_VDD NET_SPACING_TYPE=PWR 50
I57
PP5V_S0_KBDLED_F NET_SPACING_TYPE=PWR 6 38
I56 PP5V_S0_MCPREG_VCC NET_SPACING_TYPE=PWR
I59 PP5V_S3 NET_SPACING_TYPE=PWR 6 7
I58
PP5V_S3_CAMERA_F NET_SPACING_TYPE=PWR 6 59
I72
PP5V_S3_MCPREG_LDO NET_SPACING_TYPE=PWR
I71
PP5V_S3_TOPCASE_F NET_SPACING_TYPE=PWR 6 38
I73
PP5V_S3_USB2_EXTA NET_SPACING_TYPE=PWR 37
PP5V_S3_USB2_EXTA_F NET_SPACING_TYPE=PWR 6 35 37
B I74
I76
PPBUS_G3H NET_SPACING_TYPE=PWR 6 7 B
I75 PPBUS_G3HRS5_VSENSE NET_SPACING_TYPE=PWR 43
I78
PPBUS_R_G3H NET_SPACING_TYPE=PWR 6 7
I77
PPBUS_S0_LCDBKLT_EN_DIV NET_SPACING_TYPE=PWR 63
I79 PPBUS_S0_LCDBKLT_EN_L NET_SPACING_TYPE=PWR 63
I81 PPBUS_S0_LCDBKLT_FUSED NET_SPACING_TYPE=PWR 63
I80
PPBUS_S0_LCDBKLT_PWR NET_SPACING_TYPE=PWR 62 63
I83
PPDCIN_G3H NET_SPACING_TYPE=PWR 6 7
I82 PPDCIN_G3H_R NET_SPACING_TYPE=PWR 49
I84 PPMCPCORE_S0 NET_SPACING_TYPE=PWR 6 7
I86 PPVBATT_G3H_R NET_SPACING_TYPE=PWR 49 70
I85 PPVBAT_G3H_CHGR_OUT NET_SPACING_TYPE=PWR 58 70
I102
PPVBATT_G3H_R NET_SPACING_TYPE=PWR 49 70
I103
PPVBAT_G3H_CHGR_OUT NET_SPACING_TYPE=PWR 58 70
I104
PPVBAT_G3H_CHGR_REG NET_SPACING_TYPE=PWR 58
I105 PPVBAT_G3H_CHRGR_REG_0 NET_SPACING_TYPE=PWR 58
I106
PPVBAT_G3H_CHRGR_REG_R NET_SPACING_TYPE=PWR 58
I108
PPVCORE_S0_CPU NET_SPACING_TYPE=PWR 6 7
I109 PPVDCIN_G3H_PRE NET_SPACING_TYPE=PWR 43 58
I107
PPVDCIN_G3H_PRE2 NET_SPACING_TYPE=PWR 58
I110
PPVDCIN_G3H_PRE_0 NET_SPACING_TYPE=PWR 58
I112 PPVDCIN_G3H_PRE_R NET_SPACING_TYPE=PWR 58
I113 PPVIN_S5_IMVP6_VIN NET_SPACING_TYPE=PWR 50
PPVOUT_S0_LCDBKLT NET_SPACING_TYPE=PWR 6 59 62
I111
PPVOUT_S0_LCDBKLT_SW NET_SPACING_TYPE=PWR 62
M96 Power and Ground Nets
I114

SYNC_DATE=(MASTER)
A
D 051-7631 2.3.0

NONE 70 71
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
M96 BOARD-SPECIFIC SPACING & PHYSICAL CONSTRAINTS
TABLE_BOARD_INFO
BOARD LAYERS BOARD AREAS BOARD UNITS ALLEGRO TABLE_SPACING_RULE_HEAD TABLE_SPACING_ASSIGNMENT_HEAD TABLE_PHYSICAL_ASSIGNMENT_HEAD
(MIL or MM) VERSION SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET
TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_PHYSICAL_ASSIGNMENT_ITEM
TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,ISL12,ISL13,BOTTOM NO_TYPE,BGA_P1MM MM 15.2

DEFAULT * 0.1 MM ? * * BGA_P1MM BGA_P1MM MEM_50S BGA_P1MM STANDARD
TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM
ALLOW ROUTE
STANDARD * =DEFAULT ? MEM_CLK * BGA_P1MM BGA_P2MM

PHYSICAL_RULE_SET LAYER ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM
BGA_P1MM * =DEFAULT ? CLK_FSB * BGA_P1MM BGA_P2MM

DEFAULT * Y =50_OHM_SE 0.200 MM 30 MM 0 MM 0 MM TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM
BGA_P2MM * =DEFAULT ? CLK_LPC * BGA_P1MM BGA_P2MM

STANDARD * Y =DEFAULT =DEFAULT 12.7 MM =DEFAULT =DEFAULT TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM
BGA_P3MM * =DEFAULT ? CLK_PCI * BGA_P1MM BGA_P2MM

TABLE_PHYSICAL_RULE_HEAD TABLE_SPACING_ASSIGNMENT_ITEM
D PHYSICAL_RULE_SET LAYER ALLOW ROUTE

ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP

CLK_PCIE * BGA_P1MM BGA_P2MM
D
55_OHM_SE TOP,BOTTOM Y 0.210 MM 0.200 MM TABLE_SPACING_RULE_ITEM
CLK_SLOW * BGA_P1MM BGA_P2MM
1.5:1_SPACING * 0.15 MM ? TABLE_SPACING_ASSIGNMENT_ITEM
55_OHM_SE ISL2,ISL13 Y 0.075 MM 0.075 MM =STANDARD =STANDARD =STANDARD TABLE_SPACING_RULE_ITEM

FSB_DSTB FSB_DSTB BGA_P1MM BGA_P3MM
2:1_SPACING * 0.2 MM ?
55_OHM_SE * Y 0.066 MM 0.066 MM =STANDARD =STANDARD =STANDARD TABLE_SPACING_RULE_ITEM
2.5:1_SPACING * 0.25 MM ?
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_SPACING_RULE_ITEM
ON LAYER? 3:1_SPACING * 0.3 MM ?

50_OHM_SE TOP,BOTTOM Y 0.250 MM 0.200 MM TABLE_SPACING_RULE_ITEM
50_OHM_SE ISL2,ISL13 Y 0.085 MM 0.085 MM =STANDARD =STANDARD =STANDARD TABLE_SPACING_RULE_ITEM
2.28:1_SPACING * 0.228 MM ?
TABLE_PHYSICAL_RULE_HEAD TABLE_SPACING_RULE_ITEM
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 1.1:1_SPACING * 0.110 MM ?
ON LAYER?
40_OHM_SE TOP,BOTTOM Y 0.350 MM 0.200 MM TABLE_SPACING_RULE_HEAD

40_OHM_SE ISL2,ISL13 Y 0.122 MM 0.122 MM =STANDARD =STANDARD =STANDARD * TABLE_SPACING_RULE_ITEM
2X_DIELECTRIC TOP,BOTTOM 0.230 MM ?

3X_DIELECTRIC TOP,BOTTOM 0.345 MM ?

TABLE_PHYSICAL_RULE_HEAD TABLE_SPACING_RULE_ITEM
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 4X_DIELECTRIC TOP,BOTTOM 0.460 MM ?
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_ITEM
27P4_OHM_SE TOP,BOTTOM Y 0.215 MM 0.200 MM 5X_DIELECTRIC TOP,BOTTOM 0.575 MM ?

TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_ITEM
27P4_OHM_SE * Y 0.215 MM 0.215 MM =STANDARD =STANDARD =STANDARD 2X_DIELECTRIC ISL2,ISL13 0.110 MM ?

3X_DIELECTRIC ISL2,ISL13 0.165 MM ?
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_SPACING_RULE_ITEM
ON LAYER? 4X_DIELECTRIC ISL2,ISL13 0.220 MM ?
C 70_OHM_DIFF * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD

5X_DIELECTRIC ISL2,ISL13 0.275 MM ?
C
70_OHM_DIFF ISL2,ISL4,ISL5,ISL10,ISL11,ISL13 Y 0.132 MM 0.132 MM 0.200 MM 0.200 MM TABLE_SPACING_RULE_ITEM
2X_DIELECTRIC * 0.120 MM ?
70_OHM_DIFF TOP,BOTTOM Y 0.180 MM 0.180 MM 0.150 MM 0.150 MM TABLE_SPACING_RULE_ITEM
ALLOW ROUTE
PHYSICAL_RULE_SET LAYER ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_SPACING_RULE_ITEM
90_OHM_DIFF * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD
90_OHM_DIFF ISL2,ISL4,ISL5,ISL10,ISL11,ISL13 Y 0.085 MM 0.085 MM 0.250 MM 0.250 MM TABLE_SPACING_RULE_HEAD
GND * =STANDARD ?
ALLOW ROUTE
PP1V5_MEM * =STANDARD ?
100_OHM_DIFF * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD TABLE_SPACING_RULE_HEAD
100_OHM_DIFF ISL2,ISL4,ISL5,ISL10,ISL11,ISL13 Y 0.065 MM 0.065 MM 0.280 MM 0.280 MM TABLE_SPACING_RULE_ITEM
GND_P2MM * 0.2 MM 1000
PWR_P2MM * 0.2 MM 1000

PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_SPACING_RULE_HEAD
ON LAYER? SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT

100_OHM_DIFF_HDD * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD TABLE_SPACING_RULE_ITEM
MCP_STATIC =STANDARD ?
100_OHM_DIFF_HDD ISL2,ISL4,ISL5,ISL10,ISL11,ISL13 Y 0.065 MM 0.065 MM 0.280 MM 0.280 MM
100_OHM_DIFF_HDD TOP,BOTTOM Y 0.179 MM 0.179 MM 0.200 MM 0.200 MM
B PHYSICAL_RULE_SET LAYER ALLOW ROUTE

ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
B
40_OHM_SE_MEM TOP,BOTTOM Y 0.170 MM 0.110 MM 10 MM
40_OHM_SE_MEM ISL2,ISL13 Y 0.122 MM 0.066 MM 170 MM =STANDARD =STANDARD

40_OHM_SE_MEM * Y 0.110 MM 0.066 MM 170 MM =STANDARD =STANDARD
ON LAYER?
1:1_DIFFPAIR * Y =STANDARD =STANDARD =STANDARD 0.1 MM 0.1 MM
M96 RULE DEFINITIONS

A SYNC_MASTER=M97

A
D 051-7631 2.3.0

NONE 71 71
8 7 6 5 4 3 2 1

Apple Macbook Air A1304 (MLB M96) PDF

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8 7 6 5 4 3 2 1

DIMENSIONS ARE IN MILLIMETERS

METRIC APPLE INC.

DRAWING SIZE DRAWING NUMBER

Pg 10 J1300 DC/Batt Power

64-Bit J9000 TOP ALS PG 60

0.75V - 64 Bits CPU/MCP T-Diode Thermal Sensor U5515 PG 47 PG 40

A B 0 BSA MGMT ADC Fan Ser

System Block Diagram

NOTICE OF PROPRIETARY PROPERTY

SIZE DRAWING NUMBER REV.

APPLE INC. SCALE SHT OF

NOTICE OF PROPRIETARY PROPERTY

TPS51116 D 051-7631 2.3.0

BOMs BOMOPTION Groups

630-9734 PCBA,MLB,1.6GHZ,HY 2GB,SS CAP,M96 EEE_4DA,M96_COMMON,M96_HYNIX,M96_SS_CAP,CPU_1_6GHZ M96_COMMON ALTERNATE,COMMON,M96_COMMON1,M96_COMMON2,M96_COMMON3

630-9735 PCBA,MLB,1.6GHZ,HY 2GB,MU CAP,M96 EEE_4DB,M96_COMMON,M96_HYNIX,M96_MU_CAP,CPU_1_6GHZ M96_COMMON1 MCP_B02,BOOTROM_DEVEL,SMC_PRGRM,BOOT_MODE_USER,JTAG_ALLDEV,MEMRESET_HW,MEMRESET_MCP,VREFMRGN

630-9514 PCBA,MLB,1.6GHZ,HY 2GB,TY CAP,M96 EEE_2AL,M96_COMMON,M96_HYNIX,M96_TY_CAP,CPU_1_6GHZ M96_COMMON2 LPCPLUS,XDP,XDP_CONN

630-9738 PCBA,MLB,1.8GHZ,HY 2GB,SS CAP,M96 EEE_4DC,M96_COMMON,M96_HYNIX,M96_SS_CAP,CPU_1_8GHZ M96_COMMON3 MCP_CS1_NO

D 630-9516 PCBA,MLB,1.8GHZ,HY 2GB,MU CAP,M96 EEE_2AN,M96_COMMON,M96_HYNIX,M96_MU_CAP,CPU_1_8GHZ

IC,PRGRM,SMC (NEW),M96 U4900 CRITICAL SMC_PRGRM

333S0476 4 HYNIX,DDR3,128M16,9x11.5 U3200,U3210,U3220,U3230 CRITICAL DRAM_HYNIX

333S0476 4 HYNIX,DDR3,128M16,9x11.5 U3300,U3310,U3320,U3330 CRITICAL DRAM_HYNIX

333S0476 4 HYNIX,DDR3,128M16,9x11.5 U3400,U3410,U3420,U3430 CRITICAL DRAM_HYNIX

333S0475 4 MICRON,DDR3,128M16,9x11.5 U3100,U3110,U3120,U3130 CRITICAL DRAM_MICRON

333S0475 4 MICRON,DDR3,128M16,9x11.5 U3200,U3210,U3220,U3230 CRITICAL DRAM_MICRON

333S0475 4 MICRON,DDR3,128M16,9x11.5 U3300,U3310,U3320,U3330 CRITICAL DRAM_MICRON

333S0475 4 MICRON,DDR3,128M16,9x11.5 U3400,U3410,U3420,U3430 CRITICAL DRAM_MICRON

353S1938 1 IC,ISL6258,REV2,BAT CHGR, 28P QFN U7900 CRITICAL

SIZE DRAWING NUMBER REV.

APPLE INC. SCALE SHT OF

1UF 0402 CAPACITOR VENDOR TABLES FOR ACOUSTICS

2.2UF 0402 CAPACITOR VENDOR TABLES FOR ACOUSTICS

CAP, 2.2UF, 6.3V, 20%, 0402

C9900,C9901,C9902,C9903,C9904,C9905,C9906,C9907,C9908,C9909 CRITICAL SS_CAP_2_2UF

CAP, 2.2UF, 6.3V, 20%, 0402

C9900,C9901,C9902,C9903,C9904,C9905,C9906,C9907,C9908,C9909 CRITICAL MU_CAP_2_2UF

CAP, 2.2UF, 6.3V, 20%, 0402

C9900,C9901,C9902,C9903,C9904,C9905,C9906,C9907,C9908,C9909 CRITICAL TY_CAP_2_2UF

Acoustic Cap BOM Config Tables

NOTICE OF PROPRIETARY PROPERTY

SIZE DRAWING NUMBER REV.

APPLE INC. SCALE SHT OF

x2 I647 TRUE BATT_POS 49 I470 TRUE AIRPORT_RST_L 6 24 34 I92

x2 I649 TRUE GND I475 TRUE PCIE_WAKE_L 6 16 34 I454

I638 TRUE SMC_BS_ALRT_L 39 40 49 I479 TRUE CK505_SRC_CLKREQ6_L 6 I455

TRUE SMBUS_SMC_BSA_SCL 42 69 TRUE PCIE_CLK100M_MINI_N_F 34 PP1V5_S0 7 70 TRUE TP_XDP_OBSDATA_B2 12

I639 TRUE SMBUS_SMC_BSA_SDA 42 69

I476 TRUE PCIE_CLK100M_MINI_P_F 34

I684 TRUE TP_XDP_OBSDATA_B3 12 D

I480 TRUE PCIE_E_D2R_P_F 34 I458 PPMCPCORE_S0 7 70 I687 TRUE XDP_OBS20 12

x6 I648 TRUE PP18V5_DCIN 49 70 I484 TRUE PCIE_E_R2D_C_P_F 6 34 I466

I500 TRUE =SMB_AIRPORT_CLK 6 34 42 I467 PP3V3_S5 7 70 I690 TRUE JTAG_MCP_TRST_L 12 20

FUNC TEST - AIRPORT I757 PP1V8_S0 7 70 I698 TRUE XDP_CPURST_L 12 65

I741 TRUE CK505_SRC_CLKREQ6_L 6 I699 TRUE XDP_DBRESET_L 9 12

AIRPORT_RST_L FUNC TEST - SATA HDD XDP_TRST_L

I748 TRUE AUD_MIC_DATA_F 59 FUNC TEST - RIO HATCH CONNECTOR

I646 TRUE HDA_BIT_CLK 20 35 68 I721 TRUE HDMI_CEC 35 61 I657 TRUE LCDBKLT_RTN<1..6> 59 62

I735 TRUE AUD_MIC_DATA 35 59 I722 TRUE DP_HPD_Q 35 61 I658 TRUE LVDS_IG_A_DATA_N<0..2> 17 59 67

I736 TRUE HDA_SDOUT 20 35 68 I723 TRUE PP3V3_S0_DPPWR 35 61 70 I659 TRUE LVDS_IG_A_DATA_P<0..2> 17 59 67

I737 TRUE =PPVIN_S0_AUDIO 7 35 I725 TRUE USB2_EXTA_F_P 35 37 I660 TRUE PPVOUT_S0_LCDBKLT 59 62 70

I738 TRUE HDA_SDIN0 20 35 68 I726 TRUE USB2_EXTA_F_N 35 37 I661 TRUE LVDS_IG_A_CLK_F_N 59 67

I740 TRUE AUD_MIC_CLK 35 59 I727 TRUE PP5V_S3_USB2_EXTA_F 35 37 70 I662 TRUE LVDS_IG_A_CLK_F_P 59 67