SDR HB 10th Apr 13

So
Soff t ware Defined Radio Handbook

Radio
10th Edition
Sampling
Principles of SDR
Technology
Products
Applications
Links
by
Rodger H
H.. Hosking
Vice-President & Cofounder of Pentek, Inc.
Pentek, Inc.
One Park Way, Upper Saddle River, New Jersey 07458
Tel: (201) 818-5900 Fax: (201) 818-5904
Email: info@pentek.com http://www.pentek.com
Copyright 1998, 2001, 2003, 2006, 2008, 2009, 2010, 2011, 2012, 2013 Pentek, Inc.
Last updated: April 2013
All rights reserved.
Contents of this publication may not be reproduced in any form without written permission.
Specifications are subject to change without notice.
Pentek, GateFlow, ReadyFow, SystemFlow and Cobalt are registered trademarks of Pentek, Inc.
1
Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: info@pentek.com http://www.pentek.com
Software Defined Radio Handbook
Preface
SDR (Software-Defined Radio) has revolutionized electronic systems for a

variety of applications including communications, data acquisition and signal processing.
This handbook shows how DDCs (Digital Downconverters) and DUCs (Digital Upconverters),
the fundamental building blocks of SDR, can replace legacy analog receiver and transmitter designs while
offering significant benefits in performance, density and cost.
In order to fully appreciate the benefits of SDR, conventional analog receiver and transmitter
systems will be compared to their digital counterparts, highlighting similarities and differences.
The inner workings of the SDR will be explored with an in-depth description of the internal
structure and the devices used. Finally, some actual board- and system-level implementations and available
off-the-shelf SDR products and applications based on such products will be presented.
For more information on complementary subjects, the reader is referred to these Pentek Handbooks:
Putting FPGAs to Work in Software Radio Systems
Critical Techniques for High-Speed A/D Converters in Real-Time Systems
High-Speed Switched Serial Fabrics Improve System Design
High-Speed, Real-Time Recording Systems
2
Sampling
Nyquists Theorem and Sampling A Simple TTechnique

echnique to Visualize Sampling
Before we look at SDR and its various implementa-

tions in embedded systems, well review a theorem
fundamental to sampled data systems such as those Frequency
0 fs/2 fs 3fs/2 2fs 5fs/2 3fs 7fs/2
encountered in Software-Defined Radios.
Nyquists Theorem:
Any signal can be represented by discrete Zone 1 Zone 2 Zone 3 Zone 4 Zone 5 Zone 6 Zone 7
samples if the sampling frequency is at least twice
the bandwidth of the signal.
Figure 1
Notice that we highlighted the word bandwidth To visualize what happens in sampling, imagine
rather than frequency. In what follows, well attempt to that you are using transparent fan-fold computer
show the implications of this theorem and the correct paper. Use the horizontal edge of the paper as the
interpretation of sampling frequency, also known as frequency axis and scale it so that the paper folds line
sampling rate. up with integer multiples of one-half of the sampling
frequency s. Each sheet of paper now represent what we
will call a Nyquist Zone, as shown in Figure 1.
3
Sampling
Sampling Basics Baseband Sampling
0 fs/2 fs 3fs/2 2fs 5fs/2 3fs 7fs/2 0 fs/2 fs 3fs/2 2fs 5fs/2 3fs 7fs/2
Energy
No Signal Energy
Zone 1 Zone 2 Zone 3 Zone 4 Zone 5 Zone 6 Zone 7 Zone 1 Zone 2 Zone 3 Zone 4 Zone 5 Zone 6 Zone 7
Figure 2 Figure 4
Use the vertical axis of the fan-fold paper for signal A baseband signal has frequency components that
energy and plot the frequency spectrum of the signal to start at = 0 and extend up to some maximum frequency.
be sampled, as shown in Figure 2. To see the effects of
To prevent data destruction when sampling a baseband
sampling, collapse the transparent fan-fold paper into a
signal, make sure that all the signal energy falls ONLY in
stack.
the 1st Nyquist band, as shown in Figure 4.
There are two ways to do this:
0 fs/2 1. Insert a lowpass filter to eliminate all signals
Folded Signals
Fall On Top of
above s /2, or
Each Other 2. Increase the sampling frequency so all signals
present fall below s /2.
Note that s/2 is also known as the folding frequency.
Sampling Bandpass Signals
Lets consider bandpass signals like the IF frequency

Figure 3 of a communications receiver that might have a 70 MHz
center frequency and 10 MHz bandwidth. In this case,
the IF signal contains signal energery from 65 to 75 MHz.
The resulting spectrum can be seen by holding the
transparent stack up to a light and looking through it. If we follow the baseband sampling rules above, we
You can see that signals on all of the sheets or zones are must sample this signal at twice the highest signal
folded or aliased on top of each other and they frequency, meaning a sample rate of at least 150 MHz.
can no longer be separated. However, by taking advantage of a technique called
Once this folding or aliasing occurs during sampling, undersampling, we can use a much lower sampling rate.
the resulting sampled data is corrupted and can never be
recovered. The term aliasing is appropriate because
after sampling, a signal from one of the higher zones
now appears to be at a different frequency.
4
Sampling
Undersampling
Folded signals
still fall on top of
each other - but 0 fs/2
0 fs/2 fs 3fs/2 2fs 5fs/2 3fs 7fs/2
now there is
energy in
only one sheet !
No Signal Energy No Signal Energy
Zone 1 Zone 2 Zone 3 Zone 4 Zone 5 Zone 6 Zone 7
Figure 5 Figure 6
Undersampling allows us to use aliasing to our The major rule to follow for successful undersampling
advantage, providing we follow the strict rules of the is to make sure all of the energy falls entirely in one
Nyquist Theorem. Nyquist zone.
In our previous IF signal example, suppose we try a There two ways to do this:
sampling rate of 40 MHz. 1. Insert a bandpass filter to eliminate all signals
outside the one Nyquist zone.
Figure 5 shows a fan-fold paper plot with Fs = 40 MHz.
2. Increase the sampling frequency so all signals
You can see that zone 4 extends from 60 MHz to 80 MHz,
fall entirely within one Nyquist zone.
nicely containing the entire IF signal band of 65 to 75 MHz.
Now when you collapse the fan fold sheets as shown
in Figure 6, you can see that the IF signal is preserved Summar
Summaryy
after sampling because we have no signal energy in any
other zone. Baseband sampling requires the sample frequency to
be at least twice the signal bandwidth. This is the same
Also note that the odd zones fold with the lower
as saying that all of the signals fall within the first
frequency at the left (normal spectrum) and the even
Nyquist zone.
zones fold with the lower frequency at the right (reversed
spectrum). In real life, a good rule of thumb is to use the 80%
relationship:
In this case, the signals from zone 4 are frequency-
reversed. This is usually very easy to accommodate in Bandwidth = 0.8 x s/2
the following stages of SDR systems.
Undersampling allows a lower sample rate even though
signal frequencies are high, PROVIDED all of the
signal energy falls within one Nyquist zone.
To repeat the Nyquist theorem: The sampling frequency
must be at least twice the signal bandwidth not the
signal frequency.
5
Principles of SDR
Analog Radio R
Radio eceiver Block Diagram
Receiver Analog Radio R
Radio eceiver Mixer
Receiver
SPEAKER RF INPUT SIGNAL

FROM ANTENNA
ANTENNA
MIXER TRANSLATES Signal
INPUT SIGNAL BAND
ANALOG to IF FREQUENCY
MIXER
RF IF AMP DEMODULATOR AUDIO

AMP (FILTER) (Detector) AMP
ANALOG LOCAL
OSCILLATOR
ANALOG
LOCAL
OSCILLATOR
0 FIF FRF
Figure 7 Figure 8
The conventional heterodyne radio receiver shown The mixer performs an analog multiplication of the
in Figure 7, has been in use for nearly a century. Lets two inputs and generates a difference frequency signal.
review the structure of the analog receiver so comparison
The frequency of the local oscillator is set so that the
to a digital receiver becomes apparent.
difference between the local oscillator frequency and the
First the RF signal from the antenna is amplified, desired input signal (the radio station you want to
typically with a tuned RF stage that amplifies a region receive) equals the IF.
of the frequency band of interest.
For example, if you wanted to receive an FM
This amplified RF signal is then fed into a mixer station at 100.7 MHz and the IF is 10.7 MHz, you would
stage. The other input to the mixer comes from the local tune the local oscillator to:
oscillator whose frequency is determined by the tuning
100.7 - 10.7 = 90 MHz
control of the radio.
This is called downconversion or translation
The mixer translates the desired input signal to the
because a signal at a high frequency is shifted down to a
IF (Intermediate Frequency) as shown in Figure 8.
lower frequency by the mixer.
The IF stage is a bandpass amplifier that only lets
The IF stage acts as a narrowband filter which only
one signal or radio station through. Common center
passes a slice of the translated RF input. The band-
frequencies for IF stages are 455 kHz and 10.7 MHz
width of the IF stage is equal to the bandwidth of the
for commercial AM and FM broadcasts.
signal (or the radio station) that you are trying to
The demodulator recovers the original modulating receive.
signal from the IF output using one of several different
For commercial FM, the bandwidth is about
schemes.
100 kHz and for AM it is about 5 kHz. This is consis-
For example, AM uses an envelope detector and FM tent with channel spacings of 200 kHz and 10 kHz,
uses a frequency discriminator. In a typical home radio, respectively.
the demodulated output is fed to an audio power amplifier
which drives a speaker.
6
Principles of SDR
SDR Receiver Block Diagram

Receiver
DDC
Digital Downconverter
Digital
Analog Analog Digital IF Baseband
RF Signal RF IF Signal A/D Samples DIGITAL LOWPASS Samples
DSP
TUNER CONV MIXER FILTER
DIGITAL
LOCAL
OSC
Figure 9
Figure 9 shows a block diagram of a software SDR Receiver Mixer

Receiver
defined radio receiver. The RF tuner converts analog RF
signals to analog IF frequencies, the same as the first three
CHANNEL
stages of the analog receiver. BANDWIDTH MIXER TRANSLATES
INPUT SIGNAL
BAND to DC IF BW
The A/D converter that follows digitizes the IF signal Signal
thereby converting it into digital samples. These samples

are fed to the next stage which is the digital downconverter DIGITAL LOCAL
(DDC) shown within the dotted lines. OSCILLATOR
FLO = FSIG
The digital downconverter is typically a single
monolithic chip or FPGA IP, and it is a key part of the
SDR system.
0 FSIG
Figure 10
A conventional DDC has three major sections:
A digital mixer
A digital local oscillator At the output of the mixer, the high frequency
wideband signals from the A/D input (shown in Figure
An FIR lowpass filter
10 above) have been translated down to DC as complex I
The digital mixer and local oscillator translate the and Q components with a frequency shift equal to the
digital IF samples down to baseband. The FIR lowpass local oscillator frequency.
filter limits the signal bandwidth and acts as a decimat- This is similar to the analog receiver mixer except
ing lowpass filter. The digital downconverter includes a there, the mixing was done down to an IF frequency.
lot of hardware multipliers, adders and shift register Here, the complex representation of the signal allows us
memories to get the job done. to go right down to DC.
The digital baseband samples are then fed to a block By tuning the local oscillator over its range, any
labeled DSP which performs tasks such as demodulation, portion of the RF input signal can be mixed down to DC.
decoding and other processing tasks.
In effect, the wideband RF signal spectrum can be
Traditionally, these needs have been handled with slid around 0 Hz, left and right, simply by tuning the
dedicated application-specific ICs (ASICs), and program- local oscillator. Note that upper and lower sidebands are
mable DSPs. preserved.
7
Principles of SDR
DDC LLocal
ocal Oscillator and Decimation DDC Signal PProcessing
rocessing
Translation Filtering
Digital
Digital IF Baseband
A/D Samples DIGITAL LOWPASS Samples
CONV MIXER FILTER
90O
DIGITAL
LOCAL
OSC
Tuning Freq Decimation

F1 F2 F3
Figure 12
Figure 11A Local Oscillator Frequency Switching
This process is called decimation and it means keeping

A/D Sample Rate one out of every N signal samples. If the decimated
(before decimation)
Sample Rate: Fs output sample rate is kept higher than twice the output
bandwidth, no information is lost.
Decimated
Filter Output
The clear benefit is that decimated signals can be
Sample Rate: Fs/N processed easier, can be transmitted at a lower rate, or
stored in less memory. As a result, decimation can
Figure 11B FIR Filter Decimation dramatically reduce system costs!
As shown in Figure 12, the DDC performs two
signal processing operations:
Because the local oscillator uses a digital phase
accumulator, it has some very nice features. It switches 1. Frequency translation with the tuning controlled
between frequencies with phase continuity, so you can by the local oscillator.
generate FSK signals or sweeps very precisely with no
2. Lowpass filtering with the bandwidth controlled
transients as shown in Figure 11A.
by the decimation setting.
The frequency accuracy and stability are determined
We will next turn our attention to the Software-
entirely by the A/D clock so its inherently synchronous
Defined Radio Transmitter.
to the sampling frequency. There is no aging, drift or
calibration since its implemented entirely with digital logic.
Since the output of the FIR filter is band-limited, the
Nyquist theorem allows us to lower the sample rate. If
we are keeping only one out of every N samples, as shown
in Figure 11B above, we have dropped the sampling rate
by a factor of N.
8
Principles of SDR
SDR TTransmitter
ransmitter Block Diagram
Digital Digital Analog Analog

Baseband Baseband Digital IF IF RF
Samples Samples DIGITAL Samples Signal Signal
INTERPOLATION D/A RF Power
DSP
FILTER MIXER CONV Upconverter Amplifier
Fs/N Fs Fs
DUC DIGITAL
Digital Up LOCAL
Converter OSC
Figure 13
The input to the transmit side of an SDR system is DUC Signal PProcessing
rocessing
a digital baseband signal, typically generated by a DSP
stage as shown in Figure 13 above.
The digital hardware block in the dotted lines is a Digital Digital
DUC (digital upconverter) that translates the baseband Baseband Baseband Digital IF
Samples Samples DIGITAL Samples
signal to the IF frequency. INTERPOLATION
FILTER MIXER
Fs/N Fs Fs
The D/A converter that follows converts the digital
IF samples into the analog IF signal. DUC DIGITAL
Digital Up LOCAL
Next, the RF upconverter converts the analog IF Converter OSC
signal to RF frequencies.
Figure 14
Finally, the power amplifier boosts signal energy to
the antenna.
Inside the DUC shown in Figure 14, the digital
mixer and local oscillator at the right translate baseband
samples up to the IF frequency. The IF translation
frequency is determined by the local oscillator.
The mixer generates one output sample for each of
its two input samples. And, the sample frequency at
the mixer output must be equal to the D/A sample
frequency s .
Therefore, the local oscillator sample rate and the
baseband sample rate must be equal to the D/A sample
frequency s .
The local oscillator already operates at a sample rate
of s , but the input baseband sample frequency at the
left is usually much lower. This problem is solved with
the Interpolation Filter.
9
Principles of SDR
Interpolation FFilter:
ilter: Time domain Interpolation FFilter:
ilter: FFrequency
requency Domain
Fs/N Fs Digital Digital

Baseband Baseband Digital IF
I INTERPOLATING I Samples Samples Samples
LOW PASS INTERPOLATION DIGITAL
Q FIR FILTER Q Fs/N FILTER MIXER
Fs Fs
BASEBAND INTER-
INPUT POLATED DUC
OUTPUT DIGITAL
Digital Up LOCAL
Converter OSC
INTERPOLATION
FACTOR = N
INTERPOLATED
BASEBAND INPUT TRANSLATED OUTPUT
Baseband Input
MIXER
Sample Rate: Fs/N
LOCAL
OSCILLATOR
F = IF Freq
Interpolating
Filter Output
Sample Rate: Fs 0 IF Freq
Figure 15 Figure 16
The interpolation filter must boost the baseband Figure 16 is a frequency domain view of the digital
input sample frequency of s /N up to the required mixer upconversion process.
input and D/A output sample frequency of s .
This is exactly the opposite of the frequency domain
The interpolation filter increases the sample frequency view of the DDC in Figure 10.
of the baseband input signal by a factor N, known as
The local oscillator setting is set equal to the
the interpolation factor.
required IF signal frequency, just as with the DDC.
At the bottom of Figure 15, the effect of the
interpolation filter is shown in the time domain.
Notice the baseband signal frequency content is
completely preserved by filling in additional samples in
the spaces between the original input samples.
The signal processing operation performed by the
interpolation filter is the inverse of the decimation filter
we discussed previously in the DDC section.
10
Principles of SDR
DDC PProcessing
rocessing DUC PProcessing
rocessing
Translation Filtering Filtering Translation
A/D DIGITAL LOWPASS INTERPOLATE DIGITAL D/A

DSP DSP
CONV MIXER FILTER FILTER MIXER CONV
Fs Fb Fb Fs
DIGITAL N DIGITAL
LOCAL N LOCAL
OSC OSC
Freq uency Deci mation Inter polation Freq uency
Tuning Bandwidth Bandwidth Tuning

Figure 17 Figure 18
Figure 17 shows the two-step processing performed Figure 18 shows the two-step processing performed
by the digital downconverter. by the digital upconverter:
Frequency translation from IF down to baseband is The ratio between the required output sample rate
performed by the local oscillator and mixer. and the sample rate input baseband sample rate deter-
mines the interpolation factor N.
The tuning knob represents the programmability
of the local oscillator frequency to select the desired Baseband bandwidth = 0.8 x b
signal for downconversion to baseband.
Output sample frequency s = b x N
The baseband signal bandwidth is set by setting
Again, the bandwidth equation assumes a complex
decimation factor N and the lowpass FIR filter:
(I+Q) baseband input and an 80% filter.
Baseband sample frequency b = s /N
The bandwidth knob represents the programma-
Baseband bandwidth = 0.8 x b bility of the interpolation factor to select the desired
input baseband signal bandwidth.
The baseband bandwidth equation reflects a typical
80% passband characteristic, and complex (I+Q) samples. Frequency translation from baseband up to IF is
performed by the local oscillator and mixer.
The bandwidth knob represents the program-
mability of the decimation factor to select the desired The tuning knob represents the programmability
baseband signal bandwidth. of the local oscillator frequency to select the desired IF
frequency for translation up from baseband.
11
Principles of SDR
Key DDC and DUC Benefits SDR TTasks

asks
Digital
Digital IF Baseband
A/D Samples DIGITAL LOWPASS Samples
CONV MIXER FILTER
Fs Fs/N
DIGITAL
DUC
LOCAL Digital Down
OSC Converter
Digital Digital
Baseband Baseband Digital IF
Samples Samples DIGITAL Samples
INTERPOLATION D/A
FILTER MIXER CONV
Fs/N Fs Fs
DUC DIGITAL
Digital Up LOCAL
Converter OSC
Figure 19 Figure 20
Think of the DDC as a hardware preprocessor for Here weve ranked some of the popular signal
programmable DSP or GPP processor. It preselects only processing tasks associated with SDR systems on a two
the signals you are interested in and removes all others. axis graph, with computational Processing Intensity on
This provides an optimum bandwidth and minimum the vertical axis and Flexibility on the horizontal axis.
sampling rate into the processor.
What we mean by process intensity is the degree of
The same applies to the DUC. The processor only highly-repetitive and rather primitive operations. At the
needs to generate and deliver the baseband signals upper left, are dedicated functions like A/D converters
sampled at the baseband sample rate. The DUC then and DDCs that require specialized hardware structures
boosts the sampling rate in the interpolation filter, to complete the operations in real time. ASICs are usually
performs digital frequency translation, and delivers chosen for these functions.
samples to the D/A at a very high sample rate.
Flexibility pertains to the uniqueness or variability
The number of processors required in a system is of the processing and how likely the function may have
directly proportional to the sampling frequency of to be changed or customized for any specific application.
input and output data. As a result, by reducing the At the lower right are tasks like analysis and decision
sampling frequency, you can dramatically reduce the making which are highly variable and often subjective.
cost and complexity of the programmable DSPs or
Programmable general-purpose processors or DSPs
GPPs in your system.
are usually chosen for these tasks since these tasks can be
Not only do DDCs and DUCs reduce the processor easily changed by software.
workload, the reduction of bandwidth and sampling rate
Now lets temporarily step away from the software
helps save time in data transfers to another subsystem. This
radio tasks and take a deeper look at programmable
helps minimize recording time and disk space, and reduces
logic devices.
traffic and bandwidth across communication channels.
12
Technology
Early Roles for FPGAs

Roles Legacy FPGA Design Methodologies
Used primarily to replace discrete digital Tools were oriented to hardware engineers
hardware circuitry for: Schematic processors
Control logic Boolean processors
Glue logic Gates, registers, counters, multipliers
Registers and gates Successful designs required high-level

State machines hardware engineering skills for:
Counters and dividers Critical paths and propagation delays
Devices were selected by hardware engineers Pin assignment and pin locking
Signal loading and drive capabilities
Programmed functions were seldom changed
Clock distribution
after the design went into production Input signal synchronization and skew analysis
Figure 21 Figure 22
As true programmable gate functions became These programmable logic devices were mostly the
available in the 1970s, they were used extensively by domain of hardware engineers and the software tools
hardware engineers to replace control logic, registers, were tailored to meet their needs. You had tools for
gates, and state machines which otherwise would have accepting boolean equations or even schematics to help
required many discrete, dedicated ICs. generate the interconnect pattern for the growing
number of gates.
Often these programmable logic devices were one-
time factory-programmed parts that were soldered down Then, programmable logic vendors started offering
and never changed after the design went into production. predefined logic blocks for flip-flops, registers and
counters that gave the engineer a leg up on popular
hardware functions.
Nevertheless, the hardware engineer was still
intimately involved with testing and evaluating the
design using the same skills he needed for testing
discrete logic designs. He had to worry about propaga-
tion delays, loading, clocking and synchronizingall
tricky problems that usually had to be solved the hard
waywith oscilloscopes or logic analyzers.
13
Technology
FPGAs: New Device TTechnology

echnology FPGAs: New Development TTools
ools
u 500+ MHz DSP Slices and Memory Structures

u Over 3500 dedicated on-chip hardware multipliers
u On-board GHz Serial Transceivers High Level Design Tools
u
Partial Reconfigurability Maintains Block Diagram System Generators
u Operation During Changes
Schematic Processors
u Switched Fabric Interface Engines High-level language compilers for
u Over 690,000 Logic Cells VHDL & Verilog
u Gigabit Ethernet media access controllers Advanced simulation tools for modeling speed,
propagation delays, skew and board layout
u On-chip 405 PowerPC RISC micro-controller cores
Faster compilers and simulators save time
u Memory densities approaching 85 million bits
Graphically-oriented debugging tools
u Reduced power with core voltages at 1 volt
IP (Intellectual Property) Cores
u Silicon geometries to 28 nanometers
FPGA vendors offer both free and licensed cores
u High-density BGA and flip-chip packaging
FPGA vendors promote third party core vendors
u Over 1200 user I/O pins
Wide range of IP cores available
u
Configurable logic and I/O interface standards
Figure 23 Figure 24
Its virtually impossible to keep up to date on FPGA To support such powerful devices, new design tools
technology, since new advancements are being made are appearing that now open up FPGAs to both hard-
every day. ware and software engineers. Instead of just accepting
logic equations and schematics, these new tools accept
The hottest features are processor cores inside the
entire block diagrams as well as VHDL and Verilog
chip, computation clocks to 500 MHz and above, and
definitions.
lower core voltages to keep power and heat down.
Choosing the best FPGA vendor often hinges
Several years ago, dedicated hardware multipliers
heavily on the quality of the design tools available to
started appearing and now youll find literally thousands
support the parts.
of them on-chip as part of the DSP initiative launched
by virtually all FPGA vendors. Excellent simulation and modeling tools help to
quickly analyze worst case propagation delays and
High memory densities coupled with very flexible
suggest alternate routing strategies to minimize them
memory structures meet a wide range of data flow
within the part. This minimizes some of the tricky
strategies. Logic slices with the equivalent of over ten
timing work for hardware engineers and can save one
million gates result from silicon geometries shrinking
hours of tedious troubleshooting during design verifica-
below 0.1 micron.
tion and production testing.
BGA and flip-chip packages provide plenty of I/O
In the last few years, a new industry of third party
pins to support on-board gigabit serial transceivers and
IP (Intellectual Property) core vendors now offer
other user-configurable system interfaces.
thousands of application-specific algorithms. These are
New announcements seem to be coming out every ready to drop into the FPGA design process to help beat
day from chip vendors like Xilinx and Altera in a never- the time-to-market crunch and to minimize risk.
ending game of outperforming the competition.
14
Technology
FPGAs for SDR FPGAs Bridge the SDR Application Space
Parallel Processing
Hardware Multipliers for DSP
FPGAs can now have over 500 hardware multipliers
Flexible Memory Structures
Dual port RAM, FIFOs, shift registers, look up tables, etc.
Parallel and Pipelined Data Flow
Systolic simultaneous data movement
Flexible I/O
Supports a variety of devices, buses and interface standards
High Speed
Available IP cores optimized for special functions
Figure 25 Figure 26
Like ASICs, all the logic elements in FPGAs can As a result, FPGAs have significantly invaded the
execute in parallel. This includes the hardware multipli- application task space as shown by the center bubble in
ers, and you can now get over 1000 of them on a single the task diagram above.
FPGA.
They offer the advantages of parallel hardware to
This is in sharp contrast to programmable DSPs, handle some of the high process-intensity functions like
which normally have just a handful of multipliers that DDCs and the benefit of programmability to accommo-
must be operated sequentially. date some of the decoding and analysis functions of DSPs.
FPGA memory can now be configured with the These advantages may come at the expense of
design tool to implement just the right structure for increased power dissipation and increased product costs.
tasks that include dual port RAM, FIFOs, shift registers However, these considerations are often secondary to the
and other popular memory types. performance and capabilities of these remarkable devices.
These memories can be distributed along the signal
path or interspersed with the multipliers and math
blocks, so that the whole signal processing task operates
in parallel in a systolic pipelined fashion.
Again, this is dramatically different from sequential
execution and data fetches from external memory as in a
programmable DSP.
As we said, FPGAs now have specialized serial and
parallel interfaces to match requirements for high-speed
peripherals and buses.
15
Technology
Typical PPentek
entek PProducts
roducts with FFactor
actor
actoryy-Installed SDR IP Cores
Analog Sampling Input DDC Decimation Output DUC Interpol. Beam-

Model Channels Freq (max) Bits Channels Range Bits Channels Range former
7142-428 4 125 MHz 14 4 264K 16 or 24 None None No

7151 4 200 MHz 16 256 1281K 16 or 24 None None No
7152 4 200 MHz 16 32 168K 16 or 24 None None Yes
7153 4 200 MHz 16 2 or 4 264K/2256 16 or 24 None None Yes
71621 3 200 MHz 16 3 264K 16 or 24 1 2512K Yes
71641 1 or 2 3.6 or 1.8 GHz 12 1 or 2 4, 8 or 16 16 None None No
71651 2 500/400 MHz 12/14 2 2128K 16 or 24 1 2512K Yes
71661 4 200 MHz 16 4 264K 16 or 24 None None Yes
71662 4 200 MHz 16 32 168K 24 None None No
71671 None None None 16 4 21024K No
Figure 27
The above chart shows the salient characteristics for Other information thats specific to each core is
some of Penteks SDR products with factory-instlled IP included as well as an indication of the models that
cores. All these products are available off-the-self and are include an interpolation filter and output D/A. As shown
in the Pentek datasheets and catalogs. in the chart, many of these models include features that
are critical for beamforming and direction-finding
The chart provides information regarding the number
applications.
of input channels, maximum sampling frequency of their
A/Ds, the number of bits, and number of DDC chan- All the models shown here are PMC or XMC modules.
nels in each one. This information is followed by DDC As with all Pentek SDR products, these models are also
characteristics such as number of DDC channels and the available in CompactPCI, PCI Express, OpenVPX, and
decimation range. AMC formats as well.
16
Technology
FPGA Resource Comparison

Resource
Vir tex-II PPro

Virtex-II ro Vir tex-4
Virtex-4 Vir tex-5
Virtex-5 Vir tex-6
Virtex-6 Vir tex-7
Virtex-7
VP FX, LX, SX LX, SX LX, SX VX
Logic Cells 53K74K 55K110K 52K155K 128K314K 326K693K
Slices* 23K33K 24K49K 8K24K 20K49K 51K108K
CLB Flip-Flops 46K66K 48K98K 32K96K 160K392K 408K864K
Block RAM (kb) 4,1765,904 4,1766,768 4,7528,784 9,50425,344 27,00052,920
DSP Hard IP 18x18 Multipliers DSP48 DSP48E DSP48E DSP48E
DSP Slices 232328 96512 128640 4801,344 1,1203,600
Serial Gbit Transceivers N/A 020 1216 2024 2880
PCI Express Support N/A N/A N/A Gen 2 x8 Gen 2 x8, Gen 3 x8
User I/O 852996 576960 480680 600720 7001,000
*Virtex-II Pro and Virtex-4 Slices actually require 2.25 Logic Cells;
*Virtex-5, Virtex-6 and Virtex-7 Slices actually require 6.4 Logic Cells
Figure 28
The above chart compares the available resources in The Virtex-5 family LX devices offer maximum
the five Xilinx FPGA families that are used in most of logic resources, gigabit serial transceivers, and Ethernet
the Pentek products. media access controllers. The SX devices push DSP
Virtex-II Pro: VP capabilities with all of the same extras as the LX.
Virtex-4: FX, LX and SX
Virtex-5: LX and SX
The Virtex-5 devices offer lower power dissipation,
Virtex-6: LX and SX
faster clock speeds and enhanced logic slices. They also
Virtex-7: VX
improve the clocking features to handle faster memory
and gigabit interfaces. They support faster single-ended
The Virtex-II family includes hardware multipliers and differential parallel I/O buses to handle faster
that support digital filters, averagers, demodulators peripheral devices.
and FFTsa major benefit for software radio signal
The Virtex-6 and Virtex-7 devices offer still higher
processing. The Virtex-II Pro family dramatically
density, more processing power, lower power consump-
increased the number of hardware multipliers and also
tion, and updated interface features to match the latest
added embedded PowerPC microcontrollers.
technology I/O requirements including PCI Express.
The Virtex-4 family is offered as three subfamilies Virtex-6 supports PCIe 2.0 and Virtex-7 supports PCIe 3.0
that dramatically boost clock speeds and reduce power
The ample DSP slices are responsible for the
dissipation over previous generations.
majority of the processing power of the Virtex-6 and
The Virtex-4 LX family delivers maximum logic and Virtex-7 families. Increases in operating speed from 500 MHz
I/O pins while the SX family boasts of 512 DSP slices in V-4, to 550 MHz in V-5, to 600 MHz in V-6, to
for maximum DSP performance. The FX family is a 900 MHz in V-7 and continuously increasing density
generous mix of all resources and is the only family to allow more DSP slices to be included in the same-size
offer RocketIO, PowerPC cores, and the newly added package. As shown in the chart, Virtex-6 tops out at an
gigabit Ethenet ports. impressive 1,344 DSP slices, while Virtex-7 tops out at
an even more impressive 3,600 DSP slices.
17
Products
PMC, XMC, CompactPCI, PCI, PCI Express, OpenVPX, AMC, and VMEbus Sof tware R
Software adio
Radio
Half-length
PCI Express Board
3U OpenVPX Boards
PMC/XMC Module COTS and Rugged
6U CompactPCI
Board
Full-length VMEbus Board

PCI Express Board
PCI Board
AMC Board
Figure 29
The Pentek family of board-level software radio All Pentek software radio products include multiboard
products is the most comprehensive in the industry. synchronization that facilitates the design of multichannel
Most of these products are available in several formats systems with synchronous clocking, gating and triggering.
to satisfy a wide range of requirements.
Penteks comprehensive software support includes
In addition to their commercial versions, many the ReadyFlow Board Support Package, the GateFlow
software radio products are available in ruggedized and FPGA Design Kit and high-performance factory-
conduction-cooled versions. installed IP cores that expand the features and range
of many Pentek software radio products. In addition,
Most of the software radio products include input A/D
Pentek high-speed recording systems are supported with
converters. Some of these products are software radio
SystemFlow recording software that features a graphical
receivers in that they include only DDCs. Others are
user interface.
software radio transceivers and they include DDCs as
well as DUCs with output D/A converters. These come In addition to product overviews presented in the
with independent input and output clocks. pages that follow, a complete listing of these products
with active links to their datasheets on Penteks website is
included at the end of this handbook.
18
Products
Multichannel TTransceivers
ransceivers with Vir tex-4 FPGAs
Virtex-4
Model 7142 PMC/XMC Model 724

7142 2 6U cPCI Model 734
7242 73422 3U cPCI Model 7642 PCI
7642
Model 7
77 ull-length PCIe Model 7
742 FFull-length 842 Half-length PCIe Model 534
78 2 3U VPX
342
Sample
Clock In
RF In RF In RF In RF In RF Out
TIMING BUS XTL

LVDS Clock A GENERATOR A OSC A RF RF RF RF RF
XFORMR XFORMR XFORMR XFORMR XFORMR
LVDS Sync A
Clock/Sync/Gate
LVDS Gate A SYNC Bus A 16-bit D/A
LTC2255 LTC2255 LTC2255 LTC2255
TTL Gate/ INTERRUPTS 125MHz 125MHz 125MHz 125MHz DAC5686
Trigger & CONTROL Clock/Sync/Gate 14-bit A/D 14-bit A/D 14-bit A/D 14-bit A/D
DIGITAL
Bus B
TTL Sync UPCONVERTER
14 14 14 14
LVDS Gate B
32
LVDS Sync B
LVDS Clock B TIMING BUS XTL VIRTEX-4 FPGA

GENERATOR B OSC B XC4VSX55
DSP Channelizer Digital Delay Demodulation Decoding Control etc.
To All Control/
Sections Status LOCAL HI-SPEED
32 32 32 64 32 32 32
DDR 2 DDR 2 DDR 2 BUS BUSES
SDRAM SDRAM SDRAM VIRTEX-4 FPGA
256 MB 256 MB 256 MB XC4VFX60 or XC4VFX100
Model 7142 PCI 2.2 SERIAL
PMC/XMC INTERFACE INTERFACE
PCI BUS
64
(64 Bits / 66 MHz)
P15 XMC P4 PMC

VITA 42.0 FPGA I/O
(Option 104)
Figure 30
The Model 7142 is a Multichannel PMC/XMC A 9-channel DMA controller and 64 bit / 66 MHz PCI
module. It includes four 125 MHz 14-bit A/D convert- interface assures efficient transfers to and from the module.
ers and one upconverter with a 500 MHz 16-bit D/A
A high-performance 160 MHz IP core wideband digital
converter to support wideband receive and transmit
downconverter may be factory-installed in the first FPGA.
communication channels.
Two 4X switched serial ports, implemented with the
Two Xilinx Virtex-4 FPGAs are included: an
Xilinx Rocket I/O interfaces, connect the second FPGA
XC4VSX55 or LX100 and an XC4VFX60 or FX100.
to the XMC connector with two 2.5 GB/sec data links
The first FPGA is used for control and signal processing
to the carrier board.
functions, while the second one is used for implement-
ing board interface functions including the XMC interface. A dual bus system timing generator allows separate
clocks, gates and synchronization signals for the A/D
It also features 768 MB of SDRAM for implementing
and D/A converters. It also supports large, multichannel
up to 2.0 sec of transient capture or digital delay memory
applications where the relative phases must be preserved.
for signal intelligence tracking applications at 125 MHz.
Versions of the 7142 are also available as a PCIe full-
A 16 MB flash memory supports the boot code for
length board (Models 7742 and 7742D dual density),
the two on-board IBM 405 PowerPC microcontroller
PCIe half-length board (Model 7842), 3U VPX (Model
cores within the FPGA.
5342), PCI board (Model 7642), 6U cPCI (Models 7242
and 7242D dual density), and 3U cPCI (Model 7342).
19
Products
Transceivers with FFour

our Multiband DDCs and Interpolation FFilter
ilter Installed Cores
Model 7142-428 PMC/XMC Model 724

7142-428 2-428 6U cPCI Model 734
7242-428 2-428 3U cPCI
7342-428
Model 7642-428 PCI Model 7742-428 FFull-length
ull-length PCIe
Model 7742-428 Half-length PCIe Model 534
Half-length 2-428 3U VPX
342-428
RF LTC2255
AD6645
CH A A/D A 256 MB DDR
125
105 MHz
RF In XFORMR A/D B SDRAM
14-bit A/D
A/D C MEMORY
256 MB DDR
A/D D CONTROL &
LTC2255 SDRAM
RF DATA ROUTING
CH B
125 MHz A/D A D/A
RF In XFORMR 256 MB DDR
14-bit A/D A/D B DIGITAL DIGITAL
M SDRAM
DOWNCONVERTR A DOWNCONVERTR A
A/D C U
STAGE 1 STAGE 2
A/D D X
RF LTC2255 DECIMATION: 2 256 DECIMATION: 1 256
CH C
125 MHz
RF In XFORMR A/D A MEM W
14-bit A/D
A/D B DIGITAL DIGITAL FIFO
M
DOWNCONVERTR B DOWNCONVERTR B
A/D C U MEM W
LTC2255 STAGE 1 STAGE 2
RF A/D D X FIFO
CH D DECIMATION: 2 256 DECIMATION: 1 256
125 MHz A/D A PCI BUS
RF In XFORMR A/D A
14-bit A/D A/D A DDC A MUX 64 bit /
FIFO
DIGITAL DIGITAL A/D B 66 MHz
A/D B M
DOWNCONVERTR C DOWNCONVERTR
. C A/D B
A/D C U DDC B MUX
STAGE 1 STAGE 2 FIFO
A/D D X A/D C
DECIMATION: 2 256 DECIMATION: 1 256
Sample A/D C PCI 2.2
XTAL DDC C MUX
Clock In A/D A FIFO INTERFACE
CLOCK & OSC A A/D D
A/D B DIGITAL DIGITAL A/D D
SYNC M MUX
Clock/Sync DOWNCONVERTR D DOWNCONVERTR D DDC D
A/D C U FIFO
Bus GENERATOR XTAL STAGE 1 STAGE 2
A/D D X
OSC B DECIMATION: 2 256 DECIMATION: 1 256
DIGITAL DOWNCONVERTER CORE
16-bit
500 MHZ
16-bit
D/A DAC 5686 MEMORY
RF CIC CFIR
RF Out 500 MHZ DIGITAL MUX D/A FIFO D/A
XFORMR FILTER FILTER
D/A UPCONVERTER FIFO
INTERPOLATION CORE XC4VSX55
Figure 31
The Pentek IP Core 428 includes four high- Four identical Core 428 DDCs are factory installed
performance multiband DDCs and an interpolation in the 7142-428 FPGA. An input multiplexer allows
filter. Factory-installed in the Model 7142 FPGA, any DDC to independently select any of the four A/D
they add DDCs to the Model 7142 and extend the sources. The overal decimation range from 2 to 65,536,
range of its DAC5686 DUC. programmable in steps of 1, provides output bandwidths
from 50 MHz down to 1.52 kHz for an A/D sampling
The Core 428 downconverter translates any frequency
rate of 125 MHz and assuming an 80% filter.
band within the input bandwidth range down to zero
frequency. The DDCs consist of two cascaded decimat- The Core 428 interpolation filter increases the sampling
ing FIR filters. The decimation of each DDC can be set rate of real or complex baseband signals by a factor of 16 to
independently. After each filter stage is a post filter gain 2048, programmable in steps of 4, and relieves the host
stage. This gain may be used to amplify small signals processor from performing upsampling tasks. The interpola-
after out-of-band signals have been filtered out. tion filter can be used in series with the DUCs built-in
interpolation, for a maximum interpolation of 32,768.
The NCO provides over 108 dB spurious-free
dynamic range (SFDR). The FIR filter is capable of Versions of the 7142-428 are also available as a PCIe
storing and utilizing two independent sets of 18-bit full-length board (Models 7742-428 and 7742D-428 dual
coefficients. These coefficients are user-programmable by density), PCIe half-length board (Model 7842-428), PCI
using RAM structures within the FPGA. NCO tuning board (Model 7642-428), 6U cPCI (Models 7242-428 and
frequency, decimation and filter coefficients can be 7242D-428 dual density), 3U cPCI (Model 7342-428),
changed dynamically. and 3U VPX (Model 5342-428).
20
Products
Quad 200 MHz 16-bit A/D with Vir tex-5 FPGAs

Virtex-5
Model 7150 PMC/XMC Model 7250 6U cPCI Model 7350 3U cPCI Model 7650 PCI
Model 7750 FFull-length
ull-length PCIe Model 7850 Half-length PCIe Model 5350 3U VPX
RF In RF In RF In RF In
RF RF RF RF
Sample Clock In XFORMR XFORMR XFORMR XFORMR
PPS In TIMING BUS
GENERATOR Clock/Sync/
Gate/PPS Bus ADS5485 ADS5485 ADS5485 ADS5485
TTL Gate / Trigger Clock/ Sync / 200 MHz 200 MHz 200 MHz 200 MHz
TTL Sync / PPS Gate / PPS 16-bit A/D 16-bit A/D 16-bit A/D 16-bit A/D
Sample Clk
Sync Clk
16 16 16 16
Gate A
Gate B
Sync XTL
PPS OSC
Control/ PROCESSING FPGA
To All Status VIRTEX 5: LX50T, SX50T, SX95T, LX155T or FX100T
Sections
LOCAL BUS GTP GTP GTP
32 32 32 16
64 x4 x4 x4
DDR 2 DDR 2 DDR 2
FLASH LOCAL BUS GTP
SDRAM SDRAM SDRAM
32 MB
512 MB 512 MB 512 MB
INTERFACE FPGA
x8
VIRTEX-5: LX30T, SX50T or FX70T
Model 7150 PCI-X LVDS GTP

P15 XMC
PMC/XMC 64 x4
VITA 42.0
(Serial RapidIO,
P4 PMC PCI-Express,
PCI-X BUS
FPGA I/O etc.)
(32 or 64 Bits / 33, 66, 100 or 133 MHz)
Figure 32
Model 7150 is a quad, high-speed data converter capture mode with pre- and post-triggering. All memory
suitable for connection as the HF or IF input of a banks can be easily accessed through the PCI-X interface.
communications system. It features four 200 MHz,
A 9-channel DMA controller and 64 bit / 100 MHz
16-bit A/Ds supported by an array of data processing
PCI-X interface assures efficient transfers to and from the
and transport resources idealy matched to the require-
module.
ments of high-performance systems. Model 7150 uses
the popular PMC format and supports the emerging Two 4X switched serial ports, implemented with the
VITA 42 XMC standard for switched fabric interfaces. Xilinx Rocket I/O interfaces, connect the FPGA to the
XMC connector with two 2.5 GB/sec data links to the
The Model 7150 architecture includes two Virtex-5
carrier board.
FPGAs. The first FPGA is used primarily for signal
processing while the second one is dedicated to board A dual bus system timing generator allows separate
interfaces. All of the boards data and control paths are clocks, gates and synchronization signals for the A/D
accessible by the FPGAs, enabling factory installed converters. It also supports large, multichannel applica-
functions including data multiplexing, channel selection, data tions where the relative phases must be preserved.
packing, gating, triggering and SDRAM memory control.
Three independent 512 MB banks of DDR2 length board (Models 7750 and 7750D dual density),
SDRAM are available to the signal processing FPGA. PCIe half-length board (Model 7850), PCI board (Model
Built-in memory functions include an A/D data transient 7650), 6U cPCI (Models 7250 and 7250D dual density),
3U cPCI (Model 7350), and 3U VPX (Model 5350).
21
Products
256- Channel DDC Installed Core with Quad 200 MHz, 16-bit A/D
256-Channel
Model 7151 PMC Model 7251 6U cPCI Model 7351 3U cPCI Model 7651 PCI
RF ADS5485
AD6645
CH A
200
105 MHz
RF In XFORMR
16-bit
14-bit A/D
ADS5485
CH B RF
200 MHz
RF In XFORMR
16-bit A/D
RF ADS5485
CH C
200 MHz A/D A
RF In XFORMR
16-bit A/D A/D B DIGITAL A/D A
M MUX
DOWNCONVERTR I&Q DDC BANK 1 FIFO
A/D C U
BANK 1: CH 1 - 64
A/D D X
RF ADS5485 DECIMATION: 128 - 1024
CH D
200 MHz PCI BUS
RF In XFORMR A/D A
16-bit A/D A/D B 64 bit /
A/D B DIGITAL A/D B
M MUX 66 MHz
DOWNCONVERTR I&Q DDC BANK 2 FIFO
A/D C U .
BANK 2: CH 65 - 128
A/D D X
DECIMATION: 128 - 1024
PCI 2.2
A/D A
A/D C INTERFACE
Sample A/D B DIGITAL A/D C
M MUX
Clock In DOWNCONVERTR I&Q DDC BANK 3 FIFO
A/D C U
TIMING BUS BANK 3: CH 129 - 192
A/D D X
GENERATOR DECIMATION: 128 - 1024
PPS In
A/D A
Clock / Gate / DIGITAL A/D D
A/D B M A/D D
TTL In Sync / PPS DOWNCONVERTR I&Q DDC BANK 4 MUX
A/D C U FIFO
BANK 4: CH 193 - 256
A/D D X
DECIMATION: 128 - 1024
Sync Bus
XTAL DIGITAL DOWNCONVERTER CORE
OSC
XC5VSX95T
Figure 33
The Model 7151 PMC module is a 4-channel high- supporting as many as four different output bandwidths
speed digitizer with a factory-installed 256-channel for the board.
DDC core. The front end of the module accepts four
The decimating filter for each DDC bank accepts a
RF inputs and transformer-couples them into four
unique set of user-supplied 18-bit coefficients. The 80%
16-bit A/D converters running at 200 MHz. The
default filters deliver an output bandwidth of 0.8*s/N,
digitized output signals pass to a Virtex-5 FPGA for
where N is the decimation setting. The rejection of
routing, formatting and DDC signal processing.
adjacent-band components within the 80% output band-
The Model 7151 employs an advanced FPGA-based width is better than 100 dB.
digital downconverter engine consisting of four identical
Each DDC delivers a complex output stream
64-channel DDC banks. Four independently controllable
consisting of 24-bit I + 24-bit Q samples. Any number
input multiplexers select one of the four A/Ds as the
of channels can be enabled within each bank, selectable
input source for each DDC bank. Each of the 256 DDCs
from 0 to 64. Each bank includes an output sample
has an independent 32-bit tuning frequency setting.
interleaver that delivers a channel-multiplexed stream for
All of the 64 channels within a bank share a common all enabled channels within the bank.
decimation setting that can range from 128 to 1024,
Versions of the 7151 are also available as a PCIe
programmable in steps of 64. For example, with a sampling
full-length board (Models 7751 and 7751D dual density),
rate of 200 MHz, the available output bandwidths
PCIe half-length board (Model 7851), PCI board (Model
range from 156.25 kHz to 1.25 MHz. Each 64-channel
7651), 6U cPCI (Models 7251 and 7251D dual density),
bank can have its own unique decimation setting
3U cPCI (Model 7351), and 3U VPX (Model 5351).
22
Products
32- Channel DDC Installed Core with Quad 200 MHz, 16-bit A/D
32-Channel
RF ADS5485
AD6645
CH A
200
105 MHz
RF In XFORMR
16-bit
14-bit A/D
RF ADS5485
CH B
200 MHz
RF In XFORMR DIGITAL DOWNCONVERTER CORE 8x4
16-bit A/D SUM
CHANNEL
A/D A SUMMATION A/D B
A/D B DIGITAL MUX A/D A
ADS5485 M
CH C RF DOWNCONVERTR I & Q BANK 1 FIFO
200 MHz A/D C U
RF In XFORMR BANK 1: CH 1 - 8
16-bit A/D A/D D X
DEC: 16 - 8192 POWER
METER &
THRESHOLD
RF ADS5485 A/D A DETECT
CH D
200 MHz DIGITAL A/D B PCI BUS
RF In XFORMR A/D B M A/D B
16-bit A/D DOWNCONVERTR I & Q BANK 2 MUX 64 bit /
A/D C U FIFO
BANK 2: CH 9 - 16 66 MHz
A/D D X
DEC: 16 - 8192 POWER.
METER &
THRESHOLD PCI 2.2
A/D A DETECT
A/D C INTERFACE
M
Clock In DOWNCONVERTR I & Q BANK 3 MUX FIFO
A/D C U
TIMING BUS BANK 3: CH 17 - 24
A/D D X
GENERATOR DEC: 16 - 8192 POWER
PPS In METER &
THRESHOLD
Clock / Gate /
A/D A DETECT
TTL In Sync / PPS DIGITAL A/D D
A/D B M A/D D
DOWNCONVERTR I & Q BANK 4 MUX FIFO
A/D C U
BANK 4: CH 25 - 32
A/D D X POWER
Sync Bus DEC: 16 - 8192
METER &
XTAL THRESHOLD
OSC DETECT
XC5VSX95T
Figure 34
The Model 7152 PMC module is a 4-channel high- have its own unique decimation setting supporting as
speed digitizer with a factory-installed 32-channel DDC many as four different output bandwidths for the board.
core. The front end of the module accepts four RF
The decimating filter for each DDC bank accepts a unique
inputs and transformer-couples them into four
set of user-supplied 18-bit coefficients. The 80% default filters
16-bit A/D converters running at 200 MHz. The
deliver an output bandwidth of 0.8*s/N, where N is the
digitized output signals pass to a Virtex-5 FPGA for
decimation setting. The rejection of adjacent-band components
routing, formatting and DDC signal processing.
within the 80% output band-width is better than 100 dB.
The Model 7152 employs an advanced FPGA-based
Each DDC delivers a complex output stream consist-
digital downconverter engine consisting of four identical
ing of 24-bit I + 24-bit Q samples. Any number of channels
8-channel DDC banks. Four independently controllable
can be enabled within each bank, selectable from 0 to 8.
input multiplexers select one of the four A/Ds as the
Each bank includes an output sample interleaver that
input source for each DDC bank. Each of the 32 DDCs
delivers a channel-multiplexed stream for all enabled
has an independent 32-bit tuning frequency setting.
channels within the bank. Gain and phase control, power
All of the 8 channels within a bank share a common meters and threshold detectors are included.
decimation setting that can range from 16 to 8192,
programmable in steps of 8. For example, with a sampling
length board (Models 7752 and 7752D dual density), PCIe
rate of 200 MHz, the available output bandwidths range
half-length board (Model 7852), PCI board (Model 7652),
from 19.53 kHz to 10.0 MHz. Each 8-channel bank can
6U cPCI (Models 7252 and 7252D dual density), 3U cPCI
(Model 7352), and 3U VPX (Model 5352).
23
Products
4- Channel DDC and Beamformer Installed Core with four 200 MHz, 16-bit A/Ds
4-Channel
RF ADS5485
AD6645
CH A
200
105 MHz
RF In XFORMR
16-bit
14-bit A/D
RF ADS5485
CH B DIGITAL DOWNCONVERTER CORE
200 MHz
RF In XFORMR 4
16-bit A/D SUM
CHANNEL
A/D A SUMMATION A/D B
A/D B DIGITAL MUX A/D A
ADS5485 M
CH C RF DOWNCONVERTR I & Q DDC 1 FIFO
200 MHz A/D C U
RF In XFORMR CH 1
16-bit A/D A/D D X
DEC: 2 - 256 POWER
METER &
THRESHOLD
RF ADS5485 A/D A DETECT
CH D
200 MHz DIGITAL A/D B PCI BUS
RF In XFORMR A/D B M A/D B
16-bit A/D DOWNCONVERTR I & Q DDC 2 MUX 64 bit /
A/D C U FIFO
CH 2 66 MHz
A/D D X
DEC: 2 - 256 POWER.
METER &
THRESHOLD PCI 2.2
A/D A DETECT
A/D C INTERFACE
M
Clock In DOWNCONVERTR I & Q DDC 3 MUX FIFO
A/D C U
TIMING BUS CH 3
A/D D X
GENERATOR DEC: 2 - 256 POWER
PPS In METER &
THRESHOLD
Clock / Gate /
A/D A DETECT
TTL In Sync / PPS DIGITAL A/D D
A/D B M A/D D
DOWNCONVERTR I & Q DDC 4 MUX FIFO
A/D C U
CH 4
A/D D X POWER
Sync Bus DEC: 2 - 256
METER &
XTAL THRESHOLD
OSC DETECT
XC5VSX50T
Figure 35
Model 7153 is a 4-channel, high-speed software radio 0.8*s/N, where N is the decimation setting. The
module designed for processing baseband RF or IF signals. rejection of adjacent-band components within the 80%
It features four 200 MHz 16-bit A/Ds supported by a high- output band-width is better than 100 dB.
performance 4-channel DDC (digital downconverter)
In addition to the DDCs, the 7153 features a com-
installed core and a complete set of beamforming functions.
plete beamforming subsystem. Each channel contains
With built-in multiboard synchronization and an Aurora
programable I & Q phase and gain adjustments followed
gigabit serial interface, it provides everything needed for
by a power meter that continuously measures the individual
implementing multichannel beamforming systems.
average power output. The time constant of the averaging
The Model 7153 employs an advanced FPGA-based interval for each meter is programmable up to 8 ksamples.
DDC engine consisting of four identical multiband banks. The power meters present average power measurements for
Four independently controllable input multiplexers select each channel in easy-to-read registers. Each channel also
one of the four A/Ds as the input source for each DDC includes a threshold detector that sends an interrupt to
bank. Each of the 4 DDCs has an independent 32-bit the processor if the average power level of any DDC
tuning frequency setting. falls below or exceeds a programmable threshold.
All four DDCs have a decimation setting that can Versions of the 7153 are also available as a PCIe full-
range from 2 to 256, programmable independenly in length board (Models 7753 and 7753D dual density),
steps of 1. The decimating filter for each DDC bank PCIe half-length board (Model 7853), PCI board (Model
accepts a unique set of user-supplied 18-bit coefficients. 7653), 6U cPCI (Models 7253 and 7253D dual density),
The 80% default filters deliver an output bandwidth of 3U cPCI (Model 7353), and 3U VPX (Model 5353).
24
Products
Dual SDR TTransceivers

ransceivers with 400 MHz A/D, 800 MHz D/A, and Vir tex-5 FPGAs
Virtex-5
RF In RF In RF Out RF Out
RF RF RF RF
XFORMR XFORMR XFORMR XFORMR
Sample Clock In
A/D Clock Bus ADS5474 ADS5474
800 MHz 800 MHz
PPS In TIMING BUS 400 MHz 400 MHz
16-bit D/A 16-bit D/A
GENERATOR 14-bit A/D 14-bit A/D
D/A Clock Bus
TTL Gate / Trig DIGITAL UPCONVERTER
Clock/ Sync /
TTL Sync / PPS Gate / PPS
Sample Clk 14 14
Sync Clk 32
Gate A Control/
Gate B Status
Sync PROCESSING FPGA
PPS VCXO To All VIRTEX 5: LX50T, SX50T, SX95T or FX100T
Sections LVDS GTP GTP GTP
Timing Bus
32 32 16
64 4X 4X 4X
DDR 2 DDR 2
FLASH
SDRAM SDRAM GTP
32 MB
512 MB 512 MB
INTERFACE FPGA
Model 7156 VIRTEX-5: LX30T, SX50T or FX70T
PMC/XMC LVDS PCI-X GTP
32 32 64 4X
P4 PMC PCI-X BUS P15 XMC
FPGA (64 Bits VITA 42.x
I/O 133 MHz) (PCIe, etc.)
Figure 36
Model 7156 is a dual high-speed data converter A high-performance IP core wideband DDC may be
suitable for connection as the HF or IF input of a factory-installed in the processing FPGA.
communications system. It features two 400 MHz 14-bit
A 5-channel DMA controller and 64 bit/100 MHz PCI-X
A/Ds, a DUC with two 800 MHz 16-bit D/As, and
interface assures efficient transfers to and from the module.
two Virtex-5 FPGAs. Model 7156 uses the popular
PMC format and supports the VITA 42 XMC standard Two 4X switched serial ports implemented with the
for switched fabric interfaces. Xilinx Rocket I/O interfaces, connect the FPGA to the
carrier board.
processing while the second one is dedicated to board A dual bus system timing generator allows for
interfaces. All of the boards data and control paths are sample clock synchronization to an external system
accessible by the FPGAs, enabling factory installed reference. It also supports large, multichannel appli-
functions such as data multiplexing, channel selection, data cations where the relative phases must be preserved.
packing, gating, triggering and SDRAM memory control.
Two independent 512 MB banks of DDR2 SDRAM length board (Models 7756 and 7756D dual density),
are available to the signal processing FPGA. Built-in PCIe half-length board (Model 7856), PCI board
memory functions include an A/D data transient capture (Model 7656), 6U cPCI (Models 7256 and 7256D dual
mode with pre- and post-triggering. All memory banks density), 3U cPCI (Model 7356), and 3U VPX (Model
can be easily accessed through the PCI-X interface. 5356). All these products have similar features.
25
Products
Dual SDR TTransceivers

ransceivers with 500 MHz A/D, 800 MHz D/A, and Vir tex-5 FPGAs
Virtex-5
RF RF RF RF
Sample Clock /
Reference Clock In A/D Clock Bus ADS5463 ADS5463
800 MHz 800 MHz
PPS In TIMING BUS 500 MHz 500 MHz 16-bit D/A 16-bit D/A
GENERATOR 12-bit A/D 12-bit A/D
D/A Clock Bus
TTL Gate / Trig DIGITAL UPCONVERTER
Clock/ Sync /
Sample Clk 14 14
Sync Clk 32
Gate A Control/
Gate B Status
Sync PROCESSING FPGA
PPS VCXO To All VIRTEX 5: LX50T, LX155T, SX50T, SX95T or FX100T
Sections LVDS GTP GTP GTP
Timing Bus
32 32 16
64 4X 4X 4X
DDR 2 DDR 2
FLASH
SDRAM SDRAM GTP
32 MB
256 MB 256 MB
INTERFACE FPGA
Model 7158 VIRTEX-5: LX30T, SX50T or FX70T
PMC/XMC GTP
LVDS PCI-X
32 32 64 4X
P4 PMC PCI-X BUS P15 XMC
FPGA (64 Bits VITA 42.x
I/O 100 MHz) (PCIe, etc.)
Figure 37
Model 7158 is a dual high-speed data converter A 5-channel DMA controller and 64 bit / 100 MHz
suitable for connection as the HF or IF input of a PCI-X interface assures efficient transfers to and from the
communications system. It features two 500 MHz 12-bit module.
A/Ds, a digital upconverter with two 800 MHz 16-bit
Two 4X switched serial ports implemented with the
D/As, and two Virtex-5 FPGAs. Model 7158 uses the
Xilinx Rocket I/O interfaces, connect the FPGA to the
popular PMC format and supports the VITA 42 XMC
standard for switched fabric interfaces.
carrier board.
A dual bus system timing generator allows for
sample clock synchronization to an external system
processing while the second one is dedicated to board
reference. It also supports large, multichannel appli-
interfaces. All of the boards data and control paths are
cations where the relative phases must be preserved.
accessible by the FPGAs, enabling factory installed
functions such as data multiplexing, channel selection, data Versions of the 7158 are also available as a PCIe full-
packing, gating, triggering and SDRAM memory control. length board (Models 7758 and 7758D dual density),
PCIe half-length board (Model 7858), PCI board
Two independent 256 MB banks of DDR2 SDRAM
(Model 7658), 6U cPCI (Models 7258 and 7258D dual
are available to the signal processing FPGA. Built-in
density), 3U cPCI (Model 7358), and 3U VPX (Model
memory functions include an A/D data transient capture
5358). All these products have similar features.
mode with pre- and post-triggering. All memory banks
can be easily accessed through the PCI-X interface.
26
Products
3- Channel 200 MHz A/D, DUC, 2-

3-Channel Channel 800 MHz D/A, Vir
2-Channel tex-6 FPGA
Virtex-6
Model 71620 XMC Model 78620 PCIe Model 53620 3U VPX Model 56620 AMC
Model 72620 6U cPCI Model 73620 3U cPCI Model 74620 6U cPCI
RF In RF In RF In RF Out RF Out
RF RF RF RF RF
Sample Clk /
Reference Clk In A/D
TIMING BUS Clock/Sync
GENERATOR Bus 200 MHz 200 MHz 200 MHz 800 MHz 800 MHz
16-BIT A/D 16-BIT A/D 16-BIT A/D 16-BIT D/A 16-BIT D/A
TTL Gate / Trig Clock / Sync /
DIGITAL
UPCONVERTER
D/A
Sample Clk Clock/Sync 16 16 16
Reset Bus 32
Gate A/D
Gate D/A
Sync / PPS A/D
Sync / PPS D/A VIRTEX-6 FPGA
VCXO
Timing Bus LX130T, LX240T or SX315T
GTX GTX GTX LVDS
16 16 16 16 16 16 16 16 16
8X 4X 4X 40
QDRII+ QDRII+ QDRII+ QDRII+ Config
SRAM SRAM SRAM SRAM FLASH
Model 71620 8 MB 8 MB 8 MB 8 MB 64 MB
XMC QDRII+ option 150 QDRII+ option 160 x8 PCIe Gigabit FPGA
DDR3 option 155 DDR3 option 165 Serial I/O GPIO
(option 105) (option 104)
DDR3 DDR3 DDR3 DDR3
SDRAM SDRAM SDRAM SDRAM
512 MB 512 MB 512 MB 512 MB P15 P16 P14
XMC XMC PMC
Memory Banks 1 & 2 Memory Banks 3 & 4
Figure 38
Model 71620 is a member of the Cobalt family of Each member of the Cobalt family is delivered
high performance XMC modules based on the Xilinx with factory-installed applications ideally matched to the
Virtex-6 FPGA. A multichannel, high-speed data boards analog interfaces. The 71620 factory-installed
converter, it is suitable for connection to HF or IF ports functions include an A/D acquisition and a D/A waveform
of a communications or radar system. Its built-in data playback IP module. In addition, IP modules for either
capture and playback features offer an ideal turnkey solution. DDR3 or QDRII+ memories, a controller for all data
It includes three 200 MHz, 16-bit A/Ds, a DUC with clocking and synchronization functions, a test signal
two 800 MHz, 16-bit D/As and four banks of memory. generator and a PCIe interface complete the factory-
In addition to supporting PCI Express Gen. 2 as a installed functions.
native interface, the Model 71620 includes general
Multiple 71620s can be driven from the LVPECL
purpose and gigabit serial connectors for application-
bus master, supporting synchronous sampling and sync
specific I/O .
functions across all connected modules. The architecture
The Pentek Cobalt architecture features a Virtex-6 supports up to four memory banks which can be configured
FPGA. All of the boards data and control paths are acces- with all QDRII+ SRAM, DDR3 SDRAM, or as combina-
sible by the FPGA, enabling factory-installed functions tion of two banks of each type of memory.
including data multiplexing, channel selection, data packing,
Versions of the 71620 are also available as a PCIe half-
gating, triggering and memory control. The Cobalt architec-
length board (Model 78620), 3U VPX (Model 53620), AMC
ture organizes the FPGA as a container for data processing
(Model 56620), 6U cPCI (Models 72620 and 74620
applications where each function exists as an intellec-
with dual density), and 3U cPCI (Model 73620).
tual property (IP) module.
27
Products

Virtex-7
RF In RF In RF In RF Out RF Out
RF RF RF RF RF
Sample Clk /
TIMING BUS Clock/Sync
GENERATOR Bus 200 MHz 200 MHz 200 MHz 800 MHz 800 MHz
16-BIT A/D 16-BIT A/D 16-BIT A/D 16-BIT D/A 16-BIT D/A
DIGITAL
UPCONVERTER
D/A
Sample Clk Clock/Sync 16 16 16
Reset Bus 32
Gate A/D
Gate D/A
Sync / PPS A/D
Sync / PPS D/A VIRTEX-7 FPGA
VCXO
Timing Bus VX330T or VX690T
GTX GTX GTX LVDS
CONFIG FPGA 32 32 32 32
FLASH PCIe 4X 4X 48
Config Gen. 3 x8
1 GB
Model 71720 Bus DDR3 DDR3 DDR3 DDR3
XMC GATEXPRESS PCIe 1 GB 1 GB 1 GB 1 GB
CONFIGURATION
MANAGER
Gigabit FPGA
PCIe Serial I/O GPIO
Gen. 3 x8 (option 105) (option 104)
P15 P16 P14
XMC XMC PMC
Figure 39
Model 71720 is a member of the Onyx family of Each member of the Onyx family is delivered with
high-performance XMC modules based on the Xilinx factory-installed applications ideally matched to the boards
Virtex-7 FPGA. A multichannel, high-speed data converter, analog interfaces. The 71720 factory-installed functions
it is suitable for connection to HF or IF ports of a include three A/D acquisition and a D/A waveform
communications or radar system. Its built-in data playback IP modules for simplifying data capture and
capture and playback features offer an ideal turnkey data transfer. IP modules for DDR3 SDRAM memories, a
solution. It includes three 200 MHz, 16-bit A/Ds, a DUC controller for all data clocking and synchronization func-
with two 800 MHz, 16-bit D/As and four banks of tions, a test signal generator, and a PCIe interface
memory. In addition to supporting PCI Express Gen. 3 as complete the factory-installed functions.
a native interface, the Model 71720 includes general-
purpose and gigabit-serial connectors for application-
specific I/O.
functions across all connected modules.
The Pentek Onyx architecture features a Virtex-7
FPGA. All of the boards data and control paths are
length board (Model 78720), 3U VPX (Model 53720),
accessible by the FPGA, enabling factory-installed
AMC (Model 56720), 6U cPCI (Models 72720 and
functions including data multiplexing, channel selection,
74720 with dual density), and 3U cPCI (Model 73720).
data packing, gating, triggering and memory control. The
Cobalt architecture organizes the FPGA as a container for GateXpressTM is a sophisticated configuration
data processing applications where each function exists manager for loading and reloading the Virtex-7 FPGA.
as an intellectual property (IP) module. More information is available in the next page.
28
Products
GateXpress for FPGA-PCIe Configuration Management

FPGA-PCIe
ONYX: VIRTEX-7 FPGA

VX330T or VX690T
GTX GTX GTX LVDS
FPGA 32 32 32 32
Config 8X 4X 4X 40 Cobalt
Bus 48 Onyx
DDR3 DDR3 DDR3 DDR3
CONFIG GATEXPRESS PCIe SDRAM SDRAM SDRAM SDRAM
FLASH CONFIGURATION Option Option 1 GB 1 GB 1 GB 1 GB
1 GB MANAGER -105 -104
Serial FPGA
I/O GPIO
PCIe
P15 P16 P14
XMC XMC PMC
Figure 40
The Onyx architecture includes GateXpress, a sophisti- The second option is for applications where the
cated FPGA-PCIe configuration manager for loading and FPGA image must be loaded directly through the PCIe
reloading the FPGA. At power up, GateXpress immediately interface. This is important in security situations where
presents a PCIe target for the host computer to discover, there can be no latent user image left in nonvolatile
effectively giving the FPGA time to load from FLASH. memory when power is removed. In applications where
This is especially important for larger FPGAs where the the FPGA IP may need to change many times during
loading times can exceed the PCIe discovery window, the course of a mission, images can be stored on the host
typically 100 msec on most PCs. computer and loaded through PCIe as needed.
The boards configuration FLASH can hold four The third option, typically used during development,
FPGA images. Images can be factory-installed IP or allows the user to directly load the FPGA through JTAG
custom IP created by the user, and programmed into the using Xilinx iMPACT.
FLASH via JTAG using Xilinx iMPACT or through the
In all three FPGA loading scenarios, GateXpress
boards PCIe interface. At power up the user can choose
handles the hardware negotiation simplifying and stream-
which image will load based on a hardware switch setting.
lining the loading task. In addition, GateXpress preserves
Once booted, GateXpress allows the user three the PCIe configuration space allowing dynamic FPGA
options for dynamically reconfiguring the FPGA with a reconfiguration without needing to reset the host com-
new IP image. The first is the option to load an alternate puter to rediscover the board. After the reload, the
image from FLASH through software control. The user host simply continues to see the board with the expected
selects the desired image and issues a reload command. device ID.
29
Products

3-Channel Channel 800 MHz D/A, Installed IP Cores, Vir
Virtex-6
from from from to
A/D Ch 1 A/D Ch 2 A/D Ch 3 D/A
D/A loopback
TEST
SIGNAL
INPUT MULTIPLEXER GENERATOR
DDC DDC DDC INTERPOLATOR

DEC: 2 TO 65536 DEC: 2 TO 65536 DEC: 2 TO 65536 2 TO 65536
POWER POWER POWER IP CORE
METER & METER & METER &
THRESHOLD THRESHOLD THRESHOLD DATA UNPACKING
DETECT DETECT DETECT & FLOW CONTROL
MUX
DDC CORE DDC CORE DDC CORE
DATA PACKING & DATA PACKING & DATA PACKING & MUX
FLOW CONTROL FLOW CONTROL FLOW CONTROL
MEMORY MEMORY MEMORY
CONTROL CONTROL CONTROL MEMORY
METADATA METADATA METADATA
GENERATOR MUX GENERATOR MUX CONTROL
to to to GENERATOR MUX
Mem Mem Mem to LINKED-LIST
Bank 1 LINKED-LIST Bank 2 LINKED-LIST Bank 3 LINKED-LIST Mem DMA ENGINE
DMA ENGINE DMA ENGINE DMA ENGINE
Bank 4 D/A
A/D A/D A/D WAVEFORM
ACQUISITION ACQUISITION ACQUISITION PLAYBACK
Model 71621 IP MODULE 1 IP MODULE 2 IP MODULE 3 IP MODULE
XMC
AURORA sum out

GIGABIT S VIRTEX-6 FPGA DATAFLOW DETAIL PCIe INTERFACE
SERIAL SUMMER
INTERFACE sum in
BEAMFORMER CORE
4X 4X 8X
to next from previous
board board PCIe
Figure 41
Model 71621 is a member of the Cobalt family of high the A/D sampling frequency. Each DDC can have its
performance XMC modules based on the Xilinx Virtex-6 own unique decimation setting, supporting as many as
FPGA. A multichannel, high-speed data converter based on three different output bandwidths for the board. Decima-
the Model 71620 described in the previous page, it includes tions can be programmed from 2 to 65,536 providing a
factory-installed IP cores to enhance the performance of the wide range to satisfy most applications.
71620 and address the requirements of many applications.
The 71621 also features a complete beamforming
The 71621 factory-installed functions include three A/D subsystem. Each DDC core contains programable I & Q
acquisition and one D/A waveform playback IP modules. phase and gain adjustments followed by a power meter
Each of the three acquisition IP modules contains a that continuously measures the individual average power
powerful, programmable DDC IP core. The waveform output. The power meters present average power measure-
playback IP module contains an interpolation IP core, ideal ments for each DDC core output in easy-to-read registers. A
for matching playback rates to the data and decimation threshold detector automatically sends an interrupt to
rates of the acquisition modules. IP modules for either the processor if the average power level of any DDC
DDR3 or QDRII+ memories, a controller for all data core falls below or exceeds a programmable threshold.
clocking and synchronization functions, a test signal
generator, an Aurora gigabit serial interface, and a PCIe
interface complete the factory-installed functions.
Each DDC has an independent 32-bit tuning 74621 with dual density), and 3U cPCI (Model 73621).
frequency setting that ranges from DC to s, where s is
30
Products
1 GHz A/D, 1 GHz D/A, Vir tex-6 FPGA

Virtex-6
Model 78630 PCIe Model 71630 XMC Model 53630 3U VPX Model 56630 XMC
RF In RF Out
RF RF
Sample Clk / XFORMR XFORMR
Reference Clk In
TTL
PPS/Gate/Sync TIMING BUS
A/D Clock/Sync Bus 1 GHz
GENERATOR
Gate In 12-BIT A/D
Sync In Clock / Sync / 1 GHz
Gate / PPS 16-BIT D/A
A/D Sync Bus D/A Clock/Sync Bus
Gate In 12
16
Sync In
D/A Sync Bus
VIRTEX-6 FPGA
LX130T, LX240T or SX315T
VCXO
LVDS GTX GTX GTX
16 16 16 16 16 16 16 16 16 Model 78630
40 8X 4X 4X
DDR3 DDR3 DDR3 DDR3 Config x8 PCIe
SDRAM SDRAM SDRAM SDRAM FLASH
512 MB 512 MB 512 MB 512 MB 64 MB
Optional Optional
Memory Banks 1 & 2 Memory Banks 3 & 4 FPGA x8 PCIe Serial
DDR3 option 155 DDR3 option 165
GPIO I/O
QDRII+ QDRII+
SRAM SRAM Dual 4X
8 MB 8 MB 68-pin Serial
Header Conn
QDRII+ option 150
x8 PCI Express
Figure 42
Model 78630 is a member of the Cobalt family of high Each member of the Cobalt family is delivered
performance PCIe boards based on the Xilinx Virtex-6 with factory-installed applications ideally matched to the
FPGA. A high-speed data converter, it is suitable for boards analog interfaces. The 78630 factory-installed
connection to HF or IF ports of a communications or radar functions include an A/D acquisition and a D/A waveform
system. Its built-in data capture and playback features offer playback IP module. In addition, IP modules for either
an ideal turnkey solution as well as a platform for develop- DDR3 or QDRII+ memories, a controller for all data
ing and deploying custom FPGA processing IP. It includes clocking and synchronization functions, a test signal
1 GHz, 12-bit A/D, 1 GHz, 16-bit D/A converters and generator and a PCIe interface complete the factory-
four banks of memory. In addition to supporting PCI installed functions.
Express Gen. 2 as a native interface, the Model 78630
includes optional general purpose and gigabit serial card
connectors for application- specific I/O protocols.
functions across all connected boards. The architecture
The Pentek Cobalt architecture features a Virtex-6 supports up to four memory banks which can be configured
FPGA. All of the boards data and control paths are acces- with all QDRII+ SRAM, DDR3 SDRAM, or as combina-
sible by the FPGA, enabling factory-installed functions tion of two banks of each type of memory.
Versions of the 78630 are also available as an XMC
module (Model 71630), 3U VPX (Model 53630), AMC
ture organizes the FPGA as a container for data process-
ing applications where each function exists as an intellec-
31
Products
1- or 2- Channel 3.6 GHz and 2- or 4-

2-Channel Channel 1.8 GHz, 12-bit A/D, Vir
Virtex-6

RF In RF In
Block Diagram, Model 72640
Model 74640 doubles all resources
except the PCI-to-PCI Bridge
RF RF
XFORMR XFORMR
Sample Clk
TTL
PPS/Gate/Sync TIMING BUS
GENERATOR 3.6 GHz (1 Channel)
A/D Clock/Sync Bus or
Gate In Clock / Sync / 1.8 GHz (2 Channel)
Reset In Gate / PPS 12-bit A/D
Ref Clk In
Ref Clk Out 12 12
Sync Bus
VIRTEX-6 FPGA
MODEL 73640
LVDS GTX
INTERFACES ONLY
32 32 32 32 16 From/To Other
VIRTEX-6 FPGA 40 4X
x4 PCIe XMC Module of
LVDS GTX DDR3 DDR3 DDR3 DDR3 Config
SDRAM SDRAM SDRAM SDRAM FLASH MODEL 74640
512 MB 512 MB 512 MB 512 MB 64 MB PCIe
to PCI
40 BRIDGE
PCIe Memory Banks 1 & 2 Memory Banks 3 & 4
Optional to PCI
FPGA I/O BRIDGE Optional PCI Model 74640 Model 73640
to PCI
(Option -104) FPGA I/O BRIDGE Dual Density Single Density
(Option -104)
J2 PCI/PCI-X BUS
32-bit, 33/66 MHz
J3 PCI/PCI-X BUS
32/64-bit, 33/66 MHz
Figure 43
Models 72640, 73640 and 74640 are members modules. In addition, IP modules for DDR3 memories,
of the Cobalt family of high performance CompactPCI controllers for all data clocking and synchronization
boards based on the Xilinx Virtex-6 FPGA. They functions, a test signal generator and a PCIe interface
consist of one or two Model 71640 XMC modules complete the factory-installed functions.
mounted on a cPCI carrier board. These models include one
The front end accepts analog HF or IF inputs on
or two 3.6 GHz, 12-bit A/D converters and four or eight
a pair of front panel SSMC connectors with transformer
banks of memory.
coupling into a Texas Instruments ADC12D1800 12-bit
The Pentek Cobalt architecture features a Virtex-6 A/D. The converter operates in single-channel inter-
FPGA. All of the boards data and control paths are leaved mode with a sampling rate of 3.6 GHz and an
accessible by the FPGA, enabling factory-installed input bandwidth of 1.75 GHz; or, in dual-channel mode
functions including data multiplexing, channel selec- with a sampling rate of 1.8 GHz and input bandwidth of
tion, data packing, gating, triggering and memory control. 2.8 GHz. The ADC12D1800 provides a programmable
The Cobalt architecture organizes the FPGA as a container 15-bit gain adjustment allowing these models to have a full
for data processing applications where each function exists scale input range of +2 dBm to +4 dBm.
as an intellectual property (IP) module.
Model 72640 is a 6U cPCI board, while Model
Each member of the Cobalt family is delivered 73640 is a 3U cPCI board; Model 74640 is a dual
with factory-installed applications ideally matched to the density 6U cPCI board. Also available is an XMC module
boards analog interfaces. The factory-installed functions of (Model 71640), PCIe half-length board (Model 78640), 3U
these models include one or two A/D acquisition IP VPX (Model 53640), and AMC (Model 56640).
32
Products
1- or 2- Channel 3.6 GHz and 2- or 4-

2-Channel Channel 1.8 GHz, 12-bit A/D, W
4-Channel ideband DDC, Vir
Wideband tex-6 FPGA
Virtex-6
Model 56641 AMC Model 71641 XMC Model 78641 PCIe Model 53641 3U VPX
from from
A/D A/D
VIRTEX-6 FPGA DATAFLOW DETAIL

*Two channel mode shown. TEST
Programmable decimation of 8, 16 or 32 INPUT MULTIPLEXER SIGNAL
available in one channel mode. GENERATOR
DDC DDC
*DEC: 4, 8 or 16 *DEC: 4, 8 or 16
POWER POWER
METER & METER &
THRESHOLD THRESHOLD
DETECT DETECT
DDC CORE DDC CORE
DATA PACKING & DATA PACKING &
FLOW CONTROL FLOW CONTROL
MUX to MUX
MEM
CONTROL
METADATA METADATA
GENERATOR GENERATOR
LINKED-LIST LINKED-LIST
DMA ENGINE DMA ENGINE
A/D A/D
ACQUISITION ACQUISITION
MEMORY
CONTROLLER IP MODULE IP MODULE
MEMORY
CONTROLLER
Model 56641
AMC
PCIe INTERFACE
to to 8X 40 to to
Mem Mem FPGA Mem Mem
Bank 1 Bank 2 PCIe GPIO Bank 3 Bank 4
Figure 44
Model 56621 is a member of the Cobalt family of high In single-channel mode, decimation can be programmed
performance AMC modules based on the Xilinx Virtex-6 to 8x, 16x or 32x. In dual-channel mode, both channels
FPGA. A very high-speed data converter based on the Model share the same decimation rate, programmable to 4x, 8x
56640 described in the previous page, it includes additional or 16x.
factory-installed IP cores to enhance the performance of the
The decimating filter for each DDC accepts a
unique set of user-supplied 16-bit coefficients. The 80%
The 56641 factory-installed functions include an A/D default filters deliver an output bandwidth of 0.8*s/N,
acquisition IP module. In addition, within the FPGA is where N is the decimation setting. The rejection of
a powerful factory-installed DDC IP core. The core adjacent-band components within the 80% output
supports a single-channel mode, accepting data samples bandwidth is better than 100 dB. Each DDC delivers a
from the A/D at the full 3.6 GHz rate. Additionally, a complex output stream consisting of 16-bit I + 16-bit Q
dual-channel mode supports the A/Ds 1.8 GHz two- samples at a rate of s/N.
channel operation .
In dual-channel mode, each DDC has an indepen- module (Model 71641), PCIe half-length board (Model
dent 32-bit tuning frequency setting that ranges from 78641), 3U VPX (Model 53641), 6U cPCI (Models 72641
DC to s, where s is the A/D sampling frequency. and 74641 dual density), and 3U cPCI (Model 73641).
33
Products

Virtex-6
Model 53650 3U VPX Model 71650 XMC Model 78650 PCIe Model 56650 AMC
RF RF RF RF
Sample Clk / XFORMR XFORMR XFORMR XFORMR
TTL TIMING BUS Clock/Sync
PPS/Gate/Sync GENERATOR Bus 500 MHz 500 MHz 800 MHz 800 MHz
12-BIT A/D 12-BIT A/D 16-BIT D/A 16-BIT D/A
DIGITAL
D/A UPCONVERTER
Sample Clk Clock/Sync 16 16
Reset Bus 32
Gate A/D
Gate D/A
Sync / PPS A/D VIRTEX-6 FPGA
VCXO
Sync / PPS D/A LX130T, LX240T or SX315T
Timing Bus
GTX GTX GTX LVDS
16 16 16 16 16 16 16 16 16
8X 4X 4X 40
SRAM
8 MB
SRAM
8 MB
SRAM
8 MB
SRAM
8 MB
FLASH
64 MB
Model 53650 3U VPX
COTS and rugged
This Model is also QDRII+ option 150 QDRII+ option 160 x8 PCIe Gigabit FPGA
available with 400 MHz, DDR3 option 155 DDR3 option 165 Serial I/O GPIO
14-bit A/Ds DDR3
SDRAM
DDR3
SDRAM
DDR3
SDRAM
DDR3
SDRAM
512 MB 512 MB 512 MB 512 MB P15 P16 P14
XMC XMC PMC
Figure 45
high performance 3U VPX boards based on the Xilinx with factory-installed applications ideally matched to the
Virtex-6 FPGA. A two-channel, high-speed data boards analog interfaces. The 53650 factory-installed
converter, it is suitable for connection to HF or IF ports functions include an A/D acquisition and a D/A waveform
of a communications or radar system. Its built-in data playback IP module. In addition, IP modules for either
capture and playback features offer an ideal turnkey DDR3 or QDRII+ memories, a controller for all data
solution as well as a platform for developing and deploying clocking and synchronization functions, a test signal
custom FPGA processing IP. The 53650 includes two generator and a PCIe interface complete the factory-
500 MHz 12-bit A/Ds, one DUC, two 800 MHz 16-bit installed functions.
D/As and four banks of memory. It features built-in
support for PCI Express over the 3U VPX backplane.
The Pentek Cobalt architecture features a Virtex-6 functions across all connected boards. The architecture
FPGA. All of the boards data and control paths are acces- supports up to four memory banks which can be configured
sible by the FPGA, enabling factory-installed functions with all QDRII+ SRAM, DDR3 SDRAM, or as combina-
including data multiplexing, channel selection, data packing, tion of two banks of each type of memory.
ture organizes the FPGA as a container for data process-
module (Model 71650), as a PCIe half-length board (Model
ing applications where each function exists as an intellec-
78650), AMC (Model 56650), 6U cPCI (Models 72650
and 74650 with dual density), and 3U cPCI (Model 73650).
34
Products
2- or 4- Channel 500 MHz A/D, with DDCs, DUCs, 2- or 4-

Virtex-6

from from to
A/D Ch 1 A/D Ch 2 D/A
D/A loopback
TEST
SIGNAL
INPUT MULTIPLEXER GENERATOR
DDC DDC INTERPOLATOR

DEC: 2 TO 131027 DEC: 2 TO 131027 2 TO 65536
POWER POWER IP CORE
METER & METER &
THRESHOLD THRESHOLD DATA UNPACKING
DETECT DETECT & FLOW CONTROL
MUX
DDC CORE DDC CORE
DATA PACKING & DATA PACKING & MUX
FLOW CONTROL FLOW CONTROL
MEMORY MEMORY
CONTROL CONTROL MEMORY
METADATA METADATA
GENERATOR MUX GENERATOR MUX CONTROL
to to
Mem Mem to LINKED-LIST
Bank 1 LINKED-LIST Bank 2 LINKED-LIST Mem DMA ENGINE
DMA ENGINE DMA ENGINE
Bank 4 D/A
A/D A/D WAVEFORM
ACQUISITION ACQUISITION PLAYBACK
IP MODULE 1 IP MODULE 2 IP MODULE
AURORA sum out Model 74651 Model 73651

GIGABIT S
SERIAL SUMMER
PCIe INTERFACE Dual Density Single Density
INTERFACE sum in
BEAMFORMER CORE
4X 4X 4X
to next from previous VIRTEX-6 FPGA DATAFLOW DETAIL
board board PCIe
Figure 46
Models 72651, 73651 and 74651 are members of the A/D sampling frequency. Each DDC can have its
the Cobalt family of high performance CompactPCI boards own unique decimation setting, supporting as many as
based on the Xilinx Virtex-6 FPGA. They consist of two or four different output bandwidths for the board.
one or two Model 71651 XMC modules mounted on a Decimations can be programmed from 2 to 131,072
cPCI carrier board. These models include two or four A/Ds, providing a wide range to satisfy most applications.
two or four multiband DDCs, one ot two DUCs, two
In addition to the DDCs, these models feature one
or four D/As and three or six banks of memory.
or two complete beamforming subsystems. Each DDC
These models feature two or four A/D Acquisition IP core contains programable I & Q phase and gain adjust-
modules for easily capturing and moving data. Each ments followed by a power meter that continuously
module can receive data from either of the two A/Ds, a measures the individual average power output. The time
test signal generator or from the D/A Waveform Playback constant of the averaging interval for each meter is program-
IP module in loopback mode. mable up to 8K samples. The power meters present average
power measurements for each DDC core output in easy-
Within each A/D Acquisition IP Module is a
to-read registers.
powerful DDC IP core. Because of the flexible input
routing of the A/D Acquisition IP Modules, many different Model 72651 is a 6U cPCI board, while Model
configurations can be achieved including one A/D driving 73651 is a 3U cPCI board; Model 74651 is a dual
both DDCs or each of the two A/Ds driving its own DDC. density 6U cPCI board. Also available is an XMC module
(Model 71651), PCIe half-length board (Model 78651), 3U
Each DDC has an independent 32-bit tuning
VPX (Model 53651), and AMC (Model 56651).
35
Products
4- Channel 200 MHz 16-bit A/D with Vir

Virtex-6
RF RF RF RF
Sample Clk /
Reference Clk In
Gate / Trigger / TIMING BUS
Sync / PPS GENERATOR A/D Clock/Sync Bus
200 MHz 200 MHz 200 MHz 200 MHz
16-BIT A/D 16-BIT A/D 16-BIT A/D 16-BIT A/D
Sample Clk 16 16 16 16
Reset
Gate A
Gate B
Sync / PPS A
Sync / PPS B VCXO
VIRTEX-6 FPGA
Timing Bus LX130T, LX240T or SX315T
GTX GTX GTX LVDS
16 16 16 16 16 16 16 16 16
8X 4X 4X 40
SRAM SRAM SRAM SRAM FLASH
Model 71660 8 MB 8 MB 8 MB 8 MB 64 MB
XMC QDRII+ option 150 QDRII+ option 160 x8 PCIe Gigabit FPGA
DDR3 option 155 DDR3 option 165 Serial I/O GPIO
DDR3 DDR3 DDR3 DDR3
512 MB 512 MB 512 MB 512 MB P15 P16 P14
XMC XMC PMC
Figure 47
high performance XMC modules based on the Xilinx with factory-installed applications ideally matched to the
Virtex-6 FPGA. A multichannel, high-speed data boards analog interfaces. The 71660 factory-installed
converter, it is suitable for connection to HF or IF ports functions include four A/D acquisition IP modules. In
of a communications or radar system. Its built-in data addition, IP modules for either DDR3 or QDRII+
capture and playback features offer an ideal turnkey solution memories, a controller for all data clocking and syn-
as well as a platform for developing and deploying custom chronization functions, a test signal generator and a
FPGA processing IP. It includes four 200 MHz, 16-bit A/Ds PCIe interface complete the factory-installed functions.
and four banks of memory. In addition to supporting
PCI Express Gen. 2 as a native interface, the Model
71660 includes general purpose and gigabit serial connec-
functions across all connected modules. The architecture
tors for application-specific I/O .
supports up to four memory banks which can be configured
The Pentek Cobalt architecture features a Virtex-6 with all QDRII+ SRAM, DDR3 SDRAM, or as combina-
FPGA. All of the boards data and control paths are acces- tion of two banks of each type of memory.
sible by the FPGA, enabling factory-installed functions
ture organizes the FPGA as a container for data processing
36
Products
4- Channel 200 MHz, 16-bit A/D with Vir

Virtex-7
RF RF RF RF
Sample Clk /
Reference Clk In
Gate / Trigger / TIMING BUS
Sync / PPS GENERATOR A/D Clock/Sync Bus
200 MHz 200 MHz 200 MHz 200 MHz
16-BIT A/D 16-BIT A/D 16-BIT A/D 16-BIT A/D
Sample Clk 16 16 16 16
Reset
Gate A
Gate B
Sync / PPS A
Sync / PPS B VIRTEX-7 FPGA
VCXO
Timing Bus VX330T or VX690T
GTX GTX GTX LVDS
CONFIG FPGA 32 32 32 32
FLASH PCIe 4X 4X 48
Config Gen. 3 x8
1 GB
Bus DDR3 DDR3 DDR3 DDR3
Model 71760 GATEXPRESS PCIe 1 GB 1 GB 1 GB 1 GB
CONFIGURATION
XMC MANAGER
Gigabit FPGA
Gen. 3 x8 (option 105) (option 104)
P15 P16 P14
XMC XMC PMC
Figure 48
Model 71760 is a member of the Onyx family of Each member of the Onyx family is delivered with factory-
high performance XMC modules based on the Xilinx installed applications ideally matched to the boards analog
Virtex-7 FPGA. A multichannel, high-speed data converter, interfaces. The 71760 factory-installed functions include four
it is suitable for connection to HF or IF ports of a A/D acquisition IP modules for simplifying data capture and
communications or radar system. Its built-in data capture data tranfer. IP modules for DDR3 SDRAM memories, a
features offer an ideal turnkey solution as well as a controller for all data clocking and synchronization functions, a
platform for developing and deploying custom FPGA test signal generator, and a PCIe interface complete the factory-
processing IP. It includes four A/Ds and four banks of installed functions.
memory. In addition to supporting PCI Express Gen. 3 as a
The 71760 architecture supports four independent
native interface, the Model 71760 includes general purpose
DDR3 SDRAM memory banks. Each bank is 1 GB deep
and gigabit serial connectors for application-specific I/O.
and is an integral part of the modules DMA capabili-
Based on the proven design of the Pentek Cobalt family, ties, providing FIFO memory space for creating DMA
Onyx raises the processing performance with the new flagship packets. Built-in memory functions include multichannel
family of Virtex-7 FPGAs from Xilinx. As the central feature of A/D data capture, tagging and streaming.
the board architecture, the FPGA has access to all data and
control paths, enabling factory-installed functions including data
multiplexing, channel selection, data packing, gating, triggering
and memory control. The Onyx Architecture organizes the
74760 dual density), and 3U cPCI (Model 73760).
FPGA as a container for data processing applications where each
function exists as an intellectual property (IP) module. Please go to page 29 for information about GateXpress.
37
Products
4- Channel 200 MHz 16-bit A/D with Installed IP Cores, Vir

Virtex-6
from from from from
A/D Ch 1 A/D Ch 2 A/D Ch 3 A/D Ch 4
TEST
SIGNAL INPUT MULTIPLEXER
GENERATOR
DDC DDC DDC DDC

DEC: 2 TO 65536 DEC: 2 TO 65536 DEC: 2 TO 65536 DEC: 2 TO 65536
POWER POWER POWER POWER
METER & METER & METER & METER &
THRESHOLD THRESHOLD THRESHOLD THRESHOLD
DETECT DETECT DETECT DETECT
MUX
DDC CORE DDC CORE DDC CORE DDC CORE
DATA PACKING & DATA PACKING & DATA PACKING & DATA PACKING &
FLOW CONTROL FLOW CONTROL FLOW CONTROL FLOW CONTROL
MEMORY MEMORY MEMORY MEMORY
CONTROL CONTROL CONTROL CONTROL
METADATA METADATA METADATA METADATA
to GENERATOR MUX to GENERATOR MUX to GENERATOR MUX to GENERATOR MUX
Mem Mem Mem Mem
Bank 1 LINKED-LIST Bank 2 LINKED-LIST Bank 3 LINKED-LIST Bank 4 LINKED-LIST
DMA ENGINE DMA ENGINE DMA ENGINE DMA ENGINE
A/D A/D A/D A/D
ACQUISITION ACQUISITION ACQUISITION ACQUISITION
IP MODULE 1 IP MODULE 2 IP MODULE 3 IP MODULE 4
Model 71661
XMC
AURORA
sum out
GIGABIT S VIRTEX-6 FPGA DATAFLOW DETAIL PCIe INTERFACE
SERIAL SUMMER
INTERFACE sum in
BEAMFORMER CORE
4X 4X 8X
to next from previous
board board PCIe
Figure 49
Model 71661 is a member of the Cobalt family of high tions can be programmed from 2 to 65,536 providing a
performance XMC modules based on the Xilinx Virtex-6 wide range to satisfy most applications.
FPGA. A multichannel, high-speed data converter based on
The 71661 also features a complete beamforming
the Model 71660 described in the previous page, it includes
subsystem. Each DDC core contains programable I & Q
phase and gain adjustments followed by a power meter
that continuously measures the individual average power
The 71661 factory-installed functions include four A/D output. The power meters present average power measure-
acquisition IP modules. Each of the four acquisition IP ments for each DDC core output in easy-to-read registers. A
modules contains a powerful, programmable DDC IP threshold detector automatically sends an interrupt to
core. IP modules for either DDR3 or QDRII+ memo- the processor if the average power level of any DDC
ries, a controller for all data clocking and synchronization core falls below or exceeds a programmable threshold.
functions, a test signal generator, an Aurora gigabit
For larger systems, multiple 71661s can be chained
serial interface, and a PCIe interface complete the
together via the built-in Xilinx Aurora gigabit serial
factory-installed functions.
interface through the P16 XMC connector.
Each DDC has an independent 32-bit tuning
the A/D sampling frequency. Each DDC can have its
own unique decimation setting, supporting as many as
four different output bandwidths for the board. Decima-
38
Products
4- Channel 200 MHz 16-bit A/D with Installed IP Cores, Vir

Virtex-6
Model 78662 PCIe Model 71662 XMC Model 53662 3U VPX Model 56662 AMC
from from from from
A/D Ch 1 A/D Ch 2 A/D Ch 3 A/D Ch 4
TEST
SIGNAL INPUT MULTIPLEXER
GENERATOR
DIGITAL DIGITAL DIGITAL DIGITAL

DOWN- DOWN- DOWN- DOWN-
CONVERTER
.
CONVERTER
.
CONVERTER
.
CONVERTER
.
BANK 1: CH 1-8 BANK 2: CH 9-16 BANK 3: CH 17-24 BANK 4: CH 18-32

DEC: 16 TO 8192 DEC: 16 TO 8192 DEC: 16 TO 8192 DEC: 16 TO 8192
DDC DDC DDC DDC
CORE CORE CORE CORE
DATA PACKING & DATA PACKING & DATA PACKING & DATA PACKING &
FLOW CONTROL FLOW CONTROL FLOW CONTROL FLOW CONTROL
METADATA METADATA METADATA METADATA
to GENERATOR MUX to GENERATOR MUX GENERATOR MUX GENERATOR MUX
to to
Mem Mem Mem Mem
Bank 1 LINKED-LIST Bank 2 LINKED-LIST Bank 3 LINKED-LIST LINKED-LIST
DMA ENGINE DMA ENGINE DMA ENGINE
Bank 4 DMA ENGINE
A/D A/D A/D A/D
ACQUISITION ACQUISITION ACQUISITION ACQUISITION
Model 78662
x8 PCIe
VIRTEX-6 FPGA DATAFLOW DETAIL (supports user installed IP)
PCIe INTERFACE
32 32 32 32 8X 4X 4X 40
Memory Memory Memory Memory PCIe Gigabit FPGA
Bank 1 Bank 2 Bank 3 Bank 4 Serial I/O GPIO
Figure 50
Model 78662 is a member of the Cobalt family of of eight. Each 8-channel bank can have its own unique
high performance PCIe boards based on the Xilinx Virtex-6 decimation setting supporting a different bandwidth
FPGA. Based on the Model 71660 presented previously, associated with each of the four acquisition modules.
this four-channel, high-speed data converter with
The decimating filter for each DDC bank accepts
programmable DDCs is suitable for connection to HF or
a unique set of user-supplied 18-bit coefficients. The 80%
IF ports of a communications or radar system.
The 78662 factory-installed functions include four A/D where N is the decimation setting. The rejection of
acquisition IP modules. Each of the four acquisition IP adjacent-band components within the 80% output
modules contains a powerful, programmable 8-channel bandwidth is better than 100 dB.
DDC IP core. IP modules for either DDR3 or QDRII+
Each DDC delivers a complex output stream consisting
memories, a controller for all data clocking and synchroni-
of 24-bit I + 24-bit Q samples at a rate of s/N. Any
zation functions, a test signal generator, voltage and
number of channels can be enabled within each bank,
temperature monitoring, and a PCIe interface complete the
selectable from 0 to 8. Multiple 78662s can be driven
factory-installed functions.
from the LVPECL bus master, supporting synchronous
Each of the 32 DDC channels has an independent sampling and sync functions across all connected boards.
32-bit tuning frequency setting that ranges from DC to
s, where s is the A/D sampling frequency. All of the
module (Model 71662), 3U VPX (Model 53662), AMC
8 channels within a bank share a common decimation
setting ranging from 16 to 8192 programmable in steps
39
Products
4- Channel 1.25 GHz D/A with DUC, Vir

Virtex-6
Model 56670 AMC Model 71670 XMC Model 78670 PCIe Model 53670 3U VPX
RF Out RF Out RF Out RF Out
RF RF RF RF
Sample Clk /
Reference Clk In
TIMING BUS
Trigger In GENERATOR 1.25 GHz 1.25 GHz 1.25 GHz 1.25 GHz
Clock/Sync
16-BIT D/A 16-BIT D/A 16-BIT D/A 16-BIT D/A
Clock / Sync / Bus A
DIGITAL DIGITAL DIGITAL DIGITAL
Gate In Gate / PPS
UPCONVERTER UPCONVERTER UPCONVERTER UPCONVERTER
Sync In Clock/Sync
Bus B
Sync Bus A
16 16
Gate In
Sync In
Sync Bus B VIRTEX-6 FPGA
VCXO
GTX LVDS
16 16 16 16 16
8X 40
DDR3 DDR3 DDR3 DDR3 Config
SDRAM SDRAM SDRAM SDRAM FLASH IPMI
Model 56670
512 MB 512 MB 512 MB 512 MB 64 MB CONTROLLER AMC
FPGA
x8 PCIe RS-232 GPIO
(option 104)
AMC Front Front

Ports 4 to 11 Panel Panel
Figure 51
Model 56670 is a member of the Cobalt family of Each member of the Cobalt family is delivered with
high performance AMC modules based on the Xilinx factory-installed applications ideally matched to the boards
Virtex-6 FPGA. This 4-channel, high-speed data analog interfaces. The 56670 factory-installed functions
converter is suitable for connection to transmit HF or IF include four D/A waveform playback IP modules, to support
ports of a communications or radar system. Its built-in waveform generation through the D/A converters. IP modules
data playback features offer an ideal turnkey solution for DDR3 SDRAM memories, a controller for all data
for demanding transmit applications. It includes four clocking and synchronization functions, a test signal generator,
D/As, four digital upconverters and four banks of and a PCIe interface complete the factory-installed functions
memory. In addition to supporting PCI Express Gen. 2 as and enable the 56670 to operate as a complete turnkey
a native interface, the Model 56670 includes a front solution, without the need to develop any FPGA IP.
panel general-purpose connector for application-specific
The Model 56670 factory-installed functions
I/O.
include a sophisticated D/A Waveform Playback IP
The Pentek Cobalt Architecture features a Virtex-6 module. Four linked-list controllers support waveform
FPGA. All of the boards data and control paths are generation to the four D/As from tables stored in either
accessible by the FPGA, enabling factory-installed on-board memory or off-board host memory.
functions including data multiplexing, channel selection,
data packing, gating, triggering and memory control.
module (Model 71670), PCIe half-length board (Model
The Cobalt Architecture organizes the FPGA as a
78670), 3U VPX (Model 53670), 6U cPCI (Models 72670
container for data processing applications where each
and 74670 dual density), and 3U cPCI (Model 73670).
function exists as an intellectual property (IP) module.
40
Products
4- Channel 1.25 GHz D/A with DUC, Extended Interpolation

4-Channel Interpolation,, Vir tex-6 FPGA
Virtex-6
to to
16 16
D/A Ch 1 & 2 D/A Ch 3 & 4
TEST DATA DATA

SIGNAL INTERLEAVER INTERLEAVER
GENERATOR
INTERPOLATOR INTERPOLATOR INTERPOLATOR INTERPOLATOR

2 TO 65536 2 TO 65536 2 TO 65536 2 TO 65536
IP CORE IP CORE IP CORE IP CORE
DATA DATA DATA DATA

UNPACKING UNPACKING UNPACKING UNPACKING
& FLOW & FLOW & FLOW & FLOW
MUX MUX MUX MUX

to LINKED-LIST to LINKED-LIST to LINKED-LIST to LINKED-LIST

Mem DMA ENGINE Mem DMA ENGINE Mem DMA ENGINE Mem DMA ENGINE
Bank 1 D/A Bank 2 D/A Bank 3 D/A Bank 4 D/A
WAVEFORM WAVEFORM WAVEFORM WAVEFORM
PLAYBACK PLAYBACK PLAYBACK PLAYBACK
Model 71671
XMC
PCIe INTERFACE (supports user installed IP)
VIRTEX-6 FPGA DATAFLOW DETAIL
Memory Memory Memory Memory 8X 4X 4X 40

Bank 1 Bank 2 Bank 3 Bank 4 Gigabit FPGA
Figure 52
Model 71671 is a member of the Cobalt family of high selectable IF center frequency. It delivers real or quadra-
performance XMC modules based on the Xilinx Virtex-6 ture (I+Q) analog outputs to a 16-bit D/A converter.
FPGA. A multichannel, high-speed data converter based on
If translation is disabled, each D/A acts as an
the Model 71670 described in the previous page, it includes
interpolating 16-bit D/A with output sampling rates up
to 1.25 GHz. In both modes, the D/A provides interpolation
factors of 2x, 4x, 8x and 16x.
The Model 56671 factory-installed functions
In addition to the DAC3484, the 71671 features an
include a sophisticated D/A Waveform Playback IP
FPGA-based interpolation engine which adds two
module. Four linked-list controllers support waveform
additonal interpolation stages programmable from 2x to
generation to the four D/As from tables stored in either
256x. The combined interpolation results in a range
on-board memory or off-board host memory.
from 2x to 1,048,576x for each D/A channel and is ideal
Two Texas Instruments DAC3484s provide four DUC for matching the digital downconversion and data
(digital upconverter) and D/A channels. Each channel reduction used on the receiving channels of many
accepts a baseband real or complex data stream from the communications systems.
FPGA and provides that input to the upconvert, interpo-
late and D/A stage.
When operating as a DUC, it interpolates and trans- AMC (Model 56671), 6U cPCI (Models 72671 and
lates real or complex baseband input signals to a user 74671 with dual density), and 3U cPCI (Model 73671).
41
Products
L-Band RF TTuner
uner with 2- Channel 200 MHz A/D and Vir
Virtex-6
Ref RF Ref
In In Out
MAX2112
GC 12-BIT
D/A
Sample Clk / Control

Reference Clk In Ref
I Q
Trigger 1 TIMING
Trigger 2 GENERATOR A/D Clock/Sync 200 MHz 200 MHz
Clock / Sync / 16-BIT A/D 16-BIT A/D
TTL Gate / Trig Gate / PPS
TTL Sync / PPS
Sample Clk 16 16 2
Ref In
Gate A 2
IC
Gate B
Sync / PPS A
Sync / PPS B VCXO VIRTEX-6 FPGA
Timing Bus LX130T, LX240T or SX315T Option -105
Gigabit Serial I/O
LVDS GTX GTX GTX
16 16 16 16 16 16 16 16 16
40 8X 4X 4X
QDRII+ QDRII+ QDRII+ QDRII+ Config Option -104
SRAM SRAM SRAM SRAM FLASH FPGA x8
8 MB 8 MB 8 MB 8 MB 64 MB PCIe
I/O
Model 53690 3U VPX
QDRII+ option 150 QDRII+ option 160
CROSSBAR
COTS and rugged
DDR3 option 155 DDR3 option 165
SWITCH
DDR3 DDR3 DDR3 DDR3
SDRAM SDRAM SDRAM SDRAM 4X 4X 4X 4X
512 MB 512 MB 512 MB 512 MB
Gbit Gbit Gbit Gbit
Serial Serial Serial Serial
VPX-P2 VPX-P1
VPX BACKPLANE
Figure 53
Model 53690 is a member of the Cobalt family of boards analog interfaces. The 53690 factory-installed
high performance 3U VPX boards based on the Xilinx functions include two A/D acquisition IP modules. IP
Virtex-6 FPGA. A 2-Channel high-speed data converter, modules for either DDR3 or QDRII+ memories, a
it is suitable for connection directly to the RF port of a controller for all data clocking and synchronization
communications or radar system. Its built-in data capture functions, a test signal generator, and a PCIe interface
features offer an ideal turnkey solution. The Model 53690 complete the factory-installed functions.
includes an L-Band RF tuner, two 200 MHz, 16-bit
A front panel connector accepts L-Band signals
A/Ds and four banks of memory. It features built-in
between 925 MHz and 2175 MHz from an antenna
support for PCI Express over the 3U VPX backplane.
LNB. A Maxim MAX2112 tuner directly converts
The Pentek Cobalt architecture features a Virtex-6 these signals to baseband using a broadband I/Q
FPGA. All of the boards data and control paths are acces- downconverter. The device includes an RF variable-
sible by the FPGA, enabling factory-installed functions gain LNA (low-noise amplifier), a PLL synthesized
including data multiplexing, channel selection, data packing, local oscillator, quadrature (I + Q) downconverting
gating, triggering and memory control. The Cobalt architec- mixers, baseband lowpass filters and variable-gain
ture organizes the FPGA as a container for data processing baseband amplifiers.
module (Model 71690), as a PCIe half-length board (Model
Each member of the Cobalt family is delivered with 78690), AMC (Model56690), 6U cPCI (Models 72690
factory-installed applications ideally matched to the and 74690 with dual density), and 3U cPCI (Model 73690).
42
Products
2.2 GHz Clock, Sync and Gate Distribution Board
Model 6890 - VME

Front
Panel TTL / PECL Ch 1
Gate SELECTOR Ch 2
Enable LVPECL Ch 3 Front
GATE
CONTROL PROG BUFFER MUX BUFFER Ch 4 Panel
Front DELAY 1:2 2:1 Ch 5 Gate
1:8
Panel TTL / PECL REG Ch 6 Output
Gate SELECTOR Ch 7
Input Ch 8
Ch 1
Ch 2
Front POWER POWER Ch 3 Front
Panel SPLITTER SPLITTER Ch 4 Panel
Clock 1:2 BUFFER Ch 5 Clock
Input 1:8
1:2 Ch 6 Output
Ch 7
Ch 8
Front
Panel TTL / PECL Ch 1
Sync SELECTOR Ch 2
Enable REG LVPECL Ch 3 Front
SYNC BUFFER
CONTROL PROG BUFFER MUX Ch 4 Panel
DELAY 1:2 2:1 Ch 5 Sync
Front 1:8
Panel TTL / PECL Ch 6 Output
Sync SELECTOR Ch 7
Input Ch 8
Model 6890
VME
Figure 54
Model 6890 Clock, Sync and Gate Distribution splitter feeds a 1:2 buffer which distributes the clock
Board synchronizes multiple Pentek I/O boards within a signal to both the gate and synchronization circuits.
system. It enables synchronous sampling and timing
The 6890 features separate inputs for gate/trigger
for a wide range of multichannel high-speed data
and sync signals with user-selectable polarity. Each of
acquisition, DSP and software radio applications. Up
these inputs can be TTL or LVPECL. Separate Gate
to eight boards can be synchronized using the 6890,
Enable and Sync Enable inputs allow the user to enable
each receiving a common clock of up to 2.2 GHz along
or disable these circuits using an external signal.
with timing signals that can be used for synchronizing,
triggering and gating functions. A programmable delay allows the user to make
timing adjustments on the gate and sync signals before
Clock signals are applied from an external source
they are sent to an LVPECL buffer. A bank of eight
such as a high performance sine wave generator. Gate
MMCX connectors at the output of each buffer delivers
and sync signals can come from an external source, or
signals to up to eight boards.
from one supported board set to act as the master.
A 2:1 multiplexer in each circuit allows the gate/
The 6890 accepts clock input at +10 dBm to +14 dBm
trigger and sync signals to be registered with the input
with a frequency range from 800 MHz to 2.2 GHz and
clock signal before output, if desired.
uses a 1:2 power splitter to distribute the clock. The first
output of this power splitter sends the clock signal to a Sets of input and output cables for two to eight
1:8 splitter for distribution to up to eight boards using boards are available from Pentek.
SMA connectors. The second output of the 1:2 power
43
Products
System Synchronizer and Distribution Board
Model 6891 - VME

Gate
Clock Sync Bus
Sync Output 1
Ch 1
Ch 2
Front Panel Gate
Ch 3
Gate Enable GATE Clock Sync Bus
Ch 4
GATE
LVPECL to Sync Bus Sync Output 2
PROG BUFFER MUX BUFFER Ch 5
CONTROL DELAY
Outputs 2-8
Front Panel 1:2 2:1 Ch 6
MUX 1:8 Gate
GateInput REG Ch 7
2:1 Ch 8 Clock Sync Bus
Sync Output 3
Ch 1 Gate
Ch 2 Clock Sync Bus
Ch 3 Sync Output 4
CLOCK
Front Panel LVPECL Ch 4
MUX to Sync Bus
Clock Input BUFFER Ch 5 Gate
2:1 Outputs 2-8
1:10
Ch 6 Clock Sync Bus
Ch 7 Sync Output 5
Ch 8
Gate
Clock Sync Bus
Ch 1 Sync Output 6
Front Panel Ch 2
Sync Enable REG Ch 3 Gate
SYNC PROG BUFFER MUX SYNC
LVPECL Ch 4 Clock Sync Bus
CONTROL DELAY 1:2 2:1 BUFFER
to Sync Bus
Front Panel Ch 5 Sync Output 7
MUX
Outputs 2-8
Sync Input Ch 6
1:8
2:1 Ch 7 Gate
Ch 8
Clock Sync Bus
Gate Output 8
Sync
Sync Bus Clock
Input Sync
Model 6891
VME
Figure 55
Model 6891 System Synchronizer and Distribution Clock signals can be applied from an external source
Board synchronizes multiple Pentek I/O modules within a such as a high performance sine-wave generator. Gate/trigger
system. It enables synchronous sampling and timing for a and sync signals can come from an external system source.
wide range of multichannel high-speed data acquisition, Alternately, a Sync Bus connector accepts LVPECL inputs
DSP and software radio applications. from any compatible Pentek products to drive the clock,
sync and gate/trigger signals.
Up to eight modules can be synchronized using the
6891, each receiving a common clock up to 500 MHz The 6891 provides eight front panel Sync Bus output
along with timing signals that can be used for synchroniz- connectors, compatible with a wide range of Pentek I/O
ing, triggering and gating functions. For larger systems, modules. The Sync Bus is distributed through ribbon
up to eight 6891s can be linked together to provide cables, simplifying system design. The 6891 accepts clock
synchronization for up to 64 I/O modules producing input at +10 dBm to +14 dBm with a frequency range
systems with up to 256 channels. from 1 kHz to 800 MHz. This clock is used to register
all sync and gate/trigger signals as well as providing a
Model 6891 accepts three TTL input signals from
sample clock to all connected I/O modules.
external sources: one for clock, one for gate or trigger
and one for a synchronization signal. Two additional A programmable delay allows the user to make
inputs are provided for separate gate and sync enable signals. timing adjustments on the gate and sync signals before
they are sent to an LVPECL buffer for output through
the Sync Bus connectors.
44
Products
Multifrequency Clock Synthesizer
Reference Clock Out
In CLOCK 1 Out
SYNTHESIZER 1
2
QUAD AND JITTER 4 In C
VCXO CLEANER 8 Clock Out
R 2
A A 16
O
S
Clock Out
S Out
CLOCK 3
1 B
SYNTHESIZER 2 A Clock Out
QUAD AND JITTER 4 In
CLEANER
R 4
VCXO 8
B B 16
S
Clock Out
W Out
5
I
CLOCK 1
SYNTHESIZER T Clock Out
2
AND JITTER 4 C 6
QUAD In
CLEANER 8 H
VCXO
C C 16 Clock Out
Out
7
Supports:
CLOCK any In to any Out,
1
SYNTHESIZER 2 any In to multiple
QUAD AND JITTER 4 In Outs
D 16 Out
Model 7190 D 8
PMC Control
PCI INTERFACE
PCI BUS
32 (32 Bits / 66 MHz)
Figure 56
Model 7190 generates up to eight synthesized clock The CDC7005 includes phase-locking circuitry
signals suitable for driving A/D and D/A converters in that locks the frequency of its associated VCXO to an
high-performance real-time data acquisition and software input reference of 5 MHz to 100 MHz.
radio systems. The clocks offer exceptionally low phase noise
Eight front panel SMC connectors supply synthesized
and jitter to preserve the signal quality of the data converters.
clock outputs driven from the five clock output drivers.
These clocks are synthesized from on-board quad VCXOs
This supports a single identical clock to all eight outputs
and can be phase-locked to an external reference signal.
or up to five different clocks to various outputs. With
The 7190 uses four Texas Instruments CDC7005 clock four independent quad VCXOs and each CDC7005
synthesizer and jitter cleaner devices. Each CDC7005 is paired capable of providing up to five different submultiple
with a dedicated VCXO to provide the base frequency for clocks, a wide range of clock configurations is possible. In
the clock synthesizer. Each of the four VCXOs can be systems where more than five different clock outputs are
independently programmed to generate one of four frequen- required simultaneously, multiple 7190s can be used and
cies between 50 MHz and 700 MHz. phase-locked with the 5 MHz to 100 MHz system reference.
The CDC7005 can output the selected frequency Versions of the 7190 are also available as a PCIe full-
of its associated VCXO, or generate submultiples using length board (Models 7790 and 7790D dual density),
divisors of 2, 4, 8 or 16. The four CDC7005s can output PCIe half-length board (Model 7890), 3U VPX board
up to five frequencies each. The 7190 can be programmed to (Model 5390), PCI board (Model 7690), 6U cPCI
route any of these 20 frequencies to the modules five (Models 7290 and 7290D dual density), or 3U cPCI
output drivers. (Model 7390).
45
Products
Programmable Multifrequency Clock Synthesizer
Reference Clock Out
In CLOCK 1 Out
SYNTHESIZER 1
2
PROGRAM AND JITTER 4 In C
R 2
A A 16
O
S
Clock Out
S Out
CLOCK 3
1 B
SYNTHESIZER 2 A Clock Out
PROGRAM AND JITTER 4 In
CLEANER
R 4
VCXO 8
B B 16
S
Clock Out
W Out
5
I
CLOCK 1
SYNTHESIZER T Clock Out
2
AND JITTER 4 C 6
PROGRAM In
CLEANER 8 H
VCXO
C C 16 Clock Out
Out
7
Supports:
CLOCK any In to any Out,
1
SYNTHESIZER 2 any In to multiple
PROGRAM AND JITTER 4 In Outs
D 16 Out
Model 7191 D 8
PMC Control
PCI INTERFACE
PCI BUS
32 (32 Bits / 66 MHz)
Figure 57
Model 7191 generates up to eight synthesized clock The CDC7005 includes phase-locking circuitry
signals suitable for driving A/D and D/A converters in that locks the frequency of its associated VCXO to an
high-performance real-time data acquisition and software input reference of 5 MHz to 100 MHz.
radio systems. The clocks offer exceptionally low phase noise
Eight front panel SMC connectors supply synthesized
and jitter to preserve the signal quality of the data converters.
clock outputs driven from the five clock output drivers.
These clocks are synthesized from programmable VCXOs
This supports a single identical clock to all eight outputs
and can be phase-locked to an external reference signal.
or up to five different clocks to various outputs. With
The 7191 uses four Texas Instruments CDC7005 clock four programmable VCXOs and each CDC7005
synthesizer and jitter cleaner devices. Each CDC7005 is paired capable of providing up to five different submultiple
with a dedicated VCXO to provide the base frequency for clocks, a wide range of clock configurations is possible. In
the clock synthesizer. Each of the four VCXOs can be systems where more than five different clock outputs are
independently programmed to a desired frequency between required simultaneously, multiple 7191s can be used and
50 MHz and 700 MHz with 32-bit tuning resolution. phase-locked with the 5 MHz to 100 MHz system reference.
The CDC7005 can output the programmed frequency Versions of the 7191 are also available as a PCIe full-
of its associated VCXO, or generate submultiples using length board (Models 7791 and 7791D dual density),
divisors of 2, 4, 8 or 16. The four CDC7005s can output PCIe half-length board (Model 7891), 3U VPX board
up to five frequencies each. The 7191 can be programmed to (Model 5391), PCI board (Model 7691), 6U cPCI
route any of these 20 frequencies to the modules five (Models 7291 and 7291D dual density), or 3U cPCI
output drivers. (Model 7391).
46
Products
High-Speed Synchronizer and Distribution Board
Model 7192 PMC/XMC Model 7892 Half-length PCIe Model 5393 3U VPX
PROGRAMMABLE
VCXO
Sample Clk /
Reference
Clk In Clk
MUX In Clock /
Calibration Out
PLL
:N
&
DIVIDER
:N
Ref mSync 1
In Reference Clk In *
TWSI Control In
TWSI
CONTROL Gate / Trigger Out
Sync Out
Reference Clk Out
mSync 2
Gate / Trigger Out
Sync Out
Clk/ Reference Clk Out
MUX Ref
In BUFFER mSync 3
Gate / Trigger In &
Trig/ Gate / Trigger Out
Gate PROGRAM
Model 7192 In DELAYS Sync Out
Sync In Reference Clk Out
PMC/XMC Sync
In mSync 4
Gate / Trigger Out
Sync Out
* For 71640 A/D calibration Reference Clk Out
Figure 58
The Model 7192 High-Speed Synchronizer and The 7192 provides four front panel Sync output
Distribution Board synchronizes multiple Pentek Cobalt connectors, compatible with a range of high-speed
or Onyx modules within a system. It enables synchronous Pentek Cobalt and Onyx modules. The Sync signals
sampling and timing for a wide range of multichannel include a reference clock, gate/trigger and sync signals and are
high-speed data acquisition, DSP, and software radio distributed through matched cables, simplifying system
applications. Up to four modules can be synchronized design. The 7192 features a calibration output specifi-
using the 7192, with each receiving a common clock cally designed to work with the 71640 or 71740
along with timing signals that can be used for synchro- 3.6 GHz A/D module and provide a signal reference for
nizing, triggering and gating functions. phase adjustment across multiple D/As.
Model 7192 provides three front panel MMCX The 7192 supports all high-speed models in the Cobalt
connectors to accept input signals from external sources: family including the 71630 1 GHz A/D and D/A XMC,
one for clock, one for gate or trigger and one for a synchro- the 71640 3.6 GHz A/D XMC and the 71670 Four-
nization signal. Clock signals can be applied from an channel 1.25 GHz, 16-bit D/A XMC. The 7192 will also
external source such as a high performance sine-wave support high-speed models in the Onyx family as they
generator. Gate/trigger and sync signals can come from become available.
an external system source. In addition to the MMCX
connector, a reference clock can be accepted through the
length board (Model 7892), 3U VPX (Model 5392), 6U
first front panel Sync output connector, allowing a
cPCI (Models 7292 and 7492 dual density), and 3U
single Cobalt or Onyx board to generate the clock for
cPCI (Model 7392).
all subsequent boards in the system.
47
Products
System Synchronizer and Distribution Board
Model 7893 - Half-length PCIe

Sample Clk /
Reference Clk In :N
Sample Clk A Clock Out 1
MUX CLK :N
IN
PLL :N
& Clock Out 2
:
DIVIDER N Sample Clk B
:N
REF
Sample Clk A CLK CONTROL Clock Out 3
IN VOLTAGE
Sample Clk B
Gate / Trig A
Gate / Trig B Clock Out 4
Sync / PPS A PROGRAM
Sync / PPS B VCXO
Timing Bus In
Timing Bus Out 1
Control Sample Clk A
USB Sample Clk B
USB USB Gate / Trig
INTERFACE Gate / Trig A
USB Sync / PPS Gate / Trig B
Sample Clk A Sync / PPS A
Sync / PPS B
Sample Clk B
MUX Gate / Trig A BUFFER

USB Gate / Trig Timing Bus Out 2
TTL &
MUX through
Gate / Trig In PROGRAM
DELAYS Timing Bus Out 7
MUX Gate / Trig B
Timing Bus Out 8

USB Sync / PPS Sample Clk A
Sync / PPS A Sample Clk B
MUX
TTL Gate / Trig A
Sync / PPS A In Gate / Trig B
Sync / PPS A
Sync / PPS B Sync / PPS B
TTL MUX
Sync / PPS B In
Figure 59
Model 7893 System Synchronizer and Distribution The 7893 provides eight timing bus output connec-
Board synchronizes multiple Pentek Cobalt and Onyx tors for distributing all needed timing and clock signals
boards within a system. It enables synchronous sampling, to the front panels of Cobalt and Onyx boards via ribbon
playback and timing for a wide range of multichannel cables. The 7893 locks the Gate/Trigger and Sync/PPS
high-speed data acquisition, DSP and software radio signals to the systems sample clock. The 7893 also
applications. provides four front panel SMA connectors for distrib-
uting sample clocks to other boards in the system.
Up to eight boards can be synchronized using the
7893, each receiving a common clock up to 800 MHz The 7893 can accept a clock from either the front panel
along with timing signals that can be used for synchroniz- SMA connector or from the timing bus input connector. A
ing, triggering and gating functions. For larger systems, programmable on-board VCXO clock generator can be
up to eight 7893s can be linked together to provide synchro- locked to a user-supplied, 10 MHz reference.
nization for up to 64 Cobalt or Onyx boards.
The 7893 supports a wide range of products in the
The Model 7893 provides four front panel SMA Cobalt family including the 78620 and 78621 three-channel
connectors to accept LVTTL input signals from A/D 200 MHz transceivers, the 78650 and 78651 two-channel
external sources: two for Sync/PPS and one for Gate/ A/D 500 MHz transceivers, the 78660, 78661 and 78662
Trigger. In addition to the synchronization signals, a front four-channel 200 MHz A/Ds, and the 78690 L-Band RF
panel SMA connector accepts sample clocks up to 800 MHz Tuner. The 7893 also supports the Onyx 78760 four-
or, in an alternate mode, accepts a 10 MHz reference channel 200 MHz A/D and will support all complemen-
clock to lock an on-board VCXO sample clock source. tary models in the Onyx family as they become available.
48
Products
Clock and Sync Generator for I/O Modules
Model 9190 - Rack-mount

Rack-mount
Model 9190
LVDS To
DIFF. Module
DRIVERS No. 1
Timing
From Signals Timing
Module LVDS Signals To
DIFF. LVDS
Master RECEIVER DIFF. Module
Source DRIVERS No. 2
Timing
Signals Multiplexer
Front
Switches
Panel LVDS To
LINE Clock
Input DIFF. Module
RCVRS DRIVERS
SMA Ext. Clock No. 80
Connectors
Front
OPTIONAL Panel
INTERNAL LINE
DRIVERS Output
OSCILLATOR
SMA
Connectors
Figure 60
Model 9190 Clock and Sync Generator synchronizes Buffered versions of the clock and five timing
multiple Pentek I/O modules within a system to provide signals are available as outputs on the 9190s front panel
synchronous sampling and timing for a wide range of SMA connectors.
high-speed, multichannel data acquisition, DSP and
Model 9190 is housed in a line-powered, 1.75 in.
software radio applications. Up to 80 I/O modules can
high metal chassis suitable for mounting in a standard
be driven from the Model 9190, each receiving a
19 in. equipment rack, either above or below the cage
common clock and up to five different timing signals
holding the I/O modules.
which can be used for synchronizing, triggering and
gating functions. Separate cable assemblies extend from openings in
the front panel of the 9190 to the front panel clock and
Clock and timing signals can come from six front
sync connectors of each I/O module. Mounted between
panel SMA user inputs or from one I/O module set to act
two standard rack-mount card cages, Model 9190 can
as the timing signal master. (In this case, the master I/O
drive a maximum of 80 clock and sync cables, 40 to the
module will not be synchronous with the slave modules
card cage above and 40 to the card cage below. Fewer
due to delays through the 9190.) Alternately, the master
cables may be installed for smaller systems.
clock can come from a socketed, user-replaceable crystal
oscillator within the Model 9190.
49
Products
High-Speed System Synchronizer Unit
Model 9192 - Rack-mount

Rack-mount
External Clk In
Clock Out 1
PROGRAMMABLE
VCXO Clock Out 2
Sample Clk /
Reference MUX CLOCK
Clk In Clock Out 3
Clk SPLITTER
MUX In through
Clock Out 11
PLL
:N
&
DIVIDER Clock Out 12
:N
Ref mSync 1
In Reference Clk In *
Model 9192 TWSI Control In
TWSI
CONTROL Gate / Trigger Out
USB Sync Out
USB-TO-TWSI Reference Clk Out
INTERFACE
mSync 2
Gate / Trigger Out

Sync Out
Clk Reference Clk Out
MUX Ref
In
Gate / Trigger In BUFFER
Trig/ & mSync 3
Gate PROGRAM through
Sync In
In
DELAYS mSync 11
Sync
In mSync 12
Gate / Trigger Out

Sync Out
* For 71640 A/D calibration Reference Clk Out
Figure 61
Model 9192 Rack-mount High-Speed System The 9192 provides four rear panel Sync output
Synchronizer Unit synchronizes multiple Pentek Cobalt or connectors, compatible with a range of high-speed Pentek
Onyx modules within a system. It enables synchronous Cobalt and Onyx boards. The Sync signals include a
sampling and timing for a wide range of multichannel reference clock, gate/trigger and sync signals and are distrib-
high-speed data acquisition, DSP, and software radio uted through matched cables, simplifying system design.
applications. Up to twelve boards can be synchronized
The 9192 features twelve calibration outputs
using the 9192, each receiving a common clock along
specifically designed to work with the 71640 or 71740
with timing signals that can be used for synchronizing,
3.6 GHz A/D module and provide a signal reference for
triggering and gating functions.
phase adjustment across multiple D/As.
Model 9192 provides four rear panel SMA connec-
The 9192 allows programming of operation parameters
tors to accept input signals from external sources: two
including: VCXO frequency, clock dividers, and delays that
for clock, one for gate or trigger and one for a synchro-
allow the user to make timing adjustments on the gate and
nization signal. Clock signals can be applied from an
sync signals. These adjustments are made before they are sent
external source such as a high performance sine-wave
to buffers for output through the Sync connectors.
generator. Gate/trigger and sync signals can come from an
external system source. In addition to the SMA connector, The 9192 supports all high-speed models in the Cobalt
a reference clock can be accepted through the first rear family including the 71630 1 GHz A/D and D/A XMC, the
panel Sync output connector, allowing a single Cobalt 71640 3.6 GHz A/D XMC and the 71670 Four-channel
or Onyx board to generate the clock for all subsequent 1.25 GHz, 16-bit D/A XMC. The 9192 will also support high-
boards in the system. speed models in the Onyx family as they become available.
50
Products
Eight- Channel RF/IF

Eight-Channel RF/IF,, 200 MS/sec Rackmount R
Rackmount ecorder
Recorder
Model RTS 2706
2 Gigabit
Ethernet
Channels 200 MHz DIGITAL 6
DOWN- USB 2.0
In 16-bit A/D
Up to 8 CONVERTER
INTEL 2
Channels Decimation: eSATA
PROCESSOR
2 to 65,536
Model RTS 2706
COTS PS/2
DDR Keyboard
SYSTEM DRIVE SDRAM PS/2
Channels 800 MHz DIGITAL Mouse
Out or 1.25 GHz UP- Video
16-bit D/A CONVERTER Output
Up to 8 Decimation: HOST PROCESSOR
Channels GPS
2 to 65,536 RUNNING SYSTEMFLOW
Antenna
Model RTS 2706 (Optional)
Rugged
DATA DRIVES DATA DRIVES
UP TO 20 TB RAID
MODEL RTS 2706
Figure 62
The Talon RTS 2706 is a turnkey, multiband Included with this system is Penteks SystemFlow
recording and playback system for recording and recording software. Optional GPS time and position
reproducing high-bandwidth signals. The RTS 2706 stamping allows the user to record this critical signal
uses 16-bit, 200 MHz A/D converters and provides information.
sustained recording rates up to 2.0 GB/sec in four-channel
Built on a Windows 7 Professional workstation with
configuration.
high performance Intel CoreTM i7 processor, the RTS 2706
The RTS 2706 uses Penteks high-powered Virtex-6-based allows the user to install post-processing and analysis
Cobalt modules, that provide flexibility in channel count, tools to operate on the recorded data. The instrument
with optional digital downconversion capabilities. Optional records data to the native NTFS file system, providing
16-bit, 800 MHz D/A converters with digital upconversion immediate access to the data.
allow real-time reproduction of recorded signals.
The RTS 2706 is configured in a 4U 19" rackmoun-
A/D sampling rate, DDC decimation and bandwidth, table chassis, with hot-swap data drives, front panel USB
D/A sampling rate and DUC interpolation are among ports and I/O connectors on the rear panel. Systems are
the GUI-selectable system parameters, providing a fully- scalable to accommodate multiple chassis to increase
programmable system capable of recording and reproduc- channel counts and aggregate data rates. All recorder
ing a wide range of signals. chassis are connected via Ethernet and can be controlled
from a single GUI either locally or from a remote PC.
51
Products
Four
our--Channel RF/IF
RF/IF,, 500 MS/sec Rackmount R
Rackmount ecorder
Recorder
Model RTS 2707
500 MHz
12-bit A/D DIGITAL DOWN- Gigabit
Channels CONVERTER Ethernet
or
In DEC: 2 to 64K INTEL
400 MHz USB 2.0
PROCESSOR
14-bit A/D
Up to 4
PS/2
Channels Keyboard
DDR
Mouse
Channels DIGITAL UP-
800 MHz Video
Out CONVERTER Output
16-bit D/A HOST PROCESSOR
INT: 2 to 64K GPS
Up to 4 RUNNING SYSTEMFLOW
Channels Antenna
(Optional)
RAID DATA STORE

MODEL RTS 2707
Figure 63
The Talon RTS 2707 is a turnkey, multiband Included with the system is the SystemFlow Record-
recording and playback system for recording and repro- ing Software. SystemFlow features a Windows-based
ducing high-bandwidth signals. The RTS 2707 uses 12-bit, GUI that provides a simple means to configure and
500 MHz A/D converters and provides sustained recording control the recorder. SystemFlow also includes signal
rates up to 1.6 GB/sec in two-channel configuration. viewing and analysis tools, that allow the user to monitor
the signal prior to, during, and after a recording session.
The RTS 2707 uses Penteks high-powered Virtex-6-based
These tools include a virtual oscilloscope and a virtual
Cobalt modules, that provide flexibility in channel count,
spectrum analyzer.
with optional digital downconversion capabilities. Optional
16-bit, 800 MHz D/A converters with digital upconversion Built on a Windows 7 Professional workstation,
allow real-time reproduction of recorded signals. the RTS 2707 allows the user to install post-processing
and analysis tools to operate on the recorded data. The
A/D sampling rate, DDC decimation and bandwidth,
RTS 2707 records data to the native NTFS file system,
D/A sampling rate and DUC interpolation are among
providing immediate access to the data.
the GUI-selectable system parameters, providing a fully-
programmable system capable of recording and reproducing The RTS 2707 is configured in a 4U 19" rackmount-
a wide range of signals. able chassis, with hot-swappable data drives, front panel
USB ports and I/O connectors on the rear panel. Systems
Optional GPS time and position stamping allows
are scalable to increase channel counts and aggregate data rates.
the user to record this critical signal information.
52
Products
Ultra W ideband One- or TTwo

Wideband wo
wo--Channel RF/IF
RF/IF,, 3.2 GS/sec Rackmount R
Rackmount ecorder
Recorder
Model RTS 2709

Gigabit
Ethernet
Channel 1 USB
In 3.6 GHz
(1 Channel) INTEL
or PROCESSOR eSATA
Channel 2 1.8 GHz
In (2 Channel)
12-Bit A/D Keyboard
DDR
SYSTEM DRIVE SDRAM
Mouse
Video
Output
HOST PROCESSOR
GPS
RUNNING SYSTEMFLOW
Antenna
(Optional)
UP TO 20 TB RAID
MODEL RTS 2709
Figure 64
The Talon RTS 2709 is a turnkey system used for The RTS 2709 includes the SystemFlow Recording
recording extremely high-bandwidth signals. The RTS 2709 Software. SystemFlow features a Windows-based GUI
uses a 12-bit, 3.6 GHz A/D converter and can provide that provides a simple means to configure and control the
sustained recording rates up to 3.2 GB/sec. It can be system. Custom configurations can be stored as profiles
configured as a one- or two-channel system and can record and later loaded when needed, allowing the user to select
sampled data, packed as 8-bit wide consecutive samples, preconfigured settings with a single click.
or as 16-bit wide consecutive samples (12-bit digitized
SystemFlow also includes signal viewing and analysis
samples residing in the 12 MSBs of the 16-bit word.)
tools that allow the user to monitor the signal prior to,
The RTS 2709 uses Penteks high-powered Virtex-6- during, and after a recording session.
based Cobalt boards that provide the data streaming
Built on a Windows 7 Professional workstation,
engine for the high-speed A/D converter. Channel and
the RTS 2709 allows the user to install post-processing
packing modes as well as gate and trigger settings are
among the GUI-selectable system parameters, provid-
RTS 2709 records data to the native NTFS file system
ing complete control over this ultra wideband record-
that provides immediate access to the data. The RTS 2709
ing system.
is configured in a 4U 19" rackmountable chassis, with hot-
Optional GPS time and position stamping allows the user swap data drives, front panel USB ports and I/O
to capture this information in the header of each data file. connectors on the rear panel.
53
Products
Two
wo--Channel 10- Gigabit Ethernet R
10-Gigabit ackmount R
Rackmount ecorder
Recorder
Model RTS 2715
2 Gigabit
Ethernet
Ch 1 6
USB 2.0
In / Out 10G
Ethernet INTEL 2
PROCESSOR eSATA
PS/2
DDR Keyboard
Ch 2 Mouse
In / Out 10G Video
Ethernet Output
HOST PROCESSOR
GPS
RUNNING SYSTEMFLOW
Antenna
(Optional)
UP TO 20 TB RAID
MODEL RTS 2715
Figure 65
The Talon RTS 2715 is a complete turnkey recording loaded as needed, allowing the user to select preconfigured
system for storing one or two 10 gigabit Ethernet (10 GbE) settings with a single click.
streams. It is ideal for capturing any type of streaming sources
Built on a server-class Windows 7 Professional
including live transfers from sensors or data from other computers
workstation, the RTS 2715 allows the user to install
and supports both TCP and UDP protocols. Using highly-
post-processing and analysis tools to operate on the
optimized disk storage technology, the system achieves
recorded data. The RTS 2715 records data to the native
aggregate recording rates up to 2.0 GB/sec.
NTFS file system, providing immediate access to the
Two rear panel SFP+LC connectors for 850 nm multi- data.
mode or single-mode fibre cables, or CX4 connectors for copper
The RTS 2715 is configured in a 4U or 5U 19" rack-
twinax cables accommodate all popular 10 GbE interfaces.
mountable chassis, with hot-swap data drives, front panel
Optional GPS time and position stamping accurately
USB ports and I/O connectors on the rear panel. Systems
identifies each record in the file header.
are scalable to accommodate multiple chassis to increase
The RTS 2715 includes the SystemFlow Recording channel counts and aggregate data rates.
Software. SystemFlow features a Windows-based GUI
All recorder chassis are connected via Ethernet and
(Graphical User Interface) that provides a simple and
can be controlled from a single GUI either locally or
intuitive means to configure and control the system.
from a remote PC.
Custom configurations can be stored as profiles and later
54
Products
roducts
Eight- Channel Serial FPDP R

Eight-Channel ackmount R
Rackmount ecorder
Recorder
Model RTS 2716
2 Gigabit
Ch 1 Ethernet
In / Out Serial
FPDP 6
USB 2.0
Ch 2 INTEL 2
In / Out Serial eSATA
PROCESSOR
FPDP
Ch 3 PS/2
In / Out Serial Keyboard
DDR
FPDP SYSTEM DRIVE SDRAM PS/2
Ch 4 Mouse
In / Out Serial
FPDP Video
Output
Ch 5 HOST PROCESSOR
GPS
In / Out Serial RUNNING SYSTEMFLOW
Antenna
FPDP
(Optional)
Ch 6
In / Out Serial
FPDP
Ch 7
In / Out Serial DATA DRIVES DATA DRIVES
FPDP
Ch 8 DATA DRIVES DATA DRIVES

In / Out Serial
FPDP
UP TO 20 TB RAID
MODEL RTS 2716
Figure 66
The Talon RTS 2716 is a complete turnkey recording 2.125, 2.5, 3.125 and 4.25 GBaud link rates supporting data
system capable of recording and playing multiple serial transfer rates of up to 425 MB/sec per serial FPDP link.
FPDP data streams. It is ideal for capturing any type of
Built on a server-class Windows 7 Professional worksta-
streaming sources including live transfers from sensors
tion, the RTS 2716 allows the user to install post-processing
or data from other computers and is fully compatible
with the VITA 17.1 specification. Using highly-optimized
RTS 2716 records data to the native NTFS file system,
disk storage technology, the system achieves aggregate
providing immediate access to the data.
recording rates up to 3.4 GB/sec.
The RTS 2716 is configured in a 4U or 5U 19" rack-
The RTS 2716 can be populated with up to eight
mountable chassis, with hot-swap data drives, front panel
SFP connectors supporting serial FPDP over copper,
USB ports and I/O connectors on the rear panel. Up to
single-mode, or multi-mode fiber, to accommodate all
24 hot-swappable SATA drives are optionally available,
popular serial FPDP interfaces. It is capable of both
allowing up to 20 terabytes of real-time data storage space
receiving and transmitting data over these links and
in a single chassis.
supports real-time data storage to disk.
The RTS 2716 includes the SystemFlow Recording
Programmable modes include flow control in both
Software, which features a Windows-based GUI that
receive and transmit directions, CRC support, and copy/
provides a simple and intuitive means to configure and
loop modes.The system is capable of handling 1.0625,
control the system.
55
Products
Four
our--Channel RF/IF 200 MS/sec Rugged PPor
Rugged or table R
ortable ecorder
Recorder
Model RTR 2726
HIGH RESOLUTION Aux Video

Channels DIGITAL DOWN
200 MHz VIDEO DISPLAY VGA Output
In CONVERTER
16-bit A/D
DEC: 2 to 64K 1x Gigabit
Up to 4
Channels Ethernet
INTEL CORE i7
PROCESSOR 8x USB 2.0
Channels DIGITAL UP SSD 2x USB 3.0

800 MHz DDR
Out CONVERTER SYSTEM DRIVE
16-bit D/A SDRAM
INT: 2 to 512K
Up to 2 2x eSATA 3
Channels WINDOWS HOST PROCESSOR
SSD DRIVES SSD DRIVES

MODEL RTR 2726
RAID DATA STORE
Figure 67
The Talon RTR 2726 is a turnkey, multiband recording D/A converters, DDCs (Digital Downconverters), DUCs
and playback system designed to operate under conditions (Digital Upconverters), and complementary FPGA IP
of shock and vibration. It allows the user to record and cores. This architecture allows the system engineer to
reproduce high-bandwidth signals with a lightweight, take full advantage of the latest technology in a turnkey
portable and rugged package. The RTR 2726 provides system. Optional GPS time and position stamping allows
sustained recording rates of up to 1.6 GB/sec in a four-channel the user to record this critical signal information.
system and is ideal for the user who requires both
It is built on an extremely rugged, 100% aluminum
portability and solid performance in a compact record-
alloy unit, reinforced with shock absorbing rubber corners
ing system.
and an impact-resistant protective glass. Using vibration
The RTR 2726 is supplied in a small footprint and shock resistant SSDs, the RTR 2726 is designed to
portable package measuring just 16.9" W x 9.5" D x reliably operate as a portable field instrument in harsh
13.4" H and weighing about 30 pounds. With measure- environments.
ments similar to a small briefcase, this portable workstation
The eight hot-swappable SSDs provide a storage
includes an Intel Core i7 processor, a high-resolution
capacity of up to 3.8 TB. The drives can be easily removed
17" LCD monitor, and a high-performance SATA RAID
or exchanged during or after a mission to retrieve recorded
controller.
data. Because SSDs operate reliably under conditions of
At the heart of the RTR 2726 are Pentek Cobalt vibration and shock, the RTR 2726 performs well in
Series Virtex-6 software radio boards featuring A/D and ground, shipborne and airborne environments.
56
Products
Two
wo--Channel RF/IF 500 MS/sec Rugged PPor
Rugged or table R
ortable ecorder
Recorder
Model RTR 2727
500 MHz HIGH RESOLUTION Aux Video

12-bit A/D DIGITAL DOWN-
Channels VIDEO DISPLAY VGA Output
or CONVERTER
In DEC: 2 to 64K 1x Gigabit
400 MHz
14-bit A/D Ethernet
INTEL CORE i7
Up to 2
PROCESSOR 8x USB 2.0
Channels
SSD 2x USB 3.0

DDR
Channel DIGITAL UP- SYSTEM DRIVE
800 MHz SDRAM
Out CONVERTER
16-bit D/A 2x eSATA 3
INT: 2 to 64K
Up to 1 WINDOWS HOST PROCESSOR
Channel

MODEL RTR 2727
RAID DATA STORE
Figure 68
The Talon RTR 2727 is a turnkey, multiband recording D/A converters, DDCs (Digital Downconverters), DUCs
and playback system designed to operate under conditions (Digital Upconverters), and complementary FPGA IP
of shock and vibration. It allows the user to record and cores. This architecture allows the system engineer to
reproduce high-bandwidth signals with a lightweight, take full advantage of the latest technology in a turnkey
portable and rugged package. The RTR 2727 provides system. Optional GPS time and position stamping allows
sustained recording rates of up to 2.0 GB/sec in a two-channel the user to record this critical signal information.
system and is ideal for the user who requires both
It is built on an extremely rugged, 100% aluminum
portability and solid performance in a compact record-
alloy unit, reinforced with shock absorbing rubber corners
ing system.
and an impact-resistant protective glass. Using vibration
The RTR 2727 is supplied in a small footprint and shock resistant SSDs, the RTR 2727 is designed to
portable package measuring just 16.9" W x 9.5" D x reliably operate as a portable field instrument in harsh
13.4" H and weighing about 30 pounds. With measure- environments.
ments similar to a small briefcase, this portable workstation
The eight hot-swappable SSDs provide a storage
includes an Intel Core i7 processor, a high-resolution
capacity of up to 3.8 TB. The drives can be easily removed
17" LCD monitor, and a high-performance SATA RAID
or exchanged during or after a mission to retrieve recorded
controller.
data. Because SSDs operate reliably under conditions of
At the heart of the RTR 2727 are Pentek Cobalt vibration and shock, the RTR 2727 performs well in
Series Virtex-6 software radio boards featuring A/D and ground, shipborne and airborne environments.
57
Products

Eight-Channel ugged PPor
Rugged or table R
ortable ecorder
Recorder
Model RTR 2736
1 Gigabit
Ch 1 Ethernet
In / Out Serial 8
FPDP USB 2.0
2
USB 3.0
Ch 2 INTEL
In / Out Serial 2
PROCESSOR eSATA
FPDP
Ch 3 PS/2
DDR
Ch 4 Mouse
In / Out Serial
FPDP Video
Output
Ch 5 HOST PROCESSOR
GPS
Antenna
FPDP
(Optional)
Ch 6
In / Out Serial
FPDP
Ch 7
FPDP

In / Out Serial
FPDP
UP TO 3.8 TB RAID
MODEL RTR 2736
Figure 69
The Talon RTR 2736 is a complete turnkey recording The RTR 2736 includes the SystemFlow Recording
system designed to operate under conditions of shock and Software. SystemFlow features a Windows-based GUI
vibration. It records and plays back multiple serial FPDP that provides a simple and intuitive means to configure
data streams in a rugged, lightweight portable package. and control the system. Custom configurations can be
It is ideal for capturing any type of streaming sources stored as profiles and later loaded as needed, allowing the
including live transfers from sensors or data from other user to select preconfigured settings with a single click.
computers and is fully compatible with the VITA 17.1
The RTR 2736 is configured in a portable, lightweight
specification. Using highly-optimized disk storage
chassis with eight hot-swap SSDs, front panel USB ports
technology, the system achieves aggregate recording rates
and I/O connections on the side panel. It is built on an
up to 1.6 GB/sec.
extremely rugged, 100% aluminum alloy unit, reinforced
The RTR 2736 can be populated with up to eight with shock absorbing rubber corners and an impact-resistant
SFP connectors supporting serial FPDP over copper, single- protective glass. Using vibration and shock resistant SSDs,
mode, or multi-mode fiber, to accommodate all popular the RTR 2736 is designed to reliably operate as a portable
serial FPDP interfaces. It is capable of both receiving and field instrument in harsh environments.
transmitting data over these links and supports real-time data
The eight hot-swappable SSDs provide storage
storage to disk. The system is capable of handling 1.0625,
capacities of up to 3.8 TB. Drives can be easily removed
2.125, 2.5, 3.125 and 4.25 GBaud link rates supporting
or exchanged during or after a mission to retrieve
data transfer rates of up to 200 MB/sec per serial FPDP link.
recorded data.
58
Products
Eight- Channel RF/IF 200 MS/Sec R

Eight-Channel ugged R
Rugged ackmount R
Rackmount ecorder
Recorder
Model RTR 2746
2 Gigabit
Ethernet
Channels 200 MHz DIGITAL 6
DOWN- USB 2.0
In 16-bit A/D
Up to 8 CONVERTER
INTEL 2
Channels Decimation: eSATA
PROCESSOR
2 to 65,536
PS/2
DDR Keyboard
Channels 800 MHz DIGITAL Mouse
Out or 1.25 GHz UP- Video
16-bit D/A CONVERTER Output
Up to 8 Decimation: HOST PROCESSOR
Channels GPS
2 to 65,536 RUNNING SYSTEMFLOW
Antenna
(Optional)
UP TO 12 TB RAID
MODEL RTR 2746
Figure 70
The Talon RTR 2746 is a turnkey multiband recording The 24 hot-swappable SSDs provide storage capacity
and playback system designed to operate under conditions of up to 12 TB. The drives can be easily removed or
of shock and vibration. The RTR 2746 is intended for exchanged during or after a mission to retrieve recorded
military, airborne, and UAV applications requiring a rugged data. Because SSDs operate reliably under conditions of
system. With scalable A/Ds, D/As and SSD (solid-state vibration and shock, the RTR 2746 performs well in
drive) storage, the RTR 2746 can be configured to stream ground, shipborne and airborne environments.
data to and from disk at rates as high as 2.0 GB/sec.
The RTR 2746 is configured in a 4U 19" rugged
The RTR 2746 uses Penteks high-performance rackmountable chassis, with hot-swap data drives, front
Virtex-6-based Cobalt boards, that provide flexibility in panel USB ports and I/O connectors on the rear panel.
channel count with optional digital downconversion
All recorder chassis are connected via Ethernet and can
capabilities. Optional 16-bit, 800 MHz or 1.25 GHz D/A
be controlled from a single GUI either locally or from a
converters with digital upconversion allow real-time
remote PC. Multiple RAID levels, including 0, 1, 5, 6, 10,
reproduction of recorded signals.
and 50, provide a choice for the required level of redundancy.
Systems are scalable to accommodate multiple chassis
D/A sampling rate, and DUC interpolation are among the
to increase channel counts and aggregate data rates.
GUI-selectable system parameters, that provide a fully
programmable system.
59
Products
Four
our--Channel RF/IF 500 MS/Sec Rugged R
Rugged ackmount R
Rackmount ecorder
Recorder
Model RTR 2747
500 MHz
12-bit A/D DIGITAL DOWN- Gigabit
Channels CONVERTER Ethernet
or
In DEC: 2 to 64K INTEL
400 MHz USB 2.0
PROCESSOR
14-bit A/D
Up to 4
PS/2
Channels Keyboard
DDR
Mouse
Channels DIGITAL UP-
800 MHz Video
Out CONVERTER Output
16-bit D/A HOST PROCESSOR
INT: 2 to 64K GPS
Up to 4 RUNNING SYSTEMFLOW
Channels Antenna
(Optional)
RAID DATA STORE

MODEL RTR 2747
Figure 71
The Talon RTR 2747 is a turnkey multiband recording The hot-swappable SSDs provide storage capacity of
and playback system designed to operate under conditions up to 11.5 TB. The drives can be easily removed or
of shock and vibration. The RTR 2747 is intended for exchanged during or after a mission to retrieve recorded
military, airborne, and UAV applications requiring a rugged data. Because SSDs operate reliably under conditions of
system. With scalable A/Ds, D/As and SSD (solid-state vibration and shock, the RTR 2747 performs well in
drive) storage, the RTR 2747 can be configured to stream ground, shipborne and airborne environments.
data to and from disk at rates as high as 4.0 GB/sec.
The RTR 2747 is configured in a 4U 19" rugged
The RTR 2747 uses Penteks high-performance rackmountable chassis, with hot-swap data drives, front
Virtex-6-based Cobalt boards, that provide flexibility in panel USB ports and I/O connectors on the rear panel.
channel count with optional digital downconversion
All recorder chassis are connected via Ethernet and can
capabilities. Optional 16-bit, 800 MHz converters with
be controlled from a single GUI either locally or from a
digital upconversion allow real-time reproduction of
remote PC. Multiple RAID levels, including 0, 1, 5, 6, 10,
recorded signals.
and 50, provide a choice for the required level of redundancy.
Systems are scalable to accommodate multiple chassis
D/A sampling rate, and DUC interpolation are among the
to increase channel counts and aggregate data rates.
GUI-selectable system parameters, that provide a fully
programmable system.
60
Products
Ultra W ideband One- or TTwo

Wideband wo
wo--Channel RF/IF
RF/IF,, 3.2 GS/sec Rugged R
Rugged ackmount R
Rackmount ecorder
Recorder
Model RTR 2749
Gigabit
Ethernet
Channel 1 USB
In 3.6 GHz
(1 Channel) INTEL
or PROCESSOR eSATA
Channel 2 1.8 GHz
In (2 Channel)
12-Bit A/D Keyboard
DDR
SYSTEM DRIVE SDRAM
Mouse
Video
Output
HOST PROCESSOR
GPS
RUNNING SYSTEMFLOW
Antenna
(Optional)
UP TO 20 TB RAID
MODEL RTR 2749
Figure 72
Designed to operate under conditions of shock and The RTR 2749 includes the SystemFlow Recording
vibration, the Talon RTR 2749 is a turnkey system used for Software. SystemFlow features a Windows-based GUI
recording extremely high-bandwidth signals. The RTR 2749 that provides a simple means to configure and control the
uses a 12-bit, 3.6 GHz A/D converter and can provide system. Custom configurations can be stored as profiles
sustained recording rates up to 3.2 GB/sec. It can be and later loaded when needed, allowing the user to select
configured as a one- or two-channel system and can record preconfigured settings with a single click. SystemFlow
sampled data, packed as 8-bit wide consecutive samples, also includes signal viewing and analysis tools that allow
or as 16-bit wide consecutive samples (12-bit digitized the user to monitor the signal prior to, during, and after
samples residing in the 12 MSBs of the 16-bit word.) a recording session.
The RTR 2749 uses Penteks high-performance Built on a Windows 7 Professional workstation,
Virtex-6-based Cobalt boards that provide the data the RTR 2749 allows the user to install post-processing
streaming engine for the high-speed A/D converter. and analysis tools to operate on the recorded data.
Channel and packing modes as well as gate and trigger The hot-swappable SSDs provide a storage capacity of up
settings are among the GUI-selectable system parameters, to 19.2 TB. The drives can be easily removed or exchanged
providing complete control over this ultra-wideband during or after a mission to retrieve recorded data. Because
recording system. Optional GPS time and position stamping SSDs operate reliably under conditions of vibration
allows the user to capture this information in the header of and shock, the RTR 2749 performs well in ground,
each data file. shipborne and airborne environments.
61
Products
Two
wo--Channel 10- Gigabit Ethernet R
10-Gigabit ugged R
Rugged ackmount R
Rackmount ecorder
Recorder
Model RTR 2755
2 Gigabit
Ethernet
Ch 1 6
USB 2.0
In / Out 10G
Ethernet INTEL 2
PROCESSOR eSATA
PS/2
SSD Keyboard
DDR
SYSTEM DRIVE
SDRAM PS/2
Ch 2 Mouse
In / Out 10G Video
Ethernet Output
WINDOWS HOST PROCESSOR GPS
Antenna
(Optional)
RAID DATA STORE
MODEL RTR 2755
Figure 73
Designed to operate under conditions of shock and The RTR 2755 includes the SystemFlow Recording
vibration, the Talon RTR 2755 is a complete turnkey Software that provides a simple and intuitive means to
recording system for storing one or two 10 gigabit Ethernet configure and control the system. Custom configurations can
(10 GbE) streams. It is ideal for capturing any type of be stored as profiles and later loaded as needed, allowing the
streaming sources including live transfers from sensors or data user to select preconfigured settings with a single click.
from other computers and supports both TCP and UDP
Built on a server-class Windows 7 Professional
protocols.
workstation, the RTR 2755 allows the user to install
Using highly-optimized solid-state drive storage post-processing and analysis tools to operate on the
technology, the system guarantees loss-free performance recorded data. The RTR 2755 records data to the native
at aggregate recording rates up to 2.0 GB/sec. NTFS file system, providing immediate access to the
recorded data.
Two rear panel SFP+ LC connectors for 850 nm
multi-mode or single-mode fibre cables, or CX4 connec- Because SSDs operate reliably under conditions of
tors for copper twinax cables accommodate all popular vibration and shock, the RTR 2755 performs well in
10 GbE interfaces. ground, shipborne and airborne environments. The 24 hot-
swappable SSDs provide a storage capacity of up to 12 TB.
Optional GPS time and position stamping accurately The drives can be easily removed or exchanged during or
identifies each record in the file header. after a mission to retrieve recorded data.
62
Products

Eight-Channel ugged R
Rugged ackmount R
Rackmount ecorder
Recorder
Model RTR 2756
2 Gigabit
Ch 1 Ethernet
In / Out Serial
FPDP 6
USB 2.0
Ch 2 INTEL 2
In / Out Serial eSATA
PROCESSOR
FPDP
Ch 3 PS/2
DDR
Ch 4 Mouse
In / Out Serial
FPDP Video
Output
Ch 5 HOST PROCESSOR
GPS
Antenna
FPDP
(Optional)
Ch 6
In / Out Serial
FPDP
Ch 7
FPDP

In / Out Serial
FPDP
UP TO 20 TB RAID
MODEL RTR 2756
Figure 74
Designed to operate under conditions of shock and Built on a server-class Windows 7 Professional worksta-
vibration, the Talon RTR 2756 is a complete turnkey tion, the RTR 2756 allows the user to install post-processing
recording system capable of recording and playing and analysis tools to operate on the recorded data. The
multiple serial FPDP data streams. It is ideal for capturing RTR 2756 records data to the native NTFS file system,
any type of streaming sources and is fully compatible providing immediate access to the data.
with the VITA 17.1 specification. Using highly-optimized
Because SSDs operate reliably under conditions of
disk storage technology, the system achieves aggregate
vibration and shock, the RTR 2756 performs well in
recording rates up to 3.4 GB/sec.
ground, ship and airborne environments. Configurable
The RTR 2756 can be populated with up to eight with as many as 40 hot-swappable SSDs, the RTR 2756
SFP connectors supporting serial FPDP over copper, can provide storage capacities of up to 19.2 TB in a rugged
single-mode, or multi-mode fiber to accommodate all 4U chassis. Drives can be easily removed or exchanged
popular serial FPDP interfaces. It is capable of both during or after a mission to retrieve recorded data.
receiving and transmitting data over these links and
Multiple RAID levels, including 0,1,5, 6, 10 and 50
supports real-time data storage to disk. The system is
provide a choice for the required level on redundancy.
capable of handling 1.0625, 2.125, 2.5, 3.125 and 4.25
Redundant power supplies are optionally available to
GBaud link rates supporting data transfer rates of up to
provide a robust and reliable high-performance recording
425 MB/sec per serial FPDP link.
system.
63
Products
Four
our--Channel RF/IF 200 MS/Sec Extreme 3U VPX Recorder
Recorder
Model RTX 2786
DIGITAL
CH 1 200 MHz DOWN- 2 Gigabit
In 16-bit A/D CONVERTER Ethernet
DIGITAL INTEL 4 USB 2.0

CH 2 200 MHz PROCESSOR
DOWN-
In 16-bit A/D CONVERTER
DIGITAL
CH 3 200 MHz DDR
DOWN- SYSTEM DRIVE
In 16-bit A/D SDRAM
CONVERTER
Video
Output
A DIGITAL HOST PROCESSOR
Out 800 MHz
16-bit D/A UPCONVERTER
A
Sample Clk / DATA DRIVES DATA DRIVES

Reference In
CLOCK & PROGRAM
SYNC VCXO
GENERATOR DATA DRIVES DATA DRIVES
MODEL
53621 RAID
MODEL RTX 2786

Three Record Channels and One Playback Channel.
Figure 75
The Talon RTX 2786 is a turnkey, RF/IF signal The RTX 2786 includes Penteks SystemFlow
recorder designed to operate under extreme environmen- Recording Software. SystemFlow features a Windows-
tal conditions. Housed in a ATR chassis, the RTX based GUI that provides a simple means to configure
2786 leverages Penteks 3U VPX SDR modules to provide a and control the system. Custom configurations can be
rugged recording system with up to four 16-bit, 200 MHz stored as profiles and later loaded when needed, allowing
A/D converters with built-in digital downconversion the user to select preconfigured settings with a single click.
capabilities. Optionally, the RTX 2786 provides one SystemFlow also includes signal viewing and analysis
800 MHz, 16-bit D/A converter with a digital upconverter tools, that allow the user to monitor the signal prior to,
for signal playback or waveform generation. As shown in during, and after a recording session. These tools include a
the block diagram, the maximum number of record channels virtual oscilloscope and a virtual spectrum analyzer.
with this option is three.
The user API allows users to integrate the recorder as
The RTX 2786 uses conduction cooling to draw heat a subsystem of a larger system. The API is provided as a C-
from the system components allowing it to operate in reduced callable library and allows for the recorder to be controlled
air environments. It includes 1.92 TB of solid-state data over Ethernet, thus providing the ability to remotely
storage, that allows it to operate with no degradation under control the recorder from a custom interface.
conditions of extreme shock and vibration. The system is
Four built-in solid-state drives provide reliable, high-
hermetically sealed and provides five D38999 connectors
speed storage with a total capacity of 1.92 TB.
for power and I/O with four SMA connectors for analog I/O.
64
Products
Pentek SystemFlow Recording Sof

Recording tware for Analog R
Software ecorders
Recorders
Recorder Interface Hardware Configuration

Interface
Signal Viewer
Figure 76
The Pentek SystemFlow Recording Software for Analog The SystemFlow Signal Viewer includes a virtual
Recorders provides a rich set of function libraries and tools oscilloscope and spectrum analyzer for signal monitoring
for controlling all Pentek high-speed real-time recording in both the time and frequency domains. It is extremely
systems. SystemFlow software allows developers to useful for previewing live inputs prior to recording, and
configure and customize system interfaces and behavior. for monitoring signals as they are being recorded to help
ensure successful recording sessions. The viewer can also
The Recorder Interface includes configuration, record,
be used to inspect and analyze the recorded files after
playback and status screens, each with intuitive controls
the recording is complete.
and indicators. The user can easily move between screens
to set configuration parameters, control and monitor a Advanced signal analysis capabilities include automatic
recording, play back a recorded signal and monitor calculators for signal amplitude and frequency, second
board temperatures and voltage levels. and third harmonic components, THD (total harmonic
distortion) and SINAD (signal to noise and distortion).
The Hardware Configuration Interface provides
With time and frequency zoom, panning modes and dual
entries for input source, center frequency, decimation, as
annotated cursors to mark and measure points of interest,
well as gate and trigger information. All parameters
the SystemFlow Signal Viewer can often eliminate the
contain limit-checking and integrated help to provide an
need for a separate oscilloscope or spectrum analyzer in
easier-to-use out-of-the-box experience.
the field.
65
Products
Pentek SystemFlow Recording Sof

Recording tware for Digital R
Software ecorders
Recorders
Hardware Configuration
Configure Screen
Recording and Playback Screen
Figure 77
The SystemFlow Software for Digital Resorders The Recording and Playback Screen allows you to
provides the user with a control interface for the recording browse a folder and enter a file name for the recording.
system. It includes Configuration, Record, Playback, and The length of the recording for each channel can be
Status screens, each with intuitive controls and indicators. specified in megabytes or in seconds. Intuitive buttons
for Record, Pause and Stop simplify operation. Status
The user can easily move between screens to set
indicators for each channel display the mode, the number
configuration parameters, control and monitor a recording,
of recorded bytes, and the average data rate. A Data Loss
and play back a recorded stream. All parameters contain
indicator alerts the user to any problem, such as a disk-
limit-checking and integrated help to provide an easier-to-
full condition.
use out-of-the-box experience.
By checking the Master Record boxes, any combina-
The Configure Screen shows a block diagram of
tion of channels in the lower screen can be grouped for
the system, and presents operational system parameters
synchronous recording via the upper Master Record screen.
including temperature and voltages. Parameters are
The recording time can be specified, and monitoring
entered for each input or output channel specifying
functions inform the operator of recording progress.
UDP or TCP protocol, client or server connection, the
IP address and port number.
66
Applications
64- Channel Sof

64-Channel tware R
Software adio R
Radio ecording System
Recording
Input A
200 MHz
A/D
Input B
200 MHz
A/D FPGA 2 Gigabit
with
Input C Ethernet
200 MHz 4 banks of
A/D 8-Channel 6
USB 2.0
DDC
Input D INTEL
200 MHz x8 PCIe 2
PROCESSOR eSATA
A/D
PS/2
Pentek Cobalt 78622 PCIe Board DDR
SYSTEM DRIVE Keyboard
SDRAM
PS/2
Mouse
Video
Input A x8 PCIe
200 MHz HOST PROCESSOR Output
A/D GPS
Input B Antenna
200 MHz
A/D FPGA
with
Input C
200 MHz 4 banks of
A/D 8-Channel
DDC
Input D DATA DRIVES DATA DRIVES
200 MHz
A/D
Pentek Cobalt 78622 PCIe Board
UP TO 20 TB RAID
Figure 78
Shown above is a 64-channel recording system utilizing Each DDC delivers a complex output stream consist-
two Pentek Cobalt 78662 PCIe boards. The 78662 ing of 24-bit I + 24-bit Q samples at a rate of s/N. Any
samples four input channels at up to 200 megasamples number of channels can be enabled within each bank,
per second, thereby accommodating input signals with selectable from 0 to 8. Each bank includes an output
up to 80 MHz bandwidth. sample interleaver that delivers a channel-multiplexed
stream for all enabled channels within a bank.
Factory-installed in the FPGA of each 78662 is a
powerful DDC IP core containing 32 channels. Each of An internal timing bus provides all timing and synchro-
the 32 channels has an independent 32-bit tuning nization required by the eight A/D converters. It includes
frequency setting that ranges from DC to s, where s is a clock, two sync and two gate or trigger signals. An on-
the A/D sampling frequency. All of the 8 channels board clock generator receives an external sample clock.
within each bank share a common decimation setting This clock can be used directly by the A/D or divided by
that can range from 16 to 8192, programmable in steps a built-in clock synthesizer circuit.
of 8. For example, with a sampling rate of 200 MHz, the
Built on a Windows 7 Professional workstation with
available output bandwidths range from 19.53 kHz to
high performance Intel CoreTM i7 processor this system
10.0 MHz. Each 8-channel bank can have its own
allows the user to install post processing and analysis
unique decimation setting supporting a different band-
tools to operate on the recorded data. The system records
width associated with each of the four acquisition modules.
data to the native NTFS file system, providing immediate
The decimating filter for each DDC bank accepts access to the recorded data.
a unique set of user-supplied 18-bit coefficients. The 80%
Included with this system is Penteks SystemFlow
recording software. Optional GPS time and position
where N is the decimation setting. The rejection of
stamping allows the user to record this critical signal
adjacent-band components within the 80% output
information.
bandwidth is better than 100 dB.
67
Applications
L-Band Signal PProcessing

rocessing System
Analog Digital
Analog Mixer
L-Band Analog Baseband I
LNA Lowpass A/D
Filter
Baseband Amps
VIRTEX-6
Analog Mixer
RF Input Analog FPGA
Lowpass Baseband Q
A/D
Filter
Q I
Analog Local
Oscillator Maxim
Synthesizer MAX2112 x8 PCIe
Pentek 78690 PCIe Board
WINDOWS
PC
Figure 79
The Cobalt Model 78690 L-Band RF Tuner targets The complex I and Q outputs are digitized by two
reception and processing of digitally-modulated RF 200 MHz 16-bit A/D converters operating synchronously.
signals such as satellite television and terrestrial wireless
The Virtex-6 FPGA is a powerful resource for
communications. The 78690 requires only an antenna
recovering and processing a wide range of signals
and a host computer to form a complete L-band SDR
while supporting decryption, decoding, demodula-
development platform.
tion, detection, and analysis. It is ideal for intercepting
This system receives L-Band signals between 925 MHz or monitoring traffic in SIGINT and COMINT
and 2175 MHz directly from an antenna. Signals above applications. Other applications that benefit include
this range such as C Band, Ku Band and K band can be mobile phones, GPS, satellite terminals, military telem-
downconverted to L-Band through an LNB (Low Noise etry, digital video and audio in TV broadcasting satellites,
Block) downconverter installed in the receiving antenna. and voice, video and data communications.
The Maxim Max2112 L-Band Tuner IC features a This L-Band signal processing system is ideal as a
low-noise amplifier with programmable gain from 0 to front end for government and military systems. Its small
65 dB and a synthesized local oscillator programmable size adderesses space-limited applications. Ruggedized
from 925 to 2175 MHz. The complex analog mixer options are also available from Pentek with the Models
translates the input signals down to DC. Baseband 71690 XMC module and the 53690 OpenVPX board to
amplifiers provide programmable gain from 0 to 15 dB address UAV applications and other severe environments.
in steps of 1 dB. The bandwidth of the baseband lowpass
Development support for this system is provided by
filters can be programmed from 4 to 40 MHz . The
the Pentek ReadyFlow board support package for Windows,
Maxim IC accommodates full-scale input levels of -50 dBm
Linux and VxWorks. Also available is the Pentek GateFlow
to +10 dbm and delivers I and Q complex baseband outputs.
FPGA Design Kit to support custom algorithm development.
68
Applications
8- Channel OpenVPX Beamforming System

8-Channel
VPX P1
Slot 1 VPX
Model 53661 4X Sum In BACKPLANE
AURORA EP01
BEAMFORM
4X Sum Out
SUMMATION
EP02
4X Aurora
200 MHz DDC 1 FP C
RF Tuner 16-bit A/D G + Phase
x4 PCIe x4 PCIe
200 MHz DDC 2 DP01
RF Tuner 16-bit A/D G + Phase x4
PCIe
200 MHz DDC 3
RF Tuner I/F
16-bit A/D G + Phase
200 MHz DDC 4 VPX P1

RF Tuner 16-bit A/D G + Phase VPX P1
Slot 3 CPU
Slot 2
Model 53661 4X Sum In

AURORA EP01 FP A
BEAMFORM 4X Sum Out
SUMMATION
EP02 FP B
OpenVPX
CPU
200 MHz DDC 1 FPC DP02 Board
x4 PCIe x4 PCIe
200 MHz DDC 2 DP01 DP01
RF Tuner 16-bit A/D
x4
G + Phase
PCIe
200 MHz DDC 3 I/F
200 MHz DDC 4

Figure 80
Two Model 53661 boards are installed in slots 1 and The first four signal channels are processed in the
2 of an OpenVPX backplane, along with a CPU board upper left 53661 board in VPX slot 1, where the 4-channel
in slot 3. Eight dipole antennas designed for receiving beamformed sum is propagated through the 4X Aurora
2.5 GHz signals feed RF Tuners containing low noise Sum Out link across the backplane to the 4X Aurora Sum
amplifiers, local oscillators and mixers. The RF Tuners In port on the second 53661 in slot 2. The 4-channel local
translate the 2.5 GHz antenna frequency signal down summation from the second 53661 is added to the propa-
to an IF frequency of 50 MHz. gated sum from the first board to form the complete 8-channel
sum. This final sum is sent across the x4 PCIe link to the
The 200 MHz 16-bit A/Ds digitize the IF signals
CPU card in slot 3.
and perform further frequency downconversion to baseband,
with a DDC decimation of 128. This provides I+Q complex Assignment of the three OpenVPX 4X links on the
output samples with a bandwidth of about 1.25 MHz. Phase Model 53661 boards is simplified through the use of a
and gain coefficients for each channel are applied to crossbar switch which allows the 53661 to operate with
steer the array for directionality. a wide variety of different backplanes.
The CPU board in VPX slot 3 sends commands Because OpenVPX does not restrict the use of serial
and coefficients across the backplane over two x4 PCIe protocols across the backplane links, mixed protocol
links, or OpenVPX fat pipes. architectures like the one shown are fully supported.
69
Applications
8- Channel OpenVPX Beamforming Demo system

8-Channel
Beamforming Demo Control Panel Theoretical 7-lobe Beamforming Patern Real-Life Beamforming Patern
Figure 81
Beamforming Demo System sensitivity across arrival angles from -90O to +90O
perpendicular to the plane of the array.
The beamforming demo system is equipped with a
Control Panel that runs under Windows on the CPU The classic 7-lobe pattern for an ideal 8-element
board. It includes an automatic signal scanner to detect array for a signal arriving at 0O angle (directly in front of
the strongest signal frequency arriving from a test the array) is shown above. Below the lobe pattern is a
transmitter. This frequency is centered around the polar plot showing a single vector pointing to the
50 MHz IF frequency of the RF downconverter. Once computed angle of arrival. This is derived from identify-
the frequency is identified, the eight DDCs are set ing the lobe with the maximum response.
accordingly to bring that signal down to 0 Hz for
summation. An actual plot of a real-life transmitter is also shown
for a source directly in front of the display. In this case
The control panel software also allows specific the perfect lobe pattern is affected by physical objects,
hardware settings for all of the parameters for the eight reflections, cable length variations and minor differences
channels including gain, phase, and sync delay. in the antennas. Nevertheless, the directional information
is computed quite well. As the signal source is moved left
An additional display shows the beam-formed pattern of
and right in front of the array, the peak lobe moves with
the array. This display is formed by adjusting the phase
it, changing the computed angle of arrival.
shift of each of the eight channels to provide maximum
This demo system is available online at Pentek. If
you are interested in viewing a live demonstration, please
let us know of your interest by clicking on this link:
Beamforming Demo.
70
Links
The following links provide you with additional information about the Pentek products
presented in this handbook: just click on the model number. Links are also provided to other
handbooks or catalogs that may be of interest in your software radio development projects.
Model Description Page

7142 Multichannel Transceiver with Virtex-4 FPGAs - PMC/XMC 19
7242 Multichannel Transceiver with Virtex-4 FPGAs - 6U cPCI 19
7342 Multichannel Transceiver with Virtex-4 FPGAs - 3U cPCI 19
7642 Multichannel Transceiver with Virtex-4 FPGAs - PCI 19
7742 Multichannel Transceiver with Virtex-4 FPGAs - Full-length PCIe 19
7842 Multichannel Transceiver with Virtex-4 FPGAs - Half-length PCIe 19
5342 Multichannel Transceiver with Virtex-4 FPGAs - 3U VPX 19
7142-428 Multichannel Transceiver w. Four Multiband DDCs and Interpolation Filter - PMC/XMC 20
7242-428 Multichannel Transceiver w. Four Multiband DDCs and Interpolation Filter- 6U cPCI 20
7342-428 Multichannel Transceiver w. Four Multiband DDCs and Interpolation Filter- 3U cPCI 20
7642-428 Multichannel Transceiver w. Four Multiband DDCs and Interpolation Filter- PCI 20
7742-428 Multichannel Transceiver w. Four Multiband DDCs and Interpolation Filter- Full-length PCIe 20
7842-428 Multichannel Transceiver w. Four Multiband DDCs and Interpolation Filter- Half-length PCIe 20
5342-428 Multichannel Transceiver w. Four Multiband DDCs and Interpolation Filter- 3U VPX 20
7150 Quad 200 MHz, 16-bit A/D with Virtex-5 FPGAs - PMC/XMC 21
7250 Quad 200 MHz, 16-bit A/D with Virtex-5 FPGAs - 6U cPCI 21
7350 Quad 200 MHz, 16-bit A/D with Virtex-5 FPGAs - 3U cPCI 21
7650 Quad 200 MHz, 16-bit A/D with Virtex-5 FPGAs - PCI 21
7750 Quad 200 MHz, 16-bit A/D with Virtex-5 FPGAs - Full-length PCIe 21
7850 Quad 200 MHz, 16-bit A/D with Virtex-5 FPGAs - Half-length PCIe 21
5350 Quad 200 MHz, 16-bit A/D with Virtex-5 FPGAs - 3U VPX 21
7151 256-Channel DDC with Quad 200 MHz, 16-bit A/D - PMC 22
7251 256-Channel DDC with Quad 200 MHz, 16-bit A/D - 6U cPCI 22
7651 256-Channel DDC with Quad 200 MHz, 16-bit A/D - PCI 22
7751 256-Channel DDC with Quad 200 MHz, 16-bit A/D - Full-length PCIe 22
7851 256-Channel DDC with Quad 200 MHz, 16-bit A/D - Half-length PCIe 22
5351 256-Channel DDC with Quad 200 MHz, 16-bit A/D - 3U VPX 22
7152 32-Channel DDC with Quad 200 MHz, 16-bit A/D - PMC 23
7153 4-Channel DDC with Quad 200 MHz, 16-bit A/D - PMC/XMC 24
More links on the next page
71
Links

7156 Dual SDR Transceiver, 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - PMC/XMC 25
7256 Dual SDR Transceiver, 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - 6U cPCI 25
7656 Dual SDR Transceiver, 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - PCI 25
7756 Dual SDR Transceiver, 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - Full-length PCIe 25
7856 Dual SDR Transceiver, 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - Half-length PCIe 25
5356 Dual SDR Transceiver, 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - 3U VPX 25
7158 Dual SDR Transceiver, 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - PMC/XMC 26
7658 Dual SDR Transceiver, 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - PCI 26
7758 Dual SDR Transceiver, 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - Full-length PCIe 26
7858 Dual SDR Transceiver, 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - Half-length PCIe 26
5358 Dual SDR Transceiver, 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - 3U VPX 26
71620 3-Channel 200 MHz A/D, DUC, 2-Channel 800 MHz D/A, Virtex-6 FPGA - XMC 27
78620 3-Channel 200 MHz A/D, DUC, 2-Channel 800 MHz D/A, Virtex-6 FPGA - PCIe 27
53620 3-Channel 200 MHz A/D, DUC, 2-Channel 800 MHz D/A, Virtex-6 FPGA - 3U VPX 27
56620 3-Channel 200 MHz A/D, DUC, 2-Channel 800 MHz D/A, Virtex-6 FPGA - AMC 27
72620 3-Channel 200 MHz A/D, DUC, 2-Channel 800 MHz D/A, Virtex-6 FPGA - 6U cPCI 27
74620 6-Channel 200 MHz A/D, DUC, 4-Channel 800 MHz D/A, Two Virtex-6 FPGAs - 6U cPCI 27
GateXpress for FPGA-PCIE Configuration Management 29
71621 3-Channel 200 MHz A/D, DUC, 2-Channel 800 MHz D/A, Installed IP Cores - XMC 30
78621 3-Channel 200 MHz A/D, DUC, 2-Channel 800 MHz D/A, Installed IP Cores - PCIe 30
53621 3-Channel 200 MHz A/D, DUC, 2-Channel 800 MHz D/A, Installed IP Cores - 3U VPX 30
56621 3-Channel 200 MHz A/D, DUC, 2-Channel 800 MHz D/A, Installed IP Cores - AMC 30
72621 3-Channel 200 MHz A/D, DUC, 2-Channel 800 MHz D/A, Installed IP Cores - 6U cPCI 30
78630 1 GHz A/D, 1 GHz D/A, Virtex-6 FPGA - PCIe 31
71630 1 GHz A/D, 1 GHz D/A, Virtex-6 FPGA - XMC 31
53630 1 GHz A/D, 1 GHz D/A, Virtex-6 FPGA - 3U VPX 31
56630 1 GHz A/D, 1 GHz D/A, Virtex-6 FPGA - AMC 31
72630 1 GHz A/D, 1 GHz D/A, Virtex-6 FPGA - 6U cPCI 31
73630 1 GHz A/D, 1 GHz D/A, Virtex-6 FPGA - 3U cPCI 31
74630 Two 1 GHz A/Ds, Two 1 GHz D/As, Two Virtex-6 FPGAs - 6U cPCI 31
72
Links

72640 1-Channel 3.6 GHz and 2-Channel 1.8 GHz, 12-bit A/D, Virtex-6 FPGA - 6U cPCI 32
73640 1-Channel 3.6 GHz and 2-Channel 1.8 GHz, 12-bit A/D, Virtex-6 FPGA - 3U cPCI 32
74640 2-Channel 3.6 GHz and 4-Channel 1.8 GHz, 12-bit A/D, Virtex-6 FPGAs - 6U cPCI 32
71640 1-Channel 3.6 GHz and 2-Channel 1.8 GHz, 12-bit A/D, Virtex-6 FPGA - XMC 32
78640 1-Channel 3.6 GHz and 2-Channel 1.8 GHz, 12-bit A/D, Virtex-6 FPGA - PCIe 32
53640 1-Channel 3.6 GHz and 2-Channel 1.8 GHz, 12-bit A/D, Virtex-6 FPGA - 3U VPX 32
56640 1-Channel 3.6 GHz and 2-Channel 1.8 GHz, 12-bit A/D, Virtex-6 FPGA - AMC 32
56641 1-Channel 3.6 GHz and 2-Channel 1.8 GHz, 12-bit A/D, DDC, Virtex-6 FPGA - AMC 33
71641 1-Channel 3.6 GHz and 2-Channel 1.8 GHz, 12-bit A/D, DDC, Virtex-6 FPGA - XMC 33
78641 1-Channel 3.6 GHz and 2-Channel 1.8 GHz, 12-bit A/D, DDC, Virtex-6 FPGAs - PCIe 33
53641 1-Channel 3.6 GHz and 2-Channel 1.8 GHz, 12-bit A/D, DDC, Virtex-6 FPGA - 3U VPX 33
72641 1-Channel 3.6 GHz and 2-Channel 1.8 GHz, 12-bit A/D, DDC, Virtex-6 FPGA - 6U cPCI 33
73641 1-Channel 3.6 GHz and 2-Channel 1.8 GHz, 12-bit A/D, DDC, Virtex-6 FPGA - 3U cPCI 33
74641 2-Channel 3.6 GHz and 4-Channel 1.8 GHz, 12-bit A/D, DDCs, Virtex-6 FPGA - 6U cPCI 33
72651 2-Channel 500 MHz A/D, with DDCs, DUC, 2-Channel 800 MHz D/A, Virtex-6 FPGA - 6U cPCI 35
73651 2-Channel 500 MHz A/D, with DDCs, DUC, 2-Channel 800 MHz D/A, Virtex-6 FPGA - 3U cPCI 35
74651 4-Channel 500 MHz A/D, with DDCs, DUCs, 4-Channel 800 MHz D/A, Virtex-6 FPGA- 6U cPCI 35
71651 2-Channel 500 MHz A/D, with DDCs, DUC, 2-Channel 800 MHz D/A, Virtex-6 FPGA - XMC 35
78651 2-Channel 500 MHz A/D, with DDCs, DUC, 2-Channel 800 MHz D/A, Virtex-6 FPGA - PCIe 35
53651 2-Channel 500 MHz A/D, with DDCs, DUC, 2-Channel 800 MHz D/A, Virtex-6 FPGA - 3U VPX 35
56651 2-Channel 500 MHz A/D, with DDCs, DUC, 2-Channel 800 MHz D/A, Virtex-6 FPGA - AMC 35
71660 4-Channel 200 MHz 16-bit A/D with Virtex-6 FPGA - XMC 36
78660 4-Channel 200 MHz 16-bit A/D with Virtex-6 FPGA - PCIe 36
53660 4-Channel 200 MHz 16-bit A/D with Virtex-6 FPGA - 3U VPX 36
56660 4-Channel 200 MHz 16-bit A/D with Virtex-6 FPGA - AMC 36
72660 4-Channel 200 MHz 16-bit A/D with Virtex-6 FPGA - 6U cPCI 36
73660 4-Channel 200 MHz 16-bit A/D with Virtex-6 FPGAs - 3U cPCI 36
74660 8-Channel 200 MHz 16-bit A/D with Two Virtex-6 FPGAs - 6U cPCI 36
71760 4-Channel 200 MHz 16-bit A/D with Virtex-7 FPGA - XMC 37
78760 4-Channel 200 MHz 16-bit A/D with Virtex-7 FPGA - PCIe 37
53760 4-Channel 200 MHz 16-bit A/D with Virtex-7 FPGA - 3U VPX 37
56760 4-Channel 200 MHz 16-bit A/D with Virtex-7 FPGA - AMC 37
74760 8-Channel 200 MHz 16-bit A/D with Two Virtex-7 FPGAs - 6U cPCI 37
73
Links

71661 4-Channel 200 MHz 16-bit A/D with Installed IP Cores - XMC 38
78661 4-Channel 200 MHz 16-bit A/D with Installed IP Cores - PCIe 38
53661 4-Channel 200 MHz 16-bit A/D with Installed IP Cores - 3U VPX 38
56661 4-Channel 200 MHz 16-bit A/D with Installed IP Cores - AMC 38
72661 4-Channel 200 MHz 16-bit A/D with Installed IP Cores - 6U cPCI 38
78662 4-Channel 200 MHz 16-bit A/D with Installed IP Cores - PCIe 39
71662 4-Channel 200 MHz 16-bit A/D with Installed IP Cores - XMC 39
53662 4-Channel 200 MHz 16-bit A/D with Installed IP Cores - 3U VPX 39
56662 4-Channel 200 MHz 16-bit A/D with Installed IP Cores - AMC 39
56670 4-Channel 1.25 GHz D/A with DUC, Virtex-6 FPGA - AMC 40
71670 4-Channel 1.25 GHz D/A with DUC, Virtex-6 FPGA - XMC 40
78670 4-Channel 1.25 GHz D/A with DUC, Virtex-6 FPGA - PCIe 40
53670 4-Channel 1.25 GHz D/A with DUC, Virtex-6 FPGA - 3U VPX 40
72670 4-Channel 1.25 GHz D/A with DUC, Virtex-6 FPGA - 6U cPCI 40
73670 4-Channel 1.25 GHz D/A with DUC, Virtex-6 FPGA - 3U cPCI 40
74670 8-Channel 1.25 GHz D/A with DUCs, and Two Virtex-6 FPGAs - 6U cPCI 40
71671 4-Channel 1.25 GHz D/A with DUC, Extended Interpolation, Virtex-6 FPGA - XMC 41
78671 4-Channel 1.25 GHz D/A with DUC, Extended Interpolation, Virtex-6 FPGA - PCIe 41
53671 4-Channel 1.25 GHz D/A with DUC, Extended Interpolation, Virtex-6 FPGA - 3U VPX 41
56671 4-Channel 1.25 GHz D/A with DUC, Extended Interpolation, Virtex-6 FPGA - AMC 41
72671 4-Channel 1.25 GHz D/A with DUC, Extended Interpolation, Virtex-6 FPGA - 6U cPCI 41
73671 4-Channel 1.25 GHz D/A with DUC, Extended Interpolation, Virtex-6 FPGA - 3U cPCI 41
74671 8-Channel 1.25 GHz D/A with DUCs, Ext. Interpolation, Two Virtex-6 FPGAs - 6U cPCI 41
53690 L-Band RF Tuner with 2-Channel 200 MHz A/D and Virtex-6 FPGA - 3U VPX 42
71690 L-Band RF Tuner with 2-Channel 200 MHz A/D and Virtex-6 FPGA - XMC 42
78690 L-Band RF Tuner with 2-Channel 200 MHz A/D and Virtex-6 FPGA - PCIe 42
56690 L-Band RF Tuner with 2-Channel 200 MHz A/D and Virtex-6 FPGA - AMC 42
72690 L-Band RF Tuner with 2-Channel 200 MHz A/D and Virtex-6 FPGA - 6U cPCI 42
73690 L-Band RF Tuner with 2-Channel 200 MHz A/D and Virtex-6 FPGA - 3U cPCI 42
74690 Dual L-Band RF Tuner with 4-Channel 200 MHz A/D and Two Virtex-6 FPGAs - 6U cPCI 42
6890 2.2 GHz Clock, Sync and Gate Distribution Board - VME 43
6891 System Synchronizer and Distribution Board - VME 44
7190 Multifrequency Clock Synthesizer - PMC 45
7290 Multifrequency Clock Synthesizer - 6U cPCI 45
7390 Multifrequency Clock Synthesizer - 3U cPCI 45
7690 Multifrequency Clock Synthesizer - PCI 45
7790 Multifrequency Clock Synthesizer - Full-length PCIe 45
7890 Multifrequency Clock Synthesizer - Half-length PCIe 45
5390 Multifrequency Clock Synthesizer - 3U VPX 45

74
Links

7191 Programmable Multifrequency Clock Synthesizer - PMC 46
7291 Programmable Multifrequency Clock Synthesizer - 6U cPCI 46
7391 Programmable Multifrequency Clock Synthesizer - 3U cPCI 46
7691 Programmable Multifrequency Clock Synthesizer - PCI 46
7791 Programmable Multifrequency Clock Synthesizer - Full-length PCIe 46
7891 Programmable Multifrequency Clock Synthesizer - Half-length PCIe 46
5391 Programmable Multifrequency Clock Synthesizer - 3U VPX 46
7192 High-Speed Synchronizer and Distribution Board - PMC/XMC 47
7892 High-Speed Synchronizer and Distribution Board - PCIe 47
5392 High-Speed Synchronizer and Distribution Board - 3U VPX 47
7292 High-Speed Synchronizer and Distribution Board - 6U cPCI 47
7893 System Synchronizer and Distribution Board - PCIe 48
9190 Clock and Sync Generator for I/O Modules - Rackmount 49
9192 High-Speed System Synchronizer Unit - Rackmount 50
RTS 2706 Eight-Channel RF/IF 200 MS/sec Rackmount Recorder 51
RTS 2707 Four-Channel RF/IF 500 MS/sec Rackmount Recorder 52
RTS 2709 Ultra Wideband One- or Two-Channel RF/IF, 3.2 GS/sec Rackmount Recorder 53
RTS 2715 Two-Channel 10 Gigabit Ethernet Rackmount Recorder 54
RTS 2716 Eight-Channel Serial FPDP Rackmount Recorder 55
RTR 2726 Four-Channel RF/IF 200 MS/sec Rugged Portable Recorder 56
RTR 2727 Two-Channel RF/IF 500 MS/sec Rugged Portable Recorder 57
RTR 2736 Eight-Channel Serial FPDP Rugged Portable Recorder 58
RTR 2746 Eight-Channel RF/IF 200 MS/sec Rugged Rackmount Recorder 59
RTR 2747 Four-Channel RF/IF 500 MS/sec Rugged Rackmount Recorder 60
RTR 2749 Ultra Wideband One- or Two-Channel RF/IF, 3.2 GS/sec Rugged Rackmount Recorder 61
RTR 2755 Two-Channel 10 Gigabit Ethernet Rugged Rackmount Recorder 62
RTR 2756 Eight-Channel Serial FPDP Rugged Rackmount Recorder 63
RTX 2786 Four-Channel RF/IF 200 MS/sec Extreme 3U VPX Recorder 64
Handbooks and Catalogs

Click here Putting FPGAs to Work in Software Radio Systems Handbook
Click here Critical Techniques for High-Speed A/D Converters in Real-Time Systems Handbook
Click here High-Speed Switched Serial Fabrics Improve System Design Handbook
Click here High-Speed, Real-Time Recording Systems Handbook
Click here Onyx Virtex-7 and Cobalt Virtex-6 Product Catalog
Click here Pentek Product Catalog
75

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So

Soff t ware Defined Radio Handbook

SDR (Software-Defined Radio) has revolutionized electronic systems for a

Nyquists Theorem and Sampling A Simple TTechnique

Before we look at SDR and its various implementa-

Sampling Basics Baseband Sampling

Sampling Bandpass Signals

Lets consider bandpass signals like the IF frequency

No Signal Energy No Signal Energy

Zone 1 Zone 2 Zone 3 Zone 4 Zone 5 Zone 6 Zone 7

SPEAKER RF INPUT SIGNAL

RF IF AMP DEMODULATOR AUDIO

SDR Receiver Block Diagram

Figure 9 shows a block diagram of a software SDR Receiver Mixer

thereby converting it into digital samples. These samples

Tuning Freq Decimation

This process is called decimation and it means keeping

Digital Digital Analog Analog

Fs/N Fs Digital Digital

Translation Filtering Filtering Translation

A/D DIGITAL LOWPASS INTERPOLATE DIGITAL D/A

Freq uency Deci mation Inter polation Freq uency

Tuning Bandwidth Bandwidth Tuning

Key DDC and DUC Benefits SDR TTasks

Early Roles for FPGAs

Registers and gates Successful designs required high-level

FPGAs: New Device TTechnology

u 500+ MHz DSP Slices and Memory Structures

FPGAs for SDR FPGAs Bridge the SDR Application Space

Analog Sampling Input DDC Decimation Output DUC Interpol. Beam-

7142-428 4 125 MHz 14 4 264K 16 or 24 None None No

FPGA Resource Comparison

Vir tex-II PPro

Full-length VMEbus Board

Model 7142 PMC/XMC Model 724

TIMING BUS XTL

LVDS Clock B TIMING BUS XTL VIRTEX-4 FPGA

P15 XMC P4 PMC

Transceivers with FFour

Model 7142-428 PMC/XMC Model 724

DIGITAL DOWNCONVERTER CORE

INTERPOLATION CORE XC4VSX55

Quad 200 MHz 16-bit A/D with Vir tex-5 FPGAs

Model 7150 PCI-X LVDS GTP

Dual SDR TTransceivers

Dual SDR TTransceivers

3- Channel 200 MHz A/D, DUC, 2-

GTX GTX GTX LVDS

3- Channel 200 MHz A/D, DUC, 2-

GTX GTX GTX LVDS

GateXpress for FPGA-PCIe Configuration Management

ONYX: VIRTEX-7 FPGA

GTX GTX GTX LVDS

3- Channel 200 MHz A/D, DUC, 2-

DDC DDC DDC INTERPOLATOR

AURORA sum out

1 GHz A/D, 1 GHz D/A, Vir tex-6 FPGA

LVDS GTX GTX GTX

1- or 2- Channel 3.6 GHz and 2- or 4-

Model 72640 6U cPCI Model 73640 3U cPCI Model 74640 6U cPCI

1- or 2- Channel 3.6 GHz and 2- or 4-

VIRTEX-6 FPGA DATAFLOW DETAIL

2- Channel 500 MHz A/D, DUC, 2-