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PCB Revision A
Design Details Schematic Revision 1.0
Board:
Assy 6635
Chip:
SMSC LAN7500
56 Lead QFN w/ Exposed GND Pad Circuit Diagrams utilizing SMSC Products Are
Included As A Means Of Illustrating Typical
Semiconductor Applications: Consequently
Board Form Factor: Complete Information Sufficient For Construction
Purposes Is Not Necessarily Given. The Information
USB / Ethernet Dongle Has Been Carefully Checked And Is Believed To Be
C C
ITEM Page(s)
Revision History BLOCK DIAGRAM Title Page 1
Rev 1.0: LAN7500, Ethernet, USB, Magnetics 2
Initial release, Rev A
B B
A A
Title
LAN7500 USB-to-10/100/1000 Ethernet Customer EVB
Size Engineer Assembly No. PCB Rev Schematic Rev
C R. W. 6635 A 1.0
Date: Wednesday, November 03, 2010 Sheet 1 of 2
5 4 3 2 1
5 4 3 2 1
+2.5V +2.5VA_PHY
LAN7500 / Ethernet 1
FB1
2
+2.5VA_PHY
VDD12USBPLL FDUPLEX R5
1
2.0amp 120 Ohm 100MHz
+1.2V C1 C2 GPIO4/LED4
1 2 1 2
0.1uF 0.01uF
+1.2V VDD12PLL VDD12A +2.5V VDD33A 16V 25V LED1 Green LED LED_0805
10% 10% 154 +2.5VA_PHY
2
11
20
23
30
36
17
49
50
45
48
53
56
19
24
37
15
8
2
D U1 D
R14
1
R2 R8 R3 R9 R10 R11 R12 R4 GPIO0/LED0 R6 154
VDD12CORE
VDD12CORE
VDD12CORE
VDD12CORE
VDD12CORE
VDD12CORE
VDD12BIAS
VDD12A
VDD12A
VDD12A
VDD12A
VDD33A
VDD12USBPLL
VDDVARIO
VDDVARIO
VDDVARIO
VDDVARIO
VDD12PLL
49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 R13 T1 154
1
R1 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 0 THIS SIDE PHY J2
8.06K 1% 1% 1% 1% 1% 1% 1% 1% TD0P Amphenol - RJHSE-5381
1
11 + + 14
1/16W SPD0
1
1% TR0P
2
10 CT CT 15 GREEN
TR0N TD0N
13 - + 14
SPEED LED0 LED1
2
ETHRBIAS 41 12 - - 13
1
+2.5V EECLK 26 R33 R34 R35 R36
EECLK 0
EEDI 27 13 USBDP 75.0 75.0 75.0 75.0 R18
EEDO EEDI USBDP USBDM 1/10W 1/10W 1/10W 1/10W
28 EEDO USBDM 12 1 2
1
R17 EECS 29 1% 1% 1% 1%
10.0K EECS 0
1/16W
2
1%
39 TEST GND_CHASSIS
2
C 4 TDO
C
1
3 TMS
2 C33
TCK 1000pF
1 TDI XO 6
GND/EP
5 2kV
R19 XI -20% +80%
9 SW_MODE
0 Y1
2
25.000MHz
SW_MODE_R LAN7500 1 2
57
1
3
C3 C4
30pF
50V
30pF
50V
POR Monitor USB Connector
5% 5% Graphic illustration only. POR Monitor not present on 6635A
2
VCC_USB +5V
FB2
1 2
+2.5V +1.2V +3.3V
1
2.0amp 120 Ohm 100MHz
C7
2.2uF
1
6.3V
R32 C39 C38 20%
49.9K 0.1uF 0.1uF P1
2
1/10W 16V 16V 1
1% 10% 10% VCC
U3 USBDM
2
2 D-
6 1 nRESET/PME_CLEAR USBDP 3
V33 nRST D+
4 V12
5 RSTIN(0.714) 4 GND
3 nMR VSS 2
1 2 5 SHLD1
1
Thresholds: STM6719SFWB6F C16 6
R42 140ms 4700pF SHLD2
B
20.0K VCC1 (V33) = 2.925V 25V
B
1/10W 10% USB Type-A RA Plug
1%
VCC2 (V12) = 1.050V 0402
Test Points RSTIN = 0.625V
2
1 2
TP1 TP2 TP3 MTG1 MTG2 MTG3 MTG4 R30
nRESET/PME_CLEAR 1 SW_MODE_R 1 1 1 1 1 1 NOTE: 10M
POR Monitor circuit not implemented in assembly 6635A. 1/16W
A power-on reset circuit, or equivalent, is recomended for new designs. 5%
GND_USB
Refer to the data sheet for detailed power-on reset requirements.
Refer to the LAN7500 reference schematic and BOM for complete details of illustrated circuit.
1
1 2 1 2 1 2 C6 R23 L1 2.2uH
U2
6
4.7uF 7 R24 C5
EN1
1
VCC
C9 220 ohms@100MHz C10 C11 C8 C12 220 ohms@100MHz C28 220 ohms@100MHz C29 10% DEF1 1/16W 10uF EEDO 16V
3 DI
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0805 R22 1% 6.3V 1 EEDI 10%
R26 DO
16V 16V 16V 16V 16V 16V 16V 20% EECS
2
2
9 EN2 SW2 10 1 2 5 CS
10% 10% 10% 10% 10% 10% 10% 0 L2 2.2uH
2
1 2
2
ADJ2 1
1
R25
348K
1
SW_MODE_R 2 8 R27 C15 EECLK 4 2
0 MODE GND C14 360K 10uF 1/16W CLK GND
GND_EPAD 11
1
DNP 22pF 1/16W 6.3V 1% R21
50V 1% 20% 10.0K 93AA66AT-I/OT
5% 1/16W SOT23-6
2
+1.2V VDD12A 1%
2
FB3 1 2
A LP5900SD-3.3 R28 A
+5V LLP-6 +3.3V
2
1 2 VR2 115K
150mA
1
10% 10% 10% 10% 10% 10% 10% 20% 10% 10% 10% 10%
GND
PAD
C31 C32
2
0.47uF 0.47uF
6.3V 6.3V
10% 10%
3
7
Title
2