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l ndiff
pdiff
poly
Quality of Design
Electromechanical Relays
Vacuum Tubes
Bipolar Transistors
CMOS/FET Transistors
~10,000nm gates originally, now down to 90nm in production
scaling will stop somewhere below 30nm (over 100 billion
trans./chip)
Future:
3D CMOS (10 trillion transistors/system?)
Carbon Nanotubes?
Molecular Electronics?
Application
Physics
Application
Algorithm
Unit-Transaction Level (UTL) Model
Guarded Atomic Actions (Bluespec)
Register-Transfer Level (Verilog RTL)
Gates
Circuits Todays
Lecture
Devices
Physics
One chip
Photoresist
SiO2
SiO2
Develop to remove exposed resist.
Photoresist is spun onto wafer then exposed with UV light
or X-rays through mask (or written with electron beam, no mask).
SiO2
Isotropic
Remove Photoresist Mask
Dry Etching
Anisotropic
Photoresist
SiO2
SiO2
6.884 Spring 2005 Figure by MIT OCW. 2/07/2005 L03 CMOS Technology 9
FET = Field-Effect Transistor
gate
inversion
Surface of wafer happens here
Source Eh Drain
diffusion diffusion
Ev
bulk
Reverse side of wafer
INVERSION:
type channel between the source from the drain to the source.
and drain.
Metal 2
M1/M2 Via
Metal 1
Polysilicon
Mosfet
Diffusion (under polysilicon gate)
Exclusion rule
Surround rule Extension
rules
Width
rules
Spacing rules
3 3 2
1
1
3
diffusion (active)
2x2 3
poly
metal1
contact
F = (A+B).(C+D)
D
NFET connects
G G NFET only good
D and S when
at pulling down
S G=high=VDD
Ground = GND = 0V
VDD
Pullup network,
connects output to
VDD, contains only
PMOS
IN1
VOUT
IN2
INn
Pulldown network,
connects output to
GND,
For every set of input logic values, either pullup or pulldown network
makes connection to VDD or GND
If both connected, power rails would be shorted together
If neither connected, output would float (tristate logic)
A (A.B)
(A.B) B
B
B
A
(A+B) (A+B)
B
= A+B
= A.B
parallel
switches series
form OR A switches
form
(A.B) AND
B
B (A+B)
series
switches
A form parallel
AND switches
form OR
f = (A+B).C
A
pullup p = (A+B).C
B
= (A+B)+C
(A+B).C = (A.B)+C
C
pulldown f = (A+B).C
Simple Equivalent RC
G
Model of Transistor
When one gate drives another, all capacitance on the node must be
charged or discharged to change voltage to new state. Delay is
proportional to driving resistance and connected capacitance.
CgateP CgateP
01
CgateN CgateN
Delay ~ RonN(CdrainN+CdrainP+CgateP+CgateN)
L
Fold transistor to reduce
perimeter diffusion cap
Long transistors
parasitic diffusion
capacitance
W
W/2
Diffusion
has high Use multiple contacts
resistance to diffusion to reduce
resistance
not individual
transistors
??
F = (A+B).(C+D).E.G+H.(J+K)
Cin
Logical Effort
Complexity of logic function (Invert, NAND, NOR, etc)
Define inverter has logical effort = 1
Depends only on topology not transistor sizing
Electrical Effort
Ratio of output capacitance to input capacitance Cout/Cin
Parasitic Delay
Intrinsic self-loading of gate
Independent of transistor sizes and output load
Relative
Transistor 2 2 4
Widths
2 4
2
1 1 1
2
Cin
Cgate ~= Cdrain
For inverter:
RonN CdrainN
Parasitic Delay ~= 1.0
CgateN
Cin
Cout
Cin
Cout
Minimum delay when:
stage effort = logical effort x electrical effort ~= 3.4-3.8
copies of itself