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01
Flat Panel Display Control Sub-MCU
WT61P8
Flat Panel Display Control Sub-MCU
Data Sheet
Rev. 1.01
Copyright Notice
This data sheet is copyrighted by Weltrend Semiconductor, Inc. Do not reproduce, transform to any other format, or
send/transmit any part of this documentation without the express written permission of Weltrend Semiconductor, Inc.
Disclaimers
Right to make change
This document provides technical information for user. Weltrend Semiconductor, Inc. reserves the right to make
change without further notice to any products herein.
REVISION HISTORY
V1.00 11/26/2007
V0.98 7/16/2007
3. Update DDC/IIC data flow and flow chart on page 34~39.
4. Update electrical characteristic.
V0.97 7/3/2007
5. Update DDC/IIC register description, data flow and flow chart on page 34~39.
6. Add product Tube and Tape & Reel specifications
7. Update MCU clock option diagram on page 14
V0.96 6/7/2007
8. Add HV sync process block diagram on page 24.
9. Update PWM_CLK description on system level register.
10. Change Flash memory size to 64K from 52K
11. Update SFR register description on page 10~12
12. Update All register map on page41~42
V0.95 5/07/2007
1. Add XTAL_CLK(index 01H-bit2) for XTAL clock divider.
2. Update PWM_CLK description on system level register.
3. Add WDT[2] (index08-bit2) for watchdog timer reset pulse selector.
4. Change flash memory size to 52k from 64k.
V0.94 4/4/2007
1. Update UART naming
2. Add RTC block diagram in chapter 4.14
3. Update system reset description.
V0.93 2/8/2007
1. Update T2CON register on page 12.
2. Add interrupt flow chart on page 20.
V0.92 2/5/2007
1. Update memory mapping on page 8.
V0.91 1/30/2007
1. Update function block diagram on page 7.
2. Update HV Sync DPMS detector diagram on page 22.
V0.90 1/27/2006
Preliminary data sheet.
Table of Contents
1 GENERAL DESCRIPTION................................................................................................................................. 4
1.1. FEATURES.............................................................................................................................................................. 4
2. PIN ASSIGNMENT .............................................................................................................................................. 5
2.1. PACKAGE............................................................................................................................................................... 5
2.2. ORDERING INFORMATION ...................................................................................................................................... 5
2.3. PIN DESCRIPTION ................................................................................................................................................... 6
3. FUNCTIONAL BLOCK DIAGRAM.................................................................................................................. 7
6. ELECTRICAL CHARACTERISTICS............................................................................................................. 47
6.1. ABSOLUTE MAXIMUM RATINGS .......................................................................................................................... 47
6.2. POWER SUPPLY (VDD=3.3V) AT CRYSTAL OSCILLATOR = 12MHZ ..................................................................... 47
6.3. POWER SUPPLY (VDD=3.3V) AT CRYSTAL OSCILLATOR = 24MHZ ..................................................................... 47
6.4. DIGITAL I/O......................................................................................................................................................... 47
6.5. ADC CONVERTER ............................................................................................................................................... 48
6.6. LOW VDD RESET ................................................................................................................................................ 48
7. TYPICAL APPLICATION CIRCUIT.............................................................................................................. 49
7.1. CRYSTAL OSCILLATOR ........................................................................................................................................ 49
7.2. NRST PIN AND VDD PIN .................................................................................................................................... 49
7.3. PWM OUTPUT..................................................................................................................................................... 49
7.4. CEC .................................................................................................................................................................... 50
7.5. HSYNC,VSYNC AND IIC INTERFACE PROTECTION ............................................................................................... 50
8. PACKAGE DIMENSION .................................................................................................................................. 51
8.1. 44PIN LQFP ........................................................................................................................................................ 51
8.2. 48PIN LQFP ........................................................................................................................................................ 52
8.3. PRODUCT TRAY AND TAPE & REEL SPECIFICATIONS ........................................................................................... 53
1 General Description
The WT61P8 is a microcontroller for flat panel display control and power management with 1) Turbo 8052
CPU, 2) 64K bytes flash memory, 3) 1K+256 bytes SRAM, 4) 8 8-bit PWMs, 5) DPMS detector(2 H/V
inputs, Support H+V input) , 6) 4 timers and 2 UART Ports, 7) 2 DDC/CI interface, 8) Slave I2C interface, 9)
8 channel 8-bit A/D converter, 10) Real Time Clock, 11) Watch-dog timer, 12) Embedded ISP function, 13)
Power down mode, 14) Embedded ICE mode. 15) H/W CEC
1.1. Features
Embedded Turbo 8052 CPU
Normal operation mode: 12MHz, 6MHz, 3MHz, 1MHz or 24MHz, 12MHz, 6MHz, 2MHz (Selectable
Clock Sources)
Instruction execution time : Min. =250ns at OSC=12Mhz
Memory:
RAM: 1K+256 Bytes
Flash memory : 64K Bytes
4 similar 8052 timers: Timer0, Timer1, Timer2, Timer3
2 similar 8052 UART ports, support baud rate 115200 1200 at OSC = 12MHz
Sync processor for monitoring DPMS (support 2 H/V inputs, Support H+V inputs) wake up signal.
8-bit A/D converter with 8 selectable inputs, shared with IO pin
8 8-bit PWM pin output (One low frequency PWM at 150Hz for dimmer control)
Support 2 DDC/CI interface
Slave mode I2C interface
Maximum 37 programmable IO pins
Hardware universal IR Receiver
Watch Dog timer
Build-in RTC
Build-in ISP function
Embedded ICE mode
Embedded H/W CEC function
Power down mode
Selectable CPU clock sources
CPU off mode can be waked up by external interrupt
Operating temperature : -10 to +85 degree C
2. Pin Assignment
2.1. Package
GPIOE4/LPWM/P06
GPIOE4/LPWM/P06
GPIOE0/PWM0
GPIOE1/PWM1
GPIOE2/PWM2
GPIOE3/PWM3
GPIOE0/PWM0
GPIOE1/PWM1
GPIOE2/PWM2
GPIOE3/PWM3
GPIOD0/HIN1
GPIOD1/HIN2
GPIOD0/HIN1
GPIOD1/HIN2
GPIOE6/VIN2
GPIOE7/VIN1
GPIOE6/VIN2
GPIOE7/VIN1
GPIOE5/P07
GPIOE5/P07
NRST
NRST
NC4
44
43
42
41
40
39
38
37
36
35
34
48
47
46
45
44
43
42
41
40
39
38
37
VDD33V 1 33 GPIOD2/P10/AD4 NC1 1 36 GPIOD2/P10/AD4
GND 2 32 GPIOD3/P11/AD5 VDD33V 2 35 GPIOD3/P11/AD5
OSCO 3 31 GPIOD4/P12/AD6 GND 3 34 GPIOD4/P12/AD6
OSCI 4 30 GPIOD5/P13/AD7 OSCO 4 33 GPIOD5/P13/AD7
GPIOB6/SSDA 5 29 GPIOD6/TXD1 OSCI 5 32 GPIOD6/TXD1
GPIOB5/SSCL 6
61P8-RG440WT 28 GPIOD7/RXD1 GPIOB6/SSDA 6 31 GPIOD7/RXD1
GPIOB4/P05 7 (LQFP) 27 GPIOB5/SSCL 7
61P8-RG480WT 30 GPIOA0/PWM4/P00
GPIOA0/PWM4/P00
GPIOB3/P04 8 26 GPIOA1/PWM5/P01 GPIOB4/P05 8
(LQFP) 29 GPIOA1/PWM5/P01
GPIOB2/IR 9 25 GPIOA2/PWM6/P02 GPIOB3/P04 9 28 GPIOA2/PWM6/P02
GPIOB1/IRQ3/CEC 10 24 GPIOA3/PWM7/P03 GPIOB2/IR 10 27 GPIOA3/PWM7/P03
GPIOB0/IRQ2 11 23 GPIOA4/DSCL2 GPIOB1/IRQ3/CEC 11 26 GPIOA4/DSCL2
12
13
14
15
16
17
18
19
20
21
22
GPIOB0/IRQ2 12 25 GPIOA5/DSDA2
13
14
15
16
17
18
19
20
21
22
23
24
GPIOA5/DSDA2
GPIOC3/AD3
GPIOC2/AD2
GPIOC1/AD1
GPIOC0/AD0
DSDA1
DSCL1
GPIOC5/P15/TXD0
GPIOC7/P17/IRQ1
GPIOC6/P16/IRQ0
GPIOC4/P14/RXD0
GPIOC3/AD3
GPIOC2/AD2
GPIOC1/AD1
GPIOC0/AD0
DSDA1
DSCL1
GPIOC5/P15/TXD0
NC2
GPIOC7/P17/IRQ1
GPIOC6/P16/IRQ0
GPIOC4/P14/RXD0
NC3
64K bytes
Slave IIC
code flash
internal bus
Internal 256
VGA DDC
bytes SRAM
Timer0,
Timer1, DVI DDC
Timer2,
Timer3, 1 HV Sync
UART0, counter
UART1
2 HV Sync
External 1K counter
bytes SRAM
Reset IR Detector
Processor
Clock PWM/LPWM
Processor
4 IRQ
Clock off & Processor
Wake Up
GPIO
Interrupt Processor
Processor
Watchdog RTC
timer
CEC
Key Pad ADC
4. Functional Description
4.1. MCU
4.1.2. RAM
The SRAM include :
128 bytes internal SRAM are from 0x0000H to 0x007FH (direct & indirect addressing)
128 bytes internal SRAM are from 0x0080H to 0x00FFH (indirect addressing)
1K bytes external SRAM are from 0x1000H to 0x13FFH
Memory Mapping
Program memory Internal memory Data memory
$FFFFH $FFFFH
Reserved
$1400H
$13FFH
1024 bytes
RAM
$1000H
64K bytes $0FFFH
Flash Reserved
$0100H
$00FFH Upper SFR $00FFH
128 bytes Registers
$0080H SRAM Registers
$007FH Lower
128 bytes
$0000H $0000H SRAM $0000H
bit addressable
OSC clock = 12MHz, all reset signals will last 16*12*1024*FOSC = 16.384ms
OSC clock = 24MHz, all reset signals will last 16*12*1024*FOSC = 8.192ms
Reset sources
NRST
The NRST-Reset happens when there is a low level on the NRST pin.
4 clock Digital
NRST
filter
LATCH 8052
Watchdog Timer Reset
R
CPU
Peripheral
16.368ms
Circuits
Timer
XTAL_CLK
8 PWM
XTAL OSC XTAL OSC (PWM_CLK=1)
24MHz 12MHz
CHG_CLK 00 00
XTAL_CLK 0 1 0 1
MCU clock 24MHz 24MHz 12MHz 12MHz XTAL OSC=24MHz & XTAL_CLK=1: Don't use
Peripherals clock 12MHz 24MHz 6MHz 12MHz XTAL OSC=12MHz & XTAL_CLK=0: Don't use
CEC_WAKE
CEC_IN Toggle Latch CEC_TOG
reset
IR_WAKE
IR_IN Toggle Latch IR_TOG
reset
ADC_WAKE
ADC_IN Toggle Latch ADC_TOG
reset
SI2C_WAKE
SI2C_IN Toggle Latch SI2C_TOG
reset
DDC_WAKE[1:0]
DDC1/2_IN Toggle Latch DDC_TOG[1:0] System Clock
reset Clock_ON
HV_WAKE[1:0]
Toggle Latch
OSC_OFF Clock_OFF
HV1/2_IN HV_TOG[1:0]
reset
RTC_1S_WAKE
RTC1S_IN Toggle Latch RTC_1S_TOG
reset
ALARM_WAKE
ALARM_IN Toggle Latch ALARM_TOG
reset
UART_WAKE[1:0]
UART0/1_IN Toggle Latch UART_TOG[1:0]
reset
IRQ_WAKE[3:0]
IRQ0/1/2/3_IN Toggle Latch IRQ_TOG[3:0]
reset
CLR_IN_TOG
4.6. GPIO
The GPIOx0~ GPIOx7 are the general purpose IO shared with some special functions. When the special
function is disabled, it is a general purpose I/O port. If it is configured as output, it could source/sink 4mA. If
it is configured as input and GPIOx_PHN is 0, it has an internal pull-up resistor. If the GPIOx is
configured as input and the GPIOx_PHN is 1, it doesnt have an internal pull-up resistor.
INTERNAL_DATA_BUS
MCU_DATA GPIOX_PHN
D Q
GPIOX_PHN_WRITE CP QN
A1
CDN
NRST
MCU_DATA GPIO_OE
D Q
A1
pull high resistor
GPIO_OEN
GPIOX_OE_WRITE CP QN
CDN
NRST
GPIOX
MCU_DATA GPIOX_D A1
D Q
GPIOX_D_WRITE CP QN
CDN
NRST
GPIOX_D_READ A1
MCU_DATA A2
B1
B2
INT2 is caused by 2 DDC or 2 HV DPMS detector or IR detector or key pad ADC, or RTC 1sec or alarm or
4 external IRQ or CEC. Each interrupt can be enabled/disabled independently by programming IE2_xxx
register and identified by IF2_xxx register.
IE1_1DDC IF1_1DDC
VDC_AL_RDY
IE1_2DDC IF1_2DDC
DVC_AL_RDY
IE1_HV1 IF1_HV1
HV1_INT
IE1_HV2 IF1_HV2
HV2_INT
IE1_IR IF1_IR INT1
IR_INT
IE1_KADC IF1_KADC To MCU 8052 INT1
EVENT_ADC
IE1_RTC_1S IF1_RTC_1S
RTC_1S
IE1_ALARM IF1_ALARM
RTC_ALARM
IE1_CEC IF1_CEC
CEC_INT
IE1_IRQ[3:0] IF1_IRQ[3:0]
EVT_IRQ[3:0]
IE2_1DDC IF2_1DDC
VDC_AL_RDY
IE2_2DDC IF2_2DDC
DVC_AL_RDY
IE2_HV1 IF2_HV1
HV1_INT
IE2_HV2 IF2_HV2
HV2_INT
IE2_IR IF2_IR INT2
IR_INT
IE2_KADC IF2_KADC To MCU 8052 INT2
EVENT_ADC
IE2_RTC_1S IF2_RTC_1S
RTC_1S
IE2_ALARM IF2_ALARM
RTC_ALARM
IE2_CEC IF2_CEC
CEC_INT
IE2_IRQ[3:0] IF2_IRQ[3:0]
EVT_IRQ[3:0]
Hsync Hsync
Hsync Hsync Counter
Counter
Overflow Hsync
input Detector overflow flag
Vsync
Vsync
Counter
H+V Detector Vsync Counter Overflow Vsync
Detector overflow flag
Vsync
input
Hsync
Interrupt
Hfreq Counter
Enable
16 ms
16.384 ms
Hfreq Counter
clock
Vsync in
125kKhz clock ......................................................
VFx[7:0]
START 0 1 0 0
IR input 9ms 4.5ms 0.56ms 1.69ms
S1 S2 TG A4 A3 A2 A1
1 1 1 1 0 0 0
IR input 888.9us
INT_TM2=1 INT_TM2=1
TM2_HL=1 TM2_HL=0
TM2_DAT=0dh TM2_DAT=1bh
IR Timing Table
STARTH STARTL pulse H period L period
TC9290 data 9 4.5 0.56 2.25 1.125
(TC9243) keep 9 4.5 0.56 2.25
NEC uPD6P5 data 9 4.5 0.56 2.25 1.125
keep 9 2.25 0.56
Philips RC5 data 0.889 0.889 0.889 0.889 0.889
PHILIPS RC5
S1 S2 TG A4 A3 A2 A1 A0 C5 C4 C3 C2 C1 C0
1 1 1 1 0 0 0 1 0 1 1 0 0 1
IR input
888.9us 888.9us
9ms 4.5ms
0.56ms 2.25ms
CEC PAD
cec_tx Transmit
cec_tx CEC
Output
INITATOR_FSM
cec_i
FOLLOWER_FSM
Initiator
Index Default R/W Bit Name Description
1: Enable initiator state and transmit data
R/W 7 CEC_TR
0: Follower state
R/W 6 CEC_O_EOM EOM bit
71 20
1: NACK
R 5 CEC_RXACK
0: Receive ACK
4-0 Reserved
Transmit/Receive buffer
Index Default R/W Bit Name Description
75 FF R/W 7-0 CEC_DTX[7:0] CEC transmit buffer
76 00 R 7-0 CEC_DRX[7:0] CEC receive buffer
FOLLOWER INITIATOR
IDLE
IDLE
READ WRITE
write eom data to
CEC_I_EOM
next state If (CEC_TR ==0)
CEC_RX_INT==1
next state
If (EOM = 1)
CEC_TR ==0;
ACK
ACK
CEC bit7 bit2 bit1 bit0 EOM ACK next data block
CEC bit7 bit2 bit1 bit0 EOM ACK next data block
CEC_TX_INT
1. Write CLR_CEC_TX to clear "CEC_TX_INT
When ACK_END, CEC_TR== ~(CEC_O_EOM) CEC_O_EOM==1
2. Read CEC_RXACK & write next data (CEC_DTX)
CEC_TR
a: low duration
b: total duration
b
3.9 4.7
a
High Impedance
Start
Low Impedance
3.5 4.3
T3 T5 T7
High Impedance
Logic 0
Low Impedance
0.4
(ms) 0 0.6 1.5 2.4
T2 T4 T6 T8
T3 T5 T7
High Impedance
Logic 1
Low Impedance
0.4
(ms) 0 0.6 1.5 2.4
T2 T4 T6 T8
DSCL1
DSDA1 Slave Address 0 A
VGA DDC Slave I II Receive & Transmit Buffer Register (1st DDC)
Index Default R/W Bit Name Description
83 FF R/W 7-0 VDC_DTX1[7:0] Slave 1 transmit buffer
84 FF R/W 7-0 VDC_DTX2[7:0] Slave 2 transmit buffer
85 00 R 7-0 VDC_DRX[7:0] Slave 1,2, receive buffer
DVI DDC Slave I II Receive & Transmit Buffer Register (2nd DDC)
Index Default R/W Bit Name Description
93 FF R/W 7-0 DVC_DTX1[7:0] Slave 1 transmit buffer
94 FF R/W 7-0 DVC_DTX2[7:0] Slave 2 transmit buffer
95 00 R 7-0 DVC_DRX[7:0] Slave 1,2, receive buffer
Index Default
R/W Bit Name Description
96 00 R/W 7-1 DVC_SADR1[6:0] Slave 1 address
0 DVC_EN_SA1 1: Enable Slave address 1 DVC_SADR1[6:0] compare
0: Disable Slave address 1 DVC_SADR1[6:0] compare
97 00 R/W 7-1 DVC_SDAR2[6:0] Slave 2 address
0 DVC_EN_SA2 1: Enable Slave address 2 DVC_SADR2[6:0] compare
0: Disable Slave address 2 DVC_SADR2[6:0] compare
DVI DDC Slave Address Register (2nd DDC)
DSCL1
DSDA1 Slave Address 0 A RX DATA 1 A RX DATA 2 A
DSDA1 ouput A A A
set VDC_CLR_STP
VDC_AL_RDY set VDC_CLR_RT
DSCL1
DSDA1 Slave Address 1 A TX DATA 1 A TX DATA 2 N
No VDC_AL_RDY=1?
Yes
slave 2 address
No
VDC_SLV1=1? subprogram
(same as this flow chart)
Yes
No
VDC_INT_RT=1?
Yes
No VDC_INT_STP=1 ?
No
VDC_FIRST=1 ? Yes
Yes
VDC_ALRW=1 ? No set VDC_CLR_STP
No
VDC_ALRW=1 ? Yes
read VDC_DRX
Yes
No VDC_RXNAK=0 ?
END
other sended data =>
VDC_DTX1 Yes
set VDC_CLR_RT
SSCL
SSDA Slave Address 0 A
SSCL
SSDA Slave Address 0 A RX DATA 1 A RX DATA 2 A
SSDA ouput A A A
set IIC_CLR_STP
IIC_AL_RDY set IIC_CLR_RT
SSCL
SSDA Slave Address 1 A TX DATA 1 A TX DATA 2 N
No IIC_AL_RDY=1?
Yes
No
IIC_INT_RT=1?
Yes
No
IIC_INT_STP=1 ?
No
IIC_FIRST=1 ? Yes
Yes
IIC_ALRW=1 ? No set IIC_CLR_STP
No IIC_ALRW=1 ? Yes
read IIC_DRX
Yes
No
IIC_RXNAK=0 ?
END
other sended data =>
IIC_DTX Yes
set IIC_CLR_RT
WEEK
counter
(0w - 7w)
Level
EN_AD[7:0] shift
8
DA_IN[7:0] Level 8bit DAC
shift
Level
ENB shift
clock_1Mhz
SLT_CHx
4.16. PWM
PWM0 ~ PWM7 : 8-bit PWM and 3.3V push-pull output, shared with I/O GPIO E and GPIO A.
LPWM0 : 8-bit low frequency PWM shared with GPIO E4.
The corresponding PWM register controls the PWM duty cycle. Duty cycle range is from 0/256 to 255/256.
256Tpwm
6. Electrical Characteristics
WT61P8
20P
OSCI
12MHz / 24MHz
20P
OSCO
+3.3V WT61P8
4.7K
0.1u 47u
47u
WT61P8
PWM
22K
2.2u
7.4. CEC
3.3V
WT61P8
100 27K
CEC
47pF
WT61P8
47K 47K
220
VIN VSYNC
HIN HSYNC
220
100P 470P
+3.3V +3.3V
47K 10K
150
DSCL1(or DSCL2) SCL
DSDA1(or DSDA2) SDA
150
100P 100P
8. Package Dimension
8.1. 44pin LQFP
13 + 0.5
C Spindle Hole Diameter
- 0.2
24.8 + 0.6
T1 Space Between Flange LQFP 44L (10x10mm)
- 0.4
Notes:
3. Pocket position relative to sprocket hole measured as true position of pocket, not pocket hole.