Table of Contents

CHAPTER 1. INTRODUCTION.............................................................................................................4
1.1. INTRODUCTION.............................................................................................. 4
1.2. BACKGROUND AND MOTIVATION OF RESEARCH............................................4
1.2.1 VLSI DESIGN............................................................................................ 4
1.2.2 VLSI TESTING........................................................................................... 4
1.2.3 BUILT-IN SELF-TEST.................................................................................. 4
1.2.4 COMPONENTS OF BIST ARCHITECTURE...................................................4
1.3 ADVANTAGES OF BIST........................................................................................ 4
1.4 DISADVANTAGES OF BIST..................................................................................4
1.5 OBJECTS OF RESEARCH..................................................................................... 4
1.6 SCOPE AND SIGNIFICANCE................................................................................ 4
1.7 DESERTATION OUTLINE OR CONCLUSION..........................................................4
CHAPTER 2. LITERATURE SURVEY..................................................................................................5
2.1 INTRODUCTION................................................................................................. 5
2.2 LITERATURE REVIEW.......................................................................................... 5
2.2.1 IEEE TRANSACTIONS AND OTHER JOURNALS AND ARTICLES.......................5
2.3 PROBLEM IDENTIFICATION.................................................................................5
2.4 RESEARCH GAP.................................................................................................. 5
2.5 CONCLUSION..................................................................................................... 5
CHAPTER 3. RESEARCH METHODOLOGY.....................................................................................6
3.1 INTRODUCTION................................................................................................. 6
3.2 PURPOSE OF RESEARCH.................................................................................... 6
3.3 SOURCE OF INFORMATION................................................................................. 6
3.4 PROPOSED DESIGN METHODOLOGY..................................................................6
3.4.1 BIST ARCHITECTURE.................................................................................... 6
3.5 DEVELOPMENT TOOLS....................................................................................... 6
3.5.1 XILINX-ISE................................................................................................... 6
3.5.2 MENTAOR GRAPHICS MODELSIM.................................................................6
3.5.3 SYNTHESIS AND SIMULATION......................................................................6
3.6 CONCLUSION..................................................................................................... 6
CHAPTER 4. IMPLEMENTATION.......................................................................................................7
 4.1 INTRODUCTION................................................................................................. 7
4.2 BIST ARCHITECTURE.......................................................................................... 7
4.2.1 COMPONENTS OF BIST................................................................................ 7
4.2.2 INPUT OUTPUT PORT DESCRIPTION.............................................................7
4.3 COMBINATIONAL CIRCUITS AND MODULE..........................................................7
4.4 MODIFIED DECODER.......................................................................................... 7
4.5 IMPLEMENTATION OF BIST................................................................................7
4.6 CONCLUSION..................................................................................................... 7
CHAPTER 5. RESULT ANALYSIS AND VALIDATION OF BIST ARCHITECTURE.....................8
5.1 INTRODUCTION................................................................................................. 8
5.2 DEVELOPMENT AND SIMULATION......................................................................8
5.3 RTL AND SCHEMATIC RESULTS...........................................................................8
5.4 SYNTHESIS REPORT........................................................................................... 8
5.5 CONCLUSION..................................................................................................... 8
CHAPTER 6. CONCLUSION AND FUTURE SCOPE.........................................................................9
6.1 INTRODUCTION................................................................................................. 9
6.2 CONCLUSION DRWAN FROM THE RESEARCH.....................................................9
6.3 OUTCOMES OF RESEARCH.................................................................................9
6.4 FUTURE SCOPE.................................................................................................. 9
6.5 SUMMARY.......................................................................................................... 9
6.6 CONCLUSION..................................................................................................... 9
REFRENCES.............................................................................................................................................9
PUBLICATIONS.......................................................................................................................................9
CHAPTER 1. INTRODUCTION

1.1 INTRODUCTION
The functionality of electronic equipments and gadgets has achieved a phenomenal
growth over the last two decades while their physical sizes and weights have come
down drastically. The major reason is due to the rapid advances in integration
technologies [XXX], which enables fabrication of many millions of transistors in a
single integrated circuit (IC) or chip. Every IC in the industry follows Moore's law. Ac-
cording to Moore's law, number of transistors (transistor density) in an IC doubles in
every 1.5 years. With the recent advances in the technology, device shrinks to
nanometer scale, but density and complexity of the ICs keep on increasing. This
may result in many manufacturing faults and device failure. To accommodate more
number of transistors, the device feature size is reduced. Reduction in the feature
sizes results in increasing the manufacturing faults and fault detection becomes
 very difficult. A typical flow of a VLSI (Very Large Scale Integration) realization
process is shown in Figure 1.1. VLSI testing is becoming more and more important
and challenging to verify whether a device functions properly or not.

Specifiaton Design Manufctrig

Figure 1.1: VLSI realization process
Testing
1.2 BACKGROUND AND MOTIVATION OF RESEARCH

1.2.1 VLSI DESIGN

1.2.2VLSI TESTING

1.2.3 BUILT-IN SELF-TEST

1.2.4 COMPONENTS OF BIST ARCHITECTURE

1.3 ADVANTAGES OF BIST

1.4 DISADVANTAGES OF BIST

1.5 OBJECTS OF RESEARCH

1.6 SCOPE AND SIGNIFICANCE

1.7 DESERTATION OUTLINE OR CONCLUSION

CHAPTER 2. LITERATURE SURVEY

2.1 INTRODUCTION

2.2 LITERATURE REVIEW

2.2.1 IEEE TRANSACTIONS AND OTHER JOURNALS AND ARTICLES

2.3 PROBLEM IDENTIFICATION

2.4 RESEARCH GAP

2.5 CONCLUSION

CHAPTER 3. RESEARCH METHODOLOGY

CHAPTER-3 RESEARCH METHODOLOGY

3.1 INTRODUCTION
The previous chapter serves as a base for building this dissertation by hierarchal
advancement of understanding through discussion from basic concepts to actual
problems via brief literature survey and gap identification. Based on the pervious
chapter, this chapter discloses the proposed approach for solving the problem
identified earlier. Concreting those problems into one single statement has been
done in Section 3.2 followed by Section 3.3 which discusses the proposed approach
in detail. This chapter ends with discussing various conclusion and remarks of the
proposed method in the final section 3.4.

3.2 PURPOSE OF RESEARCH

Critical analysis of various researches works in the BIST architecture. The AMBA bus
specification defines an on chip communications protocol, used for designing high-
performance embedded microcontrollers and DSP processors [1].Then we realize
that to control the data transmission process between the IP cores of
microcontroller, an AHB ARBITER must be needed[13]. The method for designing
the AHB ARBITER thus adopted should be able to handle the communication
between masters and slaves or we can say that IP cores. So these factors become
the very purpose of this research which can be summed up as follows:

I. Use of Round Robin arbitration algorithm.

II. Single edge click protocol.

III. Burst transfer.

IV. Split transaction

V. No error

VI. Master switchover

VII. Wait State and Idle State

VIII. Several bus master and slaves

3.3 SOURCE OF INFORMATION

There have been numerous sources from which information was gathered but some
of them proved to be most useful. Such sources are mentioned as follows:

I. IEEE Digital Library.

II. Springers Digital Library.

III. Google Scholar.

IV. Hindawi.

V. Electrical Engineering Portal.

VI. ARM ltd AMBA Datasheet

 3.4 ARBITER DESIGN METHODOLOGY
This section presents a description of design methodology adopted to implement an
AHB Arbiter using lowest priority round-robin arbitration algorithm. The complete
design methodology shown in Figure: 4.1 are consists of software design flow and
FSM. These flows are described individually in the next section. Synthesis and
implementation is done for ensuring the proper hardware mapping & routing of AHB
Arbiter in FPGA.

3.4.1 HIERARCHICAL MODELING

For describing the design methodology of AHB Arbiter, we discuss the basic
constructs and conventions in Verilog-HDL. These conventions provide the
necessary framework for Verilog-HDL. START

I. The digital simulation of AHB Arbiter design is held on the basis of following
methodologies.
READING THE REQUEST LINE
II. Top down design methodology is used for implementing digital design.

III. Behavioral abstraction is used to design Module instances in Verilog-HDL.

IV. Design stimulus for digital design module.

If Request is High No

3.4.2 ARBITER DESIGN FLOW

This section explains the design flow of AHB Arbiter for software applications
and the tools provided for designer or simulation and
Yes verification to choose for
the work.

Yes If priority value lowest?

No

Grant is given to the request line with lowest priority value PRIORITY VALUE IS HIEST

Stop No

HGRANT

Yes

Priority value of the corresponding request is decremented

 Figure 3. 1 AHB ARBITER Design Flow.

The flow chart for lowest Priority arbitration for a single request is shown in Fig 1.
Initially the system request signals are read. If any of the request signals are high,
then corresponding lowest and highest priority values of the master that is
requesting is checked. And if the priority signal value is the lowest one, the grant is
given to that particular master. The default master is the master with the lowest
priority so whenever there will not be any request for the bus, from any of the
master, then by default the bus will be granted to the master with the lowest
priority. If the busreq & hlock signal are low and no locked transfer is going on so
the bus is granted to the master 8 as it is the default master

3.4.3 ARBITER Design Topology

The block diagram in Figure displays the design topology of the AHB Arbiter
configured for two masters and two slaves. It shows how the two systems are
connected to a single slave, through their associated AHB ARBITER. This block
diagram excludes the module which is used to generate the clock for the AHB
Arbiter module.
 Figure 3. 2 ARBITER Design Topology

3.4.4 ARBITRATION ALGORITHM

The arbitration algorithm is used to control the data transmission between masters
and slaves or it is work as a traffic controller[18][19], so in our work we are
considering Round robin arbitration algorithm with highest priority. This allows the
Arbiter to be able to dynamically change which system receives highest or lowest
priority without having to modify the Verilog-HDL source code. This can be done
utilizing module I/O ports. The Arbiter should have a signal that can control which
system has priority. The AHB Arbiter is uses a round-robin priority scheme with
Master0 having the default priority. This highest and lowest priority scheme assures
that every master equally has its turn at acquiring and completing an AHB bus
transaction[18]. Each inactive master is locked out (HCLOK) while the active master
has access to the bus to prevent contention.

The AHB Arbiter steers all, HWDATA, HADDR, HTRANS, HWRITE, HSIZE and HBURST
signaling from every master to the AHB system bus. The AHB Arbiter can easily
configure to allow up to sixteen AHB bus masters. AHB Arbiter package includes
fully tested and verified Verilog source.

3.4.4.1 ROUND ROBIN TECHNIQUE

A round-robin arbitration technique is uses token passing scheme[20]. In a token

passing network, a token or a special electronic message generated when the token
passing network is turned on. The token is then passed along from master to
master. Only the master with the token is allowed to transmit and send token to
another master. This type of network have either a bus or ring topology and are
famous because fast access and nonexistent of collision. After getting the
opportunity to transmit the data, it must hand over its turn after some maximum
period of time the right to send may be controlled in a distributed manner.

In each cycle, one of the masters has the highest priority for access to a shared
resource. If the token holding system or master does not need the bus in this cycle,
then the master will release the token. The advantages of round-robin are twofold:
Unused time slots are immediately re-allocated to masters who are ready to issue a
request, regardless to their access order. This reduces bus under utilization in
association with a fixed slot allotment that might grant the bus to a master which is
not going to carry out any communication. The uncertainty on the genuine
bandwidth that can be approved to a master is the major drawback of this scheme.
In this dissertation we are using highest and lowest priority round robin arbitration
algorithm[18].

3.5 DEVELOPMENT TOOLS

For designing AMBA AHB ARBITER we used the Xilinx Integrated Software
Environment (ISE)[3]. Here we created modules, test benches, and generating RTL
Schematic and logical diagrams. Our main method of programming was the Verilog
HDL language. Additionally for designing AHB ARBITER we are using the data sheet
of AHB ARBITER for signal and input-output ports guidance [1] .

3.5.1 Xilinx Integrated Software Environment

The design of the AMBA AHB ARBITER interface was done using the using Xilinx
Integrated Software Environment[3]. When creating a project within the ISE the user
is given many design options. For our project, we chose the ML605 as the targeted
platform and Verilog-hdl as the chosen HDL. This ensured that all clocks, user I/O,
and pins work correctly. Once the project was created the Project Navigator allowed
us to easily organize the Verilog modules. Figure 9 below shows a screenshot of the
environment.
 Figure 3. 3 Screenshot of the Xilinx Integrated Software environment

Various windows are shown to the user within the Project Navigator. On the top left
is the hierarchical view of modules within the design. Clicking on an individual
module causes the Verilog code to appear in the large window on the right where
the user can input/modify code. The bottom left window displays various processes
that are running and the status of Synthesis, Implementation, and Generation.
These steps are necessary before the design can be downloaded onto the board.
During synthesis the Verilog design becomes the net list files that are accepted as
input to the implementation step. Implement Design converts the logical design into
a physical file format to be downloaded onto the targeted platform. Implementation
is broken down into three steps, Translate, Map, and Place & Route. The final stage,
Generate Program File, creates the bit file that can be downloaded onto the board.
[3]

3.5.3 ModelSim
ModelSim is a multi-language HDL simulation tool by Mentor Graphics for simulation of
hardware description language such as VHDL, Verilog-HDL, System Verilog and
System C, and includes a built-in C debugger. ModelSim can be used
autonomously[21], or in conjunction with Altera Quartus or Xilinx ISE. Simulation is
performed using the graphical user interface (GUI) or automatically using scripts.
 Figure 3. 4 Screenshot of the Xilinx Integrated Software environment

ModelSim tool combines the simulation performance and capacity with the code-
coverage and debugging capabilities required to simulate multiple blocks and attain
ASIC gate-level sign-off. Comprehensive support of Verilog, System Verilog for
Design, VHDL, and System C provide a solid foundation for single and multi-
language design verification environments. ModelSim is easy to use and combined
debug and simulation environment provide todays FPGA designers, both the
advanced capabilities that they are growing to need and the situation that makes
their work dynamic.

3.5.2 Synthesis
Once design files have been created, the next step is to synthesize our design. This
synthesis process will check the hierarchy of design and code syntax which ensure
that our design is optimized for the design architecture. The resulting netlist is
saved to an XST file format[17].

The synthesis process can be used by Xilinx-ISE tool.

 Figure 3. 5 Screenshot of the Xilinx ISE synthesis

3.6.1 Simulation
Before the design can be implement is it important that we first verified that the
logic worked correctly and synthesize our design. Xilinx provides the Isim tool to
allow for simulation using test benches or forcing input manually. Within test
benches we created a clock and provided various input stimulus. Simulation was
done without generating a bit file and only required synthesis of the project, which
significantly reduces the time before the results can be verified[22]. Below is an
example of what a simulation in Isim looks like in Figure 3.6.
 Figure 3. 6 Screenshot of the Xilinx-ISE Simulation

The simulation was very helpful in showing timing and signal values. For our
purposes we needed to know that commands and various signals were being
asserted on the proper clock edge by the memory controller. Overall, simulation was
a very quick method of testing that allowed for simple debugging of our logic.
However, validation in simulation does not guarantee validation on hardware.

3.7 CONCLUSION
This chapter can be concluded by summing up the literature survey which proved to
be very helpful in establishing research gap, problem specification and problem
statement. In this current chapter we discussed the novel approach and its
experimental setup to achieve the desired goal.
CHAPTER 4. IMPLEMENTATION

4.1 INTRODUCTION

4.2 BIST ARCHITECTURE

4.2.1 COMPONENTS OF BIST

4.2.2 INPUT OUTPUT PORT DESCRIPTION

4.3 COMBINATIONAL CIRCUITS AND MODULE

4.4 MODIFIED DECODER

4.5 IMPLEMENTATION OF BIST

4.6 CONCLUSION
CHAPTER 5. RESULT ANALYSIS AND VALIDATION OF BIST
ARCHITECTURE

5.1 INTRODUCTION

5.2 DEVELOPMENT AND SIMULATION

5.3 RTL AND SCHEMATIC RESULTS

5.4 SYNTHESIS REPORT

5.5 CONCLUSION
CHAPTER 6. CONCLUSION AND FUTURE SCOPE

6.1 INTRODUCTION

6.2 CONCLUSION DRWAN FROM THE RESEARCH

6.3 OUTCOMES OF RESEARCH

6.4 FUTURE SCOPE

6.5 SUMMARY

6.6 CONCLUSION

REFRENCES

PUBLICATIONS