ECV917 Lab RPRT (Main) v5

ECV - 917
Circuit Simmulation Laboratory
Arjunasor Syiem
Roll #: MTV/EC14/
Department of Electronics and Communication Engineering
North-Eastern Hill University(NEHU)
Shillong - 793 022
Meghalaya
Name : ARJUNASOR SYIEM
Roll #: MTV/EC14/01
Laboratory Report
ECV - 917 Circuit Simulation Laboratory
Department of ECE, NEHU, Shillong - 793 022
October 15, 2014
List of Experiments
1 Experiment - 1 3
1.1 CMOS inveter[NOT] logic gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 SPICE Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Observation and Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Experiment - 2 6
2.1 Simulation of 2-input CMOS NAND gate . . . . . . . . . . . . . . . . . . . . . . 6
2.1.1 SPICE Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.2 Observation and Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 3-input CMOS NAND gate circuit . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2.1 SPICE deck for this 3-input NAND gate . . . . . . . . . . . . . . . . . . . 11
2.3 4-input CMOS NAND gate circuit . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3.1 SPICE deck for this 4-input NAND gate . . . . . . . . . . . . . . . . . . . 14
3 Experiment - 3 16
3.1 2-input CMOS AND gate circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1.1 SPICE deck for the 2-input CMOS AND gate . . . . . . . . . . . . . . . . 16
3.2 3-input CMOS AND gate circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2.1 SPICE deck for the 3-input CMOS AND gate . . . . . . . . . . . . . . . . 18
4 Experiment - 4 20
4.1 2-input CMOS NOR gate circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.1.1 SPICE deck for the 2-input CMOS NOR gate . . . . . . . . . . . . . . . . 20
4.2 3-input CMOS NOR gate circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.2.1 SPICE deck for the 3-input CMOS NOR gate . . . . . . . . . . . . . . . . 22
5 Experiment - 5 24
5.1 2-input CMOS OR gate circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.1.1 SPICE deck for the 2-input CMOS OR gate . . . . . . . . . . . . . . . . . 24
5.2 3-input CMOS OR gate circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.2.1 SPICE deck for the 3-input OR gate . . . . . . . . . . . . . . . . . . . . . 26
2060720-02#201400808LJS 1 / 36
Roll #: MTV/EC14/01 ECV - 917 Circuit Simulation Lab. Date: / /2014
6 Experiment - 6 28
6.1 Implementation of combination logic: Y = AB + C . . . . . . . . . . . . . . . . 28
6.1.1 SPICE deck for the 3-input combinational logic circuit . . . . . . . . . . . 28
7 Experiment - 7 29
7.1 Implementation of combination logic: Y = (A + B).C = A + B + C . . . . . . . 29
8 Experiment - 8 30
8.1 Implementation of combination logic: Y = AB + C . . . . . . . . . . . . . . . . . 30
9 Experiment - 9 31
9.1 Implementation of combination logic: Y = (A + B).C = A.B.C . . . . . . . . . 31
10 Experiment - 10 32
10.1 Implementation of combination logic: Y = AB + C . . . . . . . . . . . . . . . . . 32
11.1 Implementation of complex CMOS logic gate: Y = AB + C . . . . . . . . . . . . 33
12.1 Implementation of complex CMOS logic gate: Y = (A + B).C . . . . . . . . . . . 34
13.1 Implementation of complex CMOS logic gate: Y = AB + CD . . . . . . . . . . 35
14.1 Implementation of complex CMOS logic gate: Y = AB + CD . . . . . . . . . . 36
Note:
The transistor technology used in the experiments is 0.8 technology with the standard basic
CMOS inverter circuit of (W/L)n = (W/L)p = 2 : 1 unless stated otherwise.
Name: ARJUNASOR SYIEM ECE, NEHU, Shillong 2 / 36

Experiment - 1
1 Simulation of a CMOS inveter[NOT] logic gate

1.1 CMOS inveter[NOT] logic gate
0
VDD VDD
3
M2 2/1
Input Output Input 1 2 Output

A A A A
A Y =A M1 2/1
(a) (b) (c)
Fig. 1.1: CMOS inverter: (a) logic symbol, (b) inverter circuit, and (c) inverter
circuit for SPICE circuit description.
1.2 SPICE Circuit Description

SPICE deck of the circuit shown in Fig. 1.1(c). is provided below
CMOS INVERTER with LEVEL2 device model

*L=Length of the channnel in meter, W=Width of the channel in meter
VDD 3 0 DC 5V
VIN 1 0 PULSE 0 5 0.0 1NS 1NS 4NS 10NS
M1 2 1 0 0 N L=0.8U W=1.6U
M2 3 1 2 3 P L=0.8U W=1.6U
*Level 2 MOSFET model, TOX=oxide thickness in meter
.MODEL N NMOS Level=2 TOX=1.750000e-08
.MODEL P PMOS Level=2 TOX=1.750000e-08
.TRAN 1NS 16NS
.PROBE
.END
1.3 Observation and Result

1.3.1 Output of the SPICE deck given in 1.2
After simulating the above deck, we have got the graph of input voltage versus output
voltage as shown below in the Fig. 1.2.
(a)

(b)
Fig. 1.2: Output-voltage versus input-voltage of a CMOS INVERTER with LEVEL2

device model
1.3.2 Output of the SPICE CMOS inverter deck for various input conditions
Check the output of the circuit for
- Different duty cycle pulse input, for example,

- A sinusoidal input, say,
VIN 1 0 SIN 2.5 2.5 20MEG
VIN 1 0 SIN 0 5 20MEG 0.0 0.0
- Different Device Parameters such as
M1 2 1 0 0 N L=0.8U W=0.8U AD=3.2P AS=3.2P PD=5.2U AD=5.2U
M2 3 1 2 3 P L=0.8U W=0.8U AD=3.2P AS=3.2P PD=5.2U AD=5.2U
- Different Model Parameters, for example,
.MODEL N NMOS LEVEL=2 LD=4.000E-8 TOX=1.750000E-08
+NSUB=1.506725E+17 VTO=0.59073 KP=6.124495E-05
.MODEL P PMOS LEVEL=2 LD=4.000000E-08 TOX=1.750000E-08
- Probe Input Voltage vs Output Voltage for each case.
If we want automatic display of transient analysis graph of branch voltages, for example-
input voltage and output voltage, then the .PLOT card may be included in the SPICE
deck. Hence, the above program is rewritten as
CMOS INVERTER with LEVEL2 device model

VIN 1 0 PULSE 0 5 0.0 0.3NS 0.3NS 2NS 4.5NS
VDD 3 0 DC 5V
M1 0 1 2 0 N L=0.8U W=1.6U
M2 3 1 2 3 P L=0.8U W=1.6U
*Level 2 MOSFET model, TOX=oxide thickness in meter
.MODEL N NMOS Level=2 TOX=1.750000e-08
.MODEL P PMOS Level=2 TOX=1.750000e-08
.TRAN 1NS 16NS
.PLOT TRAN V(1) V(2)
.PROBE
.END

1.3.3 Output of the logic gate for different Transistor Ratios

Check the I/O voltage waveform for different gate sizes.
VDD VDD VDD
2/1 2/1 1/1
A Y =A A Y =A A Y =A
1/1 1/2 1/1
(a) (b) (c)
Fig. 1.3: CMOS inverter for different (W/L)p and (W/L)n ratios.
- When (W/L)n = 1 : 1 and (W/L)p = 2 : 1, we I/O waveform as

Experiment - 2
2 Simulation of CMOS NAND gates

2.1 Simulation of 2-input CMOS NAND gate
2-input NAND gate logic symbol and its CMOS circuit for 0.8 technology[Consider transistor
ratios of both QN and QP of the basic inverter is W/L = 2/1].
VDD
A
A
Y
B
B
(a) Logic symbol. (b) 2-input CMOS NAND gate circuit.
Fig. 2.1: 2-input NAND gate: Y = A.B.
The 2-input NAND gate circuit of Fig. 2.1(b) is redrawn to emphasize nodes, reference node
and transistor labels as shown in Fig. 2.3. Transistor sizing is then done based on the reference
inverter given in Fig. 2.2 in which L = 0.8m and W = 1.6m.
VDD
VDD
5
2/1
M4 M3
4
Y
A Y =A
A M2
2
3
2/1
B M1
1
0
Fig. 2.2: Reference CMOS Inverter. Fig. 2.3: Redrawn circuit with reference node
chosen and transistors labeled on the circuit of
Fig. 2.1(b).
Transistor sizing of the cmos circuit of Fig. 2.3: For the pull-up network, it is found
that all pmos transistors are in parallel. When any one of the transistor, either M 3 or M 4, is
active, the output terminal, Y, will be pulled-up to VDD , that is, the pull-up network (PUN)

shall be able to provide a charging current at least equal to that of a pmos transistor of the
basic inverter. Therefore, M 3 and M 4 will have the same transistor ratio as that of the pmos
of the basic inverter circuit, that is, W/L = 2/1.
As for transistors in the pull-down network (PDN), all of them are in series. Therefore, the worst
case scenario is obtained, that is, the lowest output current which is equal to that of the basic
inverter is resulted, when all nmos in PDN are active. Hence, the equivalent series resistance,
Reqv. , of PDN of Fig. 2.3 is obtained by adding on-resistance of each nmos transistor as
Reqv. = rDS1 + rDS2

K K
= + , where K = some constant
(W/L)1 (W/L)2

1 1
=K +
(W/L)1 (W/L)2
Assuming that all nmos transistors in the PDN have the equal transistor ratio, then, for conve-
nience, it may be denoted as (W/L)n . Thus,
1 1 1 2
= + =
(W/L)eqv. (W/L)n (W/L)n (W/L)n
That is,

W W
=2
L n L eqv.
But for the basic inverter,

W 2
=
L n, INV. 1
Hence,

W 2 4
=2 = =4:1
L n 1 1
that is, M 1 and M 2 will have the transistor ratio of W : L = 4 : 1. Complete circuit with
proper transistor sizing is then shown below in Fig. 2.4.
VDD
M4 2/1 M3 2/1
4
Y
A M2 4/1
2
3
B M1 4/1
1
0
Fig. 2.4: 2-input CMOS NAND logic circuit.

2.1.1 SPICE Circuit Description

SPICE Circuit Description of the circuit of 2-input NAND CMOS Logic Circuit of Fig. 2.4 is
2-input CMOS NAND Gate

VA 2 0 PULSE 0.0 2.5 0 1N 1N 5N 12N
VB 1 0 PULSE 0.0 2.5 2.5N 1N 1N 5N 12N
VDD 5 0 DC 2.5V
M1 3 1 0 0 N L=0.8U W=3.2U
M2 4 2 3 0 N L=0.8U W=3.2U
M3 5 2 4 5 P L=0.8U W=1.6U
M4 5 1 4 5 P L=0.8U W=1.6U
*Level 2 MOSFET model, Tox=oxide thickness in meter
.MODEL N NMOS Level=2 Tox=1.750000e-08
.MODEL P PMOS Level=2 Tox=1.750000e-08
.TRAN 1NS 50NS
.PROBE
.END
2.1.2 Observation and Result

2.1.2.1 Output of the SPICE deck given in the subsection 2.1.1
After simulating the above deck, we have got the graph of input voltage versus output
voltage as shown below in the Fig. 2.5
(a)
(b)
Fig. 2.5: Output-voltage versus input-voltage of a 2-input CMOS NAND gate with
LEVEL2 device model

2.1.2.2 With various duty cycles of the input PULSEs in the SPICE deck of sub-
section 2.1.1
- When the duty cycle of both input is 30%, we observe
- When the duty cycle of both input is 70%, we see
- When i/p A and B have 30% and 70% duty cycles respectively, input-output waveform
is
2.1.2.3 For different Device Parameters in the SPICE deck of subsection 2.1.1
Let us consider the channel length of each transistor as L = 0.25m while other
parameters like AD=3.2P AS=3.2P PD=5.2U AD=5.2U are introduced, we have the
SPICE deck of the 2-input CMOS NAND gate of Fig. 2.4 as
2-input CMOS NAND Gate for 0.25micron technology
VDD 5 0 DC 2.5V
VA 2 0 PULSE 0.0 2.5 0 1N 1N 5N 12N
VB 1 0 PULSE 0.0 2.5 2.5N 1N 1N 5N 12N

.TRAN 1NS 50NS

.PROBE
.END
Output after simulating the above SPICE deck is
2.1.2.4 For different Model Parameters in the SPICE deck of subsubsection 2.1.1
- .MODEL N NMOS Level=2 Tox=1.750000e-08

+ PHI=0.6 GAMMA=0.5 VTO=0.2 KP=6.124495E-05
- .MODEL P PMOS Level=2 Tox=1.750000e-08

+ PHI=0.6 GAMMA=0.5 VTO=0.95 KP=6.124495E-05
Output after simulating the above SPICE deck is

2.2 3-input CMOS NAND gate circuit

Here, we have considered 0.8 technology in a reference CMOS inverter with equal transistor
ratios, W = 2L, for both NMOS and PMOS.
VDD VDD
M4 2/1 M5 2/1 M6 2/1

6
Y Y
A A M3 6/1
5
4
B B M2 6/1
3
2
C C M1 6/1
1
0
(a) (b)
Fig. 2.6: 3-input CMOS NAND gate: Y = A.B.C.
Transistor sizing: Transistor sizing determination of all transistors in the circuit of Fig. 2.6(a)
is
Show transistor sizing calculation here!
2.2.1 SPICE deck for this 3-input NAND gate

VDD 7 0 DC 5.0V
VA 5 0 PULSE 0.0 5.0 0 1N 1N 5N 12N
VB 3 0 PULSE 0.0 5.0 1.5N 1N 1N 5N 12N
VC 1 0 PULSE 0.0 5.0 2.5N 1N 1N 5N 12N
M1 2 1 0 0 N L=0.8U W=4.8U
M2 4 3 2 0 N L=0.8U W=4.8U
M3 6 5 4 0 N L=0.8U W=4.8U
M4 6 1 7 7 P L=0.8U W=1.6U
M5 6 3 7 7 P L=0.8U W=1.6U
M6 6 5 7 7 P L=0.8U W=1.6U
.TRAN 1NS 50NS
.PROBE
.END


Output of the SPICE deck given in the subsection 2.1.2.3
After simulating the above deck, we have got the graph of input voltage versus output voltage
as shown below in the Fig. 2.7
(a)
(b)
LEVEL2 device model
With various duty cycles of the input PULSEs in the SPICE deck of subsec-
tion 2.1.2.3
- When i/p A and B have 30% and 70% duty cycles respectively, input-output waveform is

2.3 4-input CMOS NAND gate circuit

Here, we have considered 0.8 technology in a reference CMOS inverter with equal transistor
ratios, W = 2L, for both NMOS and PMOS.
VDD VDD
M5 2/1 M6 2/1 M7 2/1 M8 2/1

8
Y Y
A A M4 8/1
7
6
B B M3 8/1
5
4
C C M2 8/1
3
2
D D M1 8/1
1
0
(a) (b)
Fig. 2.8: 4-input CMOS NAND gate: Y = A.B.C.D.
Transistor sizing of the cmos circuit of Fig. 2.8(a):

Since all transistors in the pull-down network (PDN) are in series. Hence, the equivalent series
drain-source resistance, Reqv. , of PDN of Fig. 2.8(a) is obtained by adding on-resistance of each
nmos transistor as
Reqv. = rDS1 + rDS2 + rDS3 + rDS4

K K K K K
= + + + , where K = some constant
(W/L)eqv. (W/L)1 (W/L)2 (W/L)3 (W/L)4
1 4
=
(W/L)eqv. (W/L)n
assuming that all nmos transistors in the PDN have the equal transistor ratio and it is denoted
by (W/L)n .
Finally, for the given basic inverter transistor

W 2
=
L n, INV. 1
we arrive at the following transistor ratio

W W W 2 8
=4 =4 =4 = =8:1
L n L eqv. L n, INV. 1 1
that is, M 1, M 2, M 3 and M 4 will have the transistor ratio of W : L = 8 : 1. However, each of
the pmos transistor of Fig. 2.8(a) will have the transistor ratio equal to that of the basic inverter
circuit as all pmos transistors in this PUN are in series. Complete circuit with proper transistor
sizing is then shown in Fig. 2.8(b).

2.3.1 SPICE deck for this 4-input NAND gate

SPICE deck for the 4-input NAND gate is

*VDD Supply
VDD 9 0 DC 5.0V
* Input signals
VA 7 0 PULSE 0.0 5.0 0 1N 1N 5N 12N
VB 5 0 PULSE 0.0 5.0 1.5N 1N 1N 5N 12N
VC 3 0 PULSE 0.0 5.0 2.5N 1N 1N 5N 12N
VD 1 0 PULSE 0.0 5.0 3.5N 1N 1N 5N 12N
M1 2 1 0 0 N L=0.8U W=6.4U
M2 4 3 2 0 N L=0.8U W=6.4U
M3 6 5 4 0 N L=0.8U W=6.4U
M4 8 7 6 0 N L=0.8U W=6.4U
M5 8 1 9 9 P L=0.8U W=1.6U
M6 8 3 9 9 P L=0.8U W=1.6U
M7 8 5 9 9 P L=0.8U W=1.6U
M8 8 7 9 9 P L=0.8U W=1.6U
.TRAN 0NS 50NS
.PROBE
.END

Output of the SPICE deck given in the subsection 2.3.1
(a)

(b)
LEVEL2 device model
With various duty cycles of the input PULSEs in the SPICE deck of subsection 2.3.1

Experiment - 3
3 Simulation of CMOS AND gates

3.1 2-input CMOS AND gate circuit
Put circuit diagram here!
(a) (b)
Fig. 3.1: 2-input CMOS AND gate.
Transistor sizing of the cmos circuit of Fig. 3.1
Put transistor sizing calculation here!
3.1.1 SPICE deck for the 2-input CMOS AND gate
Put SPICE DECK for 2-input CMOS AND Gate here!

(a)

(b)
Fig. 3.2: Output-voltage versus input-voltage of a 2-input CMOS AND gate with
LEVEL2 device model

3.2 3-input CMOS AND gate circuit

(a) (b)
Fig. 3.3: 2-input CMOS NOR gate.
3.2.1 SPICE deck for the 3-input CMOS AND gate
Put SPICE DECk for 3-input CMOS AND Gate here!

as shown below in Fig. 3.4:
(a)

(b)
Fig. 3.4: Output-voltage versus input-voltage of a 3-input CMOS AND gate with
LEVEL2 device model

Experiment - 4
4 Simulation of CMOS NOR gates

4.1 2-input CMOS NOR gate circuit
(a) (b)
4.1.1 SPICE deck for the 2-input CMOS NOR gate
Put SPICE DECK for 2-input NOR Gate here!

(a)

(b)
Fig. 4.2: Output-voltage versus input-voltage of a 2-input CMOS NOR gate with
LEVEL2 device model

4.2 3-input CMOS NOR gate circuit

(a) (b)
4.2.1 SPICE deck for the 3-input CMOS NOR gate
Put SPICE DECK for 3-input NOR Gate here!

(a)

(b)
Fig. 4.4: Output-voltage versus input-voltage of a 3-input CMOS NOR gate with
LEVEL2 device model

Experiment - 5
5 Simulation of CMOS OR gates

5.1 2-input CMOS OR gate circuit
(a) (b)
Fig. 5.1: 2-input CMOS OR gate.
5.1.1 SPICE deck for the 2-input CMOS OR gate
Put SPICE DECK for 2-input OR Gate here!

(a)

(b)
Fig. 5.2: Output-voltage versus input-voltage of a 2-input CMOS OR gate with

LEVEL2 device model

5.2 3-input CMOS OR gate circuit

(a) (b)
5.2.1 SPICE deck for the 3-input OR gate
Put SPICE DECK for 3-input OR Gate here!

(a)

(b)
Fig. 5.4: Output-voltage versus input-voltage of a 3-input CMOS OR gate with

LEVEL2 device model

Experiment - 6
6 Simulation of 3-input CMOS combinational logic circuit

6.1 Implementation of combination logic: Y = AB + C
VDD VDD
5
5
M1 2W M4 2W M8 4W
8
4
A
A M3 2W M7 4W
B 1
7
3 Y
Y 6
C
B M2 2W M5 W M6 W
2 C
0 0
(a) Logic diagram of the given boolean (b) CMOS realization of (a).
function.
Fig. 6.1: CMOS circuit for Y = AB + C
The given combinational logic is presented in Fig. 6.1(b) where transistor ratios of the basic
inverter are (W/L)n = W and (W/L)p = 2W . The truth table of the given realization:
A B C Y
0 0 0 0
0 1 0 0
X= don0 t care
1 0 0 0
1 1 0 1
X X 1 0
Transistor sizing of the cmos comobinational logic circuit of Fig. 6.1(b):
6.1.1 SPICE deck for the 3-input combinational logic circuit
Put the SPICE DECK of the combinational logic here!

as shown below:
Put the output waveform after running the above SPICE DECK!

Experiment - 7

7.1 Implementation of combination logic: Y = (A + B).C = A + B + C
VDD VDD
5
5
2
A M4 4W M5 2W M8 2W
4 Y
8
A B
1
M3 4W M7 2W
3
B 3
7
Y M1 W M2 W C M6 2W
C 6
0 0
(a) Logic diagram of the given boolean (b) CMOS realzation of (a).
function.
Fig. 7.1: CMOS circuit for Y (A + B).C = A + B + C
A B C Y
X X 0 1
0 0 1 0
X= don0 t care
0 1 1 1
1 0 1 1
1 1 1 1

as shown below:

Experiment - 8

VDD VDD
7
M3 4W M6 4W
6
M8 2W
M5 4W
5
A 8 Y
5
B A M2 2W
1
3 C M4 W M7 W
Y 4
C B M1 2W
2
0
0
(a) Logic diagram of the given (b) CMOS realization of Y = AB + C.

boolean function.
A B C Y
0 0 0 0
0 1 0 0
X= don0 t care
1 0 0 0
1 1 0 1
X X 1 1

as shown below:

Experiment - 9

9.1 Implementation of combination logic: Y = (A + B).C = A.B.C
VDD VDD VDD
5 5
5
2
A M4 4W M5 2W M8 2W M10 2W
4 8
8 9 Y
1
B M3 4W M7 2W
A 3
3
B 7 M9 W
Y M1 W M2 W C M6 2W
6
C
0 0 0
(a) Logic diagram of the given (b) CMOS realization of (a).

boolean function.
A B C Y
X X 0 0
0 0 1 1
X= don0 t care
0 1 1 0
1 0 1 0
1 1 1 0

as shown below:

Experiment - 10

VDD VDD VDD
5 5
5
M1 2W M4 2W M8 4W M10 2W
8
4
A M3 2W M7 4W 9 Y
A 1
7
B 3
6
Y B M2 2W M5 W M6 W M9 W
2 C
C
0 0 0
(a) Logic diagram of the given (b) CMOS realization of (a).

boolean function.
A B C Y
0 0 0 1
0 1 0 1
X= don0 t care
1 0 0 1
1 1 0 0
X X 1 1

as shown below:

Experiment - 11
11 Simulation of 3-input complex CMOS logic circuit

11.1 Implementation of complex CMOS logic gate: Y = AB + C
VDD VDD
7 7
M3 M6 M3 4W M6 4W
6 6
M5 M5 4W
5 5
Y Y
A 5 5
B A M2 A M2 2W
1 1
3 C M4 3 C M4 W
Y 4 4
C B M1 B M1 2W
2 2
0 0
(a) Logic diagram of the given (b) CMOS realization of (a). (c) CMOS logic realization with
boolean function. proper transistor sizing.
The given combinational logic is presented in Fig. 11.1(c) where transistor ratios of the basic
A B C Y
0 0 0 1
0 1 0 1
X= don0 t care
1 0 0 1
1 1 0 0
X X 1 0
Transistor sizing of the cmos comobinational logic circuit of Fig. 11.1(c):

as shown below:

Experiment - 12

12.1 Implementation of complex CMOS logic gate: Y = (A + B).C
Since the nmos transistors act to pill the output low, we should compliment Y to obtain its
implementation. That is, Y = (A + B).C.
VDD
Thus, the nmos implementation requires two
parallel transistors with inputs A and B in series
with a third transistor with input C.
B M4 4W
Next, we apply DeMorgans law to Y :
C M6 2W
Y = (A + B).C = A + B + C = A.B + C
A M3 4W
Since the pmos function pulls the output high Y
and the devices effectively compliment each
C M2 2W
term, we should implement the function after
term-by-term complement. That is, we should
implement Y = AB + C using pmos devices. A M1 2W B M5 2W
This requires two series pmos trasistors to im-
plement AB and one parallel transistor with the
input C. The resulting function is an OR-AND-
INVERT(OAI) function. Fig. 12.1: Complex CMOS gate implementa-
tion of Y = (A + B).C
The given combinational logic is presented in Fig. 12.1 where transistor ratios of the basic
A B C Y
X X 0 1
0 0 1 1
X= don0 t care
0 1 1 0
1 0 1 0
1 1 1 0
Transistor sizing of the cmos comobinational logic circuit of Fig. 12.1:

as shown below:

Experiment - 13

13.1 Implementation of complex CMOS logic gate: Y = AB + CD
VDD
For the CMOS gate, we first take compliments A M4 4W B M8 4W

of Y to obtain the ncomplex function: Y =
AB + CD. This implies that we need only two
series nmos paths in parallel with one another C M3 4W D M7 4W
in PDN. One series path implements AB while
the other implements CD. Y
Next, we take dual of the compliment of Y : A M2 4W C M6 4W

Y dual = (A + B)(C + D)
B M1 4W D M5 4W
This is the function to be implemented in the
PUN.
Fig. 13.1: Complex CMOS gate implementa-

tion of Y = AB + CD.
inverter are (W/L)n = 2W and (W/L)p = 2W . The truth table of the given realization:
A B C D Y
0 0 0 0 1
0 0 0 1 1
.. .. .. .. .. X= don0 t care
. . . . .
X X 1 1 0
1 1 X X 0
1 1 1 1 0

as shown below:

Experiment - 14

14.1 Implementation of complex CMOS logic gate: Y = AB + CD
VDD VDD
For the CMOS gate, the given ncomplex A M4 4W B M8 4W

function, Y = AB + CD, implies that we
need only two series nmos paths in parallel M10 2W
with one another in PDN. One series path C M3 4W D M7 4W
implements AB while the other implements
CD. Y
Next, we take dual of the compliment of Y : A M2 4W C M6 4W
Y |dual = (A + B)(C + D) M9 2W
B M1 4W D M5 4W
This is the function to be implemented in
the PUN.
Fig. 14.1: Complex CMOS gate implementation of

Y = AB + CD.
inverter are (W/L)n = 2W and (W/L)p = 2W . The truth table of the given realization:
A B C D Y
0 0 0 0 0
0 0 0 1 0
.. .. .. .. .. X= don0 t care
. . . . .
X X 1 1 1
1 1 X X 1
1 1 1 1 1

as shown below:

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ECV - 917

Circuit Simmulation Laboratory

October 15, 2014

Name: ARJUNASOR SYIEM ECE, NEHU, Shillong 2 / 36

1 Simulation of a CMOS inveter[NOT] logic gate

Input Output Input 1 2 Output

(a) (b) (c)

1.2 SPICE Circuit Description

CMOS INVERTER with LEVEL2 device model

1.3 Observation and Result

Name: ARJUNASOR SYIEM ECE, NEHU, Shillong 3 / 36

Fig. 1.2: Output-voltage versus input-voltage of a CMOS INVERTER with LEVEL2

- Different duty cycle pulse input, for example,

CMOS INVERTER with LEVEL2 device model

Name: ARJUNASOR SYIEM ECE, NEHU, Shillong 4 / 36

1.3.3 Output of the logic gate for different Transistor Ratios

VDD VDD VDD

2/1 2/1 1/1

1/1 1/2 1/1

(a) (b) (c)

- When (W/L)n = 1 : 1 and (W/L)p = 2 : 1, we I/O waveform as

- When (W/L)n = 1 : 2 and (W/L)p = 2 : 1, we I/O waveform as

- When (W/L)n = 1 : 1 and (W/L)p = 1 : 1, we I/O waveform as

Name: ARJUNASOR SYIEM ECE, NEHU, Shillong 5 / 36

2 Simulation of CMOS NAND gates

(a) Logic symbol. (b) 2-input CMOS NAND gate circuit.

Fig. 2.1: 2-input NAND gate: Y = A.B.

Name: ARJUNASOR SYIEM ECE, NEHU, Shillong 6 / 36

Reqv. = rDS1 + rDS2

But for the basic inverter,

Fig. 2.4: 2-input CMOS NAND logic circuit.

Name: ARJUNASOR SYIEM ECE, NEHU, Shillong 7 / 36

2.1.1 SPICE Circuit Description

2-input CMOS NAND Gate

2.1.2 Observation and Result

Name: ARJUNASOR SYIEM ECE, NEHU, Shillong 8 / 36

- When the duty cycle of both input is 30%, we observe

- When the duty cycle of both input is 70%, we see

Name: ARJUNASOR SYIEM ECE, NEHU, Shillong 9 / 36

.TRAN 1NS 50NS

- .MODEL N NMOS Level=2 Tox=1.750000e-08

- .MODEL P PMOS Level=2 Tox=1.750000e-08

Name: ARJUNASOR SYIEM ECE, NEHU, Shillong 10 / 36

2.2 3-input CMOS NAND gate circuit

M4 2/1 M5 2/1 M6 2/1

Fig. 2.6: 3-input CMOS NAND gate: Y = A.B.C.

Show transistor sizing calculation here!

2.2.1 SPICE deck for this 3-input NAND gate

3-input CMOS NAND Gate

Name: ARJUNASOR SYIEM ECE, NEHU, Shillong 11 / 36

2.2.2 Observation and Result

Name: ARJUNASOR SYIEM ECE, NEHU, Shillong 12 / 36

2.3 4-input CMOS NAND gate circuit

M5 2/1 M6 2/1 M7 2/1 M8 2/1

Fig. 2.8: 4-input CMOS NAND gate: Y = A.B.C.D.

Transistor sizing of the cmos circuit of Fig. 2.8(a):

Reqv. = rDS1 + rDS2 + rDS3 + rDS4

we arrive at the following transistor ratio

Name: ARJUNASOR SYIEM ECE, NEHU, Shillong 13 / 36

2.3.1 SPICE deck for this 4-input NAND gate

4-input CMOS NAND Gate

2.3.2 Observation and Result

Name: ARJUNASOR SYIEM ECE, NEHU, Shillong 14 / 36