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DIAGRAMA DE BLOQUE

a
E b
x c
D ENTIDAD d
x Decodificador de e
C letras f
x g
B
x
A
x
DISTRIBUCIN DEL DISPLAY DE 7 SEGMENTOS
a
f
g b
e
c
d

TABLA DE LA VERDAD

LET F6 F5 F4 F3 F2 F1 F0
RA
Q3 Q2 Q1 Q0 a b c d e f g
0 0 0 0 a ON ON ON ON ON OF ON
F
0 0 0 1 b OF OF ON ON ON ON ON
F F
0 0 1 0 c OF OF OF ON ON OF ON
F F F F
0 0 1 1 d OF ON ON ON ON OF ON
F F
0 1 0 0 e ON ON OF ON ON ON ON
F
0 1 0 1 F ON OF OF OF ON ON ON
F F F
0 1 1 0 g ON ON ON ON OF ON ON
F
0 1 1 1 h OF OF ON OF ON ON ON
F F F
1 0 0 0 i OF OF ON OF OF OF OF
F F F F F F

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1 0 0 1 J OF ON ON ON ON OF OF
F F F
1 0 1 0 L OF OF OF ON ON ON OF
F F F F
1 0 1 1 n OF OF ON OF ON OF ON
F F F F
1 1 0 0 o OF OF ON ON ON OF ON
F F F
1 1 0 1 p ON ON OF OF ON ON ON
F F
1 1 1 0 q ON ON ON OF OF ON ON
F F
1 1 1 1 r OF OF OF OF ON OF ON
F F F F F
- OF OF OF OF OF OF ON
F F F F F F

PROGRAMA EN VHDL

1. library ieee;
2. use ieee.std_logic_1164.all;
3. entity decodificador_de_letras is port (
4. Q: in std_logic_vector (3 downto 0);
5. F: out std_logic_vector (6 downto 0);
6. end decodificador_de_letras;
7. architecture asi_funciona of decodificador_de_letras is
8. begin
9. -Inicia descripcin arquitectura;
10. with Q select
11. F<= 1111101 when 0000,
12. 0011111 when 0001,
13. 0001101 when 0010,
14. 0111101 when 0011,
15. 1101111 when 0100,
16. 1000111 when 0101,
17. 1111011 when 0110,
18. 0010111 when 0111,
19. 0010000 when 1000,
20. 0111100 when 1001,
21. 0001110 when 1010,
22. 0010101 when 1011,
23. 0011101 when 1100,
24. 1100111 when 1101,
25. 1110011 when 1110,
26. 0000101 when 1111,
27. 0000001 when others,
28. end asi_funciona;
29. -Finalizacin del cdigo en lenguaje VHDL;

2 CHRISTIAN GILBERTO MUOZ PINEDA

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