16MVD0070

S. Raveen Kumar

Task : 3 FPGA Implementation of FSM Controllers

Aim:
To design and implement a FSM controller for detecting 1010 and 0101 sequence when
enable is 1 and enable is 0 respectively.

Software Details:
For design Functional Simulation: Modelsim
For design Synthesis: Quartus II
For design Implementation: Quartus II

Hardware Details:
Family: Cyclone IV
Device: EP4C
Package: FBGA
Pin count: 780

Program Code:

//main code

module sequence_detector4(clk,rst,en,x,z);
input clk,rst,x,en;
output z;
reg z;
parameter a=2'b00,b=2'b01,c=2'b10,d=2'b11;
reg[1:0]ps,ns;

always@(posedge clk)
begin
if(rst)
ps<=a;
else
ps<=ns;
end

always@(ps or x)
begin
z<=1'b0;
if(en)
case(ps)
 16MVD0070
S. Raveen Kumar

a: ns<=x?b:a;
b: ns<=x?b:c;
c: ns<=x?d:a;
d: begin
ns<=x?b:a;
z<=x?0:1;
end
endcase

else
case(ps)
a: ns<=x?a:b;
b: ns<=x?c:b;
c: ns<=x?a:d;
d: begin
ns<=x?a:b;
z<=x?1:0;
end
endcase
end
endmodule

//test bench
module sequence_detector_tb();
reg clk,rst,en,x;
wire z;
sequence_detector4 f1(clk,rst,en,x,z);
initial
begin
clk=1'b0;
rst=1'b1;
x=1'b0;
en=1'b1;
end

initial
begin
#100 rst=~rst;
end

always #50 clk=~clk;

 16MVD0070
S. Raveen Kumar

always #100 x=~x;

always #2000 en=~en;

initial
begin
$monitor($time,"output z= %b for input x= %b",z,x);
end
endmodule

State Machine Viewer:

 16MVD0070
S. Raveen Kumar

Transcript Output:
 16MVD0070
S. Raveen Kumar

Modelsim Simulation Output:

Enable=1 ---> 1010 Sequence Detected

Enable=0 ---> 0101 Sequence Detected
 16MVD0070
S. Raveen Kumar

Implementation:
Reset = 1, Output = 0

Reset =0, Enable = 1, Output = 1 for 1010 sequence

 16MVD0070
S. Raveen Kumar

Reset = 0, Enable = 0, Output = 1 for 0101 sequence

Inference:

The design and implementation a FSM controller for detecting 1010 and 0101
sequence when enable is 1 and enable is 0 respectively is performed using the Quartus
II and verified using ModelSim. The same has been implemented in the Altera Cyclone
IV E FPGA kit and has been verified.