La-9869p Vdkte r03

A B C D E
1 1
VDKTE
2
Rosetta 10ADT/10ADTG 2
LA-9869P REV 0.3 Schematic

AMD APU RICHLAND FP2 / FCH BOLTON-M3
3
Sun Pro M2 3
2013-02-04 Rev 0.3
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2013/01/22 Deciphered Date 2014/01/21 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9869P
Date: Monday, February 04, 2013 Sheet 1 of 50
A B C D E
A B C D E
eDP Conn.
page 20 GCLK
SLG3NB283VTR (UMA)
page 29
LVDS Conn. LVDS Translator DP0 (X2) GCLK

RTD2132S PWM Fan Control
page 20 SLG3NB302VTR (DIS)
1
page 19 AMD APU page 5 page 29 1
FP2 Processor
GPU PCI-Express X8 5GHz
Sun Pro M2 Memory BUS(DDRIII)

200pin DDRIII-SO-DIMM X2
page 12~18 Trinity BGA-813 Dual Channel BANK 0, 1, 2, 3 page 10,11
27mm*31mm
1.5V DDRIII 1333/1600 MT/s
HDMI Conn DP2 (X4) page 5,6,7,8,9
page 27 DP1 Left USB2.0 Int. Camera Touch screen

PCIe X1 (X4) UMI X4 PCIe X1
USB port 0 USB port 1 USB port 4
1.2V 5GT/s 2.5GT/s 1.2V 5GT/s page 30 page 25 page 25
Right USB 3.0 Right USB 3.0

USB2.0 USB port 10 USB port 11
page 31 page 31
5V 480MHz
2 2
CRT
page 21
USB2.0 PCIeMini Card
5V 480MHz WLAN + BT
USB port 3
APU PCIe port 1
AMD FCH page 28
RTL8106E 10/100M
Hudson M3 SATA port 0 SATA HDD
5V 6GHz(600MB/s) SATA port 0
RJ45
page 30 APU PCIe port 0 page 28
page 30
SATA port 1 SATA ODD
5V 6GHz(600MB/s) SATA port 1
page 28
Cardreader Conn. FCBGA-656

USB2.0 24.5mm*24.5mm
3
GL834L 3
5V 480MHz
2 in 1 USB port 2
MMC/SD page 33 USB 3.0 USB 3.0
USB3.0 port 0
page 23,24,25,26,27 5GHz page 31
SPI Bus USB 3.0 USB 3.0

3.3V 33 MHz 5GHz USB3.0 port 1
page 31
LPC Bus HD Audio 3.3V 24MHz
3.3V 33 MHz
HDA Codec
RTC CKT. ALC259/269
SPI ROM page 32
page 19
(4MB)
page 25 ENE KB9012
page 34
DC/DC Interface CKT.
page 37 Int. SPK Conn JCRIO
page 32
4
MIC Conn (HP & page
MIC)32 4
page 33
Power Circuit DC/DC Touch Pad Int.KBD
page 36 page 35
LAN/USB board
page 38,39,40,41,42,43,
44,45,46,47,48,49 LS-9861P page 30
Power On/Off CKT. PWR/B THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
Size Document Number
Rev
page 36 LS-9862P page 36 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom
LA-9869P 0.3

A B C D E
5 4 3 2 1
DESIGN CURRENT 0.15A +3VL

DESIGN CURRENT 0A +5VL
B+
Ipeak=12A, Imax=8.4A, Iocp min=14A +5VALW
D D
SUSP
N-CHANNEL DESIGN CURRENT 4A +5VS

SI4800
RT8243A
Ipeak=8A, Imax=5.6A, Iocp min=10A
+3VALW
WOL_EN#
P-CHANNEL DESIGN CURRENT 330mA +3V_LAN

AO-3413
SUSP
N-CHANNEL DESIGN CURRENT 4A +3VS

SI4800 LCD_ENVDD
P-CHANNEL DESIGN CURRENT 1.5A +LCD_VDD

AO-3413
C C
DGPU_PWR_EN
DESIGN CURRENT 60mA +3VS_DGPU
P-CHANNEL
AO-3413
VGA_PWRGD
DESIGN CURRENT 0.5A 1.8VGSP

SY8032
DESIGN CURRENT 0.75A 2.5VSP

APL5508
SYSON
Ipeak=12A, Imax=8.4A, Iocp min=13.8A +1.5V
RT8207M SUSP
N-CHANNEL DESIGN CURRENT 2A +1.5V_CPU

FDS6676AS
DESIGN CURRENT 2A +1.5VS

PJ1
B B
DESIGN CURRENT 1.5A +0.75VS
1.1VPWR_EN
Ipeak=5.3A, Imax=3.71A, Iocp min=16A +1.1VALWP
SY8208D SUSP#
+1.1VS
FDS6676
VR_ON
Ipeak=7A, Imax=4.9A, Iocp min=16A +1.2VS
SY8208D
VR_ON
Ipeak=36A, Imax=25.2A, Iocp min=60A APU_CORE
ISL6277 Ipeak=30A, Imax=21A, Iocp min=50A APU_CORE_NB
A A
GPU_DPRSLPVR
Ipeak=21A, Imax=14.7A, Iocp min=40A VGA_CORE
ISL62881

Power Tree
0.3
LA-9869P
5 4 3 2 1
A B C D E
( O MEANS ON X MEANS OFF )

Voltage Rails
+5VS BTO Option Table
+RTCVCC B+ VL +5VALW +1.5V
+3VS
+3VL +3VALW Function APU FCH GPU
+2.5VS
1 1
power +1.5VS description Bolton
plane +1.2VS
explain R1 R3 R1 R3 R1 R3
+1.1VS
+0.75VS BTO BOLTONR1@ HUDM3R3@
+APU_CORE
+APU_CORE_NB
+1.1VALW Function 3D sensor KB LED Clock UMA/DIS
State
description K 1G U
explain G-sensor KB LED Green Clock No Green Clock DIS UMA
BTO GSENSOR@ KBL@ GCLK@ NOGCLK@ VGA@ UMA@
S0
O O O O O O
Function Panel
S1
O O O O O O description S D
2 2
S3 explain LVDS eDP

O O O O O X
BTO LVDS@ IEDP@
S5 S4/AC
O O O O X X
S5 S4/ Battery only
O O O X X X
S5 S4/AC & Battery
don't exist
O X X X X X
FCH SM Bus Address (SCL0/SDA0)
Power Device HEX Address
3
+3VS DDR SO-DIMM 0 A0 H 1010 000X b 3
+3VS DDR SO-DIMM 1 A2 H 1010 001X b

+3VS WLAN
EC SM Bus1 Address EC SM Bus3 Address
Power Device HEX Address Power Device HEX Address SIGNAL

STATE SLP_S3# SLP_S5#
+3VL Smart Battery 16 H 0001 0110 b +3VS LVDS Translator 94 H 1001 0100 b
Full ON HIGH HIGH
+3VL Charger 12 H 0001 0010 b
S1(Power On Suspend) HIGH HIGH
S3 (Suspend to RAM) LOW HIGH

EC SM Bus2 Address
S4 (Suspend to Disk) LOW HIGH
Power Device HEX Address S5 (Soft OFF) LOW LOW
4
+3VL SB-TSI 98 H 1001 1001 b 4
G3 LOW LOW
+3VS G-Sensor 40 H 0100 0000 b
+3VS VGA Thermal 82H 1000 0010 b

Notes List
Rev
Custom 0.3
LA-9869P
A B C D E
A B C D E
<12> PCIE_GTX_C_ARX_P[0..3] PCIE_ATX_C_GRX_P[0..3] <12>
<12> PCIE_GTX_C_ARX_N[0..3] PCIE_ATX_C_GRX_N[0..3] <12>
UAPUA
PCIE_GTX_C_ARX_P0 AP1 AN1 PCIE_ATX_GRX_P0 C1 1 2 VGA@ 0.1U_0402_16V7K PCIE_ATX_C_GRX_P0
PCIE_GTX_C_ARX_N0 AP2 P_GFX_RXP[0] P_GFX_TXP[0] AN2 PCIE_ATX_GRX_N0 C15 1 2 VGA@ 0.1U_0402_16V7K PCIE_ATX_C_GRX_N0
PCIE_GTX_C_ARX_P1 AM1 P_GFX_RXN[0] P_GFX_TXN[0] AM4 PCIE_ATX_GRX_P1 C17 1 2 VGA@ 0.1U_0402_16V7K PCIE_ATX_C_GRX_P1
PCIE_GTX_C_ARX_N1 AM2 P_GFX_RXP[1] P_GFX_TXP[1] AM3 PCIE_ATX_GRX_N1 C11 1 2 VGA@ 0.1U_0402_16V7K PCIE_ATX_C_GRX_N1
PCIE_GTX_C_ARX_P2 AK3 P_GFX_RXN[1] P_GFX_TXN[1] AK2 PCIE_ATX_GRX_P2 C7 1 2 VGA@ 0.1U_0402_16V7K PCIE_ATX_C_GRX_P2
1 1
PCIE_GTX_C_ARX_N2 AK4 P_GFX_RXP[2] P_GFX_TXP[2] AK1 PCIE_ATX_GRX_N2 C14 1 2 VGA@ 0.1U_0402_16V7K PCIE_ATX_C_GRX_N2
PCIE_GTX_C_ARX_P3 AJ1 P_GFX_RXN[2] P_GFX_TXN[2] AH1 PCIE_ATX_GRX_P3 C13 1 2 VGA@ 0.1U_0402_16V7K PCIE_ATX_C_GRX_P3
PCIE_GTX_C_ARX_N3 AJ2 P_GFX_RXP[3] P_GFX_TXP[3] AH2 PCIE_ATX_GRX_N3 C8 1 2 VGA@ 0.1U_0402_16V7K PCIE_ATX_C_GRX_N3
AH4 P_GFX_RXN[3] P_GFX_TXN[3] AF3
AH3 P_GFX_RXP[4] P_GFX_TXP[4] AF4
AF2 P_GFX_RXN[4] P_GFX_TXN[4] AE1
AF1 P_GFX_RXP[5] P_GFX_TXP[5] AE2
AD1 P_GFX_RXN[5] P_GFX_TXN[5] AD4
AD2 P_GFX_RXP[6] P_GFX_TXP[6] AD3
AB3 P_GFX_RXN[6] P_GFX_TXN[6] AB2
GRAPHICS
AB4 P_GFX_RXP[7] P_GFX_TXP[7] AB1
AA1 P_GFX_RXN[7] P_GFX_TXN[7] Y1
AA2 P_GFX_RXP[8] P_GFX_TXP[8] Y2
Y4 P_GFX_RXN[8] P_GFX_TXN[8] V3
Y3 P_GFX_RXP[9] P_GFX_TXP[9] V4
V2 P_GFX_RXN[9] P_GFX_TXN[9] U1
V1 P_GFX_RXP[10] P_GFX_TXP[10] U2
T1 P_GFX_RXN[10] P_GFX_TXN[10] T4
T2 P_GFX_RXP[11] P_GFX_TXP[11] T3
P3 P_GFX_RXN[11] P_GFX_TXN[11] P2
P4 P_GFX_RXP[12] P_GFX_TXP[12] P1
N1 P_GFX_RXN[12] P_GFX_TXN[12] M1
N2 P_GFX_RXP[13] P_GFX_TXP[13] M2
M4 P_GFX_RXN[13] P_GFX_TXN[13] K3
M3 P_GFX_RXP[14] P_GFX_TXP[14] K4
K2 P_GFX_RXN[14] P_GFX_TXN[14] J1
K1 P_GFX_RXP[15] P_GFX_TXP[15] J2
P_GFX_RXN[15] P_GFX_TXN[15]
2 AH5 AG7 PCIE_FTX_LANRX_P0 C50 1 2 0.1U_0402_16V7K 2
<30> PCIE_FRX_C_LANTX_P0 P_GPP_RXP[0] P_GPP_TXP[0] PCIE_FTX_C_LANRX_P0 <30>
LAN AH6 AG8 PCIE_FTX_LANRX_N0 C55 1 2 0.1U_0402_16V7K LAN
<30> PCIE_FRX_C_LANTX_N0 P_GPP_RXN[0] P_GPP_TXN[0] PCIE_FTX_C_LANRX_N0 <30>
AG5 AE7 PCIE_FTX_W LANRX_P1 C51 1 2 0.1U_0402_16V7K
<28> PCIE_FRX_W LANTX_P1 P_GPP_RXP[1] P_GPP_TXP[1] PCIE_FTX_C_W LANRX_P1 <28>
WLAN AG6 AE8 PCIE_FTX_W LANRX_N1 C54 1 2 0.1U_0402_16V7K WLAN
<28> PCIE_FRX_W LANTX_N1 P_GPP_RXN[1] P_GPP_TXN[1] PCIE_FTX_C_W LANRX_N1 <28>
AE6 AD7
AE5 P_GPP_RXP[2] P_GPP_TXP[2] AD8
AD6 P_GPP_RXN[2] P_GPP_TXN[2] AB6
GPP
AD5 P_GPP_RXP[3] P_GPP_TXP[3] AB5
P_GPP_RXN[3] P_GPP_TXN[3]
AM10 AN6 UMI_FTX_MRX_P0 C59 1 2 0.1U_0402_16V7K
<23> UMI_MTX_C_FRX_P0 P_UMI_RXP[0] P_UMI_TXP[0] UMI_FTX_C_MRX_P0 <23>
AN10 AM6 UMI_FTX_MRX_N0 C60 1 2 0.1U_0402_16V7K
<23> UMI_MTX_C_FRX_N0 P_UMI_RXN[0] P_UMI_TXN[0] UMI_FTX_C_MRX_N0 <23>
AN8 AP6 UMI_FTX_MRX_P1 C61 1 2 0.1U_0402_16V7K
AM8 AR6 UMI_FTX_MRX_N1 C62 1 2 0.1U_0402_16V7K
AP8 AP4 UMI_FTX_MRX_P2 C122 1 2 0.1U_0402_16V7K
AR8 AR4 UMI_FTX_MRX_N2 C123 1 2 0.1U_0402_16V7K
AR7 AP3 UMI_FTX_MRX_P3 C120 1 2 0.1U_0402_16V7K
AP7 AR3 UMI_FTX_MRX_N3 C121 1 2 0.1U_0402_16V7K
UMI
+1.2VS 1 2 P_ZVDDP AR11 AP11 P_ZVSS 1 2

R1 196_0402_1% P_ZVDDP P_ZVSS R2 196_0402_1%
Close to AR11 TRINITY-A8-SERIES_BGA813 Close to AP11
5745R1@
3 3
FAN Control Circuit +3VS
1
JFAN
R6
10K_0402_5% 6
5 G6
4 G5
2
3 4
<34> FANPW M 3
2
<34> FAN_SPEED1 2
1 +FAN1 1
C4 1
0.01U_0402_25V7K ACES_50273-0040N-001
@ @
2
+5VS
1A R3
2 1 +FAN1
1
0_0603_5% 1 1
@
reserve 0ohm D1 C5 C6
for Power consumption BAS16_SOT23-3 2 2
2
4 4
10U_0603_6.3V6M 1000P_0402_50V7K

AMD Trinity FP2 / GFX / UMI
Custom 0.3
LA-9869P
A B C D E
A B C D E
<11> DDR_B_DQS[0..7]
<10> DDR_A_DQS[0..7]
<11> DDR_B_DQS#[0..7]
<10> DDR_A_DQS#[0..7]
1 1
UAPUC
UAPUB <11> DDR_B_MA[0..15] Y33 C16 DDR_B_D[0..63] <11>
DDR_B_MA0 DDR_B_D0
<10> DDR_A_MA[0..15] AA28 F15 DDR_A_D[0..63] <10> R32 MB_ADD[0] MB_DATA[0] B17
DDR_A_MA0 DDR_A_D0 DDR_B_MA1 DDR_B_D1
DDR_A_MA1 R29 MA_ADD[0] MA_DATA[0] E15 DDR_A_D1 DDR_B_MA2 T31 MB_ADD[1] MB_DATA[1] B20 DDR_B_D2
DDR_A_MA2 T30 MA_ADD[1] MA_DATA[1] H19 DDR_A_D2 DDR_B_MA3 P33 MB_ADD[2] MB_DATA[2] C20 DDR_B_D3
DDR_A_MA3 R28 MA_ADD[2] MA_DATA[2] F19 DDR_A_D3 DDR_B_MA4 P32 MB_ADD[3] MB_DATA[3] A16 DDR_B_D4
DDR_A_MA4 R26 MA_ADD[3] MA_DATA[3] E14 DDR_A_D4 DDR_B_MA5 P31 MB_ADD[4] MB_DATA[4] B16 DDR_B_D5
DDR_A_MA5 P26 MA_ADD[4] MA_DATA[4] H15 DDR_A_D5 DDR_B_MA6 N32 MB_ADD[5] MB_DATA[5] B19 DDR_B_D6
DDR_A_MA6 P27 MA_ADD[5] MA_DATA[5] E17 DDR_A_D6 DDR_B_MA7 M33 MB_ADD[6] MB_DATA[6] A20 DDR_B_D7
DDR_A_MA7 P30 MA_ADD[6] MA_DATA[6] D18 DDR_A_D7 DDR_B_MA8 M32 MB_ADD[7] MB_DATA[7]
DDR_A_MA8 P29 MA_ADD[7] MA_DATA[7] DDR_B_MA9 L32 MB_ADD[8] B22 DDR_B_D8
DDR_A_MA9 M28 MA_ADD[8] G20 DDR_A_D8 DDR_B_MA10 AB31 MB_ADD[9] MB_DATA[8] C22 DDR_B_D9
DDR_A_MA10 AB26 MA_ADD[9] MA_DATA[8] E20 DDR_A_D9 DDR_B_MA11 M31 MB_ADD[10] MB_DATA[9] A26 DDR_B_D10
DDR_A_MA11 M26 MA_ADD[10] MA_DATA[9] H23 DDR_A_D10 DDR_B_MA12 K32 MB_ADD[11] MB_DATA[10] B26 DDR_B_D11
DDR_A_MA12 M29 MA_ADD[11] MA_DATA[10] G23 DDR_A_D11 DDR_B_MA13 AF33 MB_ADD[12] MB_DATA[11] B21 DDR_B_D12
DDR_A_MA13 AE27 MA_ADD[12] MA_DATA[11] E19 DDR_A_D12 DDR_B_MA14 K33 MB_ADD[13] MB_DATA[12] A22 DDR_B_D13
DDR_A_MA14 L26 MA_ADD[13] MA_DATA[12] H20 DDR_A_D13 DDR_B_MA15 J32 MB_ADD[14] MB_DATA[13] C24 DDR_B_D14
DDR_A_MA15 L27 MA_ADD[14] MA_DATA[13] E22 DDR_A_D14 MB_ADD[15] MB_DATA[14] B25 DDR_B_D15
MA_ADD[15] MA_DATA[14] D22 DDR_A_D15 DDR_B_BS0 AB33 MB_DATA[15]
DDR_A_BS0 AB27 MA_DATA[15] <11> DDR_B_BS0 DDR_B_BS1 AA32 MB_BANK[0] A28 DDR_B_D16
<10> DDR_A_BS0 AA29 MA_BANK[0] H25 <11> DDR_B_BS1 K31 MB_BANK[1] MB_DATA[16] B28
DDR_A_BS1 DDR_A_D16 DDR_B_BS2 DDR_B_D17
<10> DDR_A_BS1 M30 MA_BANK[1] MA_DATA[16] F25 <11> DDR_B_BS2 MB_BANK[2] MB_DATA[17] B31
DDR_A_BS2 DDR_A_D17 DDR_B_D18
<10> DDR_A_BS2 MA_BANK[2] MA_DATA[17] D28 <11> DDR_B_DM[0..7] C18 MB_DATA[18] A32
DDR_A_D18 DDR_B_DM0 DDR_B_D19
<10> DDR_A_DM[0..7] DDR_A_DM0 D16 MA_DATA[18] D29 DDR_A_D19 DDR_B_DM1 B23 MB_DM[0] MB_DATA[19] C26 DDR_B_D20
DDR_A_DM1 D20 MA_DM[0] MA_DATA[19] E23 DDR_A_D20 DDR_B_DM2 C28 MB_DM[1] MB_DATA[20] B27 DDR_B_D21
DDR_A_DM2 E25 MA_DM[1] MA_DATA[20] D24 DDR_A_D21 DDR_B_DM3 D31 MB_DM[2] MB_DATA[21] A30 DDR_B_D22
DDR_A_DM3 F30 MA_DM[2] MA_DATA[21] D26 DDR_A_D22 DDR_B_DM4 AM31 MB_DM[3] MB_DATA[22] C30 DDR_B_D23
DDR_A_DM4 AK29 MA_DM[3] MA_DATA[22] D27 DDR_A_D23 DDR_B_DM5 AN30 MB_DM[4] MB_DATA[23]
DDR_A_DM5 AL25 MA_DM[4] MA_DATA[23] DDR_B_DM6 AR24 MB_DM[5] B33 DDR_B_D24
2 DDR_A_DM6 AM20 MA_DM[5] G28 DDR_A_D24 DDR_B_DM7 AN18 MB_DM[6] MB_DATA[24] C32 DDR_B_D25 2
DDR_A_DM7 AM16 MA_DM[6] MA_DATA[24] G29 DDR_A_D25 MB_DM[7] MB_DATA[25] F33 DDR_B_D26
MA_DM[7] MA_DATA[25] H27 DDR_A_D26 DDR_B_DQS0 B18 MB_DATA[26] F32 DDR_B_D27
DDR_A_DQS0 G17 MA_DATA[26] J29 DDR_A_D27 DDR_B_DQS#0 A18 MB_DQS_H[0] MB_DATA[27] B32 DDR_B_D28
DDR_A_DQS#0 H17 MA_DQS_H[0] MA_DATA[27] E28 DDR_A_D28 DDR_B_DQS1 B24 MB_DQS_L[0] MB_DATA[28] C31 DDR_B_D29
DDR_A_DQS1 F22 MA_DQS_L[0] MA_DATA[28] F27 DDR_A_D29 DDR_B_DQS#1 A24 MB_DQS_H[1] MB_DATA[29] E32 DDR_B_D30
DDR_A_DQS#1 G22 MA_DQS_H[1] MA_DATA[29] H29 DDR_A_D30 DDR_B_DQS2 B30 MB_DQS_L[1] MB_DATA[30] F31 DDR_B_D31
DDR_A_DQS2 E26 MA_DQS_L[1] MA_DATA[30] H28 DDR_A_D31 DDR_B_DQS#2 B29 MB_DQS_H[2] MB_DATA[31]
DDR_A_DQS#2 F26 MA_DQS_H[2] MA_DATA[31] DDR_B_DQS3 D32 MB_DQS_L[2] AK32 DDR_B_D32
DDR_A_DQS3 H30 MA_DQS_L[2] AH29 DDR_A_D32 DDR_B_DQS#3 D33 MB_DQS_H[3] MB_DATA[32] AL32 DDR_B_D33
DDR_A_DQS#3 G30 MA_DQS_H[3] MA_DATA[32] AJ30 DDR_A_D33 DDR_B_DQS4 AM32 MB_DQS_L[3] MB_DATA[33] AP32 DDR_B_D34
DDR_A_DQS4 AL29 MA_DQS_L[3] MA_DATA[33] AM28 DDR_A_D34 DDR_B_DQS#4 AM33 MB_DQS_H[4] MB_DATA[34] AN31 DDR_B_D35
DDR_A_DQS#4 AL30 MA_DQS_H[4] MA_DATA[34] AM27 DDR_A_D35 DDR_B_DQS5 AN28 MB_DQS_L[4] MB_DATA[35] AK31 DDR_B_D36
DDR_A_DQS5 AH25 MA_DQS_L[4] MA_DATA[35] AH27 DDR_A_D36 DDR_B_DQS#5 AP29 MB_DQS_H[5] MB_DATA[36] AK33 DDR_B_D37
DDR_A_DQS#5 AJ25 MA_DQS_H[5] MA_DATA[36] AH28 DDR_A_D37 DDR_B_DQS6 AP23 MB_DQS_L[5] MB_DATA[37] AN32 DDR_B_D38
DDR_A_DQS6 AK20 MA_DQS_L[5] MA_DATA[37] AJ29 DDR_A_D38 DDR_B_DQS#6 AP24 MB_DQS_H[6] MB_DATA[38] AP33 DDR_B_D39
DDR_A_DQS#6 AL20 MA_DQS_H[6] MA_DATA[38] AK27 DDR_A_D39 DDR_B_DQS7 AR18 MB_DQS_L[6] MB_DATA[39]
DDR_A_DQS7 AK15 MA_DQS_L[6] MA_DATA[39] DDR_B_DQS#7 AP18 MB_DQS_H[7] AP30 DDR_B_D40
DDR_A_DQS#7 AL15 MA_DQS_H[7] AK26 DDR_A_D40 MB_DQS_L[7] MB_DATA[40] AR30 DDR_B_D41
MA_DQS_L[7] MA_DATA[40] AJ26 DDR_A_D41 W32 MB_DATA[41] AP27 DDR_B_D42
W29 MA_DATA[41] AK23 DDR_A_D42 <11> DDR_B_CLK0 Y32 MB_CLK_H[0] MB_DATA[42] AN26 DDR_B_D43
<10> DDR_A_CLK0 Y30 MA_CLK_H[0] MA_DATA[42] AJ23 <11> DDR_B_CLK0# V33 MB_CLK_L[0] MB_DATA[43] AR32
DDR_A_D43 DDR_B_D44
<10> DDR_A_CLK0# W26 MA_CLK_L[0] MA_DATA[43] AM26 <11> DDR_B_CLK1 V32 MB_CLK_H[1] MB_DATA[44] AP31
DDR_A_D44 DDR_B_D45
<10> DDR_A_CLK1 W27 MA_CLK_H[1] MA_DATA[44] AL26 <11> DDR_B_CLK1# U32 MB_CLK_L[1] MB_DATA[45] AR28
DDR_A_D45 DDR_B_D46
<10> DDR_A_CLK1# U29 MA_CLK_L[1] MA_DATA[45] AM24 DDR_A_D46 V31 MB_CLK_H[2] MB_DATA[46] AP28 DDR_B_D47
V30 MA_CLK_H[2] MA_DATA[46] AL23 DDR_A_D47 T33 MB_CLK_L[2] MB_DATA[47]
U26 MA_CLK_L[2] MA_DATA[47] T32 MB_CLK_H[3] AP25 DDR_B_D48
U27 MA_CLK_H[3] AK22 DDR_A_D48 MB_CLK_L[3] MB_DATA[48] AN24 DDR_B_D49
MA_CLK_L[3] MA_DATA[48] AH22 DDR_A_D49 H32 MB_DATA[49] AR22 DDR_B_D50
L29 MA_DATA[49] AK19 DDR_A_D50 <11> DDR_B_CKE0 H33 MB_CKE[0] MB_DATA[50] AP21 DDR_B_D51
<10> DDR_A_CKE0 K30 MA_CKE[0] MA_DATA[50] AH19 DDR_A_D51 <11> DDR_B_CKE1 MB_CKE[1] MB_DATA[51] AP26 DDR_B_D52
<10> DDR_A_CKE1 MA_CKE[1] MA_DATA[51] AM22 AF31 MB_DATA[52] AR26
DDR_A_D52 DDR_B_D53
3 AD30 MA_DATA[52] AL22 <11> DDR_B_ODT0 AH31 MB0_ODT[0] MB_DATA[53] AN22 3
DDR_A_D53 DDR_B_D54
<10> DDR_A_ODT0 AG28 MA0_ODT[0] MA_DATA[53] AJ20 <11> DDR_B_ODT1 AE32 MB0_ODT[1] MB_DATA[54] AP22
DDR_A_D54 DDR_B_D55
<10> DDR_A_ODT1 AE26 MA0_ODT[1] MA_DATA[54] AL19 DDR_A_D55 AH33 MB1_ODT[0] MB_DATA[55]
AG29 MA1_ODT[0] MA_DATA[55] MB1_ODT[1] AR20 DDR_B_D56
MA1_ODT[1] AK17 DDR_A_D56 AD31 MB_DATA[56] AP19 DDR_B_D57
AD26 MA_DATA[56] AJ17 <11> DDR_B_SCS0# AF32 MB0_CS_L[0] MB_DATA[57] AP16
DDR_A_D57 DDR_B_D58
<10> DDR_A_SCS0# AE29 MA0_CS_L[0] MA_DATA[57] AK14 <11> DDR_B_SCS1# AC32 MB0_CS_L[1] MB_DATA[58] AR16
DDR_A_D58 DDR_B_D59
<10> DDR_A_SCS1# AB30 MA0_CS_L[1] MA_DATA[58] AH14 DDR_A_D59 AG32 MB1_CS_L[0] MB_DATA[59] AN20 DDR_B_D60
AF30 MA1_CS_L[0] MA_DATA[59] AM18 DDR_A_D60 MB1_CS_L[1] MB_DATA[60] AP20 DDR_B_D61
MA1_CS_L[1] MA_DATA[60] AL17 DDR_A_D61 AB32 MB_DATA[61] AP17 DDR_B_D62
AB29 MA_DATA[61] AH15 <11> DDR_B_RAS# AD32 MB_RAS_L MB_DATA[62] AN16
DDR_A_D62 DDR_B_D63
<10> DDR_A_RAS# AD29 MA_RAS_L MA_DATA[62] AL14 <11> DDR_B_CAS# AD33 MB_CAS_L MB_DATA[63]
DDR_A_D63
<10> DDR_A_CAS# AD28 MA_CAS_L MA_DATA[63] <11> DDR_B_WE# MB_WE_L
<10> DDR_A_WE# MA_WE_L H31
J28 <11> MEM_MB_RST# Y31 MB_RESET_L
<10> MEM_MA_RST# AA26 MA_RESET_L <11> MEM_MB_EVENT# MB_EVENT_L
<10> MEM_MA_EVENT# MA_EVENT_L
TRINITY-A8-SERIES_BGA813
+MEM_VREF G32
M_VREF
1 2 M_ZVDDIO AJ32 5745R1@
+1.5V M_ZVDDIO
R60 39.2_0402_1%
Close to AJ32 TRINITY-A8-SERIES_BGA813
5745R1@
+1.5V
0.75V Reference Voltage
EVENT# pull high
2
4 4
R64
+1.5V 1K_0402_1%
1
+MEM_VREF
2
R15 1 2 1K_0402_5% MEM_MA_EVENT#

R65
1
C124
2 Security Classification Compal Secret Data Compal Electronics, Inc.
R61 1 2 1K_0402_5% MEM_MB_EVENT# 1K_0402_1% C125 2013/01/22 2014/01/21 Title
Issued Date Deciphered Date
1000P_0402_50V7K
2 1
0.1U_0402_25V6
AMD Trinity FP2 DDRIII I/F
1
Custom 0.3
LA-9869P
A B C D E
A B C D E
DP0_AUXP R25 2 1 1.8K_0402_5%

UAPUD DP0_AUXN R58 2 1 1.8K_0402_5%
C56 1 2 0.1U_0402_16V7K DP0_TXP0 H2 M5 DP0_AUXP C47 1 2 0.1U_0402_16V7K
<19> DP0_TXP0_C 1 2 0.1U_0402_16V7K DP0_TXN0 H1 DP0_TXP[0] DP0_AUXP M6 DP0_AUXN 1 2 0.1U_0402_16V7K DP0_AUXP_C <19> DP1_AUXP 2 1 1.8K_0402_5%
LVDS/eDP C48 C49 LVDS R10
<19> DP0_TXN0_C DP0_TXN[0] DP0_AUXN DP0_AUXN_C <19>
C58 IEDP@1 2 0.1U_0402_16V7K DP0_TXP1 H3 L5 DP1_AUXP C57 1 2 0.1U_0402_16V7K DP1_AUXN R11 2 1 1.8K_0402_5%
DISPLAY PORT 0
<20> DP0_TXP1_C DP0_TXP[1] DP1_AUXP ML_VGA_AUXP <25>
C75 IEDP@1 2 0.1U_0402_16V7K DP0_TXN1 H4 L6 DP1_AUXN C52 1 2 0.1U_0402_16V7K CRT (To FCH)
<20> DP0_TXN1_C DP0_TXN[1] DP1_AUXN ML_VGA_AUXN <25> 2 1 100K_0402_5%
LVDS_HPD R74
F4 J5
F3 DP0_TXP[2] DP2_AUXP J6 UMA_HDMI_CLK <22> FCH_CRT_HPD 2 1 100K_0402_5%
HDMI R75
DP0_TXN[2] DP2_AUXN UMA_HDMI_DATA <22>
F1 P5 Aux signal are re-configured as I2C signals for DDC HDMI_HPD R95 2 1 100K_0402_5%
F2 DP0_TXP[3] DP3_AUXP P6
1 DP0_TXN[3] DP3_AUXN APU AUX pin are 3.3V tolerant 1
DISPLAY PORT MISC.

C67 1 2 0.1U_0402_16V7K DP1_TXP0 E2 R5
<25> ML_VGA_TXP0 1 2 0.1U_0402_16V7K DP1_TXN0 E1 DP1_TXP[0] DP4_AUXP R6
C71 For 2132R
<25> ML_VGA_TXN0 DP1_TXN[0] DP4_AUXN
C66 1 2 0.1U_0402_16V7K DP1_TXP1 D4 U5
DISPLAY PORT 1
<25> ML_VGA_TXP1 1 2 0.1U_0402_16V7K DP1_TXN1 D3 DP1_TXP[1] DP5_AUXP U6 DP0_AUXP 1 2 680P_0402_50V7K
C69 C138
<25> ML_VGA_TXN1 DP1_TXN[1] DP5_AUXN
CRT C68 1 2 0.1U_0402_16V7K DP1_TXP2 D1 M7 LVDS_HPD DP0_AUXN C139 1 2 680P_0402_50V7K
<25> ML_VGA_TXP2 1 2 0.1U_0402_16V7K DP1_TXN2 D2 DP1_TXP[2] DP0_HPD L7 FCH_CRT_HPD
LVDS_HPD <19,20>
C72 3.3V Tolerance
(To FCH) <25> ML_VGA_TXN2 DP1_TXN[2] DP1_HPD J7 HDMI_HPD
FCH_CRT_HPD <25>
1 2 0.1U_0402_16V7K C1 DP2_HPD P7 HDMI_HPD <22,24>
C73 DP1_TXP3
<25> ML_VGA_TXP3 1 2 0.1U_0402_16V7K DP1_TXN3 C2 DP1_TXP[3] DP3_HPD R7
C70
<25> ML_VGA_TXN3 DP1_TXN[3] DP4_HPD U7
B2 DP5_HPD
<22> UMA_HDMI_TX2+ DP2_TXP[0]
A2 C6
<22> UMA_HDMI_TX2- DP2_TXN[0] DP_BLON DP_ENBKL <9>
D7
B3 DP_DIGON A6 DP_ENVDD <9> +1.5V
DISPLAY PORT 2
<22> UMA_HDMI_TX1+ DP2_TXP[1] DP_VARY_BL DP_INT_PWM <9>
A3
<22> UMA_HDMI_TX1- DP2_TXN[1]
HDMI B6 DP_AUX_ZVSS R16 1 2 150_0402_1%
B4 DP_AUX_ZVSS APU_SVT_R R36 2 @ 1 1K_0402_5%
<22> UMA_HDMI_TX0+ DP2_TXP[2]
A4 AL6
<22> UMA_HDMI_TX0- DP2_TXN[2] TEST6 Y23 APU_SVC_R R39 2 @ 1 1K_0402_5%
B5 TEST9 V23
<22> UMA_HDMI_TXC+ DP2_TXP[3] TEST10
A5 G9 APU_SVD_R R41 2 @ 1 1K_0402_5%
<22> UMA_HDMI_TXC- DP2_TXN[3] TEST14
clock no test point F9
AL9 TEST15 E9
<23> APU_CLK AK9 CLKIN_H TEST16 G8
100MHz (SS) <23> APU_CLK# CLKIN_L TEST17 +1.5V
F12 APU_TEST18
TEST
AL7 TEST18 E12 APU_TEST19
CLK
<23> APU_DISP_CLK AK7 DISP_CLKIN_H TEST19 F14 APU_TEST20
100MHz (Non-spread spectrum) RPC1 RPC2
<23> APU_DISP_CLK# DISP_CLKIN_L TEST20 G12 APU_TEST24 APU_TEST18 1 8 APU_SIC 1 8
R31 1 @ 2 0_0402_5% APU_SVC_R E5 TEST24 AJ8 TEST25_H R23 1 2 510_0402_1% APU_TEST19 2 7 APU_SID 2 7
2 <45> APU_SVC 1 2 0_0402_5% APU_SVD_R E6 SVC TEST25_H AH8 TEST25_L 1 2 510_0402_1% APU_TEST20 3 6 APU_ALERT# 3 6 2
R32 @ R24 +1.2VS
<45> APU_SVD SVD TEST25_L G14 4 5 4 5
T7 APU_TEST24 DMA_ACTIVE#
TEST28_H
SER.
R33 1 @ 2 0_0402_5% APU_SVT_R D6 H14
<45> APU_SVT SVT TEST28_L T8
V25 1K_0804_8P4R_5% 1K_0804_8P4R_5%
TEST30_H T9
AJ11 Y25
<9> APU_SIC SIC TEST30_L T10 +1.5V
AH11 AH32 APU_TEST31 R38 1 2 39.2_0402_1%
<9> APU_SID SID TEST31 R25
TEST32_H T17
AK11 T25
+1.5V <23> APU_RST# RESET_L TEST32_L T18
Close to JHDT AH9 AL5 APU_TEST35 R29 1 2 300_0402_5%
<23,45> APU_PWRGD PWROK TEST35 +1.5V
R30 1 @ 2 300_0402_5%
RPC3 APU_PROCHOT# AL12 AP10 APU_RST# R52 2 1 300_0402_5%
CTRL
1 8 AK5 PROCHOT_L DMAACTIVE_L DMA_ACTIVE# <23>
APU_TDI APU_THERMTRIP#
2 7 APU_TCK APU_ALERT# AR10 THERMTRIP_L T23 TEST4 APU_PWRGD R54 2 1 300_0402_5%
ALERT_L TEST4 T11
3 6 APU_TMS R23 TEST5 Change TEST35 to pull-high
TEST5 T12
4 5 APU_TRST# APU_TDI E11
APU_TDO G11 TDI for HDMI issue
T15 TDO
1K_0804_8P4R_5% APU_TCK H12 check list recommend mount R29 and R30 @ APU_RST# 1 2
APU_TMS F11 TCK L8 C126 @ 1000P_0402_50V7K
JTAG
R117 1 2 1K_0402_5% APU_DBREQ# APU_TRST# H11 TMS RSVD P8
APU_DBRDY E8 TRST_L RSVD AH12 APU_PWRGD 1 2
T16 DBRDY RSVD
APU_DBREQ# E7 AJ12 C130 180P_0402_50V8J
RSVD
DBREQ_L RSVD AK12 @ESD@
R212 1 @ 2 0_0402_5% VSS_SENSE G6 RSVD
<45> APU_VDD_RUN_FB_L H6 VSS_SENSE
T13 VDDP_SENSE
R214 1 @ 2 0_0402_5% VDDNB_SENSE H5
<45> APU_VDDNB_SEN G7 VDDNB_SENSE
SENSE
T21 VDDIO_SENSE
R215 1 @ 2 0_0402_5% VDD_SENSE G5
<45> APU_VDD_SEN H7 VDD_SENSE
T28 VDDR_SENSE
5745R1@
3 3
+1.5V
1 2 APU_SVC
C127 @ 1000P_0402_50V7K
2
1 2 APU_SVD
C140 @ 1000P_0402_50V7K R55
1K_0402_5%
1 2 APU_SVT Asserted as an input to force the
C141 @ 1000P_0402_50V7K
processor into the HTC-active state
1
APU_PROCHOT# 1 @ 2
<23> APU_PROCHOT# H_PROCHOT# <34,45>
R136 0_0402_5%
APU_PROCHOT#
2
CK0402101V05_0402-2
D31
@ESD@
+1.5V
1
R68 R69
1K_0402_5% 10K_0402_5%
Thermal Shutdown Temperature:
2 2
115 degree
B
4 4
Q5
E
APU_THERMTRIP# 3 1
H_THERMTRIP# <24>
C
MMBT3904_NL_SOT23-3

AMD Trinity FP2 Display / MISC / HDT
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9869P 0.3
A B C D E
A B C D E
UAPUF
+1.5V
A17 Y11
+1.5V VSS VSS
C74
C65
C64
C63
C89
C90
C91
C92
C93
C94
C95
C96
C97
C102
C117
C118
C119
C100
C103
C131
A19 Y12
A21 VSS VSS Y14
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VSS VSS
A23 Y15
+APU_CORE +APU_CORE A25 VSS VSS Y17
UAPUE 1 VSS VSS
0.22U_0402_10V4Z
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
0.22U_0402_10V4Z
0.22U_0402_10V4Z
0.22U_0402_10V4Z
0.22U_0402_10V4Z
0.22U_0402_10V4Z
0.22U_0402_10V4Z
0.22U_0402_10V4Z
0.22U_0402_10V4Z
180P_0402_50V8J
180P_0402_50V8J
4.7U_0603_6.3V6K
C150 A27 Y19
J12 V17 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 100U_1206_6.3V6K A29 VSS VSS Y20
J14 VDD VDD V19 @ @ A31 VSS VSS Y22
J15 VDD VDD V20 2 B1 VSS VSS AA4
1 J17 VDD VDD V22 C3 VSS VSS AA5 1
J19 VDD VDD W8 C4 VSS VSS AB7
J20 VDD VDD AA8 C33 VSS VSS AB8
J22 VDD VDD AA9 D5 VSS VSS AC1
M11 VDD VDD AA11 D9 VSS VSS AC2
R8 VDD VDD AD9 D25 VSS VSS AC19
R9 VDD 36A VDD AD11 D30 VSS VSS AC20
R11 VDD VDD AD12 E4 VSS VSS AC22
R15 VDD VDD AD17 E30 VSS VSS AE4
R17 VDD VDD AD19 E33 VSS VSS AF9
R19 VDD VDD AD20 F5 VSS VSS AF11
VDD VDD
VDDR more different VDDP more different VSS VSS
R20 AD22 F6 AF12
R22 VDD VDD AG12 F7 VSS VSS AF14
VDD VDD +1.2VS +1.2VS VSS VSS
U8 AG14 F8 AF15
VDD VDD VSS VSS
C116
C77
C655
C137
C149
C105
C152
C632
C115
C111
C110
C109
C106
C132
V9 AG15 F17 AF17
V11 VDD VDD AG17 F20 VSS VSS AF19
VDD VDD 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VSS VSS
V12 AG19 @ F23 AF20
V14 VDD VDD AG20 F28 VSS VSS AF22
VDD VDD VSS VSS
0.22U_0402_10V4Z
22U_0603_6.3V6M
22U_0603_6.3V6M
0.01U_0402_16V7K
0.01U_0402_16V7K
180P_0402_50V8J
0.22U_0402_10V4Z
22U_0603_6.3V6M
0.22U_0402_10V4Z
1000P_0402_50V7K
180P_0402_50V8J
180P_0402_50V8J
180P_0402_50V8J
0.22U_0402_10V4Z
V15 AG22 F29 AF23
VDD VDD 2 2 2 2 2 2 2 2 2 2 2 2 2 2 G1 VSS VSS AF25
G2 VSS VSS AG1
A7 B11 G4 VSS VSS AG2
+APU_CORE_NB VDDNB VDDNB +APU_CORE_NB VSS VSS
A8 B12 G15 AG4
2 A9 VDDNB VDDNB B13 G19 VSS VSS AG9 2
A10 VDDNB VDDNB B14 G25 VSS VSS AG11
A11 VDDNB VDDNB B15 G26 VSS VSS AG26
A12 VDDNB VDDNB C8 G27 VSS VSS AH7
A13 VDDNB 30A VDDNB C10 G33 VSS VSS AH17
A14 VDDNB VDDNB C12 H8 VSS VSS AH20
A15 VDDNB VDDNB C14 H9 VSS VSS AH23
B7 VDDNB VDDNB D8 H22 VSS VSS AH26
B8 VDDNB VDDNB D10 H26 VSS VSS AH30
B9 VDDNB VDDNB D12 J4 VSS VSS AJ4
B10 VDDNB VDDNB D14 J8 VSS VSS AJ5
VDDNB VDDNB J9 VSS VSS AJ6
M9 +VDDNB_CAP J11 VSS VSS AJ7
VDDNB_CAP N9 J23 VSS VSS AJ9
VDDNB_CAP VSS VSS
C163
C196
C158
J25 AJ14
J33 W33 J26 VSS VSS AJ15
+1.5V VDDIO VDDIO 1 1 1 VSS VSS
K23 AA23 J27 AJ19
K25 VDDIO VDDIO AA25 J30 VSS VSS AJ22
VDDIO VDDIO VSS VSS
22U_0603_6.3V6M
22U_0603_6.3V6M
180P_0402_50V8J
L28 AA27 K9 AJ27

L30 VDDIO VDDIO AA30 2 2 2 K11 VSS VSS AJ28
L33 VDDIO VDDIO AA33 K12 VSS VSS AJ33
M27 VDDIO VDDIO AB28 K14 VSS VSS AK6
N23 VDDIO 3.2A VDDIO AC30 K15 VSS VSS AK8
N25 VDDIO VDDIO AC33 K17 VSS VSS AK25
N30 VDDIO VDDIO AD23 K19 VSS VSS AK28
N33 VDDIO VDDIO AD25 K20 VSS VSS AK30
P28 VDDIO VDDIO AD27 K22 VSS VSS AL1
R27 VDDIO VDDIO AE28 L1 VSS VSS AL2
U28 VDDIO VDDIO AG23 M8 VSS VSS AL11
U30 VDDIO VDDIO AG25 M23 VSS VSS AL27
3 VDDIO VDDIO close to APU VSS VSS 3
U33 AG27 M25 AL28
W28 VDDIO VDDIO AG30 N4 VSS VSS AL33
W30 VDDIO VDDIO AG33 +VDDP_CAP N11 VSS VSS AM5
VDDIO VDDIO +1.5V VSS VSS
N12 AM7
VSS VSS
C168
C169
AM12 AN14 N14 AM9

+1.2VS
AN12 VDDP 3.5A VDDR AP14
+1.2VS
1 1 N15 VSS VSS AM11
AP12 VDDP VDDR AP15 N17 VSS VSS AM15
AP13 VDDP VDDR AR14 N19 VSS VSS AM17
VDDP VDDR VSS VSS
22U_0805_6.3V6M
22U_0805_6.3V6M
AR12 AR15 N20 AM19

AR13 VDDP VDDR 2 2 N22 VSS VSS AM21
VDDP 3.5A Power Sequence of APU R1 VSS VSS AM23
+VDDP_CAP AA6 R2 VSS VSS AM25
AA7 VDDP_CAP R4 VSS VSS AM29
VDDP_CAP +1.5V T9 VSS VSS AM30
AM13 T11 VSS VSS AN3
+VDDA VDDA VSS VSS
AM14 T12 AN4
VDDA 0.75A T14 VSS VSS AN33
Other signals TRINITY-A8-SERIES_BGA813 +2.5VS Group A T15 VSS VSS AP5
5745R1@ T17 VSS VSS AP9
should keep 20 T19 VSS VSS AR2
mil away with T20 VSS VSS AR5
+VDDA +1.5VS T22 VSS VSS AR9
U4 VSS VSS AR17
W1 VSS VSS AR19
W2 VSS VSS AR21
L1 +CPU_CORE W4 VSS VSS AR23
1 2 W5 VSS VSS AR25
+VDDA VSS VSS
FBMA-L11-201209-300LMA30T W6 AR27
+2.5VS VSS VSS
C165
C164
C170
W7 AR29
Group B Y9 VSS VSS AR31
1 1 1 +CPU_CORE_NB VSS VSS
4.7U_0603_6.3V6K
3300P_0402_50V7-K
0.22U_0402_10V4Z
4 5745R1@ 4
2 2 2
+1.2VS

AMD Trinity FP2 PWR / GND
Custom 0.3
LA-9869P
A B C D E
5 4 3 2 1
+3VS
SB-TSI Panel PWM
R89 LVDS@ R93 LVDS@
2.2K_0402_5% 4.7K_0402_5%
1
Q21 LVDS@ Q28 LVDS@
MMBT3904_NL_SOT23-3 2N7002KW _SOT323-3 R92 R93
47K_0402_5% 4.7K_0402_5%
R92 LVDS@ IEDP@ IEDP@
2
+1.5V 47K_0402_5%
D APU_INVT_PW M
APU_INVT_PW M <19,20> D
1
@ 2 Q28
Q16 BSH111, the Vgs is: DP_INT_PW M 1 2 APU_INVT_PW M G 2N7002KW _SOT323-3
2
AO3413_SOT23 min = 0.4V R46 0_0402_5%
IEDP@
3
S
R49 S
3
G
2 Max = 1.3V
0_0402_5% SUSP <37>
1
C
@ D DP_INT_PW M 1 2 2 Q21
<7> DP_INT_PW M
1
1
When APU High -> MOS OFF (Vgs < 0.4V ) R89 2.2K_0402_5% B MMBT3904_NL_SOT23-3
E
APU Low -> MOS ON (Vgs > 1.3V) IEDP@
3
1
+1.5V_SI IEDP@
R76
4.7K_0402_5%
2
G
Q14
2
APU_SID 3 1
<7> APU_SID EC_SMB_DA1 <31,34,39,40>
S
BSH111_SOT23-3
Vg = 1.607 V +3VS
eDP Panel ENVDD
2
G
Q15
APU_SIC 3 1
<7> APU_SIC EC_SMB_CK1 <31,34,39,40>
S
C C
1
BSH111_SOT23-3
R135 R137
47K_0402_5% 4.7K_0402_5%
IEDP@ IEDP@
2
LCD_ENVDD <19>
6
IEDP@
2 Q29A
2N7002DW -T/R7_SOT363-6
1
1
C
1 2 2 Q26
<7> DP_ENVDD
R141 2.2K_0402_5% B MMBT3904_NL_SOT23-3
IEDP@ E IEDP@
3
1
R147
100K_0402_5%
IEDP@
2
B B
+3VS
eDP Panel ENBKL
1
R144 R143
47K_0402_5% 4.7K_0402_5%
IEDP@ IEDP@
2
LCD_ENBKL <20,34>
3
IEDP@
5 Q29B
2N7002DW -T/R7_SOT363-6
4
1
C
1 2 2 Q27
<7> DP_ENBKL
R146 2.2K_0402_5% B MMBT3904_NL_SOT23-3
IEDP@ E IEDP@
3
1
R142
A 100K_0402_5% A
IEDP@
2
Security Classification Compal Secret Data
AMD Trinity FP2 Singal Level Shifter
Custom 0.3
LA-9869P
5 4 3 2 1
5 4 3 2 1
+1.5V +1.5V
1
JDDR3L
2
DDR3 SO-DIMM A
+VREF_DQA
DDR_A_D0
3
5
VREF_DQ
VSS2
VSS1
DQ4
4
6
DDR_A_D4
DDR_A_D5
Reverse Type DDR_A_DQS[0..7] <6>
7 DQ0 DQ5 8 DDR_A_DQS#[0..7] <6>

DDR_A_D1
9 DQ1 VSS3 10 DDR_A_DQS#0
VSS4 DQS#0 DDR_A_D[0..63] <6>
DDR_A_DM0 11 12 DDR_A_DQS0
13 DM0 DQS0 14
VSS5 VSS6 DDR_A_MA[0..15] <6>
DDR_A_D2 15 16 DDR_A_D6
DDR_A_D3 17 DQ2 DQ6 18 DDR_A_D7
DQ3 DQ7 DDR_A_DM[0..7] <6>
19 20
DDR_A_D8 21 VSS7 VSS8 22 DDR_A_D12
25 DQ9 DQ13 26
D DDR_A_DQS#1 27 VSS9 VSS10 28 DDR_A_DM1 D
DDR_A_DQS1 29 DQS#1 DM1 30
31 DQS1 RESET# 32 MEM_MA_RST# <6>
37 DQ11 DQ15 38
DDR_A_D16 39 VSS13 VSS14 40 DDR_A_D20 +1.5V
43 DQ17 DQ21 44
VSS15 VSS16
1
DDR_A_DQS#2 45 46 DDR_A_DM2
DDR_A_DQS2 47 DQS#2 DM2 48 R79
49 DQS2 VSS17 50 DDR_A_D22 1K_0402_1%
DDR_A_D18 51 VSS18 DQ22 52 DDR_A_D23
DDR_A_D19 53 DQ18 DQ23 54
2
55 DQ19 VSS19 56 DDR_A_D28 +VREF_DQA
DQ24 DQ29
1
DDR_A_D25 59 60
61 DQ25 VSS21 62 DDR_A_DQS#3 @1 R81
VSS22 DQS#3 1
DDR_A_DM3 63 64 DDR_A_DQS3 C156 C157 1K_0402_1%
65 DM3 DQS3 66
VSS23 VSS24
0.1U_0402_16V7K
2.2U_0402_6.3V6M
DDR_A_D26 67 68 DDR_A_D30
2
DDR_A_D27 69 DQ26 DQ30 70 DDR_A_D31 2 2
71 DQ27 DQ31 72
VSS25 VSS26
73 74
<6> DDR_A_CKE0 75 CKE0 CKE1 76 DDR_A_CKE1 <6>
77 VDD1 VDD2 78 DDR_A_MA15
79 NC1 A15 80 DDR_A_MA14
<6> DDR_A_BS2 81 BA2 A14 82
Close to JDDR3H.1
DDR_A_MA12 83 VDD3 VDD4 84 DDR_A_MA11
C DDR_A_MA9 85 A12/BC# A11 86 DDR_A_MA7 C
87 A9 A7 88
DDR_A_MA5 91 A8 A6 92 DDR_A_MA4
93 A5 A4 94
DDR_A_MA1 97 A3 A2 98 DDR_A_MA0 +1.5V
99 A1 A0 100
101 VDD9 VDD10 102
<6> DDR_A_CLK0 103 CK0 CK1 104 DDR_A_CLK1 <6>
<6> DDR_A_CLK0# CK0# CK1# DDR_A_CLK1# <6> 1
105 106 C148
DDR_A_MA10 107 VDD11 VDD12 108 +1.5V 100U_1206_6.3V6K
109 A10/AP BA1 110 DDR_A_BS1 <6>
<6> DDR_A_BS0 111 BA0 RAS# 112 DDR_A_RAS# <6> 2
VDD13 VDD14
1
113 114
<6> DDR_A_WE# 115 WE# S0# 116 DDR_A_SCS0# <6>
R80
<6> DDR_A_CAS# 117 CAS# ODT0 118 DDR_A_ODT0 <6>
1K_0402_1% SE00000O000
DDR_A_MA13 119 VDD15 VDD16 120
121 A13 ODT1 122 DDR_A_ODT1 <6>
2
<6> DDR_A_SCS1# 123 S1# NC2 124
125 VDD17 VDD18 126 +VREF_CAA
127 NCTEST VREF_CA 128
DQ32 DQ36
1
DDR_A_D33 131 132 DDR_A_D37 1 @1
133 DQ33 DQ37 134 C162 C161 R82
DDR_A_DQS#4 135 VSS29 VSS30 136 DDR_A_DM4 1K_0402_1%
DQS#4 DM4
0.1U_0402_16V7K
2.2U_0402_6.3V6M
DDR_A_DQS4 137 138 Layout Note:
139 DQS4 VSS31 140 DDR_A_D38 2 2
2
DDR_A_D34 141 VSS32 DQ38 142 DDR_A_D39 Place near JDDR3H
DDR_A_D35 143 DQ34 DQ39 144
145 DQ35 VSS33 146 DDR_A_D44
DDR_A_D40 147 VSS34 DQ44 148 DDR_A_D45 +1.5V
B DDR_A_D41 149 DQ40 DQ45 150 B
151 DQ41 VSS35 152 DDR_A_DQS#5
Layout Note:
DDR_A_DM5 153 VSS36 DQS#5 154 DDR_A_DQS5 Place near JDDR3H.203 and 204
155 DM5 DQS5 156
Close to JDDR3H.126 2 1 10U_0603_6.3V6M
C176
DDR_A_D43 159 DQ42 DQ46 160 DDR_A_D47
161 DQ43 DQ47 162 C174 2 1 10U_0603_6.3V6M
DDR_A_D49 165 DQ48 DQ52 166 DDR_A_D53 C173 2 1 10U_0603_6.3V6M +0.75VS
167 DQ49 DQ53 168
DDR_A_DQS#6 169 VSS41 VSS42 170 DDR_A_DM6 C171 2 1 10U_0603_6.3V6M
DDR_A_DQS6 171 DQS#6 DM6 172
173 DQS6 VSS43 174 DDR_A_D54 C167 2 1 10U_0603_6.3V6M
DDR_A_D51 177 DQ50 DQ55 178 C166 2 1 10U_0603_6.3V6M
179 DQ51 VSS45 180 DDR_A_D60 C84 1 2 4.7U_0603_6.3V6K
DDR_A_D56 181 VSS46 DQ60 182 DDR_A_D61 C179 1 2 0.1U_0402_16V4Z
DDR_A_D57 183 DQ56 DQ61 184
185 DQ57 VSS47 186 DDR_A_DQS#7 C178 1 2 0.1U_0402_16V4Z C186 1 2 0.1U_0402_16V4Z
DDR_A_DM7 187 VSS48 DQS#7 188 DDR_A_DQS7
189 DM7 DQS7 190 C185 1 2 0.1U_0402_16V4Z C205 1 2 0.1U_0402_16V4Z
DDR_A_D59 193 DQ58 DQ62 194 DDR_A_D63 C180 1 2 0.1U_0402_16V4Z
195 DQ59 DQ63 196
197 VSS51 VSS52 198
199 SA0 EVENT# 200 MEM_MA_EVENT# <6>
+3VS 201 VDDSPD SDA 202 FCH_SDATA0 <11,24,28>
0.1U_0402_16V4Z
203 SA1 SCL 204 FCH_SCLK0 <11,24,28>

1 +0.75VS VTT1 VTT2 +0.75VS
C182
205 206
G1 G2
2 LCN_DAN06-K4406-0103
A @ A

DDRIII-SODIMM0
Custom 0.3
LA-9869P
5 4 3 2 1
A B C D E
+1.5V +1.5V
1
JDDR3H
2
DDR3 SO-DIMM B DDR_B_DQS#[0..7] <6>
+VREF_DQB VREF_DQ VSS1
3 4 DDR_B_D4
DDR_B_D0
DDR_B_D1
5
7
VSS2
DQ0
DQ4
DQ5
6
8
DDR_B_D5 Reverse Type DDR_B_DQS[0..7] <6>
DQ1 VSS3 DDR_B_D[0..63] <6>

9 10 DDR_B_DQS#0
DDR_B_DM0 11 VSS4 DQS#0 12 DDR_B_DQS0
DM0 DQS0 DDR_B_MA[0..15] <6>
13 14
DDR_B_D2 15 VSS5 VSS6 16 DDR_B_D6
DQ2 DQ6 DDR_B_DM[0..7] <6>
DDR_B_D3 17 18 DDR_B_D7
19 DQ3 DQ7 20
DDR_B_D9 23 DQ8 DQ12 24 DDR_B_D13
25 DQ9 DQ13 26
1 DDR_B_DQS#1 27 VSS9 VSS10 28 DDR_B_DM1 1
DDR_B_DQS1 29 DQS#1 DM1 30
31 DQS1 RESET# 32 MEM_MB_RST# <6>
37 DQ11 DQ15 38
43 DQ17 DQ21 44 +1.5V
DDR_B_DQS#2 45 VSS15 VSS16 46 DDR_B_DM2
DDR_B_DQS2 47 DQS#2 DM2 48
DQS2 VSS17
1
49 50 DDR_B_D22
DDR_B_D18 51 VSS18 DQ22 52 DDR_B_D23 R83
DDR_B_D19 53 DQ18 DQ23 54 1K_0402_1%
55 DQ19 VSS19 56 DDR_B_D28
DDR_B_D24 57 VSS20 DQ28 58 DDR_B_D29
2
DDR_B_D25 59 DQ24 DQ29 60
61 DQ25 VSS21 62 DDR_B_DQS#3 +VREF_DQB
65 DM3 DQS3 66
VSS23 VSS24
1
DDR_B_D26 67 68 DDR_B_D30 1 @1
DDR_B_D27 69 DQ26 DQ30 70 DDR_B_D31 C184 C183 R84
71 DQ27 DQ31 72 1K_0402_1%
VSS25 VSS26
0.1U_0402_16V7K
2.2U_0402_6.3V6M
2 2
2
73 74
<6> DDR_B_CKE0 75 CKE0 CKE1 76 DDR_B_CKE1 <6>
77 VDD1 VDD2 78 DDR_B_MA15
79 NC1 A15 80 DDR_B_MA14
<6> DDR_B_BS2 81 BA2 A14 82
DDR_B_MA12 83 VDD3 VDD4 84 DDR_B_MA11
2 DDR_B_MA9 85 A12/BC# A11 86 DDR_B_MA7 2
87 A9 A7 88
Close to JDDR3L.1
DDR_B_MA5 91 A8 A6 92 DDR_B_MA4
93 A5 A4 94
DDR_B_MA1 97 A3 A2 98 DDR_B_MA0
99 A1 A0 100
101 VDD9 VDD10 102
<6> DDR_B_CLK0 103 CK0 CK1 104 DDR_B_CLK1 <6>
<6> DDR_B_CLK0# 105 CK0# CK1# 106 DDR_B_CLK1# <6>
DDR_B_MA10 107 VDD11 VDD12 108 +1.5V
109 A10/AP BA1 110 DDR_B_BS1 <6>
<6> DDR_B_BS0 111 BA0 RAS# 112 DDR_B_RAS# <6>
VDD13 VDD14
1
113 114
<6> DDR_B_WE# 115 WE# S0# 116 DDR_B_SCS0# <6>
R86
<6> DDR_B_CAS# 117 CAS# ODT0 118 DDR_B_ODT0 <6>
1K_0402_1%
DDR_B_MA13 119 VDD15 VDD16 120
121 A13 ODT1 122 DDR_B_ODT1 <6>
2
<6> DDR_B_SCS1# 123 S1# NC2 124
125 VDD17 VDD18 126 +VREF_CAB
127 NCTEST VREF_CA 128
DQ32 DQ36
1
DDR_B_D36 131 132 DDR_B_D33 1 @1
133 DQ33 DQ37 134 C188 C187 R94
DDR_B_DQS#4 135 VSS29 VSS30 136 DDR_B_DM4 1K_0402_1%
DQS#4 DM4
0.1U_0402_16V7K
2.2U_0402_6.3V6M
DDR_B_DQS4 137 138 Layout Note:

139 DQS4 VSS31 140 DDR_B_D38 2 2
2
DDR_B_D34 141 VSS32 DQ38 142 DDR_B_D39 Place near JDDR3L
DDR_B_D35 143 DQ34 DQ39 144
145 DQ35 VSS33 146 DDR_B_D44
DDR_B_D40 147 VSS34 DQ44 148 DDR_B_D45 +1.5V
3 DDR_B_D41 149 DQ40 DQ45 150 3
151 DQ41 VSS35 152 DDR_B_DQS#5
Layout Note:
DDR_B_DM5 153 VSS36 DQS#5 154 DDR_B_DQS5 Place near JDDRL.203 and 204
155 DM5 DQS5 156
157 VSS37 VSS38 158
Close to JDDR3L.126
DDR_B_D42 DDR_B_D46 C195 2 1 10U_0603_6.3V6M
DDR_B_D43 159 DQ42 DQ46 160 DDR_B_D47
161 DQ43 DQ47 162 C189 2 1 10U_0603_6.3V6M
DDR_B_D49 165 DQ48 DQ52 166 DDR_B_D53 C181 2 1 10U_0603_6.3V6M +0.75VS +1.5V
167 DQ49 DQ53 168
DDR_B_DQS#6 169 VSS41 VSS42 170 DDR_B_DM6 C177 2 1 10U_0603_6.3V6M @
DDR_B_DQS6 171 DQS#6 DM6 172 C197 2 1 10U_0603_6.3V6M
173 DQS6 VSS43 174 DDR_B_D50 C175 2 1 10U_0603_6.3V6M
DDR_B_D54 175 VSS44 DQ54 176 DDR_B_D51
DDR_B_D55 177 DQ50 DQ55 178 C172 2 1 10U_0603_6.3V6M
179 DQ51 VSS45 180 DDR_B_D60
DDR_B_D56 181 VSS46 DQ60 182 DDR_B_D61 C190 1 2 0.1U_0402_16V4Z
DDR_B_D57 183 DQ56 DQ61 184
185 DQ57 VSS47 186 DDR_B_DQS#7 C191 1 2 0.1U_0402_16V4Z C194 1 2 0.1U_0402_16V4Z
189 DM7 DQS7 190 C192 1 2 0.1U_0402_16V4Z C206 1 2 0.1U_0402_16V4Z
DDR_B_D59 193 DQ58 DQ62 194 DDR_B_D63 C193 1 2 0.1U_0402_16V4Z
195 DQ59 DQ63 196
197 VSS51 VSS52 198
199 SA0 EVENT# 200 MEM_MB_EVENT# <6>
+3VS 201 VDDSPD SDA 202 FCH_SDATA0 <10,24,28>
203 SA1 SCL 204 FCH_SCLK0 <10,24,28>
1 +0.75VS VTT1 VTT2 +0.75VS
205 206
C208 G1 G2
2 LCN_DAN06-K4806-0103
4 0.1U_0402_16V4Z @ 4

DDRIII-SODIMM1
Custom 0.3
LA-9869P
A B C D E
A B C D E
PCIE_ATX_C_GRX_P[3..0] UV1A PCIE_GTX_C_ARX_P[3..0]

<5> PCIE_ATX_C_GRX_P[3..0] PCIE_GTX_C_ARX_P[3..0] <5>
<5> PCIE_ATX_C_GRX_N[3..0]
PCIE_ATX_C_GRX_N[3..0] PART 1 0F 9 PCIE_GTX_C_ARX_N[3..0]
PCIE_GTX_C_ARX_N[3..0] <5> LVDS Interface
UV1D
1 1
PCIE_ATX_C_GRX_P0 AA38 Y33 PCIE_GTX_ARX_P0 .1U_0402_16V7K CV1 1 2 VGA@ PCIE_GTX_C_ARX_P0 PART 7 0F 9
PCIE_ATX_C_GRX_N0 Y37 PCIE_RX0P PCIE_TX0P Y32 PCIE_GTX_ARX_N0 1 2 VGA@ PCIE_GTX_C_ARX_N0
CV2
PCIE_RX0N PCIE_TX0N AK27
.1U_0402_16V7K RSVD/VARY_BL AJ27
Y35 W33 PCIE_GTX_ARX_P1 .1U_0402_16V7K CV3 1 2 VGA@ RSVD/DIGON
PCIE_ATX_C_GRX_P1 PCIE_GTX_C_ARX_P1
PCIE_ATX_C_GRX_N1 W36 PCIE_RX1P PCIE_TX1P W32 PCIE_GTX_ARX_N1 1 2 VGA@ PCIE_GTX_C_ARX_N1 LVDS CONTROL
CV4
PCIE_RX1N PCIE_TX1N
.1U_0402_16V7K
PCIE_ATX_C_GRX_P2 W38 U33 PCIE_GTX_ARX_P2 .1U_0402_16V7K CV5 1 2 VGA@ PCIE_GTX_C_ARX_P2 AK35

V37 PCIE_RX2P PCIE_TX2P U32 PCIE_GTX_ARX_N2 1 2 VGA@ TXCBP_DPB3P AL36
PCIE_ATX_C_GRX_N2 CV6 PCIE_GTX_C_ARX_N2
PCIE_RX2N PCIE_TX2N TXCBM_DPB3N
.1U_0402_16V7K
AJ38
V35 U30 PCIE_GTX_ARX_P3 .1U_0402_16V7K 1 2 VGA@ TX3P_DPB2P AK37
PCIE_ATX_C_GRX_P3 CV7 PCIE_GTX_C_ARX_P3
U36 PCIE_RX3P PCIE_TX3P U29 PCIE_GTX_ARX_N3 1 2 VGA@ TX3M_DPB2N
PCIE_ATX_C_GRX_N3 CV8 PCIE_GTX_C_ARX_N3
PCIE_RX3N PCIE_TX3N AH35
.1U_0402_16V7K TX4P_DPB1P AJ36
U38 T33 TX4M_DPB1N
T37 PCIE_RX4P PCIE_TX4P T32 AG38
PCIE_RX4N PCIE_TX4N TX5P_DPB0P AH37
TX5M_DPB0N
T35 T30 AF35
R36 PCIE_RX5P PCIE_TX5P T29 NC#AF35 AG36
PCIE_RX5N PCIE_TX5N NC#AG36
LVTMDP
R38 P33
P37 PCIE_RX6P PCIE_TX6P P32
PCIE_RX6N PCIE_TX6N AP34
TXCAP_DPA3P AR34
P35 P30 TXCAM_DPA3N
N36 PCIE_RX7P PCIE_TX7P P29 AW37
PCIE_RX7N PCIE_TX7N TX0P_DPA2P AU35
2 TX0M_DPA2N 2
N38 N33 AR37
M37 NC NC N32 TX1P_DPA1P AU39
NC NC AC Coupling Capacitor TX1M_DPA1N
PCI EXPRESS INTERFACE
PCIeR Gen1 and Gen2 only: Recommended value is 100 nF 10%.
AP35
M35 N30 PCIeR Gen3: Recommended value is 220 nF 10%. TX2P_DPA0P AR35
L36 NC NC N29 TX2M_DPA0N
NC NC AN36
NC AP37
L38 L33 NC
K37 NC NC L32
NC NC
K35 L30 VGA@ SUN-PRO M2_FCBGA962

J36 NC NC L29
NC NC
J38 K33
H37 NC NC K32
NC NC
H35 J33
G36 NC NC J32
NC NC
G38 K30
F37 NC NC K29
NC NC
F35 H33
E37 NC NC H32
NC NC
3 3
CLOCK
CLK_PCIE_VGA AB35
<23> CLK_PCIE_VGA
CLK_PCIE_VGA# AA36 PCIE_REFCLKP
<23> CLK_PCIE_VGA# PCIE_REFCLKN
CALIBRATION
Y30 VGA_PCIE_CALRP RV1 1 VGA@ 2 1.69K_0402_1%
PCIE_CALR_TX +0.95VGS
2 VGA@ 1 AH16 Y29 VGA_PCIE_CALRN RV3 1 VGA@ 2 1K_0402_1%
TEST_PG PCIE_CALR_RX +0.95VGS
RV2 1K_0402_5%
GPU_RST# AA30
3.3-V tolerant PERSTB
1
VGA@ SUN-PRO M2_FCBGA962

VGA@
RV212
100K_0402_5%
2
+3VS
VGA@
5
UV13
4 2 4
P
<24> PXS_RST# B 4 GPU_RST#

1 Y
<23,28,30> APU_PCIE_RST# A
G
3
MC74VHC1G08DFT2G SC70 5P

PCIE/LVDS
Rev
Custom 0.3
LA-9869P
A B C D E
A B C D E
UV1B
PART 2 0F 9
MLPS
MUTI GFX Primary Memory Aperture Size MLPS Bit Strap Name Legacy Description Settings
AD29 GENLK_CLK AU24
NC Requested at PCI Configuration
AC29 GENLK_VSYNC AV23
NC
PS_0[1] ROM_CONFIG[0] If BIOS_ROM_EN = 1, ROM_CONFIG[2:0] define the ROM type. If BIOS_ROM_EN = 0,
AT25 PS_0[2] ROM_CONFIG[1] GPIO[13:11] ROM_CONFIG[2:0] define the primary memory-aperture size. Refer to current 001
NC
AJ21 SWAPLOCKA AR24 Mars MLPS configuration Size of the Primary ROM_CONFIG [2:0]
AK21 DPA NC PS_0[3] ROM_CONFIG[2] databooks for details.
SWAPLOCKB Memory Apertures
AU26
NC
AV25
Bits[5:1] PU(1%) PD(1%) Cap
NC
xx000 NC 4.75k 128 MB 000 PS_0[4] N/A GENLK_VSYNC Reserved for internal use only. Must be 1 at reset. 1
AR8 NC AT27
NC
AU8 NC AR26
AP8
NC xx001 8.45k 2.00k
DBG_CNTL0 256 MB 001 STRAP_BIF_ Re-defined strap to indicate PCIe GEN3 capability.
AW8 NC AR30 PS_1[1] GEN3_EN_A GPIO_2 1 = PCIe GEN3 supported. 0
AR3
NC
AT29
xx010 4.53k 2.00k
NC NC 0 = PCIe GEN3 not supported.
AR1 NC 64 MB 010
+3VGS AU1 AV31
xx011 6.98k 4.99k
DBG_DATA0 NC
1 AU3 DBG_DATA1 AU30 1
AW3 DPB NC xx100 4.53k 4.99k
DBG_DATA2 Reserved 011 Determines whether or not the PCIe reference clock power
AP6 DBG_DATA3 AR32 management capability is reported in the PCI configuration space
AW5
NC
AT31
xx101 3.24k 5.62k
DBG_DATA4 NC PS_1[2] STRAP_BIF_ (otherwise known as CLKREQB).
AU5 DBG_DATA5 512 MB Not supported CLK_PM_EN GPIO_8 0
AR6 AT33
xx110 3.40k 10.0k 0 = The CLKREQB power management capability is disabled
RV12 DBG_DATA6 NC
AW6 AU32 1 = The CLKREQB power management capability is enabled
1 8 JTAG_TRSTB DBG_DATA7 NC xx111 4.75k NC
AU6 DBG_DATA8 1 GB Not supported
2 7 JTAG_TDI AT7 AU14
3 6 JTAG_TMS DBG_DATA9 NC 00xxx 680nF
AV7 DBG_DATA10 AV13
4 5 JTAG_TCK NC
AN7 DBG_DATA11 2 GB Not supported PS_1[3] N/A GENLK_CLK Reserved for internal use only. Must be 0 at reset. 0
AV9 AT15
01xxx 82nF
10K_8P4R_5% DBG_DATA12 NC
AT9 DBG_DATA13 AR14
@ AR10
NC 10xxx 10nF
DBG_DATA14 4 GB Not supported Transmitter (Tx) power savings enable.
AW10 DPC AU16 PS_1[4] TX_PWRS_ENB GPIO_0 1
DBG_DATA15 NC 11xxx NC 0 = 50% Tx output swing.
AU10 DBG_DATA16 AV15
AP10
NC 1 = Full Tx output swing.
RV13 DBG_DATA17
1 8 GPIO_16 AV11 DBG_DATA18 AT17
NC
2 7 GPIO_28_FDO AT11 DBG_DATA19 AR16
NC
3 6 VGA_SMB_CK2 AR12 DBG_DATA20 PCI EXPRESS transmitter, deemphasis enable.
4 5 VGA_SMB_DA2 AW12 DBG_DATA21 AU20 PS_1[5] TX_DEEMPH_EN GPIO_1 0 = Tx deemphasis disabled. 1
+3VGS NC
AU12 DBG_DATA22 AT19
AP12
NC 1 = Tx deemphasis enabled.
10K_8P4R_5% DBG_DATA23
VGA@ AT21
NC
AR20
NC
PS_2[1] N/A N/A Reserved. 0
VGA_SMB_CK2 AJ23 DPD AU22
SMBCLK SMBus NC
VGA_SMB_DA2 AH23 SMBDATA AV21
NC
CHECK VR PS_2[2] N/A N/A Reserved. 0
AT23
IF VR Suport PSI# and DPRSLPVR PU 10K NC
AR22
NC
to +3VGS: AK26 SCL To enable the external BIOS ROM device.
PSI# :Low load current flag AJ26 I2C PS_2[3] BIOS_ROM_EN GPIO_22 0
SDA 0 = Disable the external BIOS ROM device.
DPRSLPVR : Deeper sleep enable flag 1 = Enable the external BIOS ROM device.
AD39
R
GENERAL PURPOSE I/O AD37
AH20 AVSSN
GPU_DPRSLPVR GPIO_0
<46> GPU_DPRSLPVR
AH18 GPIO_1 AE36 VGA disable determines whether or not the card will be recognized as the
G
AN16 GPIO_2 AD35 system's VGA controller.
RV11 VGA@ AVSSN
1 2 10K_0402_5% PS_2[4] BIF_VGA_DIS GPIO_9 0 = VGA controller capacity enabled. 0
AF37
B 1 = The device will not be recognized as the systems VGA controller.
AH17 GPIO_5_AC_BATT AE38
<34> GPU_DOWN# AVSSN
GPU_VID5 AJ17 GPIO_6_TACH
<46> GPU_VID5 DAC1
AK17 GPIO_7_BLON AC36
TV1 AJ13 HSYNC AC38
2
GPU_GPIO8 GPIO_8_ROMSO VSYNC
PS_2[5] N/A N/A Reserved. 0 2
TV2 GPU_GPIO9 AH15 GPIO_9_ROMSI
TV3 GPU_GPIO10 AJ16 GPIO_10_ROMSCK
AK16 GPIO_11 AB34 PS_3[1] BOARD_CONFIG[0] Base on
AL16 RSET
GPIO_12 PS_3[2] BOARD_CONFIG[1] N/A Board configuration related strapping (such as memory ID). VRAM ID
AM16 GPIO_13 AD34
AM14 AVDD AE34
PS_3[3] BOARD_CONFIG[2]
GPIO_14_HPD2 AVSSQ
GPU_VID1 AM13 GPIO_15_PWRCNTL_0
<46> GPU_VID1
GPIO_16 AK14 GPIO_16 AC33
VDD1DI
AG30 GPIO_17_THERMAL_INT AC34 PS_0[5] AUD_PORT_CONN_ Together with PS_0[5] form the three-bit strap option to indicate the number of
AN14 VSS1DI
RV8 1 @ 2 10K_0402_5% AM17
GPIO_18_HPD3 Pin Name Type PD/PU Description PS_3[4] PINSTRAP[0] audio-capable display outputs. In a given ASIC there are as many endpoints as
GPIO_19_CTF PS_3[5] there are digital display outputs, though not all outputs are audio capable.
GPU_VID2 AL13 GPIO_20_PWRCNTL_1 V13 Power-state indicator.
<46> GPU_VID2 NC AUD_PORT_CONN_ 111 = No usable endpoints.
TV4 GPU_GPIO21 AJ14 GPIO_21 U13 Permits the voltage regulator to activate power-saving
NC PINSTRAP[1] 110 = One usable endpoint.
TV5 GPU_GPIO22 AK13 GPIO_22_ROMCSB AF33 I/O N/A
CLKREQ_PEG# AN13
NC
AF32 features. 101 = Two usable endpoints.
<24> CLKREQ_PEG# CLKREQB NC GPIO_0 3.3 V PD-reset
AA29 IF VR Suport PSI# and DPRSLPVR PU 10K to +3VGS. AUD_PORT_CONN_ 100 = Three usable endpoints.
RV141 VGA@ 2 NC
AG21 (VDDR3) PSI# :Low load current flag
NC PINSTRAP[2] 011 = Four usable endpoints. 111
GPU_VID3 AG32 GPIO_29 AC32 DPRSLPVR : Deeper sleep enable flag
10K_0402_5% <46> GPU_VID3 NC 010 = Five usable endpoints.
GPU_VID4 AG33 GPIO_30
<46> GPU_VID4 001 = Six usable endpoints.
AC31
NC_SVI2
AJ19 GENERICA AD30 (Optional) An input which allows the system to 000 = All endpoints are usable.
NC_SVI2
GENERIC_X AK19 GENERICB AD32 request a fastpower reduction by setting
NC_SVI2
Stereo-sync signal. AJ20 GENERICC
AK20 GPIO_5_AC_BATT to low (0 V). The resulting state
Indicates left/right frame, or top/bottom field. GENERICD I/O
AJ24 GPIO_5_AC_BATT PD-reset transition may disturb the display momentarily.
Can be left unconnected if not used. GENERICE_HPD4 3.3 V
AH26 GENERICF_HPD5 Power reductions that are less time critical
AH24 (VDDR3)
GENERICG_HPD6 should use the standard software methods in order
to prevent display disturbances. For MEMCLK 1GHZ Brand Description Comment PS_3[3:1] R_pu (ohm) R_pd (ohm)
PS_0 AM34 PS_0
AC30 CEC_1 skHynix H5TQ2G63DFR-N0C 1.5V/1GHz 000 NC 4750

Voltage control signals for the core (VDDC and VDDCI). gDDR3-2Gbit
AK24 HPD1 PS_1 AD31 PS_1 At reset, these signals will be inputs with weak
MLPS
PX_EN : internal pulldown resistors. Samsung K4W2G1646E-BC1A 1.5V/1GHz 111 4750 NC
High (3.3 V) switches the regulators GPIO_6
The VBIOS can define all voltage-control signals to be
off (enter BACO mode). AH13 AG31 either 3.3-V or open-drain outputs (all signals must
DBG_VREFG PS_2 PS_2 GPIO_15_PWRCNTL_0 I/O
+3VGS Low (0 V) switches the regulators PD-reset
3.3 V be the same type).
Enable JTAG access on. (Default) GPIO_20_PWRCNTL_1 For MEMCLK 900MHZ Brand Description Comment PS_3[3:1] R_pu (ohm) R_pd (ohm)
(VDDR3) The output states (high/low) of these pins are
TV9 BACO programmable for each AMD PowerPlay state when they
PX_EN AL21 PX_EN AD33 PS_3 GPIO_29
PS_3
2
are used as voltage control signals. skHynix H5TQ2G63DFR-11C 1.5V/900MHz 000 NC 4750
RV7 GPIO_30 Note: GPIO_29 and GPIO_30 are only available on 28-nm
5.11K_0402_5% ASICs, and are NC on earlier generation ASICs.
3 @ gDDR3-2Gbit Micron MT41K128M16JT-107G:K 1.35V-1.5V/900MHz 001 8450 2000 3
DEBUG DDC/AUX AM26
DDC1CLK
1
AN26
DDC1DATA
TESTEN AD28 TESTEN I Serial-ROM output from ROM. Samsung K4W2G1646E-BC11 1.5V/900MHz 111 4750 NC
AM27 3.3 V General purpose I/O or open-drain output.
AUX1P
Reserved signal, for normal ASIC operation. AL27 GPIO_8_ROMSO PD-reset
AUX1N (VDDR3)
Design: No use external VGA ROM, so use the test point.
JTAG_TRSTB AM23 AM19
JTAG_TRSTB DDC2CLK
MLPS Strap
2
JTAG_TDI AN23 JTAG_TDI AL19 Serial-ROM input to ROM.

DDC2DATA
RV9 JTAG_TCK AK23 JTAG_TCK GPIO_9_ROMSI General purpose I/O or open-drain output.
1K_0402_5% JTAG_TMS AL24 JTAG_TMS AN20
AUX2P
VGA@ TV7 JTAG_TDO AM24 JTAG_TDO AM20 O Serial-ROM clock to ROM. Bits[5:4] Bits[3:1] Capacitor R_pu R_pd
AUX2N
GPIO_10_ROMSCK 3.3 V General purpose I/O or open-drain output.
1
GPIO_28_FDO MLPS AL30 PD-reset

NC
AM30 (VDDR3) 11 001 NC 8.45K 2K
NC BIOS-ROM chip select. PS_0[5:1]
H Disable Used to enable the ROM for ROM read and program
THERMAL AL29 GPIO_22_ROMCSB
L Enable AF29
NC
AM29 operations. PS_1[5:1] 11 001 NC 8.45K 2K
DPLUS NC
AG29 DMINUS Design: No use external VGA ROM, so use the test
AN21 points.
NC
AM21 PS_2[5:1] 00 000 680 nF NC 4.75K
NC
GPIO_28_FDO AK32 GPIO_28_FDO
AK30 I/O Thermal monitor interrupt.
NC
AL31 TS_A AK29 GPIO_17_THERMAL_INT 3.3 V PD-reset An input from an external temperature sensor (ALERTb). PS_3[5:1] 11 XXX NC X X
+1.8VGS +TSVDD NC
(1.8V@13mA TSVDD) (VDDR3)
VGA@ LV3 AJ30
DDCVGACLK
1 2 +TSVDD AJ32 TSVDD AJ31 Critical temperature fault (CTF) (active high) will
DDCVGADATA
BLM15BD121SN1D_0402 AJ33 output 3.3 V if the on-die temperature sensor exceeds
1U_0402_6.3V6K
10U_0603_6.3V6M
0.1U_0402_16V4Z
TSVSS
CV17
CV18
CV19
1 1 1 a critical temperature so that the motherboard can

O Mapping to VRAM type please refer to page 6 +1.8VGS
TSVDD
120ohm
MarsCRB
1
Design
1 2 2 2
VGA@ SUN-PRO M2_FCBGA962 GPIO_19_CTF 3.3 V
(VDDR3)
PD-reset
The CTF setpoint is 109
protect the ASIC from damage by removing power.
by default, and is
programmed during ASIC initialization. See the
1
1
1
VGA@
VGA@
VGA@
0.1u 1 1 advisory for AMD PowerPlay states for more details.

@ @ @ VGA@
RV20 RV21 RV22 RV23
1u 1 1 8.45K_0402_1% 8.45K_0402_1% 8.45K_0402_1% 8.45K_0402_1% +3VGS
10u 1 1 (Optional) Voltage control signal for the
2
2
2
I/O memory-voltage regulator. PS_0
GPIO_21 3.3 V PD-reset Note: This signal must be low (0 V) at reset PS_1
PS_2
(VDDR3)
2
(failure to do so will prevent booting). PS_3 VGA@
1
VGA_SMB_CK2 1 6
EC_SMB_CK2 <34,35>
Disable MLPS: PU 10K ohm to 3.3V. @ 1 VGA@ 1 @ 1 @ 1 @ VGA@ VGA@ VGA@
5
4 4
I/O (Do not install for Mars) CV20 CV21 CV22 CV23 RV27 RV28 RV68 RV30 QV1A
GPIO_28_FDO 3.3 V PD-reset 2K_0402_1% 4.75K_0402_1% 4.75K_0402_1% 2K_0402_1% DMN66D0LDW-7 2N_SOT363-6
0.01U_0402_16V7K
0.68U_0402_10V6K
0.01U_0402_16V7K
0.01U_0402_16V7K
Enable MLPS: PD 10K ohm to GND. VGA_SMB_DA2 4 3
(VDDR3) EC_SMB_DA2 <34,35>
2
(Install for Mars) 2 2 2 2
QV1B VGA@
DMN66D0LDW-7 2N_SOT363-6
Supports the CLKREQB feature for saving power to turn
CLKREQB O on/off the REFCLK clock on the ASIC.
On/off regulator switch in AMD PowerXpress? (switchable

graphics) BACO mode.
High (3.3 V) switches the regulators off (enter BACO
PX_EN O PD mode). Security Classification Compal Secret Data Compal Electronics, Inc.
Low (0 V) switches the regulators on. (Default) Issued Date 2013/01/22 2014/01/21 Title
Deciphered Date
PX_EN is tri-state before internal TEST_PG is asserted
and PERSTb is deasserted. THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Main_MSIC
Custom 0.3
LA-9869P
A B C D E
A B C D E
UV1C
PART 9 0F 9
+1.8VGS +MPV18
LV7 VGA@ (MPLL_PVDD:1.8V@130mA )
MPLL_PVDD MarsCRB Design 1 2 AV33 VGA_X1
XTALIN VGA_X1 <29>
220ohm 1 1 BLM15BD121SN1D_0402
1U_0402_6.3V6K
0.1U_0402_16V7K
CV79
CV80
CV78
1 1
2.2U_0402_6.3V6M
0.1u 1 1 1 1 1
NOGCLK@
1u 1 1 RV31 1 2 1M_0402_5%
2.2u 1 1 2 2 2
VGA@
VGA@
VGA@
AU34 XTALOUT
XTALOUT
YV1
4 3 XTALOUT
NC OSC
+MPV18 H7 VGA_X1 1 2
MPLL_PVDD OSC NC
H8 2 2
MPLL_PVDD
27MHZ 10PF +-20PPM X3G027000DA1H
+SPV18 (SPLL_PVDD:1.8V@75mA ) AW34 CV24 NOGCLK@ CV25
SPLL_PVDD MarsCRB Design +1.8VGS
LV8 VGA@ XO_IN
15P_0402_50V8J 15P_0402_50V8J
1 1
120ohm 1 1 1 2 +SPV18 AM10
SPLL_PVDD NOGCLK@ NOGCLK@
PLLS/XTAL
BLM15BD121SN1D_0402
0.1u 1 1
CV81
CV83
CV82
0.1U_0402_16V7K
1U_0402_6.3V6K
2.2U_0402_6.3V6M
1u 1 1 1 1 1
+SPLL_VDDC AN9
SPLL_VDDC
AW35
XO_IN2
2.2u 1 1
2 2 2
VGA@
VGA@
VGA@
AN10
SPLL_PVSS
+0.95VGS AK10 Debug Only, for clock observation

SPLL_VDDC MarsCRB Design LV9 VGA@
+SPLL_VDDC
(SPLL_VDDC:0.95V@100mA ) AF30 CLKTESTA AL10
As short as possible
NC_XTAL_PVDD CLKTESTB
120ohm 1 1 1 2 AF31
NC_XTAL_PVSS
BLM15BD121SN1D_0402
0.1u 1 1
CV94
CV92
CV93
0.1U_0402_16V7K
1U_0402_6.3V6K
2.2U_0402_6.3V6M
1 1 1
2 1u 1 1 2
2.2u 1 1
2 2 2
VGA@
VGA@
VGA@
+1.5V to +1.5VGS
+1.5V +1.5VGS
+3VS to +3VGS
3 +3VGS 3
Vgs=10V,Id=14.5A,Rds=6mohm +3VS
+3VALW
VGA@
2
VGA@
QV3 RV43
470_0805_5%
8 1
D S 470_0805_5%
2
7 2
2
D S VGA@ 2@
6 3 RV45
5 D S 4
RV44 CV103 Vgs=-4.5V,Id=3A,Rds<97mohm
3 1
VGA@ 100K_0402_5% 0.1U_0402_16V7K
D G
VGA@
FDS6676AS_SO8 1 RV48 2 1
AO3413_SOT23
B+ VGA@ RV46
3 1
1
220K_0402_5%
3
S
1 QV9B 47K_0402_5%
1
6
820K_0402_5%
VGA@ CV106
VGA@ RV49
0.1U_0402_25V6
VGA@ 2N7002DW-T/R7_SOT363-6 5 PXS_PWREN# 1 2

G
2
VGA@
QV8B +3VGS
VGA@ CV104
0.01U_0402_25V7K
2 2 QV4 D
1
2 VGA_PWRGD# 5 2N7002DW-T/R7_SOT363-6 VGA@
2N7002DW-T/R7_SOT363-6
2
VGA@
6
VGA@
1
QV8A QV9A 1
2N7002DW-T/R7_SOT363-6
PXS_PWREN 2
<24,46,47> PXS_PWREN
1
+5VALW
1
RV5530
100K_0402_5%
2
4 VGA_PWRGD# VGA@ 4
1
QV188 D
2
<24,43,46> VGA_PWRGD G 2N7002KW_SOT323-3
VGA@
S Issued Date 2013/01/22 Deciphered Date 2014/01/21 Title
3
BACO POWER
Rev
Custom 0.3
LA-9869P
A B C D E
A B C D E
VDDR1 MarsCRB Design

0.01u 5 0 UV1E
+1.8VGS
+1.5VGS (PCIE_PVDD: 1.80V@100mA)
0.1u 5 0 PART 5 0F 9 +1.8VGS
PCIE_PVDD MarsCRB Design
2.2u 5 5 1u 2 2
(VDDR1:1.5V@1.5A) Maximum Current on +1.8VGS:
CV30
CV31
CV32
MEM I/O
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
10u 3 3 +1.5VGS AC7
VDDR1 NC
AA31 1 1 1 "Sun": ~0.5 A 10u 1 1
AD11 VDDR1 AA32
AF7 NC AA33
CV33
CV34
CV35
CV36
CV37
CV38
CV39
CV40
VDDR1
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
NC
1 1 1 1 1 1 1 1 AG10 VDDR1 AA34
NC 2 2 2
AJ7 W30
VGA@
VGA@
VGA@
VDDR1 NC
AK8 Y31
VDD_CT MarsCRB Design AL9
VDDR1 NC
V28 PCIE_VDDC:
2 2 2 2 2 2 2 2 VDDR1 NC_BIF_VDDC
120ohm 1 1 G11 W29
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VDDR1 NC_BIF_VDDC 0.95 V @ 1.88 A (PCIe Gen 2.0) +0.95VGS
G14 VDDR1 AB37
1
0.1u 1 1 PCIE_PVDD 0.95 V @ 2.50 A (PCIe Gen 3.0) 1
PCIE
G17
G20
VDDR1
G30 +0.95VGS
PCIE_VDDC MarsCRB Design
1u 1 1 G23
VDDR1
VDDR1
PCIE_VDDC
G31 1u 7 7
G26 PCIE_VDDC H29
10u 1 1
CV43
CV44
CV45
CV46
CV41
CV47
CV48
CV49
CV50
VDDR1
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
PCIE_VDDC 10u 2 2
G29 VDDR1 H30 1 1 1 1 1 1 1 1 1
PCIE_VDDC
H10 J29
VDDR1 PCIE_VDDC
J7 J30
VDDR1 PCIE_VDDC
J9 VDDR1 L28
K11 PCIE_VDDC M28 2 2 2 2 2 2 2 2 2
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VDDR3 Mars check list Design K13
VDDR1 PCIE_VDDC
N28
VDDR1 PCIE_VDDC
120ohm 1 1 K8
L12
VDDR1 PCIE_VDDC
R28
T28
BIF_VDDC Mars check list Design
VDDR1 PCIE_VDDC
1u 3 2 L16 VDDR1 PCIE_VDDC
U28 1u 1 1
L21 +0.95VGS
10u 1 0 L23
VDDR1
VDDR1 (BIF_VDDC: 0.95V@1.4A) 10u 1 1
0.1u 0 1 L26 N27 +0.95VGS
VDDR1 BACO BIF_VDDC
L7 T27
VDDR1 BIF_VDDC
M11 VDDR1
N11
CV68
CV69
CV67
VDDR1
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
P7 VDDR1 AA15 1 1 1 Maximum Current on +0.95VGS:
CORE VDDC
R11 AA17 "Sun": ~4.0 A for PCIe GEN 3.0 designs
+1.8VGS +VDDC_CT VDDR1 VDDC
U11 AA20
VDDR1 VDDC (estimated)
LV4 VGA@ (VDD_CT:1.8V@13mA ) U7 VDDR1 AA22
VDDC 2 2 2
@
@
1 2 Y11 AA24
VDDR1 VDDC
BLM15BD121SN1D_0402 Y7 VDDR1 AA27
VDDC
AB16
CV51
CV52
CV53
10U_0603_6.3V6M
1U_0402_6.3V6K
0.1U_0402_16V7K
VDDC AB18
1 1 1 VDDC
AB21
VDDC AB23
VDDC
LEVEL AB26
2 2 2 VDDC +VGA_CORE
AB28
VGA@
VGA@
VGA@
TRANSLATION VDDC
+VDDC_CT AF26 AC17
VDD_CT VDDC
AF27 VDD_CT AC20
AG26 VDDC AC22
VDD_CT +VGA_CORE
VDDC
AG27 VDD_CT AC24
VDDC
AC27
+3VGS +VDDR3 VDDC AD18
VDDC
2 LV5 VGA@ (VDDR3:3.3V@25mA) I/O AD21 2
1 2 AF23 VDDC AD23
+VDDR3 VDDR3 VDDC
BLM15BD121SN1D_0402 AF24 VDDR3 AD26
VDDC
AG23 AF17
CV42
CV54
CV55
VDDR3
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_16V7K
AG24 VDDC AF20
1 1 1 VDDR3 VDDC
AF22
VDDC AG16
DVP VDDC
AD12 VDDR4 AG18
2 2 2 VDDC
AF11
VGA@
VGA@
VGA@
VDDR4
AF12 AH22 +VGA_CORE
VDDR4 VDDC
AF13 VDDR4 AH27
VDDC AH28
VDDC
M26
VDDC
AF15 N24
VDDR4 VDDC
AG11 R18
VDDR4 VDDC
AG13 VDDR4 R21
AG15 VDDC R23
VDDR4 VDDC
R26
VDDC
T17
VDDC T20
VDDC
T22
VDDC T24
VDDC
U16
VDDC
U18
VDDC U21
VDDC
U23
VDDC U26
VDDC
V17
VDDC
V20
VDDC V22
VDDC
V24
VDDC V27
VDDC
Y16
VDDC
Y18
VDDC Y21
VDDC
Y23
VDDC Y26
VDDC
Y28
3 VDDC 3
AA13 +VGA_CORE
VDDCI
AB13
VDDCI AC12
VDDCI
AC15
VDDCI
AD13
VDDCI AD16
VDDCI
M15
VDDCI M16
VDDCI
M18
Route as differential pair VOLTAGE VDDCI
M23
CORE I/O
SENESE VDDCI
ISOLATED
N13
VDDCI
AF28 FB_VDDC N15
<46> VCC_GPU_SENSE VDDCI N17
VDDCI
N20
VDDCI
AG28 N22
FB_VDDCI VDDCI
TV44 R12
VDDCI
R13
AH29 VDDCI R16
<46> VSS_GPU_SENSE FB_GND VDDCI
T12
VDDCI
T15
VDDCI V15
VDDCI
Y13
VDDCI
Need check all power current and decoupling capacitors

after got SUN databook and reference schematic.
4 4

Power
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.3
LA-9869P
A B C D E
A B C D E
UV1H UV1I
PART 3 0F 9 PART 4 0F 9 MAB[0..15]
MDB[0..63] MAB[0..15] <18>
GDDR5/DDR3 <18> MDB[0..63]
C37 G24 MDB0 C5 GDDR5/DDR3 P8 MAB0 DQMB#[0..7]
DQA0_0 MAA0_0/MAA_0 DQB0_0 MAB0_0/MAB_0 DQMB#[0..7] <18>
C35 J23 MDB1 C3 T9 MAB1
DQA0_1 MAA0_1/MAA_1 DQB0_1 MAB0_1/MAB_1
A35 H24 MDB2 E3 P9 MAB2 QSB[0..7]
DQA0_2 MAA0_2/MAA_2 DQB0_2 MAB0_2/MAB_2 QSB[0..7] <18>
E34 J24 MDB3 E1 N7 MAB3
DQA0_3 MAA0_3/MAA_3 DQB0_3 MAB0_3/MAB_3 QSB#[0..7]
G32 H26 MDB4 F1 N8 MAB4
DQA0_4 MAA0_4/MAA_4 DQB0_4 MAB0_4/MAB_4 QSB#[0..7] <18>
D33 DQA0_5 MAA0_5/MAA_5 J26 MDB5 F3 MAB0_5/MAB_5 N9 MAB5
F32 H21 F5 DQB0_5 U9
DQA0_6 MAA0_6/MAA_6 MDB6 MAB0_6/MAB_6 MAB6
DQB0_6
E32 G21 MDB7 G4 U8 MAB7
MEMORY INTERFACE A
D31 H19 MDB8 H5 Y9 MAB8
F30 H20 MDB9 H6 W9 MAB9
C30 DQA0_10 MAA1_2/MAA_10 L13 MDB10 J4 MAB1_2/MAB_10 AC8 MAB10
A30 G16 K6 DQB0_10 AC9
DQA0_11 MAA1_3/MAA_11 MDB11 MAB1_3/MAB_11 MAB11
DQB0_11
F28 DQA0_12 MAA1_4/MAA_12 J16 MDB12 K5 MAB1_4/MAB_12 AA7 MAB12
1 DQB0_12 1
C28 H16 MDB13 L4 AA8 B_BA2
DQA0_13 MAA1_5/MAA_BA2 DQB0_13 MAB1_5/BA2 B_BA2 <18>
A28 J17 MDB14 M6 Y8 B_BA0
DQA0_14 MAA1_6/MAA_BA0 DQB0_14 MAB1_6/BA0 B_BA0 <18>
E28 DQA0_15 MAA1_7/MAA_BA1 H17 MDB15 M1 MAB1_7/BA1 AA9 B_BA1
DQB0_15 B_BA1 <18>
MEMORY INTERFACE B
D27 MDB16 M3
DQA0_16 DQB0_16
F26 DQA0_17 WCKA0_0/DQMA_0 A32 MDB17 M5 H3 DQMB#0
DQB0_17 WCKB0_0/DQMB_0
C26 C32 MDB18 N4 H1 DQMB#1
DQA0_18 WCKA0B_0/DQMA_1 DQB0_18 WCKB0B_0/DQMB_1
A26 D23 MDB19 P6 T3 DQMB#2
DQA0_19 WCKA0_1/DQMA_2 DQB0_19 WCKB0_1/DQMB_2
F24 DQA0_20 WCKA0B_1/DQMA_3 E22 MDB20 P5 T5 DQMB#3
C24 C14 R4 DQB0_20 WCKB0B_1/DQMB_3 AE4
DQA0_21 WCKA1_0/DQMA_4 MDB21 DQMB#4
DQB0_21 WCKB1_0/DQMB_4
A24 DQA0_22 WCKA1B_0/DQMA_5 A14 MDB22 T6 AF5 DQMB#5
DQB0_22 WCKB1B_0/DQMB_5
E24 E10 MDB23 T1 AK6 DQMB#6
DQA0_23 WCKA1_1/DQMA_6 DQB0_23 WCKB1_1/DQMB_6
C22 D9 MDB24 U4 AK5 DQMB#7
DQA0_24 WCKA1B_1/DQMA_7 DQB0_24 WCKB1B_1/DQMB_7
A22 DQA0_25 MDB25 V6
F22 C34 V1 DQB0_25 F6
DQA0_26 MDB26 QSB0
EDCA0_0/QSA_0 DQB0_26 EDCB0_0/QSB_0
D21 DQA0_27 D29 MDB27 V3 K3 QSB1
A20 D25 MDB28 Y6 P3 QSB2
DQA0_28 EDCA0_2/QSA_2 DQB0_28 EDCB0_2/QSB_2
F20 E20 MDB29 Y1 V5 QSB3
D19 DQA0_30 E16 MDB30 Y3 AB5 QSB4
E18 EDCA1_0/QSA_4 E12 Y5 DQB0_30 EDCB1_0/QSB_4 AH1
DQA0_31 MDB31 QSB5
C18 DQA1_0 J10 MDB32 AA4 AJ9 QSB6
A18 D7 MDB33 AB6 AM5 QSB7
F18 MDB34 AB1
DQA1_2 DQB1_2
D17 DQA1_3 A34 MDB35 AB3 G7 QSB#0
A16 DDBIA0_0/QSA_0B E30 AD6 DQB1_3 DDBIB0_0/QSB_0B K1
DQA1_4 MDB36 QSB#1
DDBIA0_1/QSA_1B DQB1_4 DDBIB0_1/QSB_1B
F16 DQA1_5 E26 MDB37 AD1 P1 QSB#2
D15 C20 Close to pin Y12 and AA12 MDB38 AD3 W4 QSB#3
DQA1_6 DDBIA0_3/QSA_3B DQB1_6 DDBIB0_3/QSB_3B
E14 C16 MDB39 AD5 AC4 QSB#4
DQA1_7 DDBIA1_0/QSA_4B DQB1_7 DDBIB1_0/QSB_4B
F14 DQA1_8 C12 MDB40 AF1 AH3 QSB#5
D13 DDBIA1_1/QSA_5B J11 AF3 DQB1_8 DDBIB1_1/QSB_5B AJ8
DQA1_9 MDB41 QSB#6
DDBIA1_2/QSA_6B +1.5VGS DQB1_9 DDBIB1_2/QSB_6B
F12 DQA1_10 F8 MDB42 AF6 AM3 QSB#7
A12 MDB43 AG4
DQA1_11 DQB1_11
D11 J21 MDB44 AH5 T7 ODTB0
DQA1_12 ADBIA0/ODTA0 DQB1_12 ADBIB0/ODTB0 ODTB0 <18>
1
F10 DQA1_13 G19 MDB45 AH6 W7 ODTB1
A10 ADBIA1/ODTA1 AJ4 DQB1_13 ADBIB1/ODTB1 ODTB1 <18>
DQA1_14 RV72 MDB46
DQB1_14
C10 DQA1_15 CLKA0 H27 40.2_0402_1% MDB47 AK3 L9 CLKB0
DQB1_15 CLKB0 CLKB0 <18>
G13 G27 VGA@ MDB48 AF8 L8 CLKB0#
DQA1_16 CLKA0B DQB1_16 CLKB0B CLKB0# <18>
H13 15mil MDB49 AF9
DQA1_17 DQB1_17
2
2 J13 DQA1_18 CLKA1 J14 MDB50 AG8 AD8 CLKB1 2
H11 H14 AG7 DQB1_18 CLKB1 AD7 CLKB1 <18>
DQA1_19 CLKA1B +MVREFDB_SB MDB51 CLKB1#
DQB1_19 CLKB1B CLKB1# <18>
G10 DQA1_20 MDB52 AK9
DQB1_20
G8 K23 MDB53 AL7 T10 RASB0#
DQA1_21 RASA0B DQB1_21 RASB0B RASB0# <18>
1
K9 K19 1 MDB54 AM8 Y10 RASB1#
DQA1_22 RASA1B DQB1_22 RASB1B RASB1# <18>
K10 DQA1_23 RV73 CV159 MDB55 AM7
G9 K20 AK1 DQB1_23 W10
DQA1_24 100_0402_1% 1U_0402_6.3V6K MDB56 CASB0#
CASA0B DQB1_24 CASB0B CASB0# <18>
A8 DQA1_25 K17 VGA@ VGA@ MDB57 AL4 AA10 CASB1#
CASA1B 2 DQB1_25 CASB1B CASB1# <18>
C8 MDB58 AM6
DQA1_26 DQB1_26
2
E8 CSA0B_0 K24 MDB59 AM1 P10 CSB0#_0
DQA1_27 DQB1_27 CSB0B_0 CSB0#_0 <18>
A6 DQA1_28 CSA0B_1 K27 MDB60 AN4 L10
C6 AP3 DQB1_28 CSB0B_1
DQA1_29 MDB61
DQB1_29
E6 DQA1_30 CSA1B_0 M13 MDB62 AP1 AD10 CSB1#_0
DQB1_30 CSB1B_0 CSB1#_0 <18>
A5 CSA1B_1 K16 MDB63 AP5 AC10
DQA1_31 DQB1_31 CSB1B_1
L18 MVREFDA CKEA0 K21 U10 CKEB0
L20 J20 Y12 CKEB0 AA11 CKEB0 <18>
MVREFSA CKEA1 +MVREFDB_SB CKEB1
MVREFDB CKEB1 CKEB1 <18>
AA12
MVREFSB
L27 WEA0B K26 N10 WEB0#
NC WEB0B WEB0# <18>
N12 WEA1B L15 AB11 WEB1#
NC WEB1B WEB1# <18>
AG12 NC
ZZZ2 ZZZ3 ZZZ4 ZZZ5
MAA0_8/MAA_13 H23 MAB0_8/MAB_13 T8 MAB13
RV34 1 VGA@ 2 120_0402_1% M27 J19 W8 MAB14
MEM_CALRP0 MAA1_8/MAA_14 MAB1_8/MAB_14
M21 S1G H1G S2G H2G U12 MAB15
MAA0_9/MAA_15 MAB0_9/MAB_15
M12 NC MAA1_9/RSVD M20 MAB1_9/RSVD V12
AH12 RV36 VGA@ RV70 VGA@
NC
S1G@ H1G@ S2G@ H2G@ DRAM_RST AH11 DRAM_RST#_R 1 2 1 2
DRAM_RST# <18>
10_0402_1% 51.1_0402_1%
X76xxxxxLx1 X76xxxxxLx2 X76xxxxxLx3 X76xxxxxLx4
1
2
VGA@ SUN-PRO M2_FCBGA962 VGA@
VGA@ SUN-PRO M2_FCBGA962 VGA@ CV158
RV71 120P_0402_50V9
2
4.99K_0402_1%
R_pu & R_pd resistor:
1
0402 1% resistors are required.
3 3
GPU Type Memory Bus Width VRAM Vendor Compal P/N Manufacturer P/N X76 P/N Size per part Configuration Total Memory Size/Qty PS_3[ 3 ] PS_3[ 2 ] PS_3[ 1] R_pu R_pd Place all these components close to GPU (Within 25mm)
and keep all component close to each other
64bit Hynix SA00003YOG0 H5TQ2G63DFR-11C X7648051L01 2Gbit 128M*16 1GB/4pcs RV20 RV27
SUN PRO-M2 0 0 0
NC 4.75K
SUN PRO-M2 64bit Hynix SA000065320 H5TQ2G63DFR-N0C X7648051L02 2Gbit 128M*16 1GB/4pcs 0 0 0
RV20 RV27
NC 4.75K
64bit Micron SA00005XB10 MT41K128M16JT-107G:K X7648051L03 2Gbit 128M*16 1GB/4pcs RV20 RV27
SUN PRO-M2 0 0 1
8.45K 2K
SUN PRO-M2 Samsung SA00005SH40 K4W2G1646E-BC11 X7648051L04 2Gbit 128M*16 1GB/4pcs RV20 RV27
64bit 1 1 1
4.75K NC
Samsung K4W2G1646E-BC1A 1GB/4pcs RV20 RV27

SUN PRO-M2 64bit SA000068U20 X7648051L05 2Gbit 128M*16 1 1 1
4.75K NC
4 4

MEM Interface
C 0.3
LA-9869P
A B C D E
A B C D E
UV1G
PART 6 0F 9 UV1F
AB39 A3 PART 8 0F 9
E39 GND GND A37
F34 GND GND AA16 DP_VDDR DP_VDDC
F39 GND GND AA18 AP31 +0.95VGS
G33 GND GND AA2 DP_VDDC AP32
G34 GND GND AA21 DP_VDDC AN33
H31 GND GND AA23 DP_VDDC AP33
H34 GND GND AA26 AN24 DP_VDDC AL33
H39 GND GND AA28 AP24 NC DP_VDDC AM33
J31 GND GND AA6 AP25 NC DP_VDDC AK33
1 J34 GND GND AB12 AP26 NC DP_VDDC AK34 1
GND GND NC DP_VDDC
(DP_VDDC: 0.95V@20mA)
K31 AB15 AU28 AN31
K34 GND GND AB17 AV29 NC DP_VDDC
K39 GND GND AB20 NC
L31 GND GND AB22
L34 GND GND AB24 AP20 AP13
GND GND NC NC
M34 AB27 AP21 AT13
M39 GND GND AC11 AP22 NC NC AP14
N31 GND GND AC13 AP23 NC NC AP15
N34 GND GND AC16 AU18 NC NC
P31 GND GND AC18 AV19 NC
P34 GND GND AC2 NC DP GND
P39 GND GND AC21 +1.8VGS AN27
R34 GND GND AC23 AH34 DP_VSSR AP27
T31 GND GND AC26 AJ34 DP_VDDR DP_VSSR AP28
T34 GND GND AC28 AF34 DP_VDDR DP_VSSR AW24
T39 GND GND AC6 AG34 DP_VDDR DP_VSSR AW26
U31 GND GND AD15 AM37 DP_VDDR DP_VSSR AN29
U34 GND GND AD17 AL38 DP_VDDR DP_VSSR AP29
GND GND
(DP_VDDR: 1.8V@20mA) DP_VDDR DP_VSSR
V34 AD20 AM32 AP30
V39 GND GND AD22 DP_VDDR DP_VSSR AW30
W31 GND GND AD24 DP_VSSR AW32
W34 GND GND AD27 DP_VSSR AN17
Y34 GND GND AD9 DP_VSSR AP16
Y39 GND GND AE2 DP_VSSR AP17
GND GND AE6 DP_VSSR AW14
GND AF10 DP_VSSR AW16
GND AF16 DP_VSSR AN19
GND AF18 DP_VSSR AP18
GND AF21 DP_VSSR AP19
GND GND DP_VSSR
AG17 AW20
F15 GND AG2 CALIBRATION DP_VSSR AW22
2 F17 GND GND AG20 DP_VSSR AN34 2
F19 GND GND DP_VSSR AP39
F21 GND AG6 AW28 DP_VSSR AR39
F23 GND GND AG9 NC DP_VSSR AU37
F25 GND GND AH21 DP_VSSR AF39
F27 GND GND AJ10 DP_VSSR AH39
F29 GND GND AJ11 AW18 DP_VSSR AK39
F31 GND GND AJ2 NC DP_VSSR AL34
F33 GND GND AJ28 DP_VSSR AV27
F7 GND GND AJ6 DP_VSSR AR28
F9 GND GND AK11 AM39 DP_VSSR AV17
G2 GND GND AK31 DP_CALR DP_VSSR AR18
G6 GND GND AK7 DP_VSSR AN38
H9 GND GND AL11 DP_VSSR AM35
J2 GND GND AL14 DP_VSSR AN32
J27 GND GND AL17 DP_VSSR
J6 GND GND AL2
J8 GND GND AL20
K14 GND GND
K7 GND AL23
L11 GND AL26
L17 GND GND AL32 VGA@ SUN-PRO M2_FCBGA962
L2 GND GND AL6
L22 GND GND AL8
L24 GND GND AM11
L6 GND GND AM31
M17 GND GND AM9
M22 GND GND AN11
M24 GND GND AN2
N16 GND GND AN30
N18 GND GND AN6
N2 GND GND AN8
3 N21 GND GND AP11 3
N23 GND GND AP7
N26 GND GND AP9
N6 GND GND AR5
R15 GND GND B11
R17 GND GND B13
R2 GND GND B15
R20 GND GND B17
R22 GND GND B19
R24 GND GND B21
R27 GND GND B23
R6 GND GND B25
T11 GND GND B27
T13 GND GND B29
T16 GND GND B31
T18 GND GND B33
T21 GND GND B7
T23 GND GND B9
T26 GND GND C1
U15 GND GND C39
U17 GND GND E35
U2 GND GND E5
U20 GND GND F11
U22 GND GND F13
U24 GND GND
U27 GND GND
U6 GND
V11 GND AG22
V16 GND NC
V18 GND
V21 GND
V23 GND
4 V26 GND 4
W2 GND
W6 GND
Y15 GND
Y17 GND
Y20 GND
Y22 GND A39
Y24 GND VSS_MECH AW1
Y27 GND
GND
VSS_MECH
VSS_MECH
AW39 Security Classification Compal Secret Data Compal Electronics, Inc.
PWR_GND
VGA@ SUN-PRO M2_FCBGA962 Size Document Number Rev
Custom 0.3
LA-9869P
A B C D E
5 4 3 2 1
CHANNEL B: 512MB/1024MB DDR3

UV5 UV6 UV7 UV8
+VREFC_A1_B M8 E3 MDB29 +VREFC_A2_B M8 E3 MDB17 +VREFC_A3_B M8 E3 MDB33 +VREFC_A4_B M8 E3 MDB53

H1 VREFCA DQL0 F7 MDB26 H1 VREFCA DQL0 F7 MDB19 H1 VREFCA DQL0 F7 MDB37 H1 VREFCA DQL0 F7 MDB50
VREFDQ DQL1 F2 MDB30 VREFDQ DQL1 F2 MDB16 VREFDQ DQL1 F2 MDB35 VREFDQ DQL1 F2 MDB52
MAB0 N3 DQL2 F8 MDB27 MAB0 N3 DQL2 F8 MDB22 MAB0 N3 DQL2 F8 MDB39 MAB0 N3 DQL2 F8 MDB51
MAB1 P7 A0 DQL3 H3 MDB31 MAB1 P7 A0 DQL3 H3 MDB20 MAB1 P7 A0 DQL3 H3 MDB32 MAB1 P7 A0 DQL3 H3 MDB55
MAB3 N2 A2 DQL5 G2 MDB28 MAB3 N2 A2 DQL5 G2 MDB18 MAB3 N2 A2 DQL5 G2 MDB34 MAB3 N2 A2 DQL5 G2 MDB54
MAB5 P2 A4 DQL7 MAB5 P2 A4 DQL7 MAB5 P2 A4 DQL7 MAB5 P2 A4 DQL7
MAB6 R8 A5 MAB6 R8 A5 MAB6 R8 A5 MAB6 R8 A5
MAB7 R2 A6 D7 MDB3 MAB7 R2 A6 D7 MDB15 MAB7 R2 A6 D7 MDB45 MAB7 R2 A6 D7 MDB57
D MDB[0..63] MAB8 T8 A7 DQU0 C3 MDB5 MAB8 T8 A7 DQU0 C3 MDB10 MAB8 T8 A7 DQU0 C3 MDB43 MAB8 T8 A7 DQU0 C3 MDB59 D
<16> MDB[0..63] A8 DQU1 A8 DQU1 A8 DQU1 A8 DQU1
MAB9 R3 C8 MDB1 MAB9 R3 C8 MDB12 MAB9 R3 C8 MDB47 MAB9 R3 C8 MDB63
MAB10 L7 A9 DQU2 C2 MDB6 MAB10 L7 A9 DQU2 C2 MDB8 MAB10 L7 A9 DQU2 C2 MDB42 MAB10 L7 A9 DQU2 C2 MDB62
MAB11 R7 A10/AP DQU3 A7 MDB2 MAB11 R7 A10/AP DQU3 A7 MDB13 MAB11 R7 A10/AP DQU3 A7 MDB44 MAB11 R7 A10/AP DQU3 A7 MDB56
MAB12 N7 A11 DQU4 A2 MDB7 MAB12 N7 A11 DQU4 A2 MDB9 MAB12 N7 A11 DQU4 A2 MDB40 MAB12 N7 A11 DQU4 A2 MDB61
MAB13 T3 A12 DQU5 B8 MDB0 MAB13 T3 A12 DQU5 B8 MDB14 MAB13 T3 A12 DQU5 B8 MDB46 MAB13 T3 A12 DQU5 B8 MDB58
MAB[15..0] MAB14 T7 A13 DQU6 A3 MDB4 MAB14 T7 A13 DQU6 A3 MDB11 MAB14 T7 A13 DQU6 A3 MDB41 MAB14 T7 A13 DQU6 A3 MDB60
<16> MAB[15..0] A14 DQU7 A14 DQU7 A14 DQU7 A14 DQU7
MAB15 M7 MAB15 M7 MAB15 M7 MAB15 M7
A15/BA3 +1.5VGS A15/BA3 +1.5VGS A15/BA3 +1.5VGS A15/BA3 +1.5VGS
M2 B2 B_BA0 M2 B2 B_BA0 M2 B2 B_BA0 M2 B2

<16> B_BA0 N8 BA0 VDD D9 N8 BA0 VDD D9 N8 BA0 VDD D9 N8 BA0 VDD D9
B_BA1 B_BA1 B_BA1
<16> B_BA1 BA1 VDD BA1 VDD BA1 VDD BA1 VDD
M3 G7 B_BA2 M3 G7 B_BA2 M3 G7 B_BA2 M3 G7
DQMB#[7..0] <16> B_BA2 BA2 VDD K2 BA2 VDD K2 BA2 VDD K2 BA2 VDD K2
<16> DQMB#[7..0] VDD VDD VDD VDD
K8 K8 K8 K8
VDD N1 VDD N1 VDD N1 VDD N1
J7 VDD N9 CLKB0 J7 VDD N9 J7 VDD N9 CLKB1 J7 VDD N9
<16> CLKB0 CK VDD CK VDD <16> CLKB1 CK VDD CK VDD
K7 R1 CLKB0# K7 R1 K7 R1 CLKB1# K7 R1
<16> CLKB0# K9 CK VDD R9 K9 CK VDD R9 <16> CLKB1# K9 CK VDD R9 K9 CK VDD R9
CKEB0 CKEB1
QSB[7..0] <16> CKEB0 CKE/CKE0 VDD +1.5VGS CKE/CKE0 VDD +1.5VGS <16> CKEB1 CKE/CKE0 VDD +1.5VGS CKE/CKE0 VDD +1.5VGS
<16> QSB[7..0]
K1 A1 ODTB0 K1 A1 K1 A1 ODTB1 K1 A1
<16> ODTB0 ODT/ODT0 VDDQ ODT/ODT0 VDDQ <16> ODTB1 ODT/ODT0 VDDQ ODT/ODT0 VDDQ
L2 A8 CSB0#_0 L2 A8 L2 A8 CSB1#_0 L2 A8
<16> CSB0#_0 J3 CS/CS0 VDDQ C1 J3 CS/CS0 VDDQ C1 <16> CSB1#_0 J3 CS/CS0 VDDQ C1 J3 CS/CS0 VDDQ C1
RASB0# RASB1#
<16> RASB0# RAS VDDQ RAS VDDQ <16> RASB1# RAS VDDQ RAS VDDQ
K3 C9 CASB0# K3 C9 K3 C9 CASB1# K3 C9
<16> CASB0# CAS VDDQ CAS VDDQ <16> CASB1# CAS VDDQ CAS VDDQ
L3 D2 WEB0# L3 D2 L3 D2 WEB1# L3 D2
QSB#[7..0] <16> WEB0# WE VDDQ E9 WE VDDQ E9 <16> WEB1# WE VDDQ E9 WE VDDQ E9
<16> QSB#[7..0] VDDQ VDDQ VDDQ VDDQ
F1 F1 F1 F1
QSB3 F3 VDDQ H2 QSB2 F3 VDDQ H2 QSB4 F3 VDDQ H2 QSB6 F3 VDDQ H2
QSB0 C7 DQSL VDDQ H9 QSB1 C7 DQSL VDDQ H9 QSB5 C7 DQSL VDDQ H9 QSB7 C7 DQSL VDDQ H9
DQSU VDDQ DQSU VDDQ DQSU VDDQ DQSU VDDQ
DQMB#3 E7 A9 DQMB#2 E7 A9 DQMB#4 E7 A9 DQMB#6 E7 A9

DQMB#0 D3 DML VSS B3 DQMB#1 D3 DML VSS B3 DQMB#5 D3 DML VSS B3 DQMB#7 D3 DML VSS B3
DMU VSS E1 DMU VSS E1 DMU VSS E1 DMU VSS E1
VSS G8 VSS G8 VSS G8 VSS G8
QSB#3 G3 VSS J2 QSB#2 G3 VSS J2 QSB#4 G3 VSS J2 QSB#6 G3 VSS J2
VGA@ QSB#0 B7 DQSL VSS J8 QSB#1 B7 DQSL VSS J8 QSB#5 B7 DQSL VSS J8 QSB#7 B7 DQSL VSS J8
C C
CLKB0 1 2 DQSU VSS M1 DQSU VSS M1 DQSU VSS M1 DQSU VSS M1
RV78 40.2_0402_1% VSS M9 VSS M9 VSS M9 VSS M9
VSS P1 VSS P1 VSS P1 VSS P1
VGA@ T2 VSS P9 DRAM_RST# T2 VSS P9 DRAM_RST# T2 VSS P9 DRAM_RST# T2 VSS P9
<16> DRAM_RST# RESET VSS RESET VSS RESET VSS RESET VSS
CLKB0# 1 2 T1 T1 T1 T1
RV79 40.2_0402_1% L8 VSS T9 L8 VSS T9 L8 VSS T9 L8 VSS T9
VGA@ ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS
1
CV160
1
1
1
0.01U_0402_16V7K J1 B1 J1 B1 J1 B1 J1 B1
RV80 L1 NC/ODT1 VSSQ B9 RV81 L1 NC/ODT1 VSSQ B9 RV82 L1 NC/ODT1 VSSQ B9 RV83 L1 NC/ODT1 VSSQ B9
2
243_0402_1% J9 NC/CS1 VSSQ D1 243_0402_1% J9 NC/CS1 VSSQ D1 243_0402_1% J9 NC/CS1 VSSQ D1 243_0402_1% J9 NC/CS1 VSSQ D1
VGA@ L9 NC/CE1 VSSQ D8 VGA@ L9 NC/CE1 VSSQ D8 VGA@ L9 NC/CE1 VSSQ D8 VGA@ L9 NC/CE1 VSSQ D8
NCZQ1 VSSQ E2 NCZQ1 VSSQ E2 NCZQ1 VSSQ E2 NCZQ1 VSSQ E2
2
2
2
VSSQ E8 VSSQ E8 VSSQ E8 VSSQ E8
VSSQ F9 VSSQ F9 VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1 VSSQ G1 VSSQ G1
VGA@ VSSQ G9 VSSQ G9 VSSQ G9 VSSQ G9
CLKB1 1 2 VSSQ VSSQ VSSQ VSSQ
RV84 40.2_0402_1% 96-BALL 96-BALL 96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
VGA@ K4W1G1646G-BC11_FBGA96 K4W1G1646G-BC11_FBGA96 K4W1G1646G-BC11_FBGA96 K4W1G1646G-BC11_FBGA96
CLKB1# 1 2 @ @ @ @
RV85 40.2_0402_1% VGA@
1
CV161
0.01U_0402_16V7K
2
Supported Memory Configurations: Up to 4 Gbit/part for DDR3.
+1.5VGS +1.5VGS +1.5VGS +1.5VGS

B B
1
1
VGA@ VGA@ VGA@ VGA@
RV86 RV87 RV88 RV89
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
15mil 15mil 15mil 15mil

2
2
+VREFC_A1_B +VREFC_A2_B +VREFC_A3_B +VREFC_A4_B
1
1
VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1
RV90 RV91 RV92 RV93
CV162
CV163
CV164
CV165
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
2 2 2 2
2
2
VGA@ VGA@ VGA@ VGA@
+1.5VGS +1.5VGS close to UV7 UV8

+1.5VGS +1.5VGS close to UV9 UV10
CV179
CV186
CV187
CV196
CV167
CV170
CV173
CV183
CV184
CV185
CV188
CV194
CV195
CV197
CV198
CV166
CV168
CV169
CV171
CV172
CV193
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
close to UV9 UV10
22U_0603_6.3V6M
A 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 A
VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@

VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
close to UV7 UV8 VGA@

VRAM Channel B
C 0.3
LA-9869P
5 4 3 2 1
5 4 3 2 1
SWR / LDO Mode select Mode Configure

ROM only mode : PIN 30 4.7k pull low, Pin 31 4.7k pull high.
EP
LDO SWR mode : PIN 30 4.7k pull high, Pin 31 4.7k pull low.
EEPROM : PIN 30 4.7k pull high, Pin 31 4.7k pull high.
R476/481/480/482 need to place under UT2
In orfer to reduce sub-trace Default mode
DP0_AUXP_C R476 1 IEDP@ 2 0_0402_5% LCD_EDID_CLK +3VS_RT +3VS_RT
D
2132R RT24 mount LT3 D
DP0_AUXN_C R481 1 2 0_0402_5% LCD_EDID_DATA
IEDP@
If use 2132R, please select LDO mode as default.
2
DP0_AUXP_C RT4 RT12
<7> DP0_AUXP_C
DP0_AUXN_C @ 4.7K_0402_5% LVDS@ 4.7K_0402_5%
<7> DP0_AUXN_C
DP0_TXP0_C
<7> DP0_TXP0_C
1
DP0_TXN0_C MIIC_SDA MIIC_SCL
<7> DP0_TXN0_C
reserve 0ohm
DP0_TXP0_C R480 1 IEDP@ 2 0_0402_5% LCD_TXOUT0+
for Power consumption
2
DP0_TXN0_C R482 1 2 0_0402_5% LCD_TXOUT0-
IEDP@ RT6 RT7
+3VS +3VS_RT LVDS@ 4.7K_0402_5% @ 4.7K_0402_5%
80mil LVDS@ 80mil PIN30 PIN31
1
1 RT1 2
0_0603_5%
Close to Pin3
+DP_V33
+3VS_RT
10U_0603_6.3V6M
0.1U_0402_16V4Z
0.1U_0402_16V4Z
UT2
1 1 1 LVDS@ 19
TXEC+ LCD_TXCLK+ <20>
LT1 2 1 +DP_V33 40mil 3 20
DP_V33 TXEC- LCD_TXCLK- <20>
CT1
CT2
CT3
FBMA-L11-201209-221LMA30T_0805
LVDS@ 13 21 +3VS_RT
2 2 2 100mil SWR_VDD TXE2+ LCD_TXOUT2+ <20>
Power
100mil LT2 2 1 +SWR_VDD 40mil 18
PVCC TXE2-
22
LCD_TXOUT2- <20> LVDS@
LVDS
FBMA-L11-201209-221LMA30T_0805 LCD_EDID_DATA RT9 1 2 4.7K_0402_5%
+SWR_V12 40mil 12 23 LVDS@
C SWR_LX TXE1+ LCD_TXOUT1+ <20> C
LVDS@ LVDS@ LVDS@ 40mil 11 24 LCD_EDID_CLK RT10 1 2 4.7K_0402_5%
SWR_VCCK TXE1- LCD_TXOUT1- <20>
40mil 27
7 VCCK 25 LCD_TXOUT0+
40mil DP_V12 TXE0+ LCD_TXOUT0+ <20>
26 LCD_TXOUT0-
TXE0- LCD_TXOUT0- <20>
Close to LT2 Close to Pin18 R8 for power consumption

RTD2132R Remove on PVT phase
+SWR_VDD DP0_AUXP_C 2
AUX_P
DP-IN
DP0_AUXN_C 1 14 TL_INVT_PWM
AUX_N GPIO(PWM OUT) TL_INVT_PWM <20>
GPIO
22U_0603_6.3V6M
0.1U_0402_16V4Z
0.1U_0402_16V4Z
10U_0603_6.3V6M
0.1U_0402_16V4Z
15 80mil +LCD_VDD_R
DP0_TXP0_C 5 GPIO(Panel_VCC) 16 +LCD_VDD
1 1 1 1 1 LANE0P GPIO(PWM IN) APU_INVT_PWM <20,9>
DP0_TXN0_C 6 17 LVDS@
LANE0N GPIO(BL_EN) EC_ENBKL <34>
CT4
CT6
CT7
CT5
CT8
+LCD_VDD_R 2 1 +LCD_VDD
R8 0_0805_5%
2 2 2 2 2 9 LVDS 29 LCD_EDID_CLK
<34> EC_SMB_CK3 CIICSCL1 MIICSCL1 LCD_EDID_CLK <20>
1
10 28 LCD_EDID_DATA 2
<34> EC_SMB_DA3 CIICSDA1 EDID MIICDA1 LCD_EDID_DATA <20>
Other
RT113
CT13 100K_0402_5%
LVDS@ LVDS@ LVDS@ LVDS@ LVDS@ 32 ROM 31 MIIC_SCL 4.7U_0603_6.3V6K
<20,7> LVDS_HPD HPD MIICSCL0 LVDS@
Close to Pin13 30 MIIC_SDA LVDS@ 1
2
8 MIICSDA0
4 DP_REXT 33
DP_GND GND
2
Close to Panel conn.

Close to L29
RT8 LVDS@ RTD2132R-VE-CG_QFN32_5X5
+SWR_V12 12K_0402_1% SA000069200
LVDS@
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Close to Pin8
10U_0603_6.3V6M
1 1 1 1
CT12
CT9
CT10
CT11
B B
2 2 2 2
PIN15 PIN16 Accept voltage input (high level)

LVDS@
LVDS@ LVDS@ LVDS@
Close to 2132S TL_ENVDD 2132S 3.3V
Pin27 Close to Pin7
2132R +LCD_VDD * 2132R 1.5~3.3V
LCD POWER CIRCUIT (For eDP panel only)
* Version R internal Power Switch, can * Version R has internal level shifter, remove
output 1A, Rds(on)=0.2 ohm level shifter circuit on AMD platform
Different between 2132S and 2132R

+3VS
+LCD_VDD
U18
2132S 2132R
1
W=80mils
W=80mils 5 VOUT
VIN 1. Support SWR mode 1. Support LDO mode and SWR mode
+LCD_VDD_SS 4 GND
2 2. Internal ROM
SS IEDP@ Close to Pin15 3. Support LCD_VDD(internal Power switch)
1
3 1 2
C2 EN R104 0_0402_5%
LCD_ENVDD <9> 4. Integrates Level shifter
APL3512ABI-TRG_SOT23-5
2
A 1500P_0402_50V7K IEDP@ A
IEDP@ SA00003AR00 R112
100K_0402_5%
1
IEDP@

LVDS Translator - RTD2132S
Custom 0.3
LA-9869P
5 4 3 2 1
A B C D E
For LVDS 1ch Panel EMI@

USB20_P1_R 1 2 USB20_P1 <24>
1 2
<19> LCD_TXOUT0+ LCD_TXOUT0+

USB20_N1_R 4 3 USB20_N1 <24>
LCD_TXOUT0- 4 3
<19> LCD_TXOUT0-
L55 W CM-2012-900T_0805
1 <19> LCD_TXOUT1- LCD_TXOUT1- 1
<19> LCD_TXOUT2- LCD_TXOUT2- @TOUCH_EMI@

1 2
<19> LCD_TXCLK+ LCD_TXCLK+ R155 0_0402_5%
<19> LCD_TXCLK- LCD_TXCLK- TOUCH_EMI@

USB20_N4_R 1 2 USB20_N4 <24>
LCD_EDID_CLK 1 2
<19> LCD_EDID_CLK
LCD_EDID_DATA USB20_P4_R 4 3 USB20_P4 <24>
<19> LCD_EDID_DATA 4 3
L56
W CM-2012-900T_0805
@TOUCH_EMI@
1 2
R156 0_0402_5%
For eDP Panel
D32 ESD@
USB20_P1_R 4 3 USB20_N1_R
4 3
<7> DP0_TXP1_C R102 1 IEDP@ 2 0_0402_5% LCD_TXOUT1+
2
<7> DP0_TXN1_C R105 1 IEDP@ 2 0_0402_5% LCD_TXOUT1- 2
IEDP@ +3VS
LCD_EDID_DATA 2 1 +3VS
R149 100K_0402_5% 5 2
LCD_EDID_CLK 2 1 Vbus GND
R150 100K_0402_5%
IEDP@
Reserve for eDP panel potience issue INT_MIC_DATA 6 1 INT_MIC_CLK

6 1
+3VS +5VS SC300001400 close to LVDS conn.
JLVDS @
1 +5VS_LVDS_TOUCH 1 @ 2
1 2 USB20_N4_R R391 0_0603_5%
IEDP@1 2 IEDP@ 2 3 USB20_P4_R
3
5
R103 0_0402_5% U19 4 BKOFF#

1 4 5 INT_MIC_DATA
P
IN1 LCD_ENBKL <34,9> 5 INT_MIC_DATA <32>

BKOFF#_R 1 2 4 6 INT_MIC_CLK
O 6 INT_MIC_CLK <32>
D16 RB751V40_SC76-2 2 7
IN2 BKOFF# <34> 7
G
8 USB20_P1_R +3VS
LVDS@ 8
1
9 USB20_N1_R
3
R114 SN74AHC1G08DCKR_SC70-5 9 10 +3VS_LVDS_CAM 1 @ 2

10 11 R392 0_0603_5%
10K_0402_5% 11
3 12 3
12
+LCD_VDD +LCD_VDD Irush=1.5A
13 +3VS
2
1 2 13 14 LCD_EDID_CLK
R152 0_0402_5% 14 15 LCD_EDID_DATA
LVDS@ 15 16 LCD_TXOUT0-
16 17 LCD_TXOUT0+
17 18 LCD_TXOUT1-
18 19 LCD_TXOUT1+
19 20
1.5A 20
LCD_TXOUT2-
21 LCD_TXOUT2+
+LCD_INV B+ 21 22
L2 EMI@ 22 23 LCD_TXCLK-
2 1 23 24 LCD_TXCLK+
FBMA-L11-201209-221LMA30T_0805 24 25 1 IEDP@ 2
25 LVDS_HPD <19,7>
26 LED_PW M R154 0_0402_5%
26 27 BKOFF#_R
27 28
28 29
29 30
30 +LCD_INV 1.5A
IEDP@ 31
1 2 GND 32
APU_INVT_PW M <19,9> GND
R108 0_0402_5% 33
GND 34
GND 35
LED_PW M 1 2 GND
TL_INVT_PW M <19>
D17 STARC_111H30-000000-G4-R
RB751V40_SC76-2
1
4 4
R133
47K_0402_5%
2

LVDS
Custom 0.3
LA-9869P
A B C D E
A B C D E
1 1
EMI@
<25> UMA_CRT_R L3 1 2 NBQ100505T-800Y_0402 CRT_R_L
EMI@
<25> UMA_CRT_G L4 1 2 NBQ100505T-800Y_0402 CRT_G_L
EMI@
<25> UMA_CRT_B L5 1 2 NBQ100505T-800Y_0402 CRT_B_L
JCRT @
6
T65 PAD 11
R138 R139 R140 CRT_R_L 1
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
7
150_0402_1%
150_0402_1%
150_0402_1%
1 1 1 1 1 1
1
EMI@ CRT_DDC_DAT 12
C238 C239 C240 C241 C242 C243 CRT_G_L 2
8
EMI@ 2 2 2 2 2 2 HSYNC 13
CRT_B_L 3
2
2
+HDMI_5V_OUT 9
EMI@ EMI@ EMI@ EMI@ VSYNC 14 G 16
T66 PAD 4 17
G
10
CRT_DDC_CLK 15
5
2 C-H_13-12201513CP 2
+HDMI_5V_OUT
2
C282
U4 +HDMI_5V_OUT
0.1U_0402_10V7K
1 1 8 1 2
+HDMI_5V_OUT VCC_SYNC BYP
Near U3.1 C19 0.22U_0402_16V7K
+3VS 2 3 CRT_B_L
VCC_VIDEO VIDEO1
2
+3VS 7 4 CRT_G_L R153 R159
VCC_DDC VIDEO2 4.7K_0402_5% 4.7K_0402_5%
<25> UMA_CRT_DATA UMA_CRT_DATA 10 5 CRT_R_L
1
DDC_IN1 VIDEO3
<25> UMA_CRT_CLK UMA_CRT_CLK 11 9 CRT_DDC_DAT

3 DDC_IN2 DDC_OUT1 3
UMA_CRT_VSYNC 13 12 CRT_DDC_CLK
<25> UMA_CRT_VSYNC SYNC_IN1 DDC_OUT2
R67
UMA_CRT_HSYNC 15 14 VSYNC_R 1 2 22_0402_5% VSYNC
<25> UMA_CRT_HSYNC SYNC_IN2 SYNC_OUT1
R66
6 16 HSYNC_R 1 2 22_0402_5% HSYNC
GND SYNC_OUT2
TPD7S019-15DBQR_SSOP16
SA000068B00
4 4

CRT
0.3
LA-9869P
A B C D E
5 4 3 2 1
HDMI POWER CIRCUIT

VIN = 5V, IOUT = 0.5A , RDS(ON) TYP=95m ; MAX=115m
Current Limit: TYP=0.8A ; MAX=1A
CV308 1 2 0.1U_0402_16V7K VGA_DVI_TXC+ HDMI_R_CK+ 1 2
<7> UMA_HDMI_TXC+
R195 604_0402_1%
CV304 1 2 0.1U_0402_16V7K VGA_DVI_TXC- HDMI_R_CK- 1 2 ZZZ HDMI45@
<7> UMA_HDMI_TXC- +HDMI_5V_OUT +5VS
R197 604_0402_1% HDMI Royalty
CV306 1 2 0.1U_0402_16V7K VGA_DVI_TXD0+ HDMI_R_D1- 1 2 U17
RO0000003HM
<7> UMA_HDMI_TX0+
1 5
R198 604_0402_1%
CV302 1 2 0.1U_0402_16V7K VGA_DVI_TXD0- HDMI_R_D1+ 1 2 OUT IN
<7> UMA_HDMI_TX0-
2
D R202 604_0402_1% 1 D
CV303 1 2 0.1U_0402_16V7K VGA_DVI_TXD1+ HDMI_R_D0+ 1 2 C284 GND HDMI W/Logo + HDCP
<7> UMA_HDMI_TX1+ 3 4
R201 604_0402_1%
CV301 1 2 0.1U_0402_16V7K VGA_DVI_TXD1- HDMI_R_D0- 1 2 0.1U_0402_10V7K FLG EN
<7> UMA_HDMI_TX1-
R203 604_0402_1% 2 HDMI W/O Logo: RO0000001HM
AP2151DWG-7_SOT25-5
<7> UMA_HDMI_TX2+
CV307 1 2 0.1U_0402_16V7K VGA_DVI_TXD2+ HDMI_R_D2- 1 2 SA00006H000 HDMI W/Logo: RO0000002HM
R205 604_0402_1%
CV305 1 2 0.1U_0402_16V7K VGA_DVI_TXD2- HDMI_R_D2+ 1 2 HDMI W/Logo + HDCP: RO0000003HM
<7> UMA_HDMI_TX2-
R206 604_0402_1%
1
D
2 Q24
+5VS
G 2N7002KW_SOT323-3
3
Change R184 and R185 from 2K to 4.7K
for HDMI detect issue on Comal
EMI@ L8
VGA_DVI_TXC- 1 2 HDMI_R_CK-
1 2
VGA_DVI_TXC+ 4 3 HDMI_R_CK+ +3VS

4 3 +HDMI_5V_OUT
WCM-2012-900T_0805 R145
HDMI_HPD_U 1 2 HDMI_HPD_C
1K_0402_5%
2
HDMI Connector
2
R186 C265
1
U9 100K_0402_5% 0.1U_0402_16V4Z
C C
OE#
2
1
G
EMI@ L9 2 4 HDMI_HPD JHDMI @
VGA_DVI_TXD0- 1 2 HDMI_R_D0- A Y HDMI_HPD_C 19
1
1 2 HP_DET
G
UMA_HDMI_CLK 3 1 HDMI_SCLK 74AHCT1G125GW_SOT353-5 18
<7> UMA_HDMI_CLK +HDMI_5V_OUT +5V
17
3
VGA_DVI_TXD0+ 4 3 HDMI_R_D0+ Q18 HDMI_SDATA 16 DDC/CEC_GND
4 3 FDV301N-NL_SOT23-3 HDMI_SCLK 15 SDA
WCM-2012-900T_0805 14 SCL
Reserved
2
G
13
HDMI_R_CK- 12 CEC
UMA_HDMI_DATA 3 1 HDMI_SDATA 11 CK-
<7> UMA_HDMI_DATA CK_shield
HDMI_R_CK+ 10
D
Q19 HDMI_R_D0- 9 CK+
FDV301N-NL_SOT23-3 8 D0-
2 1 HDMI_R_D0+ 7 D0_shield
+3VS D0+
EMI@ L10 Q18/Q19 R571 HDMI_R_D1- 6
VGA_DVI_TXD1- 1 2 HDMI_R_D1- 2.2K_0402_5% 5 D1-
1 2 Change to FDV301 due to BSH111 EOL HDMI_R_D1+ 4 D1_shield 23
HDMI_HPD HDMI_R_D2- 3 D1+ GND 22
4 3 HDMI_HPD <24,7> D2- GND
VGA_DVI_TXD1+ HDMI_R_D1+ 2 21
4 3 HDMI_R_D2+ 1 D2_shield GND 20
WCM-2012-900T_0805 D2+ GND
TYCO_2041343-1~D
EMI@ L11 RP1

VGA_DVI_TXD2- 1 2 HDMI_R_D2- 1 8 UMA_HDMI_DATA
1 2 +3VS
2 7 UMA_HDMI_CLK
3 6 HDMI_SCLK
+HDMI_5V_OUT
VGA_DVI_TXD2+ 4 3 HDMI_R_D2+ 4 5 HDMI_SDATA
4 3
WCM-2012-900T_0805 4.7K_8P4R_5%
B B
A A

HDMI Conn./CEC
0.3
LA-9869P
5 4 3 2 1
A B C D E
U1A
HUDSON-3
APU_PCIE_RST#_R AE2 AF3
Near FCH
LPC_RST#_R AD5 PCIE_RST# PCICLK0 AF1
PCI CLKS
A_RST# PCICLK1/GPO36 AF5 PCI_CLK1 <26>
1 2 UMI_MTX_FRX_P0 AE30 PCICLK2/GPO37 AG2
PCIE_RST# is for PCIE devices on APU
C202 0.1U_0402_16V7K
<5> UMI_MTX_C_FRX_P0 1 2 UMI_MTX_FRX_N0 AE32 UMI_TX0P PCICLK3/GPO38 AF6 PCI_CLK3 <26>
C203 0.1U_0402_16V7K
<5> UMI_MTX_C_FRX_N0 1 2 AD33 UMI_TX0N PCICLK4/14M_OSC/GPO39 PCI_CLK4 <26>
C204 0.1U_0402_16V7K UMI_MTX_FRX_P1 APU_PCIE_RST#_R R225 1 2 33_0402_5%
<5> UMI_MTX_C_FRX_P1 UMI_TX1P APU_PCIE_RST# <12,28,30>
2
C209 1 2 0.1U_0402_16V7K UMI_MTX_FRX_N1 AD31 AB5
<5> UMI_MTX_C_FRX_N1 1 2 UMI_MTX_FRX_P2 AD28 UMI_TX1N PCIRST#
C210 0.1U_0402_16V7K 1 R223
<5> UMI_MTX_C_FRX_P2 1 2 UMI_MTX_FRX_N2 AD29 UMI_TX2P
C211 0.1U_0402_16V7K C221 100K_0402_5%
<5> UMI_MTX_C_FRX_N2 1 2 UMI_MTX_FRX_P3 AC30 UMI_TX2N AJ3
C213 0.1U_0402_16V7K @
<5> UMI_MTX_C_FRX_P3 1 2 UMI_MTX_FRX_N3 AC32 UMI_TX3P AD0/GPIO0 AL5
C212 0.1U_0402_16V7K 150P_0402_50V8J
<5> UMI_MTX_C_FRX_N3
1
UMI_TX3N AD1/GPIO1 AG4 2
1 AB33 AD2/GPIO2 AL6 1
<5> UMI_FTX_C_MRX_P0 AB31 UMI_RX0P AD3/GPIO3 AH3
<5> UMI_FTX_C_MRX_N0 UMI_RX0N AD4/GPIO4
PCI EXPRESS INTERFACES

AB28 AJ5 A_RST# is for LPC devices
<5> UMI_FTX_C_MRX_P1 AB29 UMI_RX1P AD5/GPIO5 AL1
<5> UMI_FTX_C_MRX_N1 Y33 UMI_RX1N AD6/GPIO6 AN5 LPC_RST#_R R226 1 2 33_0402_5%
<5> UMI_FTX_C_MRX_P2 UMI_RX2P AD7/GPIO7 LPC_RST# <34>
2
Y31 AN6
<5> UMI_FTX_C_MRX_N2 Y28 UMI_RX2N AD8/GPIO8 AJ1 1 R224
<5> UMI_FTX_C_MRX_P3 Y29 UMI_RX3P AD9/GPIO9 AL8 C222 100K_0402_5%
<5> UMI_FTX_C_MRX_N3 UMI_RX3N AD10/GPIO10 AL3 @
R220 1 2 590_0402_1% PCIE_CALRP AF29 AD11/GPIO11 AM7 150P_0402_50V8J
1
R221 1 2 2K_0402_1% PCIE_CALRN AF31 PCIE_CALRP AD12/GPIO12 AJ6 2
+PCIE_VDDR_FCH PCIE_CALRN AD13/GPIO13 AK7
V33 AD14/GPIO14 AN8
V31 GPP_TX0P AD15/GPIO15 AG9
W30 GPP_TX0N AD16/GPIO16 AM11
W32 GPP_TX1P AD17/GPIO17 AJ10 +3VS
AB26 GPP_TX1N AD18/GPIO18 AL12
AB27 GPP_TX2P AD19/GPIO19 AK11 VGA@ UMA@
AA24 GPP_TX2N AD20/GPIO20 AN12 1 2 GPIO30 1 2
AA23 GPP_TX3P AD21/GPIO21 AG12 R337 10K_0402_5% R332 10K_0402_5%
GPP_TX3N AD22/GPIO22 AE12 VGA@
AA27 AD23/GPIO23 AC12 PCI_AD23 <26> 1 2 GPIO31 1 UMA@ 2
AA26 GPP_RX0P AD24/GPIO24 AE13 PCI_AD24 <26>
Strap R340 10K_0402_5% R339 10K_0402_5%
W27 GPP_RX0N AD25/GPIO25 AF13 PCI_AD25 <26>
V27 GPP_RX1P AD26/GPIO26 AH13 PCI_AD26 <26>
PCI INTERFACE
V26 GPP_RX1N AD27/GPIO27 AH14 PCI_AD27 <26>
W26 GPP_RX2P AD28/GPIO28 AD15 VRAM_SEL
W24 GPP_RX2N AD29/GPIO29 AC15 GPIO30
W23 GPP_RX3P AD30/GPIO30 AE16 GPIO31
GPP_RX3N AD31/GPIO31 Function GPIO30 GPIO31
AN3
CBE0# AJ8 +3VS
CBE1# PowerXpress 0 0
AN10
2 R228 1 2 2K_0402_1% CLK_CALRN F27 CBE2# AD12 2
+1.1VS_CKVDD CLK_CALRN CBE3# Reserved 0 1
AG10
FRAME#
2
AK9 Discrete 1 0
DEVSEL# AL10 RC95
Input from external clock generator G30 IRDY# AF10
PCIE_RCLKP TRDY# 10K_0402_5% UMA 1 1
NC for internal clock generator G28 AE10
SS PCIE_RCLKN PAR AH1
@
1
R26 STOP# AM9
<7> APU_DISP_CLK T26 DISP_CLKP PERR# AH8 VRAM_SEL
APU DISP <7> APU_DISP_CLK# DISP_CLKN SERR# AG15
H33 REQ0# AG13
NSS DISP2_CLKP REQ1#/GPIO40
2
clock no test point H31 AF15 X76
DISP2_CLKN REQ2#/CLK_REQ8#/GPIO41 AM17 RC99
T24
INT 15K PU REQ3#/CLK_REQ5#/GPIO42 AD16
<7> APU_CLK T23 APU_CLKP GNT0# AD13
H:1G 10K_0402_5%
APU <7> APU_CLK# APU_CLKN GNT1#/GPO44 AD21 L:900M @
1
CLK_PCIE_VGA J30 GNT2#/SD_LED/GPO45 AK17
For DIS <12> CLK_PCIE_VGA
CLK_PCIE_VGA# K29 SLT_GFX_CLKP GNT3#/CLK_REQ7#/GPIO46 AD19
+RTCBATT
<12> CLK_PCIE_VGA# SLT_GFX_CLKN INT 8.2K PU CLKRUN# AH9
LOCK#
1
H27
H28 GPP_CLK0P AF18
GPP_CLK0N INTE#/GPIO32 AE18 DH1
J27 INTF#/GPIO33 AC16 +RTCBATT_D BAS40-04_SOT23-3
K26 GPP_CLK1P INT 8.2K PU INTG#/GPIO34 AD18
GPP_CLK1N INTH#/GPIO35
2
0.1U_0402_10V7K
F33
WLAN <28> CLK_WLAN F31 GPP_CLK2P +3VL
1
CLOCK GENERATOR
<28> CLK_WLAN# GPP_CLK2N
C253
B25 LPC_CLK0 R255 1 EMI@ 2 22_0402_5%
SS E33 LPCCLK0 CLK_PCI_EC <26,34>
<30> CLK_LAN GPP_CLK3P
E31 D25 LPC_CLK1 R258 1 EMI@ 2 22_0402_5%
LAN <30> CLK_LAN# GPP_CLK3N LPCCLK1 D27 CLK_PCI_DDR <26> 2
M23 LAD0 C28 LPC_AD0 <34>
3 M24 GPP_CLK4P LAD1 A26 LPC_AD1 <34> 3
GPP_CLK4N LAD2 LPC_AD2 <34>
Place close to Y2 A29 LPC_AD3 <34>
M27 LAD3 A31
LPC
M26 GPP_CLK5P LFRAME# B27 LPC_FRAME# <34>

1 @ 2 32K_X1 GPP_CLK5N LDRQ0# AE27
<29> FCH_RTCX1_R N25 LDRQ1#/CLK_REQ6#/GPIO49 AE19
R207 0_0402_5% INT 8.2K PU SERIRQ <34>
N26 GPP_CLK6P SERIRQ/GPIO48
GPP_CLK6N DMA active. The FCH drives the DMA_ACTIVE# to
R23 APU to notify DMA activity. This will cause the APU
1 2 R24 GPP_CLK7P G25
<29> FCH_X1_R
@ 25M_X1
GPP_CLK7N DMA_ACTIVE# DMA_ACTIVE# <7> to reestablish the UMI link quicker.
R208 0_0402_5% E28 APU_PROCHOT#
N27 PROCHOT# E26 APU_PROCHOT# <7>
APU_PWRGD
R27 GPP_CLK8P APU_PG G26 APU_PWRGD <45,7>
Place close to Y1 GPP_CLK8N LDT_STP# F26 APU_RST#
APU
APU_RST# APU_RST# <7>

APU_PG/APU_RST#/LDT_STP# : OD pin
J26 DMA_ACTIVE# : IN/OD, 0.8V threshold
C220 1 2 27P_0402_50V8J 14M_25M_48M_OSC H7
S5_CORE_EN T35 PROCHOT# : IN, 0.8V threshold
NOGCLK@ 1 F1 1 @ 2 LDT_STP : No use, NC
RTCCLK RTC_CLK <26,34>
25MHZ 12PF X3G025000DK1H-X
F3 R260 0_0402_5%
25M_X1 C31 INTRUDER_ALERT# E6 +RTCVCC_R
1 25M_X1 VDDBT_RTC_G
NOGCLK@
Y3
2 G2 32K_X1
S5 PLUS
GND 32K_X1
R229 25M_X2 C33 +RTCBATT_D
1M_0402_5% 25M_X2 +RTCVCC
4 NOGCLK@ G4 32K_X2 20 mils R271 R277
GND 32K_X2 1 2 1 2
120_0402_5% 120_0402_5%
3
1 1
NOGCLK@ 2180755042A13HUDSON_FCBGA656 BOLTONR1@ C250 C252 1
1
1 2 27P_0402_50V8J 3 JCMOS C295
C230 @
4 0.1U_0402_16V4Z 2 2 0.1U_0402_16V4Z 4
2
1U_0402_6.3V6K 2
NOGCLK@ C248 1 2 18P_0402_50V8J 32K_X1 CMOS Setting
Place under DDR
1
Y2 Door
R230 32.768KHZ_12.5P_1TJF125DP1A000D
20M_0402_5% NOGCLK@
NOGCLK@ Security Classification Compal Secret Data Compal Electronics, Inc.
1

2
1 2 32K_X2 @EMI@ C507

NOGCLK@ C249 18P_0402_50V8J 25M_X1 2 1 1 2 @EMI@
Hudson-M3-UMI/PCI/CLOCK/LPC/RTC
Change C248/C249 to 18P 10_0402_5% R116
10P_0402_50V8J Custom 0.3
for RTC issue on pre-MP DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
LA-9869P
A B C D E
A B C D E
GEVENT#2~22 INT 10K PU

U1D
PCIE_RST2# is for PCIE devices on FCH
HUDSON-3
T50 AB6 G8
USB MISC
R2 PCIE_RST2#/GEVENT4# USBCLK/14M_25M_48M_OSC
+3VS +3VALW_FCH <34> EC_LID_OUT# RI#/GEVENT22#
W7 B9 USB_RCOMP R329 1 2 11.8K_0402_1%
T3 SPI_CS3#/GBE_STAT1/GEVENT21# USB_RCOMP
<34> SLP_S3# W2 SLP_S3# H1
<34> SLP_S5# SLP_S5# INT 15K PD USB_FSD1P/GPIO186
2
J4 H3
<34> PBTN_OUT# N7 PWR_BTN# USB_FSD1N
R283 FCH_PWRGD Hudson-M2/M3
2
<34> FCH_PWRGD PWR_GOOD
G
10K_0402_5% INT 15K PD H6
OHCI (DEV-20, FUN-5)
USB 1.1
TEST0 T9 USB_FSD0P/GPIO185 H5
ACPI / WAKE UP EVENTS

TEST1 T10 TEST0 USB_FSD0N
1
3 1 HDMI_HPD_FCH TEST2 V9 TEST1/TMS H10
<22,7> HDMI_HPD TEST2 USB_HSD13P G10
D
S AE22 USB_HSD13N
1
<34> GATEA20 GA20IN/GEVENT0# INT 8.2K PU Hudson-M2 1
Q30 K10
2N7002KW_SOT323-3 AG19 USB_HSD12P J12 OHCI (DEV-22, FUN-0)
<34> KB_RST# KBRST#/GEVENT1# INT 8.2K PU USB_HSD12N
<34> EC_SCI#
R9
PME#/GEVENT3#
EHCI (DEV-22, FUN-2)
C26 G12
<34> EC_SMI# T5 LPC_SMI#/GEVENT23# USB_HSD11P F12 USB20_P11 <31>
LPC_PD#/GEVENT5# USB_HSD11N USB20_N11 <31> USB 3.0-Right 2 Hudson-M3
U4
K1 SYS_RESET#/GEVENT19# K12 XHCI (DEV-16, FUN-0)
<30> FCH_PCIE_WAKE# WAKE#/GEVENT8# USB_HSD10P USB20_P10 <31>
V7
IR_RX1/GEVENT20# USB_HSD10N
K13
USB20_N10 <31> USB 3.0-Right 1 XHCI (DEV-16, FUN-1)
R10
1 2 <7> H_THERMTRIP# AF19 THRMTRIP#/SMBALERT#/GEVENT2# B11
+3VS WD_PWRGD
@ESD@ R279 10K_0402_5% WD_PWRGD USB_HSD9P D11
1 2 FCH_PWRGD U2 USB_HSD9N
<34> EC_RSMRST# RSMRST# E10
C505 180P_0402_50V8J
AG24 USB_HSD8P F10
AE24 CLK_REQ4#/SATA_IS0#/GPIO64 USB_HSD8N
<30> CLKREQ_LAN# CLK_REQ3#/SATA_IS1#/GPIO63 Hudson-M2/M3
AE26 C10
AF22 SMARTVOLT1/SATA_IS2#/GPIO50INT 8.2K PU USB_HSD7P A10 OHCI (DEV-19, FUN-0)
CLK_REQ0#/SATA_IS3#/GPIO60 USB_HSD7N
AH17 EHCI (DEV-19, FUN-2)
USB 2.0
AG18 SATA_IS4#/FANOUT3/GPIO55 H9
AF24 SATA_IS5#/FANIN3/GPIO59 USB_HSD6P G9
<32> FCH_SPKR AD26 SPKR/GPIO66 USB_HSD6N
FCH_SCLK0
GPIO
<10,11,28> FCH_SCLK0 FCH_SDATA0 AD25 SCL0/GPIO43 A8
SM Bus 0-->S0 PWR domain <10,11,28> FCH_SDATA0 SDA0/GPIO47 USB_HSD5P
FCH_SCLK1 T7 C8
SM Bus 1-->S5 PWR domain <36> FCH_SCLK1
FCH_SDATA1 R7 SCL1/GPIO227 USB_HSD5N
<36> FCH_SDATA1 SDA1/GPIO228
(for ASF device only) <28> CLKREQ_WLAN#
AG25
CLK_REQ2#/FANIN4/GPIO62 USB_HSD4P
F8
USB20_P4 <20>
AG22 E8 Touch
J2 CLK_REQ1#/FANOUT4/GPIO61 USB_HSD4N USB20_N4 <20>
AG26 IR_LED#/LLB#/GPIO184 INT 10K PU C6
For DIS <14,43,46> VGA_PWRGD
V8 SMARTVOLT2/SHUTDOWN#/GPIO51 USB_HSD3P A6 USB20_P3 <28>
DDR3_RST#/GEVENT7#/VGA_PD USB_HSD3N USB20_N3 <28> WLAN (BT) Hudson-M2/M3
W8
<30> LAN_EN Y6 GBE_LED0/GPIO183INT 10K PU C5 OHCI (DEV-18, FUN-0)
SPI_HOLD#/GBE_LED1/GEVENT9# USB_HSD2P USB20_P2 <33>
VGA_PD: Support CRT power saving HDMI_HPD_FCH V10
GBE_LED2/GEVENT10# USB_HSD2N
A5
USB20_N2 <33> Card reader EHCI (DEV-18, FUN-2)
AA8
L: MLDAC power on R295 1 2 0_0402_5% AF25 GBE_STAT0/GEVENT11# C1 <Support Wakeup>
<13> CLKREQ_PEG# CLK_REQG#/GPIO65/OSCIN/IDLEEXIT# USB_HSD1P C3 USB20_P1 <20>
H: MLDAC power off USB_HSD1N USB20_N1 <20> Int. Camera
For DIS R129 2 @ 1 100K_0402_5%
M7 E1
R8 BLINK/USB_OC7#/GEVENT18# USB_HSD0P E3 USB20_P0 <30>
ODD_DA#_FCH USB-Left 1
2
T1 USB_OC6#/IR_TX1/GEVENT6# USB_HSD0N USB20_N0 <30> 2
USB OC
P6 USB_OC5#/IR_TX0/GEVENT17# C16 USBSS_CALRP R330 1 2 1K_0402_1%
<28> ODD_PLUGIN# F5 USB_OC4#/IR_RX0/GEVENT16# USBSS_CALRP A16 USBSS_CALRN R334 1 2 1K_0402_1%
+FCH_VDD_11_SSUSB_S
USB_OC#2 P5 USB_OC3#/AC_PRES/TDO/GEVENT15# USBSS_CALRN
USB_OC2# is for right USB2.0 ports <30,34> USB_OC#2 USB_OC2#/TCK/GEVENT14#
USB_CHG_OC# is for right USB3.0 ports USB_CHG_OC# J7 A14
<31,34> USB_CHG_OC# T8 USB_OC1#/TDI/GEVENT13# USB_SS_TX3P C14
USB_OC0# is for right USB3.0 ports USB_OC#0
<31,34> USB_OC#0 USB_OC0#/SPI_TPM_CS#/TRST#/GEVENT12# USB_SS_TX3N
For ESD request C12
USB_SS_RX3P A12
@ESD@ USB_SS_RX3N
1 2 PXS_RST# R320 1 EMI@ 2 33_0402_5% HDA_BITCLK AB3 D15
<32> AZ_BITCLK_HD AZ_BITCLK USB_SS_TX2P B15
C503 180P_0402_50V8J R321 1 2 33_0402_5% HDA_SDOUT AB1
1 2 <32> AZ_SDOUT_HD AA2 AZ_SDOUT USB_SS_TX2N
ODD_DA#_FCH
HD AUDIO
<32> AZ_SDIN0_HD AZ_SDIN1_HD Y5 AZ_SDIN0/GPIO167 E14
C504 180P_0402_50V8J Hudson-M3
Y3 AZ_SDIN1/GPIO168 USB_SS_RX2P F14
USB 3.0
ESD@ AZ_SDIN2_HD INT 50K PD
AZ_SDIN3_HD Y1 AZ_SDIN2/GPIO169 USB_SS_RX2N XHCI (DEV-16, FUN-0)
R322 1 2 33_0402_5% HDA_SYNC AD6 AZ_SDIN3/GPIO170 F15 XHCI (DEV-16, FUN-1)
<32> AZ_SYNC_HD AE4 AZ_SYNC USB_SS_TX1P G15 USB30_TX1P <31>
R323 1 2 33_0402_5% HDA_RST#
<32> AZ_RST_HD# AZ_RST# USB_SS_TX1N USB30_TX1N <31>
H13
USB 3.0-Right 2
USB_SS_RX1P G13 USB30_RX1P <31>
+3VALW_FCH USB_SS_RX1N USB30_RX1N <31>
RP12 T26 K19 J16
1 8 J19 PS2_DAT/SDA4/GPIO187 USB_SS_TX0P H16 USB30_TX0P <31>
H_THERMTRIP# INT 10K PU
2 7 J21 PS2_CLK/CEC/SCL4/GPIO188 USB_SS_TX0N USB30_TX0N <31>
USB_OC#0
3 6 USB_CHG_OC# SPI_CS2#/GBE_STAT2/GPIO166 J15
4 5 USB_OC#2 USB_SS_RX0P K15 USB30_RX0P <31> USB 3.0-Right 1
USB_SS_RX0N USB30_RX0N <31>
10K_8P4R_5% D21 RP8
C20 PS2KB_DAT/GPIO189 H19 GPIO193 1 8
PXS_RST# D23 PS2KB_CLK/GPIO190 SCL2/GPIO193 G19 GPIO194 2 7
For DIS <12> PXS_RST#
PXS_PWREN C22 PS2M_DAT/GPIO191 INT 10K PU EMBEDDED CTRL SDA2/GPIO194 G22 GPIO195 3 6
<14,46,47> PXS_PWREN PS2M_CLK/GPIO192 SCL3_LV/GPIO195 G21 4 5
GPIO196
+3VALW_FCH SDA3_LV/GPIO196 E22
EC_PWM0/EC_TIMER0/GPIO197 H22 10K_8P4R_5%
2 @ 1 EC_LID_OUT# F21 EC_PWM1/EC_TIMER1/GPIO198 J22
KSO_0/GPIO209 EC_PWM2/EC_TIMER2/WOL_EN/GPIO199 EC_PWM2 <26> Strap
R282 100K_0402_5% E20 INT 10K PU H21
1 2 FCH_PCIE_WAKE# F20 KSO_1/GPIO210 EC_PWM3/EC_TIMER3/GPIO200
R281 10K_0402_5% A22 KSO_2/GPIO211 K21
3 3
1 2 FCH_SCLK1 E18 KSO_3/GPIO212 KSI_0/GPIO201 K22
KSO_4/GPIO213 KSI_1/GPIO202 For PCIE device reset on FS1
R288 2.2K_0402_5% A20 F22
1 2 FCH_SDATA1 J18 KSO_5/GPIO214 KSI_2/GPIO203 F24
(GFX,GLAN,WLAN,LVDS Travis)
R289 2.2K_0402_5% H18 KSO_6/GPIO215 KSI_3/GPIO204 E24
G18 KSO_7/GPIO216 INT 10K PU KSI_4/GPIO205 B23
B21 KSO_8/GPIO217 INT 10K PU KSI_5/GPIO206 C24
K18 KSO_9/GPIO218 KSI_6/GPIO207 F18
For FCH internal debug use KSO_10/GPIO219 KSI_7/GPIO208
1 @ 2 TEST0 D19
R290 2.2K_0402_5% A18 KSO_11/GPIO220
1 @ 2 TEST1 C18 KSO_12/GPIO221
R292 2.2K_0402_5% B19 KSO_13/GPIO222
1 @ 2 TEST2 B17 KSO_14/XDB0/GPIO223
R293 2.2K_0402_5% A24 KSO_15/XDB1/GPIO224
D17 KSO_16/XDB2/GPIO225
1 2 PXS_PWREN KSO_17/XDB3/GPIO226
R296 10K_0402_5% For DIS
2180755042A13HUDSON_FCBGA656 BOLTONR1@
+3VS
1 2 FCH_SCLK0
R286 2.2K_0402_5%
1 2 FCH_SDATA0
R287 2.2K_0402_5% +3VS +3VS
1 2 CLKREQ_WLAN#
R291 8.2K_0402_5% For DIS
2
1 2 CLKREQ_LAN#
R284 8.2K_0402_5% Q5530A R311
2N7002KDWH_SOT363-6
Place R425 and C363
10K_0402_5%
2
PXS_PWREN 6 1 close to FCH for ESD @
G
Q32
1
Q5530B +3VALW
2N7002KDWH_SOT363-6 ODD_DA#_FCH 1 @ 2 ODD_DA#_Q 1 3
For DIS ODD_DA# <28>
2
4 3 10K_0402_5% 2 1 R216 R425 0_0402_5%
S
1 @ 2 PXS_PWREN 2N7002KW_SOT323-3
R297 10K_0402_5% @
4 4
1 2 EC_RSMRST# EC_PXCONTROL
EC_PXCONTROL <34>
5
R280 2.2K_0402_5%
1 @ 2 HDA_BITCLK
R324 10K_0402_5%
1 @ 2 PXS_RST#
R269 1K_0402_5%
RP10
1 8 AZ_SDIN1_HD
2 7 AZ_SDIN3_HD
3 6 AZ_SDIN2_HD Security Classification Compal Secret Data Compal Electronics, Inc.
4 5 AZ_SDIN0_HD 2013/01/22 2014/01/21 Title
10K_8P4R_5%
Hudson-M3-ACPI/USB/EC
@ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.3
LA-9869P
A B C D E
A B C D E
U1B HDMI_EN# (Internal 8.2K PU)
HUDSON-3 R443 1K_0402_1% HDMI_EN#

AK19 AL14 HDMI_EN# 2 1
H L
<28> SATA_FTX_DRX_P0 AM19 SATA_TX0P SD_CLK/SCLK_0/GPIO73 AN14 SPK_DET
<28> SATA_FTX_DRX_N0 SATA_TX0N SD_CMD/SLOAD_0/GPIO74 AJ12 SPK_DET <33>
SD_CD#/GPIO75 Non-HDMI
HDD AL20 INT 8.2K PU AH12 SKU HDMI SKU
<28> SATA_FRX_C_DTX_N0 AN20 SATA_RX0N SD_WP/GPIO76 AK13 SKU
<28> SATA_FRX_C_DTX_P0 SATA_RX0P SD_DATA0/SDATI_0/GPIO77
SD CARD
AM13
AN22 SD_DATA1/SDATO_0/GPIO78 AH15
<28> SATA_FTX_DRX_P1 AL22 SATA_TX1P SD_DATA2/GPIO79 AJ14
<28> SATA_FTX_DRX_N1 SATA_TX1N SD_DATA3/GPIO80
1
ODD AH20 AC4 1
<28> SATA_FRX_C_DTX_N1 SATA_RX1N GBE_COL For EMI request
AJ20 AD3
<28> SATA_FRX_C_DTX_P1 SATA_RX1P GBE_CRS AD9
AJ22 GBE_MDCK W10 R118 C508
AH22 SATA_TX2P GBE_MDIO AB8 FCH_SPI_CLK_R 2 1 1 2
SATA_TX2N GBE_RXCLK AH7 10_0402_5%
AM23 GBE_RXD3 AF7 EMI@ 10P_0402_50V8J
AK23 SATA_RX2N GBE_RXD2 AE7 EMI@
SATA_RX2P GBE_RXD1 AD7
AH24 GBE_RXD0 AG8
AJ24 SATA_TX3P GBE_RXCTL/RXDV AD1
SATA_TX3N GBE_RXERR AB7
AN24 GBE_TXCLK AF9
GBE LAN
AL24 SATA_RX3N GBE_TXD3 AG6
SATA_RX3P GBE_TXD2 If an SPI ROM is shared between FCH
AE8
AL26 GBE_TXD1 AD8 and the Embedded Controller, a 10-k
SATA_TX4P GBE_TXD0
AN26
SATA_TX4N GBE_TXCTL/TXEN
AB9 pull-up resistor to +3.3V_S5 is installed
AC2
SERIAL ATA
AJ26 GBE_PHY_PD AA7
AH26 SATA_RX4N GBE_PHY_RST# W9 GBE_PHY_INTR 1 2
SATA_RX4P GBE_PHY_INTR +3VALW_FCH
R352 10K_0402_5%
AN29 +3VALW_FCH
AL28 SATA_TX5P V6 FCH_SPI_MISO
SATA_TX5N SPI_DI/GPIO164 V5 FCH_SPI_MOSI 885@
AK27
INT 10K PU SPI_DO/GPIO163 V3 FCH_SPI_CLK_R 1 2 FCH_SPI_CLK FCH_SPI_CS1# 1 2
@
SATA_RX5N SPI_CLK/GPIO162
SPI ROM
AM27 T6 FCH_SPI_CS1# R111 0_0402_5% R113 10K_0402_5%
SATA_RX5P SPI_CS1#/GPIO165 V1
AL29 ROM_RST#/SPI_WP#/GPIO161
AN31 NC6
NC7 L30
AL31 VGA_RED UMA_CRT_R <21> +3VS
AL33 NC8
2 NC9 L32 2
AH33 VGA_GREEN UMA_CRT_G <21> 1 2
UMA_CRT_DATA
AH31 NC10 R455 2.2K_0402_5%
NC11 M29 UMA_CRT_CLK 1 2
AJ33 VGA_BLUE UMA_CRT_B <21>
BIOS NC12
R462 2.2K_0402_5%
SM_EN SPK TYPE AJ31
VGA DAC
SETUP NC13 M28
VGA_HSYNC/GPO68 N30 UMA_CRT_HSYNC <21>
VGA_VSYNC/GPO69 UMA_CRT_VSYNC <21> 1 2
S&M HARMAN UMA_CRT_R
M33 R367 150_0402_1%
1 OPTION KARDON 2 1 SATA_CALRP AF28 VGA_DDC_SDA/GPO70 N32 UMA_CRT_DATA <21> UMA_CRT_G 1 2
SATA_CALRP VGA_DDC_SCL/GPO71 UMA_CRT_CLK <21>
R336 1K_0402_1% R368 150_0402_1%
2 1 SATA_CALRN AF27 UMA_CRT_B 1 2
+AVDD_SATA SATA_CALRN
NO NO HARMAN R130 931_0402_1% K31 VGA_DAC_RSET 1 2 R369 150_0402_1%
0 VGA_DAC_RSET R366 715_0402_1%
AD22
SATA_ACT#/GPIO67 V28
AUX_VGA_CH_P V29 ML_VGA_AUXP <7>
+3VS AF21 AUX_VGA_CH_N ML_VGA_AUXN <7>
VGA MAINLINK
SATA_X1 U28 AUXCAL 1 2
AUXCAL +VDDAN_11_ML
R364 100_0402_1%
1
T31 ML_VGA_TXP0
ML_VGA_L0P T33 ML_VGA_TXP0 <7>
R439 ML_VGA_TXN0
AG21 ML_VGA_L0N T29 ML_VGA_TXN0 <7>
10K_0402_5% ML_VGA_TXP1
SATA_X2 ML_VGA_L1P T28 ML_VGA_TXN1 ML_VGA_TXP1 <7> +FCH_VDDAN_33_DAC_R
269@
ML_VGA_L1N R32 ML_VGA_TXP2 ML_VGA_TXN1 <7>
2
ML_VGA_L2P R30 ML_VGA_TXP2 <7> 1 2

SM_EN ML_VGA_TXN2 FCH_CRT_HPD
ML_VGA_L2N P29 ML_VGA_TXN2 <7>
ML_VGA_TXP3 R365 10K_0402_5%
ML_VGA_L3P ML_VGA_TXP3 <7>
1
P28 ML_VGA_TXN3
ML_VGA_L3N ML_VGA_TXN3 <7>
R438
10K_0402_5% PW_CLEAR# RP9
C29 FCH_CRT_HPD GPIO175 1 8
3 ML_VGA_HPD/GPIO229 FCH_CRT_HPD <7> 2 7 3
GPIO178
2
JPW Place JPW GPIO176 3 6

@ AH16 N2 GPIO175 GPIO177 4 5
under DDR Door AM15 FANOUT0/GPIO52 VIN0/GPIO175
2
AJ16 FANOUT1/GPIO53 HW MONITOR M3 GPIO176 10K_8P4R_5%

FANOUT2/GPIO54 VIN1/GPIO176
RP11 PW_CLEAR# AK15 L2 GPIO177
1 8 AN16 FANIN0/GPIO56 VIN2/SDATI_1/GPIO177
T20 FANIN1/GPIO57
2 7 GPIO172 AL16 N4 GPIO178
3 6 GPIO182 FANIN2/GPIO58 VIN3/SDATO_1/GPIO178
4 5 GPIO181 P1 SLP_CHG_CB1
ODD_PWR K6 VIN4/SLOAD_1/GPIO179
<37> ODD_PWR TEMPIN0/GPIO171 P3 SLP_CHG_CB0
10K_8P4R_5%
VIN5/SCLK_1/GPIO180
GPIO172 K5 M1 GPIO181
TEMPIN1/GPIO172 VIN6/GBE_STAT3/GPIO181
M5 GPIO182
SM_EN K3 VIN7/GBE_LED3/GPIO182
+3VALW_FCH TEMPIN2/GPIO173 +3VALW_FCH
AG16
1 2 FCH_ALERT# M6 NC1 AH10 SLP_CHG_CB0 1 @ 2
TEMPIN3/TALERT#/GPIO174 NC2 A28 <31> SLP_CHG_CB0
R437 10K_0402_5% R134 10K_0402_5%
NC3 G27 SLP_CHG_CB1 1 @ 2
NC4 L4 <31> SLP_CHG_CB1
R151 10K_0402_5%
NC5
+3VALW_FCH
4M Byte 2180755042A13HUDSON_FCBGA656 BOLTONR1@
C498 U13
1 2 8 4
VCC VSS
0.1U_0402_16V4Z 3
4 W 4
7
HOLD SA00003K800
R88 2 885@ 1 33_0402_5% FCH_SPI_CS1# 1
<34> EC_CS0# S SA00004LI00
R107 2 885@ 1 33_0402_5% FCH_SPI_CLK 6
<34> EC_SCK C
R110 2 885@ 1 33_0402_5% FCH_SPI_MOSI 5 2 FCH_SPI_MISO 2 885@ 1
<34> EC_SDI D Q 33_0402_5% R106
EC_SDIO <34> Security Classification Compal Secret Data Compal Electronics, Inc.
MX25L3206EM2I-12G_SO8 2013/01/22 2014/01/21 Title
45@
Hudson-M3-SATA/GBE/HWM
Socket PN: SP07000F500/SP07000H900 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Custom 0.3
LA-9869P
A B C D E
A B C D E
STRAP PINS
PCI_CLK1 PCI_CLK3 PCI_CLK4 LPC_CLK0 LPC_CLK1 EC_PWM2 RTC_CLK
PULL ALLOW ENABLE NON_FUSION EC CLKGEN LPC ROM S5 PLUS

HIGH PCIE GEN2 DEBUG CLOCK MODE ENABLED ENABLED (INTERNAL MODE
1 STRAP 10K PULL-UP) DISABLED 1
DEFAULT DEFAULT DEFAULT
PULL FORCE DISABLE FUSION EC CLKGEN SPI ROM S5 PLUS

LOW PCIE GEN1 DEBUG CLOCK DISABLED DISABLE MODE
STRAP MODE ENABLED
DEFAULT DEFAULT DEFAULT DEFAULT
+3VS +3VS +3VALW_FCH +3VALW_FCH

1
1
R231 R241 R238 R240
@
10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
2
2
PCI_CLK1
<23> PCI_CLK1
PCI_CLK3
<23> PCI_CLK3
PCI_CLK4
<23> PCI_CLK4
2 CLK_PCI_EC 2
<23,34> CLK_PCI_EC
CLK_PCI_DDR
<23> CLK_PCI_DDR
EC_PWM2
<24> EC_PWM2
RTC_CLK
<23,34> RTC_CLK
1
1
R233 R234 R237 R239
10K_0402_5% 10K_0402_5% 10K_0402_5% 2.2K_0402_5%

2
DEBUG STRAPS
FCH HAS 15K INTERNAL PU-UP FOR PCI_AD[27:23]
+3VALW
PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23

3 3
USE PCI DISABLE USE FC USE DEFAULT DISABLE PCI 2 Vgs=-4.5V,Id=3A,Rds<97mohm

PULL PLL ILA PLL PCIE STRAPS MEM BOOT C523
HIGH AUTORUN 0.1U_0402_10V7K
DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT 1
3
S
R5 Q3
G
1 2 2
<37> FCH_PWR_EN#
PULL BYPASS ENABLE BYPASS USE EEPROM ENABLE PCI
PCI PLL ILA FC PLL PCIE STRAPS MEM BOOT 47K_0402_5% 2 AO3413_SOT23 D
LOW
1
AUTORUN C521 +3VALW_FCH
0.01U_0402_25V7K
1
PCI_AD27
<23> PCI_AD27
PCI_AD26
<23> PCI_AD26
PCI_AD25
<23> PCI_AD25
PCI_AD24
<23> PCI_AD24
PCI_AD23
<23> PCI_AD23
1
R247 R248 R249 R250 R251

4 @ @ @ @ @ 4
2.2K_0402_5% 2.2K_0402_5% 2.2K_0402_5% 2.2K_0402_5% 2.2K_0402_5%
2

Check with FAE whether can delete or reserve test point or not Issued Date 2013/01/22 Deciphered Date 2014/01/21 Title
Hudson-M3-STRAP
Custom 0.3
LA-9869P
A B C D E
A B C D E
reserve 0ohm
reserve 0ohm for Power consumption
+3VS for Power consumption +1.1VS
L32 U1C
1007mA
1 2 +FCH_VDDAN_33_DAC_R +3VS 131mA +VCC_FCH_R 1 2
10mils
1U_0402_16V6K
1U_0402_16V6K
0.1U_0402_25V6
0.1U_0402_25V6
2.2U_0402_6.3V6M
22U_0805_6.3V6M
MBK1608221YZF_2P HUDSON-3 R28 0_0603_5% No more than two balls sharing any single via.
50mils
C285
2.2U_0402_6.3V6M
C288
0.1U_0402_16V7K
C312
C311
C334
C335
C315
C317
1 2 +VDDIO_33_PCIGP AB17 T14
VDDIO_33_PCIGP_1 VDDCR_11_1 Note: Use of a single via per ball is preferred.
22U_0805_6.3V6M
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
R20 0_0603_5% AB18 T17 1 1 1 1 1 1 1
VDDIO_33_PCIGP_2 VDDCR_11_2 U1E
C573
C266
C572
C571
1 1 AE9 T20
PCI/GPIO I/O
AD10 VDDIO_33_PCIGP_3 VDDCR_11_3 U16 C831
1 1 1 1 VDDIO_33_PCIGP_4 VDDCR_11_4
AG7 U18 @ @ 10U_0805_25V6K HUDSON-3
AC13 VDDIO_33_PCIGP_5 VDDCR_11_5 V14 2 2 2 2 2 2 2 A3 T25
2 2 VDDIO_33_PCIGP_6 VDDCR_11_6 VSS_1 VSS_65
CORE S0
1 AB12 V17 A33 T27 1
2 2 2 2 AB13 VDDIO_33_PCIGP_7 VDDCR_11_7 V20 B7 VSS_2 VSS_66 U6
AB14 VDDIO_33_PCIGP_8 VDDCR_11_8 Y17 B13 VSS_3 VSS_67 U14
AB16 VDDIO_33_PCIGP_9 VDDCR_11_9 +1.1VS_CKVDD +1.1VS D9 VSS_4 VSS_68 U17
VDDIO_33_PCIGP_10 R44 D13 VSS_5 VSS_69 U20
47mA 10milsH24 20mils 340mA VSS_6 VSS_70
+3VS +VDDPL_3.3V H26 1 @ 2 E5 U21
L30 VDDPL_33_SYS VDDAN_11_CLK_1 VSS_7 VSS_71
1U_0402_16V6K
1U_0402_16V6K
0.1U_0402_25V6
0.1U_0402_25V6
2.2U_0402_6.3V6M
20mA J25 E12 U30
10milsV22 VDDAN_11_CLK_2 VSS_8 VSS_72
C348
C320
C336
C337
C323
C620
1 2 +VDDPL_3.3V +FCH_VDDPL_33_MLDAC 1 @ 2 +VDDPL_33_DAC K24 0_0402_5% E16 U32
CLKGEN I/O
VDDPL_33_DAC VDDAN_11_CLK_3 VSS_9 VSS_73
2.2U_0402_6.3V6M
22U_0805_6.3V6M
BLM15BB221SN1D 0402 20mA R34 0_0402_5% 10milsU22 L22 E29 V11
0.1U_0402_25V6 VDDAN_11_CLK_4 1 1 1 1 1 1 VSS_10 VSS_74
C272
C273
1 @ 2 +VDDPL_33_ML M22 F7 V16

VDDPL_33_ML VDDAN_11_CLK_5 N21 F9 VSS_11 VSS_75 V18
1 1 200mA R35 0_0402_5% 10milsT22 VDDAN_11_CLK_6 VSS_12 VSS_76
VDDPL_33_SSUSB_S +FCH_VDDAN_33_DAC_R N22 F11 W4
VDDAN_33_DAC VDDAN_11_CLK_7 P22 2 2 2 2 2 2 F13 VSS_13 VSS_77 W6
For Hudson M3 USB3.0 only 20mA 10milsL18 VDDAN_11_CLK_8 VSS_14 VSS_78
+FCH_VDDPL_33_SSUSB_S F16 W25
2 2 For Hudson M2, connect to GND 17mA
VDDPL_33_SSUSB_S F17 VSS_15 VSS_79 W28
+FCH_VDDPL_33_USB_S
10mils D7 +PCIE_VDDR_FCH +1.1VS F19 VSS_16 VSS_80 Y14
VDDPL_33_USB_S 50mils
AB24 F23 VSS_17 VSS_81 Y16
43mA 10mils VDDAN_11_PCIE_1 1088mA VSS_18 VSS_82
+VDDPL_33_PCIE AH29 Y21 1 @ 2 F25 Y18
VDDPL_33_PCIE VDDAN_11_PCIE_2 VSS_19 VSS_83
1U_0402_16V6K
22U_0603_6.3V6M
0.1U_0402_25V6
1U_0402_16V6K
0.1U_0402_25V6
93mA 10mils AE25 R14 0_0805_5% F29 AA6
VDDAN_11_PCIE_3 VSS_20 VSS_84
PCI EXPRESS
+FCH_VDDAN_33_DAC_R
C328
C499
C327
C338
C339
LDO_CAP: Internally generated 1.8V +VDDPL_33_SATA AG28 AD24 G6 AA12
VDDPL_33_SATA VDDAN_11_PCIE_4 AB23 G16 VSS_21 VSS_85 AA13
supply for the RGB outputs VDDAN_11_PCIE_5 1 1 1 1 1 VSS_22 VSS_86
1 @ 2 +FCH_VDDPL_33_MLDAC For A11: Cap = 1nF @ AA22 G32 AA14
R42 0_0402_5% 1 2 M31 VDDAN_11_PCIE_6 AF26 H12 VSS_23 VSS_87 AA16
+1.1VS For A12, Cap = DNI LDO_CAP VDDAN_11_PCIE_7 VSS_24 VSS_88
2.2U_0402_6.3V6M
C298 2.2U_0402_6.3V6M AG27 @ @ H15 AA17

0.1U_0402_25V6
+3VS VDDAN_11_PCIE_8 2 2 2 2 2 VSS_25 VSS_89

C274
C275
L24 7mA 10mils H29 AA25
GROUND
L33 1 2 1 2 V21 J6 VSS_26 VSS_90 AA28
@ 1 1 @ +VDDPL_11_DAC
1 2 MBK1608221YZF_2P R37 0_0402_5% VDDPL_11_DAC +1.1VS J9 VSS_27 VSS_91 AA30
BLM15BB221SN1D 0402 +VDDAN_11_ML 60mils
AA21 +AVDD_SATA J10 VSS_28 VSS_92 AA32
220 ohm/2A 226mA VDDAN_11_SATA_1 1337mA VSS_29 VSS_93
1 @ 2 20mils Y20 1 @ 2 J13 AB25
2 2 VDDAN_11_SATA_4 VSS_30 VSS_94
1U_0402_16V6K
22U_0805_6.3V6M
0.1U_0402_25V6
1U_0402_16V6K
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
R12 0_0603_5% Y22 AB21 R40 0_0805_5% J28 AC6
VDDAN_11_ML_1 VDDAN_11_SATA_2 VSS_31 VSS_95
C128
C589
4.7U_0603_6.3V6K
C502
C500
C340
C129
C501
C151
C341
V23 AB22 J32 AC18
SERIAL ATA
MAIN LINK
VDDAN_11_ML_2 VDDAN_11_SATA_3 VSS_32 VSS_96
22U_0805_6.3V6M
1 1 1 V24 AC22 1 1 1 1 1 1 K7 AC28
2 V25 VDDAN_11_ML_3 VDDAN_11_SATA_5 AC21 K16 VSS_33 VSS_97 AD27 2
VDDAN_11_ML_4 VDDAN_11_SATA_6 AA20 K27 VSS_34 VSS_98 AE6
VDDAN_11_SATA_7 AA18 @ K28 VSS_35 VSS_99 AE15
+3VALW_FCH 2 2 2 VDDAN_11_SATA_8 AB20 2 2 2 2 2 2 L6 VSS_36 VSS_100 AE21
L31 VDDAN_11_SATA_9 AC19 L12 VSS_37 VSS_101 AE28
1 2 +FCH_VDDPL_33_SSUSB_S AB10 VDDAN_11_SATA_10 +3VALW_FCH L13 VSS_38 VSS_102 AF8
VDDIO_33_GBE_S VSS_39 VSS_103
0.1U_0402_25V6
2.2U_0402_6.3V6M
BLM15BB221SN1D 0402 10mils 59mA L15 AF12

VSS_40 VSS_104
C279
C278
AB11 N18 +VDDIO_33_S 1 @ 2 L16 AF16

VDDCR_11_GBE_S_1 VDDIO_33_S_1 VSS_41 VSS_105
0.1U_0402_25V6
0.1U_0402_25V6
2.2U_0402_6.3V6M
1 1 AA11 L19 R26 0_0402_5% L21 AF33
GBE LAN
VDDCR_11_GBE_S_2 VDDIO_33_S_2 VSS_42 VSS_106
C342
C343
C506
M18 M13 AG30
1 @ 2 AA9 VDDIO_33_S_3 V12 M16 VSS_43 VSS_107 AG32
VDDIO_GBE_S_1 VDDIO_33_S_4 1 1 1 VSS_44 VSS_108
3.3V_S5 I/O
R87 0_0402_5% AA10 V13 M21 AH5
2 2 +3VALW_FCH VDDIO_GBE_S_2 VDDIO_33_S_5 Y12 M25 VSS_45 VSS_109 AH11
L25 VDDIO_33_S_6 Y13 N6 VSS_46 VSS_110 AH18
658mA 30mils VDDIO_33_S_7 2 2 2 VSS_47 VSS_111
1 2 +VDDAN_33_USB G7 W11 N11 AH19
VDDAN_33_USB_S_1 VDDIO_33_S_8 VSS_48 VSS_112
1U_0402_16V6K
0.1U_0402_25V6
1U_0402_16V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
MBK1608221YZF_2P H8 N13 AH21
VDDAN_33_USB_S_2 VSS_49 VSS_113
C310
C134
+3VALW_FCH
C133
C135
C136
J8 +3VALW_FCH N23 AH23

L34 K8 VDDAN_33_USB_S_3 L37 N24 VSS_50 VSS_114 AH25
1 1 1 1 1 VDDAN_33_USB_S_4 10mils 5mA VSS_51 VSS_115
1 2 +FCH_VDDPL_33_USB_S K9 G24 +VDDXL_3.3V 1 2 P12 AH27
VDDAN_33_USB_S_5 VDDXL_33_S VSS_52 VSS_116
0.1U_0402_25V6
2.2U_0402_6.3V6M
0.1U_0402_25V6
2.2U_0402_6.3V6M
BLM15BB221SN1D 0402 M9 BLM15BB221SN1D 0402 P18 AJ18

VDDAN_33_USB_S_6 VSS_53 VSS_117
C510
C509
C281
C280
M10 P20 AJ28

2 2 2 2 2 N9 VDDAN_33_USB_S_7 P21 VSS_54 VSS_118 AJ29
1 1 VDDAN_33_USB_S_8 1 1 VSS_55 VSS_119
N10 P31 AK21
M12 VDDAN_33_USB_S_9 P33 VSS_56 VSS_120 AK25
N12 VDDAN_33_USB_S_10 R4 VSS_57 VSS_121 AL18
2 2 M11 VDDAN_33_USB_S_11 2 2 R11 VSS_58 VSS_122 AM21
+1.1VALW VDDAN_33_USB_S_12 R25 VSS_59 VSS_123 AM25
L38 +1.1VALW R28 VSS_60 VSS_124 AN1
140mA 10mils VSS_61 VSS_125
1 2 +VDDAN_11_USB_S U12 10mils 187mA T11 AN18
USB
+3VS VDDAN_11_USB_S_1 VSS_62 VSS_126
2.2U_0402_6.3V6M
0.1U_0402_25V6
0.1U_0402_25V6
BLM15BB221SN1D 0402 U13 N20 +VDDCR_1.1V 1 @ 2 T16 AN28

L35 VDDAN_11_USB_S_2 VDDCR_11_S_1 VSS_63 VSS_127
C303
1U_0402_16V6K
C302
C305
1U_0402_16V6K
M20 R167 0_0402_5% T18 AN33
VDDCR_11_S_2 VSS_64 VSS_128
C512
C518
1 2 +VDDPL_33_PCIE 1 1 1
2.2U_0402_6.3V6M
0.1U_0402_25V6
3 BLM15BB221SN1D 0402 N8 T21 3

1 1 VSSAN_HWM VSSPL_DAC
C294
C293
L28
K25 VSSAN_DAC K33
1 1 2 2 2 VSSXL VSSANQ_DAC
@ N28
2 2 H25 VSSIO_DAC
VSSPL_SYS R6
2 2 +1.1VALW EFUSE
L39 +1.1VALW
197mA 10mils L41
1 2 +VDDCR_1.1V_USB T12 10mils 70mA
VDDCR_11_USB_S_1
10U_0603_6.3V6M
2.2U_0402_6.3V6M
0.1U_0402_25V6
0.1U_0402_25V6
BLM15BB221SN1D 0402 T13 J24 +VDDPL_1.1V 1 2

VDDCR_11_USB_S_2 VDDPL_11_SYS_S 2180755042A13HUDSON_FCBGA656
C832
C316
2.2U_0402_6.3V6M
C304
C324
BLM15BB221SN1D 0402
0.1U_0402_25V6
+3VS
C514
C513
1 1 1 1 BOLTONR1@
L36
1 1
1 2 +VDDPL_33_SATA Connect to GND through a dedicated via
2.2U_0402_6.3V6M
0.1U_0402_25V6
BLM15BB221SN1D 0402 @
2 2 2 2
C297
C296
2 2
1 1
@ +3VALW_FCH
+FCH_VDD_11_SSUSB_S 12mA
2 2 20mils
P16
10mils
M8 +VDDAN_33_HWM 1 2
282mA @
VDDAN_11_SSUSB_S_1 VDDAN_33_HWM_S
2.2U_0402_6.3V6M
1 @ 2 +VDDAN_SSUSB M14 R43 0_0402_5% AMD reply:
0.1U_0402_25V6
VDDAN_11_SSUSB_S_2
C516
1U_0402_16V6K
0.1U_0402_25V6
0.1U_0402_25V6
C515
R90 N14 VDDAN_33_HWM_S: Please connect
VDDAN_11_SSUSB_S_3
C331
C325
C318
40mils 0_0402_5% P13 1 1 it to +3.3V_S5 directly if HWM is not used.

+FCH_VDD_11_SSUSB_S
P14 VDDAN_11_SSUSB_S_4
1 1 1 VDDAN_11_SSUSB_S_5
USB SS
2 2
2 2 2 30mils
N16
N17 VDDCR_11_SSUSB_S_1 +3VS
P17 VDDCR_11_SSUSB_S_2 VDDIO_AZ_S should be tied to
VDDCR_11_SSUSB_S_3 10mils 26mA
M17 AA4 +VDDIO_AZ 1 2 +3.3/1.5V_S5 rail if Wake on Ring
4 VDDCR_11_SSUSB_S_4 VDDIO_AZ_S R45 0_0402_5% 4
is supported
+1.1VALW POWER 1 2
L61 424mA C517 2.2U_0402_6.3V6M reserve 0ohm
2 1 1 @ 2 +VDDCR_11_SSUSB BOLTONR1@ @ 1 2
2180755042A13HUDSON_FCBGA656 for Power consumption
1U_0402_16V6K
0.1U_0402_25V6
10U_0603_6.3V6M
0.1U_0402_25V6
FBMA-L11-201209-221LMA30T_0805 R132 0_0603_5% C519 0.1U_0402_25V6

C319
C333
C155
C332
1 1 1 1
2 2 2 2 Issued Date 2013/01/22 Deciphered Date 2014/01/21 Title
Hudson-M3-POWER/GND
Custom 0.3
LA-9869P
A B C D E
A B C D E
SATA HDD Conn. SATA ODD Conn

@ JHDD
Close to JHDD
1
GND 2 SATA_FTX_C_DRX_P0 C369 1 2 0.01U_0402_25V7K
A+ SATA_FTX_DRX_P0 <25> Power Consumption
3 SATA_FTX_C_DRX_N0 C367 1 2 0.01U_0402_25V7K
A- 4 SATA_FTX_DRX_N0 <25>
JODD
GND 5 SATA_FRX_DTX_N0 C368 1 2 0.01U_0402_25V7K
Close to JODD Peak 1800 mA
B- 6 SATA_FRX_C_DTX_N0 <25>
SATA_FRX_DTX_P0 C370 1 2 0.01U_0402_25V7K 1
Read (CD) 1100 mA
B+ 7 SATA_FRX_C_DTX_P0 <25> GND 2 SATA_FTX_C_DRX_P1 C376 1 2 0.01U_0402_25V7K
GND A+ 3 SATA_FTX_DRX_P1 <25> Read (DVD) 950 mA
SATA_FTX_C_DRX_N1 C377 1 2 0.01U_0402_25V7K
A- SATA_FTX_DRX_N1 <25>
4 Write 1300 mA
8 GND 5 SATA_FRX_DTX_N1 C378 1 2 0.01U_0402_25V7K
1 V33 B- SATA_FRX_C_DTX_N1 <25> Standby 20mA 1
9 6 SATA_FRX_DTX_P1 C375 1 2 0.01U_0402_25V7K
V33 10 +3VS B+ 7 SATA_FRX_C_DTX_P1 <25>
V33 11 GND
GND 12
GND 13 8
GND 14 DP 9 ODD_PLUGIN# <24> +5VS_ODD
V5 +5V +5VS_ODD Place components closely ODD CONN.
15 10 1.1A
V5 16 +5V 11
V5 17 +5VS +5VS 15 MD 12 ODD_DA# <24>
GND 18
Place closely JHDD SATA CONN. 14 GND GND 13
1 1 1
DAS/DSS
1.2A GND GND
C355
19 C380 C360
23 GND 20 10U_0603_6.3V6M 0.1U_0402_10V7K
GND V12 1 1 1 2 2 2
24 21 C356 C357 C358 SANTA_202401-1
GND V12 22 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K
V12 @
10U_0603_6.3V6M
2 2 2
SUYIN_127043FR022G196ZR
Slot 1 Half PCIe Mini Card-WLAN

WLAN&BT Combo module circuits
2 BT BT 2
on module on module
+3V_WLAN
40 mils Enable Disable
+3VS PJ6 +3V_WLAN
0.1U_0402_16V4Z BT_ON H L
1 1 1 2 1
CM1 CM2 CM3 @ PAD-OPEN 2x2m

2 2 2 4.7U_0603_6.3V6K
0.1U_0402_16V4Z Short for WIFI
BT_ON 1 R327 2 E51_RXD

<34> BT_ON
1K_0402_5%
+3V_WLAN For isolate BT_CTRL and
Compal Debug Card.
@ JWLAN
R1443 1 2
0_0402_5% 3 1 2 4
BT_ON 1 2 BT_CTRL_R 5 3 4 6
7 5 6 8
<24> CLKREQ_WLAN# 9 7 8 10
11 9 10 12
<23> CLK_WLAN# 13 11 12 14
<23> CLK_WLAN 15 13 14 16
3 17 15 16 18 3
19 17 18 20
21 19 20 22 WL_OFF# <34>
23 21 22 24 APU_PCIE_RST# <12,23,30>
<5> PCIE_FRX_WLANTX_N1 25 23 24 26
<5> PCIE_FRX_WLANTX_P1 27 25 26 28
29 27 28 30
29 30 FCH_SCLK0 <10,11,24>
31 32
<5> PCIE_FTX_C_WLANRX_N1 31 32 FCH_SDATA0 <10,11,24>
33 34
<5> PCIE_FTX_C_WLANRX_P1 35 33 34 36
35 36 USB20_N3 <24>
37 38 BT
37 38 USB20_P3 <24>
39 40
+3V_WLAN 39 40
41 42
WLAN/ WiFi 43 41 42 44
45 43 44 46
45 46
1
47 48
49 47 48 50 R63
<34> E51_TXD 51 49 50 52 300_0402_5%
<34> E51_RXD 51 52 @
53 54
2
GND1 GND2
Debug card using 1
C263
LCN_DAN08-52406-0500 10P_0402_50V8J
@
2@
Reserved for EHCI CRC errors
4 4

SATA-HDD/ODD/USB
Size
Document Number Rev
0.3
LA-9869P
A B C D E
A B C D E F G H
Green Clock Generator
+3V_LAN +3VL +1.8VGS +3VALW_FCH CCL2

1 1
CCL1 2.2U_0402_6.3V6M
1 1
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
22U_0805_6.3V6M GCLK@ For DIS
1 1 1 1 GCLK@
2 UCL1 UGCLK@ 2 UCL1 VGA@
CCL13 CCL15 CCL18 CCL14
@ GCLK@ GCLK@ GCLK@ 2 GCLK@ 1 +VBAT 10 14 +VDD_RTC_OUT
2 2 2 2 +RTC VBAT VDD_RTC_OUT
RCL10 120_0603_5%
15
+3VL +V3.3A
2 SLG3NB302VTR_TQFN16_2X3
+3VALW VDD 9 SA00006D500
32kHz FCH_RTCX1_R <23>
+3VALW
VGA@
11 12 VGA_X1_R RCL11 2 1 10_0402_5%
+1.8VGS VDDIO_27M 27MHz VGA_X1 <14>
0.1U_0402_10V7K
1 @ 2 +3V_LAN_R 8 6 LAN_X1_R_R RCL8 1 2
1 +3V_LAN VDDIO_25M_A 25MHz_A LAN_X1_R <30>
RCL12 0_0402_5% @ 33_0402_5%
CCL20 3 5 FCH_X1_R_R RCL7 1 2
+3VALW_FCH VDDIO_25M_B 25MHz_B FCH_X1_R <23>
GCLK@ GCLK@ 33_0402_5%
2 CLK_X1 1
CLK_X2 16 XTAL_IN
XTAL_OUT
GND1
GND2
GND3
GND4
SLG3NB238VTR_TQFN16_2X3
4
7
13
17
@
change part number to SA00005DO00 LAN_X1_R_R 1 2
CCL10 5P_0402_50V8C
SJ10000EF00
Reserved for Swing Level adjustment
GCLK@
2 YCL1 25MHZ 12PF X3G025000DK1H-X ( Close GCLK side ) 2
CLK_X1 1 3 CLK_X2
1 3
GND GND
2 2 4 2
CCL11 CCL12
18P_0402_50V8J 18P_0402_50V8J
1 GCLK@ 1 GCLK@
3 3
4 4

PCIe-WLAN/GCLK
Size
Document Number Rev
0.3
LA-9869P
A B C D E F G H
A B C D E
Left USB 2.0 x 1
+5VALW W=60mils
2.0A +USB_VCCC
U14 @EMI@
EMI@ LR7 2 6 1 2
<24> USB20_P0 USB20_P0 3 4 USB20_P0_L 3 IN OUT 7 C76 1000P_0402_50V7K
1 3 4 4 IN OUT 8 1
<34> USB_EN#2 1 EN/ENB OUT 5
GND OCB USB_OC#2 <24,34>
<24> USB20_N0 USB20_N0 2 1 USB20_N0_L
2 1 SY6288DCAC_MSOP8 JLAN @
WCM-2012-900T_0805 SA00004KB00 1
+3V_LAN 1
2
SA00003TV00 <12,23,28> APU_PCIE_RST# LANCLK_REQ# 3 2 2
ISOLATE# 4 3
5 4 4
<24> FCH_PCIE_WAKE# 6 5
LAN_X1_R 7 6 6
<29> LAN_X1_R 8 7
EMI@
RL8 1 2 0_0402_5% 9 8 8
<23> CLK_LAN# 9
RL9 1 2 0_0402_5% 10
<23> CLK_LAN 11 10 10
EMI@
12 11
<5> PCIE_FTX_C_LANRX_N0 12 12
13
<5> PCIE_FTX_C_LANRX_P0 13
14
<5> PCIE_FRX_C_LANTX_N0 15 14 14
<5> PCIE_FRX_C_LANTX_P0 16 15
USB20_P0_L 17 16 16
USB20_N0_L 18 17
+USB_VCCC 19 18 18
+3VS +USB_VCCC 19
20
For LAN function +3VS
20 20
W=60mils 21
G1 22
G2
1
23
G3 24
LAN_EN G4
2
<24> LAN_EN 1K_0402_5%
R333 RL6 ACES_50559-02001-001
2
@
G
10K_0402_5%
2
2 2
ISOLATE# 1 @ 2
CLKREQ_LAN# 1 3 LANCLK_REQ# 1 RL433 0_0402_5% WOL_EN# <34>
<24> CLKREQ_LAN#
D
QL53 RL7
2N7002KW_SOT323-3 15K_0402_5%
Sx Enable Sx Disable S0
+3V_LAN
Wake up Wake up
@ PJ29
2 1 WOL_EN# LOW HIGH HIGH
+3VALW_FCH 2 1
JUMP_43X39
+3V_LAN rising time (10%~90%) need > 1ms and <100ms.
LAN WOL LAN_EN ISOLATEB

S0 Sx S0 Sx
----------------------------------------------
3 0 0 0 0 1 1 3
0 1 0 0 1 1
1 0 1 1 1 1
1 1 1 1 1 0*
*
S3: after SUSP# assert low over 100ms
S4/S5: after SYSON assert low over 100ms
4 4

PCIe-LAN-RTL8105E/8111F
Custom 0.3
LA-9869P
A B C D E
5 4 3 2 1
U15 14640@
SA00006C400 USB Sleep & Charge
U15 14641@ RR3
1 8 CHG_CB0 2 1 0_0402_5% SLP_CHG_CB0 <25>
<34> CHG_PWR_GATE#
USB20_DN10 2 CEN CB0 7 USB20_N10
SA00006KL00 DM TDM USB20_N10 <24> State table for MAX14641
USB20_DP10 3 6 USB20_P10
DP TDP USB20_P10 <24>
<25> SLP_CHG_CB1 RR2 2 1 CHG_CB1 4 5
+5VALW
MAX14640ETA 0_0402_5% 9 CB1 VCC
PGND 1 CB0 CB1 Mode STATUS
14641@ CR10
MAX14641ETA+TGH7_TDFN-EP8_2X2 0.1U_0402_10V7K 2A auto-detection charger mode for Apple device.
14641@ AM2 Resistor dividers are connected to DP/DM. Including DCP
2 0 0
Forced 1A charger mode for Apple devices.
0 1 AP1 Resistor dividers are connected to DP/DM.
D D
1 0 PM USB pass-through mode.DP/DM are connected to TDP/TDM

USB pass-through mode with CDP emulation.
+3VALW 1 1 CM
+USB_VCCA +3VALW Auto connects DP/DM to TDP/TDM depending
W=100mils on CDP detection status.
2 1
CR43 0.1U_0402_10V7K
2
1 2 RR4 RR5
CR42 47U_0805_6.3V6M 4.7K_0402_5% 4.7K_0402_5%
14640@ 14640@
2
W=100mils
G
QR1A
2.5A
1
+5VALW +USB_VCCA 14640@
UR4 @EMI@
2 6 1 2 EC_SMB_CK1 6 1 CHG_CB1
<34,39,40,9> EC_SMB_CK1
S
3 IN OUT 7 C78 1000P_0402_50V7K
D
IN OUT
5
USB_CHG_EN# 4 8 2N7002KDWH_SOT363-6
G
<34> USB_CHG_EN# 1 EN/ENB OUT 5
GND OCB USB_CHG_OC# <24,34>
QR1B
G547N2P81U_MSOP8 14640@
SA00006DN00 EC_SMB_DA1 3 4 CHG_CB0
<34,39,40,9> EC_SMB_DA1
S
D
2N7002KDWH_SOT363-6
Front with S&C

LR1 EMI@ LR3 EMI@
C USB30_RX0N 4 3 USB30_RX0N_L USB20_DP10 1 2 USB20_P10_L C
<24> USB30_RX0N 4 3 1 2
DR7 @ESD@ JUSBF @
USB30_RX0P 1 2 USB30_RX0P_L USB20_DN10 4 3 USB20_N10_L USB30_TX0P_C_L 1 9 USB30_TX0P_C_L USB30_TX0P_C_L 9 13
<24> USB30_RX0P 1 2 4 3 USB30_TX0N_C_L 8 StdA-SSTX+ GND 12
KINGCORE WCM-2012HS-670T WCM-2012-900T_0805 USB30_TX0N_C_L 2 8 USB30_TX0N_C_L 7 StdA-SSTX- GND 11
USB30_RX0P_L 6 GND-DRAIN GND 10
USB30_RX0P_L 4 7 USB30_RX0P_L USB30_RX0N_L 5 StdA-SSRX+ GND
4 StdA-SSRX-
USB30_RX0N_L 5 6 USB30_RX0N_L USB20_P10_L 3 GND
USB20_N10_L 2 D+
LR2 EMI@ 1 D-
+USB_VCCA VBUS
<24> USB30_TX0N 1 2 USB30_TX0N_C 4 3 USB30_TX0N_C_L
CB22 0.1U_0402_16V7K 4 3 3 LOTES_AUSB0015-P001A
1 2 USB30_TX0P_C 1 2 USB30_TX0P_C_L TVWDF1004AD0_DFN9

<24> USB30_TX0P 1 2
CB21 0.1U_0402_16V7K
KINGCORE WCM-2012HS-670T
Rear
W=80mils
+5VALW
W=80mils +USB_VCCB
+USB_VCCB
B B
UR3 @EMI@ 0.1U_0402_10V7K
2 6 1 2
3 IN OUT 7 C79 1000P_0402_50V7K 1
1
USB_EN#0 4 IN OUT 8 CR46 CR44

<34> USB_EN#0 1 EN/ENB OUT 5
GND OCB USB_OC#0 <24,34>
2
SY6288DCAC_MSOP8 2
SA00004KB00
47U_0805_6.3V6M
SA00003TV00
LR4 EMI@
LR5 EMI@ USB20_P11 4 3 USB20_P11_L
4 3 <24> USB20_P11 4 3 JUSBR @
USB30_RX1N USB30_RX1N_L
<24> USB30_RX1N 4 3 USB30_TX1P_C_L 9 13
1 2 DR8 @ESD@ USB30_TX1N_C_L 8 StdA-SSTX+ GND 12
USB20_N11 USB20_N11_L
1 2 <24> USB20_N11 1 2 USB30_TX1P_C_L 1 9 USB30_TX1P_C_L 7 StdA-SSTX- GND 11
USB30_RX1P USB30_RX1P_L
<24> USB30_RX1P 1 2 USB30_RX1P_L 6 GND-DRAIN GND 10
WCM-2012-900T_0805
USB30_TX1N_C_L 2 8 USB30_TX1N_C_L USB30_RX1N_L 5 StdA-SSRX+ GND
4 StdA-SSRX-
USB30_RX1P_L 4 7 USB30_RX1P_L USB20_P11_L 3 GND
USB20_N11_L 2 D+
USB30_RX1N_L 5 6 USB30_RX1N_L 1 D-
+USB_VCCB VBUS
LOTES_AUSB0015-P001A
LR6 EMI@
1 2 USB30_TX1N_C 4 3 USB30_TX1N_C_L 3
<24> USB30_TX1N 4 3
CB24 0.1U_0402_16V7K
TVWDF1004AD0_DFN9
1 2 USB30_TX1P_C 1 2 USB30_TX1P_C_L
A <24> USB30_TX1P 1 2 A
CB23 0.1U_0402_16V7K

USB3.0
Custom 0.3
LA-9869P
5 4 3 2 1
5 4 3 2 1
20 mil 35mA for 3.3V level 40 mil 650mA for 5V level

259: SA000054P00 RA22
UA1 close to pin 25 close to pin 38 RA18
+DVDD 0_0402_5% +AVDD 0.1U_0402_10V7K 0.1U_0402_10V7K 1 2
+3VS +5VALW
MIC1_LINE1_R_R 4.7U_0603_6.3V6K CA58 22 1 +DVDD 1 2 1 2 1 0_0603_5%
MIC1_LINE1_R_L 4.7U_0603_6.3V6K CA57 21 MIC1_R DVDD 9 +DVDD
MIC1_L DVDD_IO 1
CA4 CA42 CA47 CA37 CA50
17 25 +AVDD 0.1U_0402_16V4Z CA3
16 MIC2_R AVDD1 38 +AVDD 2 10U_0603_6.3V6M 1 2 1 2
MIC2_L AVDD2 close to pin1 2
2.2U_0402_6.3V6M
10U_0603_6.3V6M
31 39 +PVDD
+MIC1_VREFO_L MIC1_VREFO_L PVDD1
30 46 +PVDD
+MIC1_VREFO_R MIC1_VREFO_R PVDD2
29 1
<34> EC_MUTE_INT MIC2_VREFO
D
60 mil D
15 45 SPKR+ CA45 RA24
14 LINE2_R SPK_OUT_R+ 44 SPKR- 0.1U_0402_16V4Z +PVDD 1 2
LINE2_L SPK_OUT_R- 2 +5VALW
1 2 0_0603_5%
close to pin9 CA33
20 40 SPKL+ 0.1U_0402_10V7K
MONO_OUT SPK_OUT_L+ 41 SPKL-
SPK_OUT_L-
close to pin39 CA35
MONO_IN 12 2 1 10U_0603_6.3V6M
PCBEEP 75_0402_1%
10 33 RA19 HP_R <33>
<24> AZ_SYNC_HD SYNC HPOUT_R 32 RA20
11 HPOUT_L 75_0402_1% HP_L <33>
<24> AZ_RST_HD# RESET# 1
CA32
close to pin 28 close to pin19 10 mil 5 0.1U_0402_10V7K
SDATA_OUT AZ_SDOUT_HD <24>
8 AZ_SDIN0_HD_R 2 1 close to pin46
2 RA30 1 19 SDATA_IN AZ_SDIN0_HD <24> 2
AC_JDREF RA23 33_0402_5%
10U_0603_6.3V6M
10U_0603_6.3V6M1 2 CA60 20K_0402_1% LDO_CAP 28 JDREF 6 AZ_BITCLK_HD
AC_VREF 27 LDO_CAP BCLK AZ_BITCLK_HD <24>
1 2 CPVEE 34 VREF 269@
CA54 CBN 35 CPVEE 23 LINE1_R_C_L CA9 2 1 1U_0402_6.3V4Z MIC1_LINE1_R_L
2.2U_0402_6.3V6M 1 2 CBP 36 CBN LINE1_L 24 LINE1_R_C_R CA10 2 1 1U_0402_6.3V4Z MIC1_LINE1_R_R
1 CBP LINE1_R 48
For S&M
CA53
CA55 2.2U_0402_6.3V6M NC 269@
0.1U_0402_10V7K 2
2 <20> INT_MIC_DATA
INT_MIC_CLK_R 3 GPIO0/DMIC_DATA 26
GPIO1/DMIC_CLK AVSS1 37
AVSS2 42
SENSE_A 13 PVSS1 43
2 @ 1 SENSE_B 18 SENSE_A PVSS2 7
RA34 20K_0402_1% SENSE_B DVSS
47 AGND
4 EAPD 49 @
<34> EC_MUTE# PD# Thermal Pad 1 2
C RA44 680P_0603_50V8J C
For P/N and footprint
For EMI reserve ALC259-VC2-CG_MQFN48_6X6 For EMI reserve @ Please place them to ISPD page
2
1 2
EMI@ RA50 placed close to codec RA43 680P_0603_50V8J
<20> INT_MIC_CLK RA42 INT_MIC_CLK_R 4.7K_0402_5% @ UA1
FBMA-10-100505-301T 269@ DGND @EMI@ CA51 1 2
To solve S&M noise issue AZ_BITCLK_HD 2 1 1 2 @EMI@ RA31 680P_0603_50V8J
1
10_0402_5% RA41 1 @EMI@ 2 269: SA00006BW00

Internal AMP 10P_0402_50V8J RA38 0_0603_5%
EC_MUTE# 1 @EMI@ 2
Hight Enable RA39 0_0603_5% ALC269Q-VB6-CG
LOW Disable 269@
Beep sound SPK MIC/LINE IN

RA47 2 1
+MIC1_VREFO_R
2W 4ohm =40mil For EMI reserve 1K_0402_5% RA48 2.2K_0402_5%
1W 8ohm =20mil MIC1_LINE1_R_R 2 1 MIC1_R <33>
close to codec
MIC1_LINE1_R_L 2 1 MIC1_L <33>
1K_0402_5%
SPKL+ 1 @ 2 RA45 2 1
PCI Beep CA70 RA7 0_0603_5%
SPK_L1 <33>
RA46 2.2K_0402_5%
+MIC1_VREFO_L
1 RA52 2 1 2 MONO_IN
B <24> FCH_SPKR
SPKL- 1 2 B
47K_0402_5% @ SPK_L2 <33>
0.1U_0402_10V7K RA8 0_0603_5% MIC_SENSE
1 1
6
2
1 CA31 CA30 RA29 269@

RA49 1000P_0402_50V7K 1000P_0402_50V7K QA1A 100K_0402_5%
CA15 2 2 2N7002DW-T/R7_SOT363-6 2
4.7K_0402_5% @EMI@ @EMI@
269@
2 100P_0402_50V8J
1
1
RA37
Add CA15 for better 0_0402_5%
+3VL RA35 100K_0402_5%
sound by A51 SPKR+ 1 @ 2 SPK_R1 <33> 259@
RA9 0_0603_5%
<34> SM_SENSE#
3
SPKR- 1
RA10
@ 2
0_0603_5%
SPK_R2 <33> EC QA1B
2N7002DW-T/R7_SOT363-6 5 JACK_SENSE <33>
269@
1 1
4
Sense Pin Impedance Codec Signals Function CA34 CA36
1000P_0402_50V7K 1000P_0402_50V7K
2 2
39.2K PORT-I (PIN 32, 33) Headphone out @EMI@ @EMI@
place close to chip

20K PORT-B (PIN 21, 22) Ext. MIC
SENSE A MIC_SENSE 2 1 SENSE_A
10K PORT-C (PIN 23, 24) RA32 20K_0402_1%
A A
5.1K (PIN 48)

<33> NBA_PLUG
39.2K PORT-E (PIN 14, 15) RA33 39.2K_0402_1%
SENSE B 20K PORT-F (PIN 16, 17) Security Classification Compal Secret Data Compal Electronics, Inc.
10K PORT-H (PIN 20) Cover Sheet
Custom 0.3
5 4 3 2 1
Card reader SPK CONN. Non-Harman detection
please close the pin4 of UW1 please close the pin19 of UW1 0 ONKYO
+3VS_CR +3VS_CR SDCLK 1 2 SDCLK_R

SPK_DET0
+3VS_CR +3VS_CR
30mils
RW 5 0_0402_5% 2 1 Non-Brand
1 1 30mils 1
EMI@ CW 10 @EMI@
CW 3 CW 4 CW 2 10P_0402_50V8J
2.2U_0402_6.3V6M 0.1U_0402_16V4Z 1
2 2 2
0.1U_0402_16V4Z Please check SPK_DET pull high 10K to +3VS
+3VS
For common design,
pull-high resistor should
2
be placed at connector
RA95
side. 10K_0402_5%
1
CW 8 ACES_50228-0067N-001
1
0.1U_0402_16V4Z UW 1 8
2 7 GND
22 GND
RSTZ SA00005M300
For power consumption measurement 6
<32> SPK_R1 6
and remove it after Pre-MP phase 5 5
MS_INS <32> SPK_R2 5
2 17 SD_DATA2 4
<24> USB20_N2 DM SD_D2/MS_D5/SB13 <32> SPK_L1 4
3 16 SD_DATA3 3
<24> USB20_P2 DP SD_D3/MS_D4/SB12 <32> SPK_L2 3
15 SDCMD 2
30mils SD CMD/SD_CMD <25> SPK_DET 2
14 SDCLK 1
1 2 +3VS_CR 1 SD CLK/SD_CLK 21 SDCD# 1
+3VS DVDD SD_CDZ
2
@ JSPK
CK0402101V05_0402-2
CK0402101V05_0402-2
CK0402101V05_0402-2
CK0402101V05_0402-2
RW 2 0_0402_5% +VCC_3IN1 24 13 SD_DATA0
PMOS SD_D0/MS_D6/SB9
@ESD@
@ESD@
D27
D30
@ESD@
D28
@ESD@
D29
1 12 SD_DATA1
CW 1 30mils SD_D1/MS_D7/SB8 11
2.2U_0402_6.3V6M +3VS_CR 19 MS BS/MS_BS 10 SDW P
+3VS_CR 23 DVDD SD_WP/MS_D1/SB5 9
2 20 DVDD SD_D4/MS_D0/SB4 8
1
GPIO0 SD_D5/MS_D2/SB3 7
+3VS_CR 4 SD_D6/MS_D3/SB1 6
+VDD18 18 AVDD SD_D7/MS_CLK/SB0
VDD18
12mils
1 25
Thermal pad
CW 5 GL834L-OGY01_QFN24_4X4
0.1U_0402_16V4Z
2
For normal close type connector invert circuit

HeadPhone/LINE Out JACK
NC (default)
10K pull down +3VS_CR JLINE @
6
GPIO0 Power saving mode Normal mode 1
1
2
SDW P 1 @ 2 HP_R_L
<32> HP_L
RW 4 RA21 0_0402_5% 3
100K_0402_5% 1 @ 2 HP_R_R
<32> HP_R
RA25 0_0402_5% 4
2
3
QW 1B D
<32> NBA_PLUG
SDW P# 5 5
G
DA6
2N7002KDW H_SOT363-6 SINGA_2SJ-0960-D11
S 3
4
1
+3VS_CR 2
YSDA0502C_SOT23-3
1
@ESD@
RW 3 SDCD#
CD_SW WP_SW 100K_0402_5%
2
Protect disable Protect Enable QW 1A D

Card Uninsertion SDCD 2
Close G
Close Close S
2N7002KDW H_SOT363-6
Ext.MIC/LINE IN JACK
1
JEXMIC @
6
Card Insertion 1
Open Open Close 1 @ 2 MIC1_R_L 2
<32> MIC1_L
RA26 0_0402_5%
1 @ 2 MIC1_R_R 3
<32> MIC1_R
< 2 in 1 Card Reader > Close to connector Close to IC RA27 0_0402_5%
JCARD 30mil 4
<32> JACK_SENSE
DA7
5 +VCC_3IN1 +3VL 5
VDD 3 SDCMD 3 RA40
CMD 1 1
6 SDCLK_R CW 6 CW 7 1 4.7K_0402_5% SINGA_2SJ-0960-D11
CLK 7 2 269@ RA36
VSS 0.1U_0402_16V4Z 2.2U_0402_6.3V6M
4 0_0402_5%
VSS 2 2
YSDA0502C_SOT23-3 259@
8 SD_DATA0
DAT0 9 SD_DATA1 @ESD@
DAT1 1 SD_DATA2
DAT2 2 SD_DATA3
CD/DAT3
12 10 SDW P#
13 GND_SW WP_SW 11 SDCD
GND_SW CD_SW
@ T-SOL_156-2000302604 2013/01/22 2014/01/21 Title
"Normal Close" type connector THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CR & Audio Conn.
0.3
LA-9869P
5 4 3 2 1
+3VL +3VL
0.1U_0402_10V7K 0.1U_0402_10V7K 1000P_0402_50V7K CB3

1 1 1 1 1 1 0.1U_0402_10V7K
CB1 CB2 CB5 CB7 1 2
0.1U_0402_10V7K
For EMI 2 2
CB4
2 2
CB6
2 2
111
125
0.1U_0402_10V7K 1000P_0402_50V7K
22
33
96
67
9
CLK_PCI_EC UB1
BATT_PRES 1 2
EC_VDD0
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/AVCC
1
CB9 100P_0402_50V8J
RB3
10_0402_5% ACIN_D 1 2
@EMI@ 1 21 CB10 100P_0402_50V8J
D <24> GATEA20 2 GATEA20/GPIO00 GPIO0F 23 WL_BT_LED# <35> D
<24> KB_RST# USB_EN#0 <31>
2
3 KBRST#/GPIO01 BEEP#/GPIO10 26
1 <23> SERIRQ SERIRQ GPIO12 FANPWM <5>
CB11 4 27
<23> LPC_FRAME# 5 LPC_FRAME# ACOFF/GPIO13
22P_0402_50V8J
<23> LPC_AD3 7 LPC_AD3
@EMI@
2 <23> LPC_AD2 LPC_AD2 PWM Output
8 63
<23> LPC_AD1 10 LPC_AD1 BATT_TEMP/GPIO38 64 BATT_PRES <39>
<23> LPC_AD0 LPC_AD0LPC & MISC GPIO39 USB_OC#0 <24,31>
65
12 ADP_I/GPIO3A 66 ADP_I <39,40>
<23,26> CLK_PCI_EC CLK_PCI_EC AD Input GPIO3B ADP_V <40>
LVDS@
13 75 EC_SMB_CK3 1 2
<23> LPC_RST# PCIRST#/GPIO05 GPIO42 HDPLOCK <35> +3VS
EC_RST# 37 76 RB135 4.7K_0402_5%
+3VL 20 EC_RST# IMON/GPIO43 EC_ENBKL <19> EC_SMB_DA3 1 2
RB2
<24> EC_SCI# 38 EC_SCII#/GPIO0E
47K_0402_5% RB136 4.7K_0402_5%
1 2 EC_RST# GPIO1D 68 LVDS@
DAC_BRIG/GPIO3C 70 HDPINT <35>
885_EC_ON
1 2 EN_DFAN1/GPIO3D 71
DA Output IREF/GPIO3E
CB12 0.1U_0402_10V7K KSI0 55 72
KSI1 56 KSI0/GPIO30 CHGVADJ/GPIO3F +3VL
KSI2 57 KSI1/GPIO31
KSI3 58 KSI2/GPIO32 83
+3VL 59 KSI3/GPIO33 EC_MUTE#/GPIO4A 84 EC_MUTE# <32> 1 2
KSI4 LID_SW#
KSI5 60 KSI4/GPIO34 USB_EN#/GPIO4B 85 RB35 47K_0402_5%
1 2 CHG_PWR_GATE# KSI6 61 KSI5/GPIO35 CAP_INT#/GPIO4C 86 EC_SMB_CK3 <19>
KSI6/GPIO36 PS2 Interface EAPD/GPIO4D EC_SMB_DA3 <19>
RB25 10K_0402_5% KSI7 62 87
39 KSI7/GPIO37 TP_CLK/GPIO4E 88 TP_CLK <36>
KSO0
40 KSO0/GPIO20 TP_DATA/GPIO4F TP_DATA <36>
KSO1
KSI[0..7] KSO2 41 KSO1/GPIO21
<35> KSI[0..7] KSO3 42 KSO2/GPIO22 97
KSO[0..15] 43 KSO3/GPIO23 CPU1.5V_S3_GATE/GPXIOA00 98 VGATE <45>
KSO4
<35> KSO[0..15] 44 KSO4/GPIO24 WOL_EN/GPXIOA01 99 GPU_DOWN# <13>
KSO5
KSO6 45 KSO5/GPIO25 Int. K/B ME_EN/GPXIOA02 109 POK <41>
VCIN0_PH connect to +3VS
KSO7 46 KSO6/GPIO26 Matrix VCIN0_PH/GPXIOD00 VCIN0_PH <39>
C KSO7/GPIO27 SPI Device Interface power portion (9012 only) C
KSO8 47 TP_CLK 1 2
KSO9 48 KSO8/GPIO28 119 RB8 4.7K_0402_5%
+3VALW_FCH 49 KSO9/GPIO29 SPIDI/GPIO5B 120 EC_SDIO <25>
KSO10
50 KSO10/GPIO2A SPIDO/GPIO5C 126 EC_SDI <25> 1 2
LVDS@ KSO11 SPI Flash ROM Nuvoton EC share ROM TP_DATA
KSO11/GPIO2B SPICLK/GPIO58 EC_SCK <25>
RB28 2 1 10K_0402_5% TRANS_SEL KSO12 51 128 RB9 4.7K_0402_5%
KSO13 52 KSO12/GPIO2C SPICS#/GPIO5A EC_CS0# <25>
KSO14 53 KSO13/GPIO2D
KSO15 54 KSO14/GPIO2E 73 SYSON 1 2
81 KSO15/GPIO2F ENBKL/GPIO40 74 LCD_ENBKL <20,9>
TRANS_SEL RB10 4.7K_0402_5%
CHG_PWR_GATE# 82 KSO16/GPIO48 PECI_KB930/GPIO41 89 WOL_EN# <30>
RPB1
1 8 EC_SMB_CK1 <31> CHG_PWR_GATE# KSO17/GPIO49 FSTCHG/GPIO50 90 BATT_FULL_LED# HDPACT <35>
+3VL BATT_CHG_LED#/GPIO52 BATT_FULL_LED# <35>
2 7 EC_SMB_DA1 91
3 6 77 CAPS_LED#/GPIO53 92 CAPS_LED# <35> 1 2
+3VS EC_SMB_CK2 GPIO @
4 5 <31,39,40,9> EC_SMB_CK1 78 EC_SMB_CK1/GPIO44 PWR_LED#/GPIO54 93 PWR_SUSP_LED# <35>
EC_SMB_DA2 RB14 0_0402_5%
<31,39,40,9> EC_SMB_DA1 79 EC_SMB_DA1/GPIO45 BATT_LOW_LED#/GPIO55 95 BATT_CHG_LOW_LED# <35>
<13,35> EC_SMB_CK2 SM
EC_SMB_CK2/GPIO46 Bus SYSON/GPIO56 SYSON <37,42>
2.2K_0804_8P4R_5% 80 121
<13,35> EC_SMB_DA2 EC_SMB_DA2/GPIO47 VR_ON/GPIO57 127 VR_ON <37,44,45>
PM_SLP_S4#/GPIO59 1.1VPWR_EN <43>
VCOUT0_PH_L 1 @ 2
6 100 VS_ON <41>
RB34 0_0402_5%
<24> SLP_S3# 14 PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 101 EC_RSMRST# <24>
<24> SLP_S5# EC_LID_OUT# <24>
VCOUT0_PH connect to power portion (9012 only)
15 PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04 102
@ <24> EC_SMI# EC_SMI#/GPIO08 PROCHOT_IN/GPXIOA05 PROCHOT_IN <39>
1 2 LPC_RST# 16 103 H_PROCHOT_EC
<24,30> USB_OC#2 17 GPIO0A H_PROCHOT#_EC/GPXIOA06 104
CB13 1U_0402_6.3V6K VCOUT0_PH_L
<24,31> USB_CHG_OC# 18 GPIO0B VCOUT0_PH/GPXIOA07 105
<31> USB_CHG_EN# GPIO0C GPO BKOFF#/GPXIOA08 BKOFF# <20>
@ESD@ 19 GPIO 106 RB18
<30> USB_EN#2 25 GPIO0D PBTN_OUT#/GPXIOA09 107 PBTN_OUT# <24>
1 2 SUSP# 330K_0402_5%
<35> KB_LED 28 EC_INVT_PWM/GPIO11 PCH_APWROK/GPXIOA10 108 FCH_PWR_EN <37> 2 1
CB14 180P_0402_50V8J <5> FAN_SPEED1 FAN_SPEED1/GPIO14 SA_PGOOD/GPXIOA11 EC_PXCONTROL <24> +3VL
29
<28> WL_OFF# 30 EC_PME#/GPIO15
<28> E51_TXD 31 EC_TX/GPIO16 110 ACIN_D ACIN_D 2 1
<28> E51_RXD FCH_PWRGD 32 EC_RX/GPIO17 AC_IN/GPXIOD01 112 EC_ON_R
ACIN <40>
RB751V40_SC76-2 DB1
B <24> FCH_PWRGD 34 PCH_PWROK/GPIO18 EC_ON/GPXIOD02 114 B
<28> BT_ON 36 SUSP_LED#/GPIO19 ON/OFF/GPXIOD03 115 ON/OFFBTN# <36>
Close to EC <32> SM_SENSE# NUM_LED#/GPIO1A GPI LID_SW#/GPXIOD04 LID_SW# <36>
116
SUSP#/GPXIOD05 117 SUSP# <37,42>
GPXIOD06 118
PECI_KB9012/GPXIOD07
AGND/AGND
1 @ 2 EC_MUTE_INT_R 122 SUSP# 1 2

<32> EC_MUTE_INT XCLKI/GPIO5D
RB38 1 @ 2 0_0402_5% XCLKO 123 124 +EC_V18R RB21 10K_0402_5%
GND/GND
GND/GND
GND/GND
GND/GND
<23,26> RTC_CLK XCLKO/GPIO5E V18R

RB20 0_0402_5% 1
GND0
VR_ON 1 2
@ESD@ CB15 RB23 10K_0402_5%
1
1 2 FCH_PWRGD 1 4.7U_0805_10V4Z H_PROCHOT_EC

CB17 180P_0402_50V8J RB22 CB16 KB9012QF-A3_LQFP128_14X14 2
11
24
35
94
113
69
100K_0402_5% 20P_0402_50V8 9012@
2
CK0402101V05_0402-2
2
DB2
@ESD@
UB1 885@
2
NPCE885NB0DX LQFP 128P
RB37
1
47K_0402_5%
1 2 EC_MUTE_INT_R
H_PROCHOT# <45,7>
885@
2 1 Low Active (+1.5V)
+3VL
RB27 RB19 330K_0402_5%
1
D
100K_0402_5% 9012@
1 2 E51_TXD EC_ON_R 1 2 H_PROCHOT_EC 2 QB1
EC_ON <41> G
RB36 0_0402_5% High Active 2N7002KW_SOT323-3
1
S
3
1U_0402_6.3V6K
1 3 CB50
S
D
2 @
A
Voltage Comparator Pins FOR 9012 A3 QB2 +3VS A
2N7002KW_SOT323-3
885@ H_PROCHOT_EC 1 @ 2
G
VCIN0 pin109 >1.2V <1.2V RB6 10K_0402_5%

2
VCIN1 pin102 885_EC_ON

2
VCOUT0 pin104 HIGH LOW 885@ RB24

10K_0402_5%
VCOUT1 pin103 LOW HIGH LPC-EC-KB9012
1
0.3
LA-9869P
5 4 3 2 1
1 2 3 4 5 6 7 8
Battery Reset
G-SENSOR
+5VS +3VS_HDP
UG3 GSENSOR@
2 3 VOUTXCG4 1 2 0.033U_0402_16V7K GSENSOR@
+3VS_HDP Vdd1 Voutx
1 1 12 5 VOUTYCG5 1 2 0.033U_0402_16V7K GSENSOR@
CG3 UG2 GSENSOR@ CG1 Vdd2 Vouty 7 VOUTZCG6 1 2 0.033U_0402_16V7K GSENSOR@
1U_0402_6.3V6K 1U_0402_6.3V6K Voutz
GSENSOR@ 1 5 GSENSOR@ SELF_TEST 4 10
2 VIN VOUT 2 6 ST NC1 11
A 2 8 PD NC2 14 A
SW6 GND CG2 FS NC3 15
TJG-533-V-T/R_6P 3 4 2 1 NC4 16
3 1 SHDN# BP NC5
@ 9 1
4 2 +3VS_HDP Rev GND1
G9191-330T1U_SOT23-5 0.22U_0402_10V4Z 13
<41> ENLDO GND2
SA000022I00
TSH352TR LGA 16P
5
6
SA00004GB00
UG1 GSENSOR@
1 11
<13,34> EC_SMB_CK2 P3_5/SSCK/SCL/CMP1_2 P1_6/CLK0/SSI01 HDPACT <34>
2
SELF_TEST 2 12 RG2
+3VS_HDP P3_7/CNTR0#/SSO/TXD1 P1_5/RXD0/CNTR01/INT11# 47K_0402_5%
RPG1 GSENSOR@
Keyboard LED G_RESET# 3 13
1
1 8 G_RESET# RESET# P1_4/TXD0
2 7 GXOUT
Q38 KBL@ 3 6 GXIN GXOUT 4 14
+5VS AO3413_SOT23 XOUT/P4_7 P1_3/KI3#/AN11/TZOUT HDPLOCK <34>
JBLG @ 4 5 G_MODE SA00003A600
1 RG4 47K_0402_5%
3 1 2 1 5 15 2 1
S
4.7K_8P4R_5% VOUTZ
+5VS_LED 2 VSS/AVSS P1_2/KI2#/AN10/CMP0_2
3 GSENSOR@ GSENSOR@
3
1
4
+5VS_LED 4
R587 5 GXIN 6 16
G
+3VS_HDP
2
10K_0402_5% 6 GND +3VS_HDP XIN/P4_6 P4_2/VREF

B KBL@ GND B
1
ACES_50578-0040N-001 7 17 VOUTX CG7
2
VCC/AVCC P1_1/KI1#/AN9/CMP0_1 0.1U_0402_10V7K

GSENSOR@
G_MODE 8 18 VOUTY 2
MODE P1_0/KI0#/AN8/CMP0_0
1
D
2 Q52
<34> KB_LED G 2N7002KW_SOT323-3 RG7 2 1 1K_0402_5% 9 19
<34> HDPINT GSENSOR@ P4_5/INT0#/RXD1 P3_3/TCIN/INT3#/SSI00/CMP1_0
KBL@
S
3
1 1 10 20
P1_7/CNTR00/INT10# P3_4/SCS#/SDA/CMP1_1 EC_SMB_DA2 <13,34>
CG9
CG8 GSENSOR@
0.1U_0402_10V7K 0.1U_0402_10V7K R5F211B4D34SP
GSENSOR@ 2 2
NEW KEYBOARD CONN.

LED BATT CHARGE(Blink) /FULL LED
KSI[0..7] D7 R19
KSI[0..7] <34> 2 1 1 2
KSO[0..15] BATT_FULL_LED# <34>
KSO[0..15] <34> +5VALW HT-F196BP5_WHITE 390_0402_5%
C C
D9 R21
2 1 1 2
BATT_CHG_LOW_LED# <34>
JKB
1 HT-191UD5_AMBER_0603 510_0402_5%
2 1
2 White LED bright when both AC-adaptor is plugged in and Battery is full charged
3
<34> CAPS_LED# 2 1 4 3 Amber LED bright while charging battery from AC-adaptor.
+3VS 4
R7 300_0402_5% KSI1 5
5 Amber LED blink during Critical Low Battery
KSI6 6
KSI5 7 6
KSI0 8 7
KSI4 9
10
8
9
POWER LED(Blink)
KSI3
KSI2 11 10
KSI7 12 11 D8 R18
KSO15 13 12 2 1 1 2
13 +5VALW PWR_SUSP_LED# <34>
KSO12 14
KSO11 15 14 HT-F196BP5_WHITE 390_0402_5%
KSO10 16 15
KSO9 17 16
17 White LED bright when system is power on.
KSO8 18
KSO13 19 18 White LED blink when system is sleep mode.
KSO7 20 19
KSO6 21 20
KSO14 22 21
KSO5 23
24
22
23
WLAN LED
KSO3
KSO4 25 24
KSO0 26 25 D26 R22
KSO1 27 26 2 1 1 2
27 +5VS WL_BT_LED# <34>
KSO2 28
D 29 28 HT-191UD5_AMBER_0603 510_0402_5% D
30 29
31 30
32 31
33 32
34 33
34 35
GND1 36
GND2 Security Classification Compal Secret Data Compal Electronics, Inc.
CVILU_CF17341U0R0-NH 2013/01/22 2014/01/21 Title
@
Debug/KB
Size
Document Number Rev
0.3
LA-9869P
1 2 3 4 5 6 7 8
5 4 3 2 1
Conn. Screw Hole

+3VL
JPW R CPU VGA FCH
2
1 2 ON/OFFBTN#
R397 3 1 2 4 H1 H2 H3 H4 H5 H8
5 3 4 6
For debug 5 6
H_4P2 H_4P6 H_4P2x4P6 H_3P3 H_3P3 H_3P0
100K_0402_5% 7 8 +5VS @ @ @ @ @ @
7 8
1
D SW 5 ACES_50611-0040N-001 D
1 2 ON/OFFBTN# @
ON/OFFBTN# <34>
Place on TOP 3 4
PTH
G
G
NTC017-DA1J-D160T_4P
6
5
H7 H10 H11 H12 H13 H15 H17

H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P2 H_3P0
@ @ @ @ @ @ @
1
H18 H29 H21
H_4P0 H_3P3 H_7P0
@ @ @ NPTH
1
+3VS H22 H9 H16
H_3P2N H_3P2x3P7N H_3P2N
Touchpad Connector +3VS
@ @ @
1
2
2
R298 R299
4.7K_0402_5% 4.7K_0402_5%
+3VS
JTP
2
C 15 16 C
1
13 15 16 14
13 14 TP_DATA <34>
11 12 TP_FCH_SCLK1 1 6
11 12 TP_CLK <34> FCH_SCLK1 <24>
9 10
9 10
5
7 8 Q5331A
5 7 8 6 TP_FCH_SDATA1 DMN66D0LDW -7 2N_SOT363-6
3
1
5
3
1
6
4
2
4
2
TP_FCH_SCLK1 TP_FCH_SDATA1 4 3
FCH_SDATA1 <24> PCB Fedical Mark PAD
Q5331B
@ DMN66D0LDW -7 2N_SOT363-6 FD1 FD2 FD3 FD4
HB_A060877-SAVR01
1 @ 2 @ @ @ @
R300 0_0402_5%
1
1
1
1 @ 2
R301 0_0402_5%
ISPD Lid SW
ZZZ PJP1 45@
UAPU 5745R3@ UAPU1 5357R1@ UAPU2 5357R3@ +3VL
5745R1@ DA8000XI000 U21

APX9132ATI-TRL_SOT23-3
SA00006KK00
B SA00006KH00 PCB LA-9869P CONN SET 0CL DCJACK-MB 322215-3 2 3 B
GND
VDD VOUT LID_SW # <34>
A10-5745M-AM5745SIE44HL A6-5357M-AM5357DFE24HL A6-5357M-AM5357DFE24HL
1 1
1
UAPU 5545R1@ UAPU 5545R3@ UAPU3 5145R1@ UAPU4 5145R3@ C453
U1 BOLTONR3@ 0.1U_0402_25V6 C452
10P_0402_50V8J
2 2
SA00006KE00 SA00006KC00
A8-5545M-AM5545SHE44HL A8-5545M-AM5545SHE44HL A4-5145M-AM5145SHE23HL A4-5145M-AM5145SHE23HL
218-0755097 A14 BOLTON-M3
UAPU 5345R1@ UAPU 5345R3@
SA00006KD00
B+ B+
A6-5345M-AM5345SHE24HL A6-5345M-AM5345SHE24HL
10U_0805_25V6K
0.1U_0402_25V6
1 1
C475
C833
2 2
SA00006KI00
A A
A10-5757M-AM5757DFE44HL A10-5757M-AM5757DFE44HL Close to PR816

SA00006KJ00 2013/01/22 2014/01/21 Title
A8-5557M-AM5557DFE44HL A8-5557M-AM5557DFE44HL
TP/HDD LED/Screw
0.3
LA-9869P
5 4 3 2 1
A B C D E
+5VALW TO +5VS +5VALW VIN 5V and 3.3V (VBIAS=5V),IMAX(per channel)=6A,Rds=18mohm

+5VS
+3VALW TO +3VS 1
U2
14 +5VS_LS 1
PJ3
2
VIN1 VOUT1
Load switch C45 1
2
VIN1 VOUT1
13
C20 180P_0402_50V8J PAD-OPEN 4x4m
@ SUSP# 3 12 1 2 @ 1
ON1 CT1 @ C46
1U_0402_6.3V6K +5VALW 4 11
2 VBIAS GND C21 330P_0402_50V7K 0.1U_0402_25V6
SUSP# 5 10 1 2 2
ON2 CT2 +3VS
6 9 PJ5
1 +3VALW 7 VIN2 VOUT2 8 +3VS_LS 1 2 1
VIN2 VOUT2
15 PAD-OPEN 4x4m 1
GPAD @ @ C53
TPS22966DPUR_SON14_2X3
1 SA00004MM00 0.1U_0402_25V6
@ C44 2
1U_0402_6.3V6K
2
+5VALW +1.5V
+3VL +1.2VS
2
+0.75VS +5VALW
2
+5VALW
2
R478
2 470_0805_5% R479 +5VALW 2
R5545
2
2
2
10K_0402_5% 470_0805_5%
2
R5546 R477 R422
3 1
2
10K_0402_5% R432 470_0805_5% 100K_0402_5%
3 1
1
885@ FCH_PWR_EN# 100K_0402_5% R448

FCH_PWR_EN# <26> Q22B 100K_0402_5%
1
1
1
Q13B SUSP
<9> SUSP
1
2N7002KDWH_SOT363-6 5 SYSON#
1
1
6
D 2N7002KDWH_SOT363-6 5 VR_ON#
6
2 Q25 Q6B Q6A
<34> FCH_PWR_EN
6
G 2N7002KW_SOT323-3 Q22A
4
1
Q13A 5 SUSP SUSP# 2 2N7002KDWH_SOT363-6

2 <34,42> SUSP#
S 2N7002KDWH_SOT363-6
<34,42> SYSON
3
R5529 2 2N7002KDWH_SOT363-6 2N7002KDWH_SOT363-6

<34,44,45> VR_ON
1
100K_0402_5%
1
9012@
2
1
+5VS_ODD
+5VS TO +5VS_ODD
3 3
2
+1.1VALW to +1.1VS +1.1VS R457
470_0805_5%
ZP@
3 1
2
R417
+1.1VALW +1.1VS 470_0805_5% Q53B
Vgs=10V,Id=14.5A,Rds=6mohm 4.7U_0805_10V4Z 5 ODD_PWR# +5VS

3 1
1 1 2N7002KDWH_SOT363-6
Q44 C476 C472 ZP@
4
8 1 Q23B +5VS
7 D S 2
6 D S 3 2 2 SUSP 5 2N7002KDWH_SOT363-6
D S 2
2
5 4 ZP@ C471 Vgs=-4.5V,Id=3A,Rds<97mohm
D G 1U_0402_6.3V6K R441 0.1U_0402_16V7K
4
FDS6676AS_SO8 1 R415 2 B+ 100K_0402_5% ZP@
2
220K_0402_5% ZP@ 1
1 1
4.7U_0805_10V4Z
3
6
S
R440 Q45 PJ28
2
0.1U_0402_25V6
1
G
C474 C477 R416 Q23A ODD_PWR# 1 2 2 JUMP_43X79
820K_0402_5% @
2 2 +5VS_ODD
1
2 1 @ 2 SUSP 47K_0402_5% 2
D
1
2N7002KDWH_SOT363-6 R385 0_0402_5% AO3413_SOT23
2
1
6
2 C217 ZP@
1
C200 Q53A 0.01U_0402_25V7K

0.1U_0402_16V4Z 1 ZP@
@ 2 2N7002KDWH_SOT363-6
1 <25> ODD_PWR
ZP@
Need to delay after
1
4 +3VS ramp up 4

DC-DC INTERFACE
0.3
LA-9869P
A B C D E
A B C D
EMI Part (47.1)

Other component (37.1)
A51 need add fuse PL1 EMI@
HCB2012KF-121T50_0805
1 2
VIN
1 1
PL3 EMI@
@PJP1
@ PJP1 PF1 HCB2012KF-121T50_0805
1 1 2 DC_IN_S1 1 2
1 2
2 3 7A_32V_S1206-H-7.0A
3 4
4
ACES_50299-00401-001
1
PC102 EMI@ PC103 EMI@ PC101 EMI@ PC104 EMI@
1000P_0603_50V7K 100P_0603_50V8 100P_0603_50V8 1000P_0603_50V7K
2
2 For ML1220 RTC (38.2) 2
- PBJ101 @ + PR101
560_0603_5%
PR102
560_0603_5%
2 1 1 1
2 +RTC_R 2
+RTCBATT
ML1220T13RE
+RTC
3 3
4 4

DCIN/PRECHARGE
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
LA-9869P
Date: Sheet 38 of 49
A B C D
A B C D
PL4 EMI@
HCB2012KF-121T50_0805
1 2 EMI Part (47.1)
Other component (37.1)
VMB
@ PL5 EMI@
ACES_50299-01001-W01 PF2 HCB2012KF-121T50_0805
1 BATT_S1 1 2 1 2
1 2 BATT+
2 3 10A_125V_TR2/6125FF10-R
3 4 BATT_P4
4 5 BATT_P5
5 6 OTP (39.7)
1
EC_SMDA PC8 EMI@
6 7 PC7 EMI@
1
EC_SMCA
7 8 PR14 1000P_0402_50V7K 0.01U_0402_25V7K
2
1
8 9 1K_0402_1%
1
9 10
10
2
PJP2
+3VL
<34,40> ADP_I
12.1K_0402_1%
2
1
1K_0402_1%
PR4
PR1
PR16
2
6.49K_0402_1% @ PR2 @ PR5
2 1 0_0402_5% 0_0402_5%
+3VL 1 2 1 2
100K_0402_1%_TSM0B104F4251RZ
PR19 <34> PROCHOT_IN <34> VCIN0_PH
1 2
BATT_PRES <34>
1
20K_0402_1%
1K_0402_1%
1
@ PC11
PR3
PH1
0.1U_0402_10V7K
2
2
PR20 PR21
2
100_0402_1% 100_0402_1%
1
EC_SMB_DA1 <31,34,40,9>
2 2
EC_SMB_CK1 <31,34,40,9>
3 3
4 4

BATTERY CONN / OTP
A B C D
A B C D
for reverse input protection
Charger controller (40.1), Support component (40.2)
1
D
2 PQ209
G SSM3K7002FU_SC70-3
S
3
PR225 PR226
1 2 1 2
10U_0805_25V6K
1
1M_0402_5% 3M_0402_5%
EMI Part (47.1) 1
PC211
TPCA 8057 PQ205
VIN P1 P2 B+ S TR SI7716ADN
2
PQ203 SI7716ADN-T1-GE3_POWERPAK8-5 PR211 PL201EMI@ PQ207
0.01_1206_1% 1UH_NRS4018T1R0NDGJ_3.2A_30%
1 1 1 4 1 2 1
2200P_0402_25V7K
2 2 2
10U_0805_25V6K
5 3 3 5 2 3 5 3
0.1U_0402_25V6
1
PC213
@EMI@ PC214
2200P_0402_50V7K
0.01U_0402_50V7K
1
PC231 VIN
4
PC234
2
2
1 2
PC230
2
1
2
3
2
PC236
0.1U_0402_25V6 PD230
2
BQ24725_ACDRV_1 BAS40CW_SOT323-3
BQ24725_BATDRV 1 2 BQ24725_BATDRV_1
0.1U_0402_25V6
0.1U_0402_25V6
0.047U_0402_25V7K PR233
1 1
10_1206_1%
4.12K_0603_1%
PC237
1
PC238
PC235
PR228
1 2
5
2
1
2.2_0603_5%
PR229
PD231
BQ24725_VCC
2
RB751V-40_SOD323-2 PR210 PQ201
0_0603_5% AON7408L
DH_CHG 1 2 4
BQ24725_BST 2
BQ24725_REGN2
4.12K_0603_1%
4.12K_0603_1%
2
PC239 2
BQ24725_LX
1
1 2 BATT+
PR235
PR234
DH_CHG
PL202
3
2
1
1U_0603_25V6K PC205 4.7UH_ETQP3W4R7WFN_5.5A_20% PR227
BQ24725_ACP
BQ24725_ACN
1 2 0.01_1206_1%
BQ24725_LX 1 2 CHG 1 4
2
1U_0603_25V6K
5
2 3
20
19
18
17
16
4.7_1206_5%
PU200
CSON1
CSOP1
1
@EMI@ PR206
BTST
PHASE
HIDRV
VCC
REGN
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
21 PQ202
PAD
0.1U_0402_25V6
0.1U_0402_25V6
PC221
PC222
PC223
1
1
1
1 15 DL_CHG 4 AON7406L
ACN LODRV
PC240
PC241
2
2
2
2
2 14
680P_0603_50V8J
@
ACP GND PR236
3
2
1
2
1
10_0603_1%
SRP1 2 CSOP1
@EMI@ PC206
BQ24725_CMSRC 3 13
CMSRC SRP
1
PR237
2
6.8_0603_5%
BQ24725_ACDRV 4 12 SRN1 2 CSON1
2
ACDRV SRN
5 11 BQ24725_BATDRV PC242
ACOK BATDRV 0.1U_0603_16V7K
EMI Part (35.33)
ACDET
IOUT
SDA
SCL
ILIM
1 2 +3VALW
+3VL
6
10
PR239 10K_0402_1% BQ24725RGRR_QFN20_3P5X3P5
3 3
BQ24725_ILIM 1 2
PR241
0.01U_0402_25V7K
<34> ACIN VIN
100K_0402_1%
357K_0402_1%
1
PC243
PR242
1
BQ24725_ACDET
VIN
1
422K_0402_1%
2
1
PR247
PR244
309K_0402_1%
PR248
2
10K_0402_1%
2
1 2
ADP_V <34>
Vin Dectector
0.1U_0402_25V6
1
66.5K_0402_1%
EC_SMB_CK1 <31,34,39,9>
1
1
@ PC247
Min. Typ Max. PR249
1
PR245
0.1U_0402_10V7K
PC244
47K_0402_1%
H-->L 17.23V
2
EC_SMB_DA1 <31,34,39,9>
2
2
L--> H 17.63V
2
@ PR246
PC245 0_0402_5%
2 1 1 2
ILIM and external DPM ADP_I <34,39>
100P_0402_50V8J
3.97A For A51 ADP_V function
1
@ PC246
0.1U_0402_10V7K
2
4 4
Please locate the RC

Near EC chip
2011-02-22
CHARGER
Custom 0.1
A B C D
A B C D
3/5VALW controller (35.1), Support component (35.2)
1 5V_3.3V controller (35.1), Support component (35.2) 1
PR350
30K_0402_1%
EMI Part (47.1) 1 2
B+ PR330
EMI@ PL331 3/5V_B+
14K_0402_1%
1 2 3/5V_B+
HCB2012KF-121T50_0805
210K_0402_1%
174K_0402_1%
1
1
1 2 PR331
56K_0402_1%
20K_0402_1%
PR337
PR342
PR357
1 2 FB_3V PR351
10U_0805_25V6K
2200P_0402_50V7K
10U_0805_25V6K
VL 19.1K_0402_1%
FB_5V 1 2
1
PC340
2
1
1
@EMI@ PC339
PC361
<34> POK
100K_0402_1%
1
PR335
2
2
5
AON7408L
1
PQ331
PQ351
4
FB2
ENTRIP2
ENTRIP1
FB1
TON
21
2
PAD AON7408L
6
PC335 PR333 PGOOD 20 4
0.1U_0402_10V7K 0_0402_5% BYP1 PR355 PC355
1
2
3
1 2 BST1_3V 1 2 BST_3V 7 0_0402_5% 0.1U_0402_10V7K
BOOT2 19 BST_5V 1 2 BST1_5V 1 2
PL332 BOOT1
3
2
1
UG_3V 8
2 UGATE2 18 UG_5V 2
4.7UH_ETQP3W4R7WFN_5.5A_20% UGATE1 PL352
1 2 LX_3V 9 2.2UH_MMD-06CZ-2R2M-V1_8A_20%
+3VALWP PHASE2 17 LX_5V 1 2
PHASE1 +5VALWP
5
LG_3V 10
LGATE2
1
16 EMI Part (47.1)

4.7_1206_5%
LG_5V
150U_D2_6.3VY_R15M
ENLDO
SECFB
LGATE1
1
@EMI@ PR336
4.7_1206_5%
LDO5
LDO3
1
VIN
@EMI@ PR356
150U_D2_6.3VY_R15M
+
PC354
1
4 PU330
1 SNUB_3V 2
11
12
13
14
15
+
PC353
RT8243AZQW_WQFN20_3X3
2
SNUB_5V
2 4
AON7406L PR334 +3VLP 2

1
2
3
PQ352
680P_0603_50V8J
680P_0603_50V8J
PQ332 499K_0402_1%
1
1 2 PC341 FDMC7692S_MLP8-5
3/5V_B+
3
2
1
@EMI@ PC336
4.7U_0603_10V6K
VL
1
100K_0402_1%
@EMI@ PC356
1U_0603_10V6K
0.1U_0603_25V7K
2
1
2
1
PC360
PR338
PC342
2
2
1
<35> ENLDO PC344
2
4.7U_0603_10V6K
EMI Part (35.33)
2
PR340 5V
2.2K_0402_1%
1 2 Peak Current 10A
<34> EC_ON OCP current 12A
3
@ PR341 3
0_0402_5%
3.3V 1 2 FSW=390kHz
Peak Current 8A <34> VS_ON Delta I=2.791A,ripple=2.791*15m=41.865mV
4.7U_0805_25V6-K
100K_0402_5%
DCR 18~20mohm
1
OCP current 10A
PC343
@ PR332
Delta I=1.160A ,ripple=1.160 x17m=19.27mV 2 TYP MAX
FSW=455kHz H/S Rds(on) ::27mohm , 34mohm
1
@
DCR 35mohm +/-15% L/S Rds(on) :10.8mohm , 13.6mohm
TYP MAX
H/S Rds(on) :27mohm , 34mohm @ PJ332 @ PJ331
2 1 1 2
L/S Rds(on) :19mohm , 23.5mohm +3VLP 2 1 +3VL +3VALWP 1 2 +3VALW
JUMP_43X39 JUMP_43X118
(100mA,20mils ,Via NO.= 1) (8A,160mils ,Via NO.= 16)
@ PJ351
1 2
+5VALWP 1 2 +5VALW
JUMP_43X118
(12A,240mils ,Via NO.= 24)
4 4

3VALW/5VALW
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
A B C D
A
DDR controller (35.3), Support component (35.4)
EMI@ PL151
HCB2012KF-121T50_0805
EMI Part (47.1)
B+ 1 2 1.5V_B+ PR155
0_0603_5%
BST_1.5V-1 1 2 BST_1.5V +1.5V
PC152@EMI@
2200P_0402_50V7K
10U_0805_25V6K
DH_1.5V +0.75VSP
0.1U_0603_25V7K
PC154
2
PC155
10U_0603_6.3V6M
10U_0603_6.3V6M
SW_1.5V
1
PC159
PC160
1
5
DL_1.5V
16
17
18
19
20
PU150
2
BOOT
VTT
PHASE
UGATE
VLDOIN
21
AON7408L
PAD
PQ151
4 15 1
LGATE VTTGND
PR158 14 2
PL152 17.4K_0402_1% PGND VTTSNS
1
2
3
1UH_VMPI0703AR-1R0M-Z01_11A_20% 1 2CS_1.5V
2 1 13 3
+1.5VP PC162 CS RT8207MZQW_WQFN20_3X3 GND
5
1U_0603_10V6K
1 2 12 4 VTTREF_1.5V
FDMC7692S_MLP8-5
PR159 VDDP VTTREF
1
5.1_0603_5%
330U_D2_2V_Y
1
+1.5VP
PQ152
1 2 VDD_1.5V 11 5
+ VDD VDDQ
PC157
PR156 @EMI@ 4
PGOOD
1
4.7_1206_5%
TON
+5VALW PC163
FB
S5
S3
SNUB_+1.5VP 2
1
2 0.033U_0402_16V7K
2
PC164
1
2
3
10
6
1U_0603_10V6K
+5VALW
2
PR160
10.2K_0402_1%
FB_1.5V 2 1 +1.5VP
TON_1.5V
1
PC156 @EMI@
680P_0402_50V7K
2
2
PR161
887K_0402_1% PR162
@ PR163 1.5V_B+ 1 2 10K_0402_1%
0_0402_5%
1 2 EN_1.5V
<34,37> SYSON
1
1 1
EN_0.75VSP
1
@ PC166 PR164
@ PJ151 0.1U_0402_10V7K 0_0402_5%
2 1 2 1
2
2 1 <34,37> SUSP#
JUMP_43X118
@ PJ750 @ PJ152
1
2 1 2 1
+0.75VSP 2 1 +0.75VS +1.5VP 2 1 +1.5V @ PC167
JUMP_43X79 JUMP_43X118 0.1U_0402_10V7K
2
(0.5A,40mils ,Via NO.= 1) (12A, 480mils ,Via NO.= 24)
OCP=13.8A
1.5V
Peak Current 12A
OCP current 13.34A
FSW=300kHz
DCR 8.3 ~ 10mohm
TYP MAX
H/S Rds(on) :27mohm , 34mohm
L/S Rds(on) :10.8mohm , 13.6mohm
STATE S3 S5 1.5VP VTT_REFP 0.75VSP

S0 Hi Hi On On On
Off
S3 Lo Hi On On (Hi-Z)
S4/S5 Lo Lo Off Off Off

(Discharge) (Discharge) (Discharge) Security Classification Compal Secret Data Compal Electronics, Inc.
Note: S3 - sleep ; S5 - power off THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.5VP/0.75VSP/1.8VSP
A
A B C D
1.8V controller (35.15), Support component (35.16)

1 1
+3VS
Note:Iload(max)=3A
PU450 PL451
1UH_NRS4018T1R0NDGJ_3.2A_30%
4 3 1 2
22P_0402_50V8J
22U_0603_6.3V6M
IN LX +1.8VGSP
1
5 2 @EMI@
PG GND PR451
1
PC458
PR456
1
6 1 100K_0402_1%
PC450
22U_0603_6.3V6M
22U_0603_6.3V6M
FB EN 4.7_1206_5%
2
SY8032ABC_SOT23-6
1
PC452
PC451
FB=0.6V 1.8V
2 SNB_1.8V
PR452 Peak Current 0.5A
2
220K_0402_1%
1
<14,24,46> VGA_PWRGD 1 2 +1.8_EN OCP current 3.5A
PR453 FSW=800kHz
1
@EMI@ PC456 49.9K_0402_1%
1
@ PR454 680P_0603_50V7K
2
PC453 22K_0402_5%
H/S Rds(on) :100mohm ,
2
@ PJ451 0.1U_0402_16V7K
2
L/S Rds(on) :80mohm ,
2
1 2
+1.8VGSP 1 2 +1.8VGS
2
JUMP_43X79 2
(0.5A,20mils ,Via NO.=1)

@ PJ401
1 2 PR404
+1.1VALWP 1 2 +1.1VALW 0_0402_5%
2 1
JUMP_43X79 1.1VPWR_EN <34>
(5.3A,220mils ,Via NO.=10)
2
PR405
10K_0402_1%
EMI Part (47.1)
1
EMI Part (47.1)
@EMI@ PR401 @EMI@PC403
4.7_1206_5% 680P_0603_50V7K
3 PL402 EMI@ 1 2SNB_1.1V 1 2 3
HCB2012KF-121T50_0805 PU400
B+ 2 1 B+_1.1V 8
IN EN
1 PC405
0.1U_0603_25V7K
10U_0805_25V6K
2200P_0402_50V7K
6 1 2 PL401
BS
1
1
PC410
1UH_PCMB063T-1R0MS_12A_20%
+1.1VALWP
@EMI@ PC404
9 10 LX_1.1V 1 2
GND LX
2
84.5K_0402_1%
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
S CER CAP 4700P 25V K X7R 0402
1
4
PR402
FB
PC409
PC408
PC407
PC406
PC401
PC412
3 7
+3VALW +3VALW
2
ILMT BYP
2
1.1V
2
2 5 FB=0.6V @
4.7U_0603_6.3V6K
2.2U_0603_6.3V6K
PG LDO
1
Peak Current 5.3A

PC411
1
1
PC402
SY8206DQNC_QFN10_3X3 PR406
OCP current 12A
2
1K_0402_1%
FSW=800kHz
2
2
1
PR403
H/S Rds(on) :22mohm , 100K_0402_1%
2
4
The current limit is set to 8A, 12A or 16A when this pin 4
is pull low, floating or pull high respectively.

+1.8VALWP
Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9869P
A B C D
5 4 3 2 1
PR702
D 0_0402_5% D
2 1
VR_ON <34,37,45>
EMI Part (47.1) EMI Part (47.1)

@EMI@PR706
@EMI@PR706 @EMI@PC706
EMI@ PL702 4.7_1206_5% 680P_0603_50V7K
1 2SNB_1.2V 1 2
HCB2012KF-121T50_0805 PU700
B+ 2 1 B+_1.2V 8
IN EN
1 PC704
0.1U_0603_25V7K
2200P_0402_50V7K
10U_0805_25V6K
6 1 2 PL701 (7A,280mils ,Via NO.= 14)
BS
1
1UH_MMD-05CZ-1R0M-M7L_7A_20%
PC709
9 10 LX_1.2V 1 2
+1.2VS
@EMI@ PC702
GND LX
102K_0402_1%
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1
S CER CAP 4700P 25V K X7R 0402
1
1
1
4
PR701
FB
PC713
PC710
PC708
PC711
PC703
PC712
3 7
2
+3VS +3VS
2
ILMT BYP
2
2 5 @
4.7U_0603_6.3V6K
2.2U_0603_6.3V6K
C PG LDO C
1
PC701
1.2V
1
SY8206DQNC_QFN10_3X3 PR407
PC707
Peak Current 7A
2
1K_0402_1%
2
OCP current 12A
2
1
FSW=800kHz PR703
100K_0402_1%
2
PU702
APL5508-25DC-TRL_SOT89-3
B B
2 3
+3VS IN OUT
+2.5VSP
4.7U_0805_6.3V6K
GND
1
PC798
1U_0402_6.3V6K 1 @ PR798
PC799
150_1206_5%
2
@ PJ702
+2.5VSP 1 2 +2.5VS
1 2
JUMP_43X39
(0.75A,30mils ,Via NO.= 2)
A A

+1.2VSP/+2.5VSP
Custom 0.1
LA-9869P
5 4 3 2 1
A B C D E
10/9 NB_Vdroop=-4m ohm EMI Part (47.1) PL501 EMI@

PR502
2K_0402_1%
PC502
330P_0402_50V7K
CPU controller (36.1),Driver (36.2) Support component (36.3) CPU_B+
HCB2012KF-121T50_0805
1 2
B+
2 1 1 2 PL506
2200P_0402_50V7K
100U_25V_M
100U_25V_M
PR504 PR505 PC503 PR542 HCB2012KF-121T50_0805 EMI@
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
PR503 1 2
+APU_CORE_NB 2.94K_0402_1% 137K_0402_1% 390P_0402_50V7K 0_0603_5% 1 1
+APU_CORE
1
@EMI@ PC545
1 2 1 2 1 2 1 2 1 2
UGATE1
@PC511
PC501
PC504 + +
TDC (AB)22A (C)36A
1
PC537
PC538
PC539
@PR507
@PR507
2
10_0402_1% 1000P_0402_50V7K PC505
2
1 2 1 2 1 2 1 2
PR508
PR509
42.2K_0402_1%
EDC (AB)35A (C)50A 2 2
2
<7> APU_VDDNB_SEN @ PC507
0_0402_5%
1 2 301_0402_1%
100P_0402_50V8J OCP current (AB)43.56A PL502
1
Load line -2.1mV/A 0.22UH_MMD-06DZNR22ME_25A_20%
330P_0402_50V7K PHASE1
FSW=450kHz +APU_CORE
4.7_1206_5%
1 PR510 1
@EMI@
VSUM+_NB 2.2_0603_5%
DCR 1mohm~1.2mohm
D1
G1
S1/D2
BOOT1 1 2 1 2 PR513 PR514
1
1
PQ501
TYP MAX 10K_0402_1% 10K_0402_1%
FDMS3664S_POWER56-8-7
PR506
0.022U_0402_25V7K
0.1U_0402_10V6K
PC508 ISEN11 2 1 2 ISEN2
H/S Rds(on) :8.5mohm , 11mohm
1
1
11K_0402_1%
PC509
2.61K_0402_1% 0.22U_0603_25V7K
G2
S2
S2
S2
680P_0603_50V7K
PC510
PR511 PR515
PR512
3.65K_0402_1%
1 2
1 2
10/9 OCP=50A for 35W(511 ohm)
6
@ VSUM+1 2
EMI@
@EMI@ PC506
PL507
2
PH502 PR517
+APU_CORE_NB LGATE1 1_0402_1%
CPU_B+_NB HCB2012KF-121T50_0805
1 2
2
VSUM-1 2
10K_0402_1%_ERTJ0EG103FA PR518
681_0402_1%
TDC (AB)22A (C)30A
CPU_B+
2
VSUM-_NB 1 2 EDC (AB)33A (C)40A

PR520 OCP current (AB)41.51A
2
1
PC551 @ PR519 @ PC512 121K_0402_1% CPU_B+

0.1U_0402_25V6 1 2 1 2 Load line -4mV/A EMI Part (47.1)
2200P_0402_50V7K
2
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
100_0402_1% 220P_0402_50V7K
FSW=450kHz
FCCM_NB 1
1
@EMI@ PC548
DCR 1mohm ~1.2mohm
NB_LGATE1
NB_UGATE1
NB_PHASE1
@
1 PC559
1
1
PC542
PC540
PC541
2
PWM2_NB
0.22U_0402_16V7K TYP MAX
2
PR562 PR560
H/S Rds(on) :7.4mohm , 8.8mohm
2
2
2
10K_0402_1% 0_0603_5%
1 2 UGATE2 1 2
L/S Rds(on) :2.6mohm , 3.1mohm PL503
@ PC560 48
47
46
45
44
43
42
41
40
39
38
37
0.22U_0402_16V7K 0.22UH_MMD-06DZNR22ME_25A_20%
2 1 PU501
PR523 PHASE2
ISEN1_NB
ISUMP_NB
ISUMN_NB
VSEN_NB
FB_NB
COMP_NB
PGOOD_NB
FCCM_NB
PWM2_NB
LGATEX
PHASEX
UGATEX
+APU_CORE
4.7_1206_5%
PR522 27.4K_0402_1% PR521
7
2 1 2 1 2 +5VS 0_0402_5% 2.2_0603_5% 2
1 PR564 2 1 36 NB_BOOT1 PR527 BOOT2 1 2 1 2 PR524 PR525
D1
G1
S1/D2
ISEN2_NB BOOTX
PQ502
1
10.5K_0402_1% PH501 0_0603_5% CPU_B+ 10K_0402_1% 10K_0402_1%
FDMS3664S_POWER56-8-7
PR516
PC514 2 1 2 35 1 2 PC513 ISEN21 2 1 2 ISEN1
1000P_0402_50V7K 470K_0402_5%_TSM0B474J4702RE NTC_NB VIN 0.22U_0603_25V7K
680P_0603_50V7K
G2
1 2 3 34
S2
S2
S2
BOOT2 PC515 PR530
IMON_NB BOOT2 0.22U_0603_50V7K @EMI@ 3.65K_0402_1%
1 2
2PR528 1 4 33 UGATE2 VSUM+1 2
6
@ PR532
2
<7> APU_SVC SVC UGATE2
PC516
127K_0402_1% 0_0402_5%
1 2 5 32 PHASE2 PR531
<34,7> H_PROCHOT# VR_HOT_L PHASE2 1_0402_1%
2
6 31 LGATE2 PR569 @EMI@VSUM-1 2
<7> APU_SVD @ PR533 SVD S IC ISL6277HRZ-TR5570 QFN 48P PWM LGATE2 0_0402_5% +5VALW
+1.5V 0_0402_5%
1 @ PR5592 1 2 7 30 1 2
+1.5V VDDIO VDDP
2 1 PC555 0.1U_0402_25V6 LGATE2
100K_0402_1% 8 29 1 PR501 2
@ PR535 SVT VDD
<7> APU_SVT
0_0402_5% EMI Part (47.1)
PC517 1 2 9 28 1_0603_5% CPU_B+_NB
@ PR536 ENABLE PWM_Y
1
1000P_0402_50V7K<34,37,44> VR_ON
1U_0603_16V6K
PC518
0_0402_5% PC519
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
1 2 1 2 10 27 LGATE1 1U_0603_16V6K
<23,7> APU_PWRGD PWROK LGATE1
1
@EMI@ PC550
2
2
2PR537 1 11 26 PHASE1
1
1
1
PC543
PC544
PC520
118K_0402_1% IMON PHASE1
@ PQ503
+APU_CORE_NB
1 2 1 PR539 2 12 25 UGATE1
2
NTC UGATE1 PR561 CSD87351Q5D_SON8~D
PGOOD
27.4K_0402_1%
2
2
2
BOOT1
1
ISUMN
ISUMP
@ @ @
COMP
0_0603_5% @
ISEN3
ISEN2
ISEN1
VSEN
PR538 PH503
RTN
1 2 2
FB2
10.5K_0402_1% 2 1
FB
TP
PU502 @ PL504
470K_0402_5%_TSM0B474J4702RE
+3VS 1 8 0.22UH_MMD-06DZNR22ME_25A_20%
UGATE PHASE
13
14
ISEN1 15
16
17
18
19
20
21
22
23
24
49
+5VS 0_0402_5% PR568 @ PR541 @ 7

1 2 2 7 @PR570 +5VALW 2.2_0603_5% PC521 3 6 APU_NB_SW2
BOOT FCCM 1 2 1 2 5
1
0_0402_5% 0_0402_5%
4.7_1206_5%
BOOT1
3 @ PR540 2
@1 ISEN2 PR558 PWM2_NB 3 6 1 2 4 3
1
PWM VCC
PR526
@PC524 0.22U_0603_25V7K
100K_0402_1%
1
4 5 @ PR578
0.22U_0402_16V7K
0.22U_0402_16V7K
PR563 GND LGATE

2
2
1U_0603_16V6K
2
PC523
@ 10K_0402_1% 10K_0402_1%
2
2
@ISL6208BCRZ-T_QFN8_2X2 @EMI@ISEN2_NB @PR580

@ PR580
PC522
1 2 1 2
8
VGATE <34> 10K_0402_1%
1
1
@ PR579
1 2
VSUM- CPU_B+_NB 3.65K_0402_1%
680P_0603_50V7K
PC526
ISEN1_NB 1
1
VSUM+_NB 2
PC525 EMI Part (35.33)
VSUM+ 1 2 @PR577
2
@EMI@ 1_0402_1%
EMI Part (35.33)
1
10P_0402_50V8J 1
VSUM-_NB 2
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
0.15U_0402_10V6K
0.022U_0402_16V7K
1
1
11K_0402_1%
PC527
2.61K_0402_1% PC528 PR546 PC530
1
PC556
@EMI@PC556
PC529
PR544 1 2 1 2 1 2
1
1
PC552
PC553
PC554
PR545
1 2
PQ504
330P_0402_50V8J
1000P_0402_50V7K 301_0402_1% 100P_0402_50V8J
2
@EMI@
1
PR574 CSD87351Q5D_SON8~D
PC531
2
2
1
2
PH504 PR548 PR549 PC532 0_0603_5%

1 2 1 2 1 2 NB_UGATE1 1 2 2
2
10K_0402_1%_ERTJ0EG103FA PR550 @
422_0402_1% 1.65K_0402_1% 137K_0402_1% 390P_0402_50V7K PL505
2
VSUM- 1 2 7 0.22UH_MMD-06DZNR22ME_25A_20%
4.7_1206_5%
2
PR551 NB_PHASE1 3 6 APU_NB_SW

+APU_CORE_NB
1
@PR552
@ PR552 PR572 5
2K_0402_1%
2
4
PC533 @ PR553 @ PC534 PC535 32.4K_0402_1% 2.2_0603_5%
1
1
NB_BOOT1 2 1 2 @ PR571 @PR576
@ PR576
0.1U_0402_25V6 1 2 1 2
PR573
2 1
2
0.01U_0402_50V7K 10K_0402_1% 10K_0402_1%

1
100_0402_1% 820P_0402_50V7K PC557 1

ISEN1_NB 2 1 2 ISEN2_NB
1
1
680P_0603_50V7K
PC536 0.22U_0603_25V7K
@EMI@
8
@ PR554 @PR555
@PR555 PR575
1 2
680P_0402_50V7K
10/9 OCP=62.5A for 35W (634)
1
4 0_0402_5% 0_0402_5% NB_LGATE1 3.65K_0402_1% 4

1
VSUM+_NB 2
@EMI@ PC558
PR556 PR557
2
2
1 2 1 2 PR566
+APU_CORE 10/9 CPU_Vdroop=-2.1m ohm
2
1_0402_1%
10_0402_5% 10_0402_5% 1
VSUM-_NB 2
<7> APU_VDD_RUN_FB_L APU_VDD_SEN <7>

Issued Date 2011/07/29 Deciphered Date Title
+CPU_CORE/VDDNBP
Custom QML70 LA-8371P 0.1
A B C D E
5 4 3 2 1
D D
VGA controller (43.1),Driver (43.2) Support component (43.3)

EMI Part (47.1)
EMI@ PL801
HCB2012KF-121T50_0805 +VGA_CORE
B+
1 2 GPU_B+ TDC 21A
EDC 31.5A
1
10U_0805_25V6K
10U_0805_25V6K
2200P_0402_50V7K
PR801
PR802
1_0603_5%
OCP current 40A
PC803
PC804
@EMI@ PC802
0.22U_0603_25V7K
1
1
1_0603_5% FSW=300kHz
PC807
+5VALW 1 2
DCR 1.4m ohm +-5%
1 2
2
1
PC806
1U_0603_6.3V6M TYP MAX
H/S Rds(on) :11.7mohm , 14.5mohm
2
PR804
+5VALW
10_0402_5%
2 1 GPU_ISUM+
TR TPCA8065-H 1N PPAK56-8
5
PC809 PR805 PC810
1000P_0402_50V7K GPU_ISUM- 2.2_0603_5% 0.1U_0603_25V7K
1
2 1 BST_GPU 2 1 2 1
PQ801
<15> VSS_GPU_SENSE PR841
2
C PC812 0_0402_5% C
330P_0402_50V7K 4
<15> VCC_GPU_SENSE 2 1
29
10
11
12
13
14
1
2
8
9
+VGA_CORE PC811
AGND
RTN
ISUM+
VDD
VIN
IMON
BOOT
ISUM-
1 2 330P_0402_50V7K
3
2
1
PR806 PL802
10_0402_5%
7 15 DH_GPU 0.36UH_PDME064T-R36MS_24A_20%
VSEN UGATE
6 16 LX_GPU 1 4
FB PHASE +VGA_CORE
5
5 17 2 3
S TR TPCA8059-H 1N PPAK56-8
S TR TPCA8059-H 1N PPAK56-8
COMP VSSP
1
@EMI@
4 PU801 18 DL_GPU PR808
PQ802
PQ803
VW LGATE
1
ISL62881CHRTZ-T_TQFN28_4X4 4.7_1206_5%
PR813 2 1 3 19 PR810 @ PR811 1
560U_D2_2VM_R4.5M
PR812 226K_0402_1% PC815 PR809 RBIAS VCCP 4 4 3.65K_0805_1% 0_0402_5%
2
2.37K_0402_1% 1000P_0402_50V7K 47K_0402_1% 2 20 +
PC899
1 2 1 2 1 2 2 1 PGOOD VID0 2 1
+5VALW @EMI@
2
147K for CPU 1 21 PR814 PR815 PH7
DPRSLPVR
CLK_EN# VID1
2
PC814 1_0603_5% PC816 1 2 1 2 2
47K for GPU
3
2
1
3
2
1
1
390P_0402_50V7K 680P_0603_50V7K
VR_ON
+3VS
2.61K_0402_1% 10KB_0402_5%_ERTJ1VR103J
VID6
VID5
VID4
VID3
VID2
1
PC819 PC817
2
56P_0402_50V8 2.2U_0603_6.3V6K B value:4250K2%
1 2 1 2 1 2 2 1
28
27
26
25
24
23
22
1 2
PR816 PR817 PR818
1
PC818 715_0402_1% 8.06K_0402_1% 11K_0402_1%

1000P_0402_50V7K PR835 +3VGS
Layout Note:
0.1U_0402_16V7K
120K_0402_1% PR718
1.8K_0402_1% Place near Choke 1 2
2
1
1
1
PR832
PC820
PR823
@ PR830
PR831
@ PR833
10K_0402_1%
10K_0402_1%
10K_0402_1%
10K_0402_1%
10K_0402_1%
.047U_0402_16V7K
1
B <14,24,43> VGA_PWRGD PR29 B

1 2
2
2
1
0_0402_5%
PC823
PC821
0.1U_0402_16V7K
2
2
1
GPIO6 GPIO30 GPIO29 GPIO20 GPIO15
VID5 VID4 VID3 VID2 VID1 VDDC PR822
1.2K_0402_1%
0 1 1 1 0 1.15V GPU_ISUM+
2
0 1 1 1 1 1.125V
<13>
GPU_ISUM-
GPU_DPRSLPVR
0.1U_0402_25V6
1 0 0 0 0 1.100V
1
1
1
0_0402_5%
1 0 0 0 1 1.075V
0_0402_5%
0_0402_5%
PR837
PR840
@ PR836
@ PR838
PR839
0_0402_5%
0_0402_5%
10K_0402_1%
10K_0402_1%
10K_0402_1%
10K_0402_1%
10K_0402_1%
1 0 0 1 0 1.050V
47K_0402_5% PR828
@
2
2
2
2
2
1
1 0 0 1 1 1.025V
2
2
2
1
PR824
PR826
PR821
1 0 1 0 0 1.000V
PR827
PR825
1PC822
1 0 1 0 1 0.975V
1
1
1
2
1
2
@ @ @
1 0 1 1 0 0.950V Default @ @
1 0 1 1 1 0.925V
1 1 0 0 0 0.900V
<13>
<14,24,47>
PXS_PWREN
GPU_VID1
<13>
<13>
<13>
<13>
GPU_VID4
GPU_VID2
GPU_VID3
1 1 0 0 1 0.875V
GPU_VID5
1 1 0 1 0 0.850V
1 1 0 1 1 0.825V
A 1 1 1 0 0 0.800V A
1 1 1 0 1 0.775V

+VPU_COREP
C 0.1
LA-9869P
5 4 3 2 1
A B C D
1 1
+1.1VALW +5VS
1
2 2
PJ602
1
JUMP_43X79
2
2
1
PC601
1
PC604 1U_0603_6.3V6M
22U_0805_6.3V6M 2
2
PU600
6
PR602 +0.95VS_VIN 5 VCNTL 3
VIN VOUT +0.95VGSP
9 4
VIN VOUT
1
10K_0402_1%
39P_0402_50V8J
22U_0805_6.3V6M
1
1
1 2 +0.95VS_EN 8 PR604
<14,24,46> PXS_PW REN 1 2+0.95VS_POK 7 EN 2
PC600
PC603
10K_0402_1%
GND
+3VS POK FB @
PJ601
2
PR601
+0.95VGSP 1 2 +0.95VGS
2
1
@1K_0402_1% +0.95VS_FB
1
PC602 APL5916KAI-TRL_SO8 JUMP_43X118
1
0.01U_0402_25V6
2
PR603
56K_0402_1%
(4A,160mils ,Via NO.= 4)
2
3 3
0.95V
Peak Current 4A
OCP current 16A
FSW=800kHz

4 4

+1.5VPCIE/0.935V
0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9869P
A B C D
A
B
C
D
PC1006 PC1019 PC1027 PC1010 PC1000
0.22U_0402_16V7K 0.22U_0402_16V7K 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1 2 1
PC1007 PC1020
0.22U_0402_16V7K 0.22U_0402_16V7K
2 1 2 1
+APU_CORE
5
5
PC1008 PC1021 PC1018 PC1011 PC1001
+APU_CORE
0.01U_0402_50V7K 0.01U_0402_50V7K 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1 2 1
PC1009 PC1022
2
1
0.01U_0402_50V7K
+
0.01U_0402_50V7K
PC1100 2 1 2 1
560U_D2_2VM_R4.5M
PC1023
0.01U_0402_50V7K PC1015 PC1013 PC1002
Local
2 1 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1
PC1005
180P_0402_50V8J
2
1
+
PC1101 2 1
330U_D2_2V_Y
PC1024 PC1016 PC1014 PC1003
180P_0402_50V8J 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1
+APU_CORE
PC1026
180P_0402_50V8J
2 1
2
1
+
@
PC1102
330U_D2_2V_Y PC1025 PC1012 PC1004
180P_0402_50V8J 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1
4
4
PC1017
220P_0402_25V8K
CPU_Core output CAP (Including MLCC) 36.4
PC1069 PC1050 PC1076 PC1043

1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M
2 1 2 1 2 1 2 1
PC1060 PC1051 PC1077 PC1042

1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M
2 1 2 1 2 1 2 1
PC1034 PC1028
+VGA_CORE
PC1068 PC1052 PC1078 PC1040 0.22U_0402_16V7K 22U_0603_6.3V6M

1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M 2 1 2 1
2 1 2 1 2 1 2 1
PC1035
PC1061 PC1053 PC1044 PC1041 0.22U_0402_16V7K
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M 2 1
2 1 2 1 2 1 2 1 PC1029
Issued Date
+VGA_CORE
22U_0603_6.3V6M
PC1036 2 1
PC1062 PC1054 PC1045 180P_0402_50V8J
Security Classification
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 2 1 PC1030
+VDDC
+APU_CORE_NB
2 1 2 1 2 1 22U_0603_6.3V6M
2 1
3
PC1037
3
PC1063 PC1055 PC1079 180P_0402_50V8J

+APU_CORE_NB
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 2 1

2 1 2 1 2 1
PC1038 PC1031
PC1064 PC1056 PC1046 180P_0402_50V8J 22U_0603_6.3V6M
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 2 1 2 1
2011/07/29
2 1 2 1 2 1
PC1065 PC1057 PC1047

1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K
2 1 2 1 2 1
PC1066 PC1058 PC1048

1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K
2 1 2 1 2 1
PC1067 PC1059 PC1049

VGA
VDD
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K

VDD_NB
2
1
+
Richland
2 1 2 1 2 1
Compal Secret Data

PC1032
Deciphered Date
560U_D2_2VM_R4.5M
1
+
2@
PC1033
330U_D2_2V_Y
2
2
+APU_CORE_NB
1
4
560u x1
Local
330uF*9m
A3
4
Size
Title
Date:
15
22uF
10u x 4
GFX output CAP (Including MLCC) 36.5
Document Number
5
0.01u
1u x30
Monday, February 04, 2013

VGA_Core output CAP (Including MLCC 43.9)
LA-8712P
1
1
2
4
Sheet
0.22uF
48
of
Compal Electronics, Inc.
3
4
49
PROCESSOR DECOUPLING
180P
Rev
0.1
A
B
C
D
5 4 3 2 1
Version change list (P.I.R. List) Page 1 of 1

for PWR
Item Reason for change PG# Modify List Date Phase
D D
Item Time (When) Page (Where) Location/ Discription( How/ What) Request (Who)
1 EVT--2012/11/28 P39-PWR-BATTERYCONN/ OTP change PF2vandor for cost downplane PWR
2 EVT--2012/11/28 P41-PWR-+3VALW/5VALW change PR337 235Kto210K&PR5357156kto174k PWR
3 EVT--2012/11/28 P41-PWR-+3VALW/5VALW Delate PC351addPC353 150uD2 cap PWR
4 EVT--2012/11/28 P43-PWR_+1.8VSGP/+1.1VALWP change PC157 220uH=4.5mmto 330uD2capH=2mm PWR
5 EVT--2012/11/28 P43-PWR_+1.8VSGP/+1.1VALWP change PR158 16.2Kto17.4K PWR
C C
6 EVT--2012/11/28 P50-PWR-CPU_CORE change the PC1101560uto330u PWR
B B
A A

PIR (PWR)
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom VCUAA 0.2
5 4 3 2 1
5 4 3 2 1
HW PIR (Product Improve Record)

VDKTE LA-9869P SCHEMATIC CHANGE LIST
REVISION CHANGE: 0.2
GERBER-OUT DATE: 2012/12/25
-------------------------------------------------------------------------------------------------------------------------------------------------------------------
Item Page Date Request Solution
-------------------------------------------------------------------------------------------------------------------------------------------------------------------
1) 21 2012/12/04a For CRT undershoot issue Add R66 & R67 for CRT issue.
2) 14 2012/12/04a For VGA_CORE display unomunt CR103.
3) 22 2012/12/13a For EMI request Change L8/L9/L10/L11 part number for EMI requesrt.
4) 34 2012/12/13a For change EC PIN Change 1.1VPWR_EN from pin 71 to pin 127 and USB_EN#0 from pin84 to pin 23.
D
5) 19 2012/12/14a For LVDS translator Delete all of RTD2132S components. D
6) 31 2012/12/14a For S&C port wake Add CHG_PWR_GATE# on U15 pin 1 and connect to EC pin82.
7) 24 2012/12/17a For leakage with PXS_PWREN Change Power rail from +3VALW_FCH to +3VALW on R216 pin1
8) 07 2012/12/22a For leakge Delete R47, D18.
9) 24 2012/12/22a For NV suggestion Add R283 & Q30.
10) 34 2012/12/25a For S&C port wake Add RB25.
C C
B B
A A

HW-PIR
Custom 0.3
NHQAA LA-6831P M/B
5 4 3 2 1

La-9869p Vdkte r03

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La-9869p Vdkte r03

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Доступные форматы

A B C D E

LA-9869P REV 0.3 Schematic

2013-02-04 Rev 0.3

Security Classification Compal Secret Data Compal Electronics, Inc.

LVDS Conn. LVDS Translator DP0 (X2) GCLK

Sun Pro M2 Memory BUS(DDRIII)

page 27 DP1 Left USB2.0 Int. Camera Touch screen

Right USB 3.0 Right USB 3.0

Cardreader Conn. FCBGA-656

SPI Bus USB 3.0 USB 3.0

Date: Monday, February 04, 2013 Sheet 2 of 50

DESIGN CURRENT 0.15A +3VL

N-CHANNEL DESIGN CURRENT 4A +5VS

P-CHANNEL DESIGN CURRENT 330mA +3V_LAN

N-CHANNEL DESIGN CURRENT 4A +3VS

P-CHANNEL DESIGN CURRENT 1.5A +LCD_VDD

DESIGN CURRENT 0.5A 1.8VGSP

DESIGN CURRENT 0.75A 2.5VSP

N-CHANNEL DESIGN CURRENT 2A +1.5V_CPU

DESIGN CURRENT 2A +1.5VS

DESIGN CURRENT 1.5A +0.75VS

Security Classification Compal Secret Data Compal Electronics, Inc.

( O MEANS ON X MEANS OFF )

explain G-sensor KB LED Green Clock No Green Clock DIS UMA

BTO GSENSOR@ KBL@ GCLK@ NOGCLK@ VGA@ UMA@

S3 explain LVDS eDP

FCH SM Bus Address (SCL0/SDA0)

Power Device HEX Address

+3VS DDR SO-DIMM 1 A2 H 1010 001X b

EC SM Bus1 Address EC SM Bus3 Address

Power Device HEX Address Power Device HEX Address SIGNAL

S3 (Suspend to RAM) LOW HIGH

Security Classification Compal Secret Data Compal Electronics, Inc.

<12> PCIE_GTX_C_ARX_P[0..3] PCIE_ATX_C_GRX_P[0..3] <12>

<12> PCIE_GTX_C_ARX_N[0..3] PCIE_ATX_C_GRX_N[0..3] <12>

<23> UMI_MTX_C_FRX_N3 P_UMI_RXN[3] P_UMI_TXN[3] UMI_FTX_C_MRX_N3 <23>

+1.2VS 1 2 P_ZVDDP AR11 AP11 P_ZVSS 1 2

FAN Control Circuit +3VS

Security Classification Compal Secret Data Compal Electronics, Inc.

R15 1 2 1K_0402_5% MEM_MA_EVENT#

DP0_AUXP R25 2 1 1.8K_0402_5%

DISPLAY PORT MISC.

Thermal Shutdown Temperature:

Security Classification Compal Secret Data Compal Electronics, Inc.

L28 AA27 K9 AJ27

AM12 AN14 N14 AM9

AR12 AR15 N20 AM19

Security Classification Compal Secret Data Compal Electronics, Inc.

eDP Panel ENBKL

7 DQ0 DQ5 8 DDR_A_DQS#[0..7] <6>

203 SA1 SCL 204 FCH_SCLK0 <11,24,28>

Security Classification Compal Secret Data Compal Electronics, Inc.

DQ1 VSS3 DDR_B_D[0..63] <6>

DDR_B_DQS4 137 138 Layout Note:

Security Classification Compal Secret Data Compal Electronics, Inc.

PCIE_ATX_C_GRX_P[3..0] UV1A PCIE_GTX_C_ARX_P[3..0]

PCIE_ATX_C_GRX_P2 W38 U33 PCIE_GTX_ARX_P2 .1U_0402_16V7K CV5 1 2 VGA@ PCIE_GTX_C_ARX_P2 AK35

K35 L30 VGA@ SUN-PRO M2_FCBGA962

VGA@ SUN-PRO M2_FCBGA962

<24> PXS_RST# B 4 GPU_RST#

Security Classification Compal Secret Data Compal Electronics, Inc.

AC30 CEC_1 skHynix H5TQ2G63DFR-N0C 1.5V/1GHz 000 NC 4750

JTAG_TDI AN23 JTAG_TDI AL19 Serial-ROM input to ROM.

GPIO_28_FDO MLPS AL30 PD-reset