ECT 357L: Microprocessors I

Implementing Verilog Testbenches Using Xilinx ISE

1) Start the Xilinx ISE application, open Start All Programs Xilinx ISE 12.4i
Project Navigator or use the shortcut on the desktop ( ).
2) Open a project or create a new project (use the C:\ET357 directory)
3) Create a Verilog testbench file to exercise the digital design needing to be analyzed
a) In the Design panel select the Simulation option at the top and either right-
click on the project name in the and select the New Source option or select
the New Source . . . icon () ).
b) In the New Source Wizard window select the Verilog Module option and
provide a meaningful name for this waveform file (can be same as the project or
schematic names, remember to not use spaces in names) as shown in Figure 1.
Make sure the Add to project option is marked and select Next
i) Select Next on following dialogue to ignore port assignments, and then select
the Finish option to complete the testbench creation.

Figure 1: New source window setup for adding a waveform

4) Once the newly added Verilog module has opened, the test bench module must be
formatted
a) The module being tested by newly added testbench is referred to as the Unit
Under Test (UUT)
b) Testbench modules do not contain ports
i) Registers (reg) are used to drive the UUT input ports
ii) Wires (wire) are used to read the UUT output port signals
 c) The UUT must be instantiated (typically named UUT) using associated registers
and wires
d) Timed testing sequences are implemented inside the initial procedural block
i) always procedural blocks can be used to generate auxiliary timing and other
dynamic signals
e) Textual output can be generated using the $display Verilog system task as
$display(format string, argument list);
i) The format string contains both text and value/signal place holders such as:
%d = decimal value, %b = binary value, and %h = hexadecimal value
ii) The argument list provides the values to replace the place holders in the
format string
f) An example testbench Verilog module for testing the 2-bit add model from LSN2
is shown in Figure 2.

Connections
defined for
U UT

Instantiate
UUT

Display output test_out in binary

Test sequence

Figure 2: Sample testbench for AND gate module

5) The developed testbench Verilog module should appear with the UUT listed under it
within the Hierarchy window as shown in Figure 3.

Figure 3: "Sources" hierarchy view of testbench and UUT

6) The Verilog testbench can now be exercised.

a) Highlight the testbench file in the Hierarchy window
b) In the Processes window, select the ISim Simulator category and right-click
on the Simulate Behavioral Model option and chose the Run option, as shown
in Figure 4.
i) The type of simulation to run is determined by the simulation type user
control at the top of the Design window as shown in Figure 5. The
simulation types include Behavioral, Post-Translate, Post-Map, and
Post-Route.

Figure 4: Simulating the developed testbench

 Figure 5: Selecting the type of simulator to run

7) The simulation window will automatically open with the output values from the
simulation as shown in Figure 6.

Figure 6: ISim simulator output from testbench simulation