2016

WORKBOOK
Detailed Explanations of
Try Yourself Questions

Computer Science & IT

Digital Logic
 1 Boolean Algebra and
Logic Gates

T1 : Solution

(b)

( x + ( x + y )) + (y + ( x + y ))

= ( x + ( x y )) + (y + ( x y ))

= ( x + y) + ( y + x )

= x y+ yx

= ( x y) ( y x)

= (x + y) ( y + x)

= xy + x y

= xe y

T2 : Solution

(d)
1
When output is 1 both input can be 1.

1
No input is permanantly high.

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 Workbook 3

T3 : Solution

(b)
AA AA AA AA A
Y =
O O O O
= OOOOA
= OA
y = A

T4 : Solution

(b)
F(A, B) = A B F (x y, z) = x y z
F (F (x y, z), w) = F (x y z, w)
= xyzw

T5 : Solution

(b)

T6 : Solution

(d)
P : X = YZ
RHS Y Z = YZ + Y Z

= Y (X Y ) + Y (X + Y )

= Y (XY + X Y ) + Y (XY + X Y )

= XY + Y (X + Y )(X + Y )

= XY + Y (X + Y )

= XY + X Y
= X LHS
Y = XZ
RHS: X Z
= XZ + X Z

= X (X Y ) + X ( X + Z )

= X (XY + XY ) + X (X + Y )(X + Y )

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4 Computer Science & IT Digital Logic

= XY + 0 + X (X + Y )(X + Y )
= XY + X (X + Y )

= XY + X Y
= Y LHS
R :X Y Z = 1
X X
XX + X X
X +X
1

T7 : Solution

(c)
A+B = 1
AB = 0
A = B ...(1)
AC = BC
BC = BC
C = 0 ...(2)
A+C = 1
A = 1 ...(3)
B = 0 ...(4)
A = 1, B = 0, C = 0

T8 : Solution

(b)
P : A B = 0 when A = B
Q : A + B = 0 A B = 0 A = 1 and B = 1
R : A + B = 0 B = 0 and A = 1
S : A B A =BA B

T9 : Solution

(b)
x A 1
T1(x, 1) = x
T
1 B gate

y A 2
T2(y, x) = y x = (x +y)
T
B gate NOR gate operation

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 Workbook 5

T10 : Solution

(d)
a + ab = a + b
= a + ab + a bc
= a + b + a bc
= a+b+c

T11 : Solution

(a)
Ex-NOR is coincidence logic gate.
F = AB + A B is coincidence logic.

F = AB + A B

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 2 Number System

T1 : Solution

(d)
(3527)8 = (01 11 01 01 01 11)2
= (131113)4
= (757)16
= (1879)10
So all of these.

T2 : Solution

(b)
(1217)8 = (001010001111)2
= (28f)16

T3 : Solution

(d)
(66.3)8 = (110 110 011)2

T4 : Solution

(a)
Range of n bits 2s complement numbers = 2n1 to (2n1 1)

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 Workbook 7

T5 : Solution

(d)
A forbit 2s complement number is to be represented as 6 bit 2s complement number.
As example: x3 x2 x1 x0 x3 x3 x3 x2 x1 x0

T6 : Solution

(d)
(135)x + (144)x = (323)x
x2 + 3x + 5 + x2+4x + 4 = 3x2 + 2x + 3
2x2 + 7x + 9 = 3x2 + 2x + 3
x2 + 5x 6 = 0
(x 6)(x + 1) = 0
x = 6, x = 1 base cant be negative.

T7 : Solution

(b)
(BA)16 (AB)16 : 10111010
10101011
00001111 = (F)16
(BC)16 (CB)16 : 10111100
11001011
11110001 (F)16
(CB)16 (BC)16 : 11001011
10111100
00001111 (F)16

T8 : Solution

(a)
(92.1)10
10s = 100.0
92.1
07.9

9s = 99.9
92.1
07.8
(1011.11)2
2s = 0100.01
1s = 0100.00

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8 Computer Science & IT Digital Logic

T9 : Solution

(a)
Possitive number: 2s complement is same as binary : 01111111.

T10 : Solution

(a & d)
2s complement = 1s complement + 1
1s complement = 2s complement 1

T11 : Solution

(d)
(73)x = (54)y
7x + 3 = 5y + 4
x = 8 56 + 3
= 5y + 4
y = 11

T12 : Solution

(5)
312
= 13.1
20
3 x2 + x + 2 1
= x+3+
2x x
3 x2 + x + 2 1
= x+3+
2x x

2x/ ( x2 + 3 x + 1)
3x2 + x + 2 =
x/
3x2 +x+2 = 2x2 + 6x + 2
x2 5x = 0
x(x 5) = 0
(x = 5)

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 Workbook 9

T13 : Solution

(3)
(123)5 = (x 8)y
52 + 2 5 + 3 = xy + 8
25 + 10 + 3 = xy + 8
xy = 30, y > 8
1. y = 10, x = 3
2. y = 15 , x = 1
3. y = 30, x = 1

T14 : Solution

(210212.2011)
(7 2 5 6 4)9

(21 02 12 20 11)3
= 2102122011

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 3 K-maps

T1 : Solution

(b)
F = A + B C
F = (1, 4, 5, 8, 7)
BC
A
0 1 3 2

4 5 7 6

T2 : Solution

(b)
F = AD + BD Independent of C.
CD
AB
0 1 3 2
4 5 7 6
BD
12 13 15 14 AD
8 9 11 10

T3 : Solution

(c)
F = A BD + AB D + BCD + BCD
= A (BD + B D ) + C (BD + BD )
= A (B e D ) + C (B e D )
= (A + C)(B e D)

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 Workbook 11

T4 : Solution

(c)
F1 = (0, 1, 3, 5)
F2 = (4, 5)
F1 + F2 = (0, 1, 3, 4, 5
F1 + F2 = (0, 1, 3, 4, 5

F = (1, 4, 5) F3 = (1,4,5) + d (2,6,7)

T5 : Solution

(3)
f(A, B, C) = C + AB
= (C + A) (C + B) POS from.
A

B f (A,B,C)

3 NOR gates.

T6 : Solution

(c)
f1 (w, x, y, z) = w x z + yz + xz
f1 (w, x, y, z) = m(2, 4, 6, 9, 10, 11, 12, 14)
w,x w
f1 yz
1 1
f2
1 z
f y xz
1 wxz
f3 yz 1 1 1 1
x

Required f(w, x, y, z) = m(1, 3, 5, 6, 9, 12, 13)

then the function f2 = m(6, 9, 12) + d(0, 1, 3, 5, 7, 8, 13, 15)

and f3 = m(1, 3, 5, 13) + d(6, 9, 12)

So that f3 is f3(w, x, y, z) = m(0, 2, 4, 7, 8, 10, 11, 14, 15) + d(6, 9, 12)

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12 Computer Science & IT Digital Logic

T7 : Solution

(3)
3 essential prime implement.
YZ
1 2
WX
1 0 1 1 3 2

1 4 1 5 7 7 6

12 1 13 1 15 14

8 9 1 11 110 3

T8 : Solution

(3)
(i) If cell 4 and 5 are grouped then 18 and 15 only can be grouped in minimal expression.
(ii) 5 and 13 are grouped then: (a) 13 and 15 can be grouped (b) 15 and 11 can be grouped.
Three minimal expression can be formed.

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 4 Combination Circuit

T1 : Solution

(d)
Output = Control Input + Control Input

1 Phase 0 as it is
inverted passed
Output = Control Input
= EXOR gate

T2 : Solution

(a)
As per the problem description for generating carry the delay is 2 time units, and 2 time units delay is
involved for generating sum output after knowing carry. Hence the total delay is 4 time units.
Carry
2 units
Circuit

Sum
2 units
Circuit

T3 : Solution

(c)
A = A3 A2 A1 A0
B = B3 B2 B1 B0
A>B

(i) If A3 > B3 A3 B3
or

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14 Computer Science & IT Digital Logic

(ii) A3 = B3 but A2 > B2 (A3  B3) A 2B2 = X 3 A 2B2

(iii) A3 = B3, A2 = B2 but A1 > B1 X 3 X 2 A1 B1

(iv) A3 = B3, A2 = B2, A1 = B1, but A0 > B0 X 3 X 2 X1A 0B0

So that if A > B then the expression is

A 3B3 +X 3 A 2B2 +X 3 X 2 A1B1+X 3 X 2 X1A 0B0

T4 : Solution

(b)
Y = Y3 Y2 Y1 0
X = X3 X2 X1 0
Y3 Y2 Y1 Y0
X3 X2 X1 X0 YX

T5 : Solution

(b)
Carry look ahead adder is implemented using k logic levels and each logic gate delay is d.
Hence maximum delay is kd.

T6 : Solution

(c)

The occurance of overflow is indicated by the boolean function which is X Y Z + X Y Z .

T7 : Solution

(b)
In 2s complement addition, overflow cannot occur when a positive value is added to a negative value.

T8 : Solution

(a)
X = I1(ABC ) + I 4 (ABC ) + I 5 (ABC )

= D(ABC) + 1(ABC) + D(ABC)

= ABCD + ABC + ABCD
= ABCD + ABC (D + D) + ABCD
= ABCD + ABCD + ABCD + ABCD

= (3, 9, 8, 10)

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 Workbook 15

T9 : Solution

(c)
Y = x0 (S2S1S0 ) + x3 (S2S1S0 ) + x5 (S2S1S0 ) + x6 (S2S1S0 )

Y = 1(CBA) + 1(CBA) + 1(CBA) + 1(CBA)

= (CBA) + CBA + CBA + CBA

= C BA + BA + C BA + BA

= C [A e B ] + C [A B ]

= C [A B ] + C [A B ]

T10 : Solution

(a)

0 I0 0 I0

1 I1 1 I1
4-to-1 4-to-1
MUX MUX Y X
1 I2 Z 1 I2

0 I3 0 I3
S1 S0 S1 S0

Z
A B C

Output of 1st 4 to 1 MUX = AB + A B = Z

Output of 2nd 4 to 1 MUX = Z C + Z C

= (AB + AB) C + (AB + AB) C

= ((A + B )(A + B)) C + ABC + ABC

X = ABC + ABC + ABC + ABC

T11 : Solution

(a)
f = a, b
Using multiplier = f = x3 x2 + x3 ( x1 b + x1a)
(a) x1 = b, x2 = 0, x3 = a
a 0 + a(bb + ba) = ab

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16 Computer Science & IT Digital Logic

T12 : Solution

(c)
To implement n variable function we require a data selector with n 1 select inputs and 2n1 data inputs. So
minimum size of multiplexer needed is 2n1 line to 1 line.

T13 : Solution

(c)
A multiplexer: (i) selects one of the several inputs and transmits it to a single output. (ii) Converts parallel
data into serial data and (iii) is a combinational circuit.

T14 : Solution

(c)
Q1 = G0 I 0 + G0 I1

Q2 = G1 I 2 + G1I 3

Q = G2 Q1 + G2Q2

( ) (
= G2 G0 I 0 + G0 I1 + G2 G1 I 2 + G1I 3 )
= G0 G2 I 0 + G0G2 I1 + G2G1 I 2 + G2G1I 3

T15 : Solution

(2)
f = ABC + ABC = AB

0
2 to 1
0 AB=f
MUX
2 to 1 A
MUX
1

A B

T16 : Solution

(d)
If A = 0, C = 0 f = I2 = B+C
If A = 0, C = 1 f = I0 = B
If A = 1, C = 0 f = I3 = B+C

If A = 1, C = 1 f = I1 = C
f(A, B, C) = m(0, 1, 4)
= AB+BC

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 Workbook 17

T17 : Solution

(a)
Z
T R f
R X

{
0 0 0
X R MUX f
0 1 1
{ 1 Y

Y { 1
1
0
1
1
1
{ 1 Z

T18 : Solution

(d)
When two 16-input multiplexers drive a 2-input MUX resulted 32-input MUX.

T19 : Solution

(5)
I1
I2

2 to 4

EN

2 to 4

EN
I3
I4 2 to 4

2 to 4

EN

2 to 4

EN

5 decoders required.

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18 Computer Science & IT Digital Logic

T20 : Solution

(a)
The carry generate function can be given as
Ci = Gi+Gi1 Pi+Gi2 Pi Pi1 +...+ G0 Pi Pi1...Pi ...(A)
where Gi = ai bi and Pi = ai + bi in the above equation (A)
Given: a = a2 a1 a0 and b = b2 b1 b0. The carry generate function is C2 while adding the given two 3 bit
binary numbers is
C2 = G2+G1P2 + G0+P2P1 ...(1)
Substituting G2, G1, G0, P2 and P1 values in the equation (1)
C2 = a2b2 + a1b1(a2+b2) + a0b0(a2+b2) (a1+b1)
= a2b2 + a2 a1b1 + a1 b2b1 + a0 b0 [a2 a1 + a2 b1 + a1b2 + b2 b1]
= a2b2 + a2 a1b1 + a1 b2b1 + a2 a1a0 b0 + a2 a0 b1b0 + a1a0 b2b0 + a0b2b1b0

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 5 Sequential Circuit

T1 : Solution

(d)
If x = 0 Qn+1 = Qn
x = 1 Qn+1 = Qn
Qn
x T
Qn
It is T-flipflop.

T2 : Solution

(b)
X Qn X
D Q

Clock Q

If x = 0 Qn+1 = Qn
x = 1 Qn+1 = Qn

It is T-flipflop.

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20 Computer Science & IT Digital Logic

T3 : Solution

(d)
+
S R A B Q Q
1 0 0 0 0 1
1 0 0 0 1 1
0 1 0 1 0 0
0 1 0 1 1 0
0 0 1 0 0 0
0 0 1 0 1 1
1 1 1 1 0 X
1 1 1 1 1 Y
S = A  B; R = B
Q+(A, B, Qn) = m(0, 1, 5) + Q(6, 7)
= A B+BQn

or = A B+AQn

T4 : Solution

(a)
): Consider initially X = 1 and Y = 0
Case ((i):
B is replaced with the sequence 101010...
X = 1 1 0 0 0 0 0...
Y = 0 1 1 1 1 1...
B101010
X fixed to 0 and Y fixed to 1.
): Consider initially X = 0 and Y = 1
Case ((ii):
X = 0 0 0 0 0 0 0...
Y = 1 1 1 1 1 1...
B101010
X fixed to 0 and Y fixed to 1.

T5 : Solution

(d)
Q J=1 K = Qn
1 1 1

0 1 0

1 1 1

0 1 0

1 1 1

0 1 0

1 1 1

0

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 Workbook 21

T6 : Solution

(a)
A B Qn Qn+1 J K
0 0 0 0 1 1 X
1 0 0 1 0 X 1
2 0 1 0 1 1 X
3 0 1 1 1 X 0
4 1 0 0 0 0 X
5 1 0 1 1 X 0
6 1 1 0 0 0 X
7 1 1 1 0 X 1

Problem is converting JK flip-flop to A-B flip-flop.

J(A, B, Qn) = m(0, 2) + d(1, 3, 5, 2) = A

K(A, B, Q11) = m(1, 7) + d(0, 2, 4, 6) = A B+AB = A  B

T7 : Solution

(b)
A B Qn Qn+1 J K
0 0 0 0 1 1 X
1 0 0 1 1 X 1
2 0 1 0 1 1 X
3 0 1 1 0 X 0
4 1 0 0 0 0 X
5 1 0 1 1 X 0
6 1 1 0 0 0 X
7 1 1 1 0 X 1

Problem is converting JK flip-flop to X-Y flip-flop.

J(X, Y, Qn) = m(0, 2) + d(1, 3, 5, 7) = X

K(X, Y, Qn) = m(3, 7) + d(0, 2, 4, 6) = Y

T8 : Solution

(b)
For NAND gates: Inputs [(0,1); (1,1)]
Output [(1, 0) ; (1, 0)]
For NOR gates : Inputs [(0, 1); (1,1)]
Output [(1,0); (0,0)]

T9 : Solution

(c)
Consider 4 bit shift register with data 0101
0 1 0 1 (5)10 Left shift by one bit the data is
1 0 1 0 (10)10 Multiplication by 2

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22 Computer Science & IT Digital Logic

T10 : Solution

(7)
Clk SI Q3 Q2 Q1 Q0
1 0 1 0
1 1 1 1 0 1
2 0 0 1 1 0
3 0 0 0 1 1
4 0 0 0 0 1
5 1 1 0 0 0
6 0 0 1 0 0
7 1 1 0 1 0

Hence answer is 7.

T11 : Solution

(a)

A pulse train can be delayed by a finite number of clock periods using a serial-in-serial-out shift register.

T12 : Solution

(d)
Clk Q2 Q1 Q0 J2 = Q0 K2 = Q0
1 0 1 0 1
1 0 1 0 1 0
2 1 0 1

After 2 clock pulses Johnsn counter is counting to intial state. Hence the frequency of output Q2Q1Q0 will
be fc / 2.

T13 : Solution

(d)

D A = QD Q C
Clk QD QC QB QA QA Clk QD QC QB QA QA
0 0 0 1 0 0 0 1 1
1 0 0 1 0 0 1 0 1 1 0 0
2 0 1 0 0 0
3 1 0 0 1 1 Not matching to the given sequence.

Not matching to the given sequence.

Clk QD QC QB QA QA
1 1 1 0
1 1 1 0 0 0

Not matching to the given sequence.

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 Workbook 23

T14 : Solution

(100)
1 1
1 0
1 1
T0 Q0 T1 Q1 T2 Q2

CLK 0 0 1
Q0 Q1 Q2

When Q0 output 0.
Then clock of T1 is 1 and it generate output 0.
Then clock of T2 is 1 and it generate output 1.
So answer is 100.

T15 : Solution

(24)
NAND gate input Q4 and Q3. Hence the state is
Q4 Q3 Q2 Q1 Q0
1 1 0 0 0

Mod value is 24.

T16 : Solution

(d)
P Flip-flop input Q Flip-flop input
Clk P Q
J=1 K=1 D=P
0 1 1 1 0
1 1 0 1 1 1
2 0 1 1 1 0
3 1 0

After three clock cycles P, Q values are 1, 0 respected.

T17 : Solution

(a)

Q1 Q0 D1 (Q0 ) D0 (Q1 )
0 0 0 1
0 1 1 1
1 1 1 0
1 0 0 0

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24 Computer Science & IT Digital Logic

T18 : Solution

(c)
Initially cleared so q2 q1 q0 = 000

Clock Data q0 = Data q1+ = q0 q2 q2 = q1

st
1 1 1 0 0
nd
2 0 0 1 0
rd
3 0 0 0 1
th
4 1 1 1 0
th
5 1 1 1 1
th
6 0 0 0 1
th
7 0 0 1 0
th
8 0 0 0 1
th
9 0 0 1 0

At 9th clock pulse 010 will be present.

T19 : Solution

(d)
FF0 FF1
Clock Q0 Q1
D0 = Q0 D1 = Q1 Q0
Initial state 0 0 1 1
1 1 1 0 1
2 0 1 1 0
3 1 0 0 0
4 0 0

00 11 01 10
The state sequence is

T20 : Solution

(a)
A shift register can be used for parallel to serial conversion.
A multiplexer can be used as a many to one switch.
A decoder can be used to generate memory chip select.

T21 : Solution

(c)
Consider the propagation delay of each flip-flop as tp.
n stage syndroms counter delay = tp (here 20 nsec)
n stage asynchronous (ripple) counter delay = ntp (here 4 20 nsec = 80 nsec)

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 Workbook 25

T22 : Solution

(c)

1 0 0 0 0
1 1 2 0 1 0 0
2 n-bit 2 3 0 0 1 0
n-bit 3 Up- 3
M counter M M M M M M
n n-bit n
2
0 0 0 1
n
Ring counter of 2 bits

T23 : Solution

(40)
10 bit ring counter is divided by 10 counter
4 bit parallel counter is divided by 16 counter
Mod 25 ripple counter is divided by 25 counter
4 bit Johnson counter is divided by 8 counter
Input clock frequency = 160 kHz.
160
W = = 16kHz
10
16
X = = 1 kHz
16
1000
Y = = 40 Hz
25

T24 : Solution

(c)
Count = 1, load = 0 externally connected to the counter. Based on the function table, whenever clear input
is 0 the counter will increment its value by one and whenever clear input is 1, all the flip-flops is the counter
will get value as 0.
Clock A4 A3 A2 A1 Clear = A3 A1
Initial state 0 0 0 0 0
1 0 0 0 1 0
2 0 0 1 0 0
3 0 0 1 1 0
4 0 1 0 0 0
5 0 1 0 1 1
0 0 0 0 Transition

Hence the switching sequence is 0, 1, 2, 3, 4.

T25 : Solution

(d)
A B Ci S Co
st
After 1 CP 1 1 0 0 1
nd
After 2 CP 1 1 1 1 1

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