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HomeCOMPUTERSCIENCENS2ProjectsA65nmCMOSDACBasedonaDifferentiatingArbitraryWaveformGeneratorArchitecturefor5GHandsetTransmitter

A 65-NM CMOS DAC BASED ON A DIFFERENTIATING ARBITRARY WAVEFORM GENERATOR

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ARCHITECTURE FOR 5G HANDSET TRANSMITTER
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NS2Projects February7,2017

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A 65nm CMOS DAC Based on a Differentiating Arbitrary Waveform Generator

Architecturefor5GHandsetTransmitter
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Abstract:
Subject
The data rate expected for the forthcoming 5G standard induces stringent
constraints for handset transceivers. Wideband carrier aggregation will be Re: A 65nm CMOS DAC Based on a Differentiating Arbitrary Waveform Generator Arc
handled with flexible and lowpower architectures implemented in lowcost
Message
technologies. An architecture of a wideband signal generator intended to target
sub6GHz5Gtransmissionrequirementsispresented.Thearchitectureisbased
onadifferentialpulsecodemodulationcodingschemeandacustomintegrating
DAC named the Riemann pump. It performs a 9dB improvement of the signaltonoise ratio per doubling of the oversampling ratio
whileensuringaflatquantizationnoiseflooroverthewholemultigigahertzconversionband.Itsinherentabilitytogeneratesynchronous
signalsallowsustoaddresscarrieraggregationpurposesthegenerationof10synchronized64QAMmodulatedsignalsbetween1.8
and 3.6 GHz is simulated. Postlayout simulations of the Riemann pump implemented in 65nm CMOS technology fit the exposed
theoreticalfeatureswithasubmilliwattlevelpowerconsumption.

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