Mechanism of Void Formation in Cu Post Solder Joint under Electromigration

Min-Young Kim1, Liang-Shan Chen1, 2, Seung-Hyun Chae3, Choong-Un Kim1, 4

1
Department of Materials Science and Engineering, University of Texas at Arlington
501 West First Street, Box 19031, Arlington, Texas 76019
2
present: Globalfoundries, 400 Stone Break Extension, Malta, New York 12020
3
Texas Instruments, 12500 TI Boulevard, Dallas, TX 75243
4
contact e-mail: choongun@uta.edu

The proliferation of Cu-pillar or Cu-post based flip chip

Abstract
This paper reports experimental observations made on the
mechanism of electromigration (EM) voiding and its kinetics
active in low-profile solder joint consisting of long Cu-post
(~300x110m), thin solder layer (15m), and Ni coated Cu-
lead frame assembly. When EM testing on the samples was
conducted at accelerated conditions it revealed that although
they are immune to EM failure, they contained a small
amount of residual void as a result of EM. Kinetic analysis of
EM voiding was done based on the analysis of resistance
change and post EM microstructural characterization. Our
analysis suggests that the origin of the residual voids is EM in
Sn and it occurred prior to conversion of Sn to Cu6Sn5 phase.
It further suggests that the extent of voiding is determined by
the two competing kinetic factors that are producing opposite
effect on the voiding. The first is the kinetics of Sn EM
because it determines the amount of vacancy responsible for
voiding while the second is the Cu EM as it promotes the
growth of Cu6Sn5 phase that interrupts voids growth by
removing Sn phase in the joint. The kinetic interplay between
these two factors makes EM voiding kinetics of the low-
profile solder joint to be different from the more conventional
solder joint where Cu EM has a rather insignificant influence.
Keywords: low-profile solder joint; Cu-post, Cu-bump,
electromigration voiding, Intermetallic compounds
Introduction
Continuing demand for high performance as well as high
power electronic devices has spurred the recent development
of the packaging technology allowing the use of low-profile
solder joints in the assembly [1-4,7-9]. Some of the known
examples of such packaging structure include the ones used in
the flip chip (FC) assembly, including the flip chip on lead
(FCOL) [10], where Cu pillars or Cu posts are placed on top
of Si chip to join with the mating Cu bumps, pads or lead-
frame via thin Pb-free solder layer. Unlike in more
conventional packaging structure such as the Ball Grid Array
(BGA) [5-6], the solder joint in these structures can be as thin
as a few tens of micro-meters, leading to extremely low-
profile device form factor. While such packaging methods can
result in an increase in process complexity and requirement
for tighter control of structural and process variables, their
ability to produce low profile devices with high density
interconnects makes them highly attractive and ideal for
advanced electronics. Various devices with such packaging
structure are already introduced and used in places like mobile
electronics and many more are expected to be introduced in
the near future [1,3,7].
packaging technology has resulted in a large number of
investigations in recent years with an aim to identify factors
and mechanisms affecting the stability of the joint in the
assembly [1,3-4,8-13,15]. These studies are successful in
revealing mechanisms of microstructure development, its
relation with process conditions, and its impacts on the joint
reliability. However, focused more on the thermo-mechanical
reliability, these studies are less successful in identifying
factors affecting the electromigration (EM) reliability
specially when EM induced failure is emerging as one of the
critical reliability concerns in those assemblies [9-13]. The
high density electric current can subject the solder layer to
more severe EM condition than in the conventional assembly
and may make the joint to be EM failure prone. A simple
extension of understandings made from the EM studies
conducted on the conventional solder joint may not work in
this case because kinetic mechanism of EM and the resulting
void development can be substantially different in low-profile
solder joint.
One obvious reason why the EM voiding mechanism is
expected to be different in low profile solder joint is related to
the fact that the joint contains limited amount of solder so that
it can be quickly converted to Cu-Sn intermetallic compounds
(IMC) prior to EM developing sizable damage [1]. In solder
joint, there are at least two active atomic species, Sn and Cu,
constituting the total EM flux. Among these two, Sn EM flux
is regarded as the main source of voids because commonly
used Pb-free solder contains Sn in excess of 95 wt.% [1,14].
The contribution of Cu EM on void volume should be
negligibly small because extremely low solubility of Cu in Sn
solder makes Cu EM flux to be small and also Cu is
continuously replenished by its source, i.e. cathode end of the
joint. However, Cu EM can play a significant role in low-
profile solder joint not necessarily because it changes the rate
of Sn EM but because an accelerated growth of Cu-Sn IMC
can interfere with the void growth. In cases where Sn solder
layer is very thin, the growth front of Cu-Sn IMC layers on
both sides of solder joints can converge prior to formation of
EM voids in Sn solder. Once Sn solder is replaced with Cu-Sn
IMCs, EM of both species and failure development should be
terminated. A few previous studies on EM voiding suggest
such possibility. For example, the work conducted by Chao et
al. [16-17] reports that EM voiding in Cu-Sn system cannot be
solely characterized by Sn EM flux but has to include the
influence of enhanced Cu-Sn IMC growth rate.
Consideration of EM mechanism suggests that EM failure
mechanism in low-profile solder joint can be substantially
different from what is known from the conventional solder

978-1-4799-8609-5/15/$31.00 2015 IEEE 135 2015 Electronic Components & Technology Conference
joint because the failure may develop by two kinetically
competing processes, which are the rate of voiding by Sn EM
and IMC growth by Cu EM. This speculation is indeed proven
in our study that investigates the kinetic mechanism of EM
damage in low-profile solder joint made of Cu-post, Sn--Ag
solder, and Ni coated Cu lead-frame. Our study finds that EM
damage stops when Sn solder layer is fully converted to Cu-
Sn IMCs and that the joint is left with residual voids
developed in Sn prior to its conversion to Cu-Sn IMCs. The
residual damage appears as voids surrounded by IMC phase,
and the degree of voiding is found to be affected by EM
condition. This paper presents examples of our data with
weighted emphasis on the effect of EM on the rate of Sn
conversion to IMC and the degree of EM damage appearing
as residual voids.
Experimental Method and Sample Configuration
The samples used in our investigation are based on a flip
chip on lead-frame structure with Pb-free Sn solder containing
approximately 2.5% Ag. As presented in Figure 1(a), where
cross-sectional view of the joint is shown, the Cu-post is
patterned on top of Si wafer. The dimension of Cu post is
approximately 300m in length, 110m in width 35m in
height. The mating electrode of the bump is the Cu-lead frame
(LF) coated with 1m thick Ni. The solder layer was formed
by plating the solder alloy and by subjecting the assembly to a
standard reflow condition. The distance between the top of the
Cu-post and bottom of LF is approximately 15m. Due to
formation of Cu6Sn5 at the post interface and (Cu,Ni)6Sn5 at
the LF interface, the actual solder layer thickness is reduced to
~12m after the first reflow. In order to simulate the reflow
condition that the chip may receive in its application, the
samples were subjected to three additional reflow treatments.
Figure 1. Cross-section micrographs showing the overall view
of the Cu-post/LF solder joint (a), the joint microstructure
after the first reflow (b), and after additional reflow treatments
(c).
This induces an additional growth of the Cu6Sn5 and
(Cu,Ni)6Sn5 IMCs but the growth is found to be more
extensive in a few places along the long-axis direction. As
shown in Figures 1(b) and (c), where cross-sectional SEM
view of the joint after the first reflow and additional reflow is
compared, the growth of IMC phase on both interfaces,
post/solder and solder/LF, makes the solder layer to be
136
substantially reduced. There exists a few places where IMC
growth is found to be highly enhanced, which is a subject of
our ongoing research; however, the resulting solder joint
microstructure, consisting of narrow channels of Sn encased
by thick IMC, provides us with an ideal condition for studying
the EM voiding mechanism with limited amount Sn in the
joint.
In order to confine the EM damage to the target joint, we
placed a number of supporting posts near the EM post and
used them to provide distributed current exit paths to the post
under EM testing. This arrangement is used to make the test
current from the LF to Cu-post, meaning that EM occurs from
the post to the LF direction. Also developed for this study was
a customized EM test oven to enable effective joule heat
dissipation and maintenance of temperature uniformity and
stability for duration of EM testing. The developed oven
system uses a large surface heater with high speed blower and
min-air conduits made of Al fin arrays. High speed forced air
circulation over the array of samples enabled us to keep the
joule heat induced temperature rise to under 6oC at 7.6A
(~27kA/cm2) test current and 150oC test temperature. EM
testing was conducted at five different conditions: 150oC (6.4,
7.0, 7.6A), 140oC/7.0A, and 160oC/7.0A. The temperatures
used in our testing were determined by the on-chip
temperature sensor. An average of 16 samples were used per
test condition. During EM testing, resistance of the joint was
closely tracked in order to monitor the level of damage
resulted by EM.
Results
80
t
P
70 6.4A
60 R
P
R(t)/R(0), %
7.0A
50
40 7.6A
30
20
10
0
0 500 1000 1500 2000 2500 3000
Time, hrs
Figure 2. A plot showing the representative change in the
sample resistance during EM testing at 150oC under three
different test currents.
EM Damage Measured by Resistance Change
No complete EM failure was seen in our EM testing that
lasted well over 4000 hours in most test splits. There were a
few samples, less than 5%, that showed complete failure at
early stage of the testing but subsequent failure analysis
indicated that these early failures were not the result of EM.
Judging from the fact that they were more or less random in
terms of test conditions, we concluded that they were
associated with the flaws introduced during assembly process,
such as uneven stand-off or residual stress distribution. Since
such flaws can be eliminated by improved process
optimization and they were not related to EM reliability, they
were removed from our EM analysis.
While the majority of samples showed no clear sign of
EM failure, we found a consistent trend that could be related
to EM induced residual damage in the joint. The indicator for
the residual damage was found from the increase in the joint
resistance. Figure 2 compares the most representative
resistance traces taken from samples tested at 3 different
stress currents at 150oC. Note that the resistance change is not
a monotonic function of time. Rather, it shows an initial stage
of rapid increase followed by the slowly decaying stage. As a
result, there exists a peak point in the resistance change (RP).
The existence of the resistance peak may appear odd because
both the conversion of Sn to Cu6Sn5 IMC and EM damage are
likely to increase the joint resistance. However, we find that
the peak resistance appears because conversion of Cu6Sn5 to
Cu3Sn IMC phase reduces the joint resistance.
Figure 3. SEM micrographs showing the post-EM
microstructure of the joint. This sample was tested at 150 oC
under 7.0A current for duration of ~5200 hours.
The electrical resistivity of Sn, Cu6Sn5 and Cu3Sn is
known to be 11.5, 17.5, and 8.9 ohm-cm at room
temperature, respectively [18], and the relative difference in
the resistivity among these phases should be maintained at
temperatures used in our EM testing. Upon commencement of
EM testing, both EM induced voiding and conversion of Sn to
Cu6Sn5 begins to proceed, constituting main part of the
resistance increase. The growth of Cu6Sn5 phase is deemed to
be faster at the LF side due to the polarity effect [17]. More
precisely, the growing IMC phase is (Cu,Ni)6Sn5 because of
the concurrent diffusion of Ni from the LF side, but we shall
call it Cu6Sn5 for simplicity. The Cu6Sn5 phase gradually
consumes the Sn layer while it is growing toward the IMC
layer at the Cu-post interface. Since the resistivity of Cu6Sn5
is ~50% higher than that of Sn, this conversion plus the void
formation in Sn makes the joint resistance to increase. On the
other hand, the formation and growth of low resistivity Cu3Sn,
which forms at the Cu-post/Cu6Sn5 interface, should make the
joint resistance to decrease. As its growth is mainly driven by
the interdiffusion of Cu and Sn across Cu6Sn5 phase, it grows
by consuming Cu6Sn5 as well as the Cu-post.
Since Cu3Sn growth begins after considerable growth of
Cu6Sn5, its influence appears when the Sn conversion to
137
Cu6Sn5 is at its terminal stage where EM induced voiding is
disrupted. The amount of initial Sn in solder layer is likely to
be similar among samples, making the contribution of Sn
consumption by Cu6Sn5 on the joint resistance more or less
the same irrespective of sample and EM test conditions.
Therefore, it is reasonable to assume that the variation in the
peak resistance reflects the total amount of EM induced
damage in the Sn phase prior to its complete conversion of
Cu6Sn5 IMC phase. Also it is reasonable to assume the peak
time to be the time for completion of Sn to Cu6Sn5
conversion.
Post EM Joint Microstructure
In order to substantiate our assumption that the phase
conversion and EM induced damage in Sn layer is responsible
for the unique change in the joint resistance shown in Figure
2, EM tested samples were subjected to microscopic
inspection. This analysis, conducted on multiple samples per
test condition, revealed that the joint could be characterized
by two types of isolated voids trapped inside of Cu6Sn5 and
Cu3Sn formed at Cu6Sn5/Cu-post interface. An example of
such microstructure is shown in Figures 3, where SEM
micrographs of the joint taken after ~5200 hours of EM
testing at 150oC under 7.0A are presented. Note that there is
no Sn phase remaining in the joint. This means that Sn phase
is completely consumed and replaced by Cu6Sn5 phase. It also
indicates that the voids visible within the Cu6Sn5 phase are
developed during Sn consumption process because low
diffusivity of Sn and Cu in Cu6Sn5 phase would prevent EM
from occurring to a degree to induce voids of such a scale.
Our inspection on multiple samples suggests that there is no
clear preference for the voiding site.
Figure 4. SEM micrographs comparing the thickness of Cu3Sn
phase formed in (a) an EM stressed joint and (b) a reference
joint without current stressing.
There are also small voids near the interface of Cu3Sn
and Cu-post. However, their formation is not related to EM as
various prior studies on Sn/Cu interfacial reaction suggest that
they are formed during the conversion of Cu6Sn5 to Cu3Sn
phase and that they can form without assistance of EM [13,
19]. While these Kirkendall voids are not related to EM, the
growth extent of Cu3Sn phase is found to be influenced by
EM. An example evidence of the accelerated Cu3Sn phase
growth is shown in Figures 4. The joint microstructure shown
in Figure 4 was taken from a sample tested at 150oC under
7.6A stress current after ~4900 hours. It can be seen that the
thickness of the Cu3Sn phase formed in EM tested joint is
considerably thicker than the one found in the reference joint
in the same sample that was subject to thermal aging only.
Since the reference joint was not subjected to EM, the Cu3Sn
phase must have been formed by pure inter-diffusion. Thus,
the net thickness difference in these two joints is attributed to
the growth acceleration by Cu EM while Sn phase was
surviving in the joint. It should be noted that the accelerated
growth of Cu3Sn phase is not a result of Cu EM in Cu-post
nor in Cu6Sn5 phase as low diffusivity of Cu in those phases
would make the Cu EM flux to be negligibly small. The
growth of Cu3Sn is known to proceed when the Cu6Sn phase
is sizable [20], and therefore thicker Cu3Sn phase seen in EM
stressed joint can be attributed to the fact that faster
conversion of Sn to Cu6Sn5 makes Cu3Sn growth process to
start faster. It then follows that Cu EM in Sn phase induces
accelerated growth of both Cu6Sn5 and Cu3Sn IMC phases.
This conclusion is in good agreement with the findings made
from the peak time analysis detailed below.
Dependence of RP and tP on EM Condition
Our attempts to characterize the peak time, tP, of EM
tested samples indicate that it is indeed affected by the EM
condition. We were not able to determine RP and tP from all
samples because some showed resistance with too much
fluctuation when it approached to the peak point while the
resistance of others, especially the ones tested at 140oC, did
not reach the condition to provide clear determination of the
peak within the given EM testing time. However, we were
able to collect RP and tP from a reasonably good number of
samples, which was sufficient to draw statistically meaningful
conclusions.
4 more time for Sn EM to continue, yet such effect is somewhat
1 10
100
8000
6000
tP, hrs
R , %
P
4000
2000
10
6 6.5 7 7.5 8
Current, A
Figure 5. A summary plot showing the dependence of RP
and tP on stress current at 150oC.
Figure 5 shows the summary of the data, average RP in
percent increase and tP, collected from the samples tested at
150oC under 3 different currents. Decrease in the average tP
with increasing stress current is evident in the plot. Because tP
approximately corresponds to the time for the completion of
138
120
100
7.6A 6.4A
80
RP
60
40
20
0
0 500 1000 1500 2000 2500 3000 3500 4000
tP, hrs
Figure 6. A plot showing RP of samples tested at 150oC
under 6.4 and 7.0A as a function of tP.
Sn consumption, the result showing decrease in average tP
with increase in stress current is consistent with the
expectation. What is unexpected at first glance, though, is the
result that the average RP is almost independent of current or
slightly increases with decreasing current. There is a
considerable scatter in RP, but there exists an unmistakable
trend that it is more or less independent of current. Since RP
is proportional to the amount of voids formed while Sn is
remaining in the joint and Sn EM is a predominant source of
the void, it is expected to increase with the current. In this
respect, the result shown in Figure 5 appears to be odd and
disagrees with the usual EM damage model. However, we
believe that our result may be explained when the effect of tP
on EM voiding kinetics is considered. It is important to note
here that the EM voiding stops when Sn phase is completely
consumed. In this circumstance, the extent of voiding may not
be a function of the current but can be affected by tP. At lower
current, it takes longer time for Sn to be consumed, providing
counter-balanced by the smaller Sn-EM flux. This can result
in RP that is at similar or higher level than at higher current.
While there may be other contributing factors, such as the
thermal voiding, our view is supported by the observation of
the strong dependence of RP on tP within samples tested at
identical condition. This result is shown in Figure 6 where
RP of samples tested at 150oC under 6.4 and 7.6A is plotted
as a function of their tP. The linear dependence of RP on tP is
clearly evident, suggesting that the extent of EM voiding is
strongly affected by the time to consume the Sn phase.
The same analysis performed on the data collected from
samples tested at 140, 150, 160oC under 7.0A provides
additional evidence supporting that Sn conversion rate is
affected by EM and it affects the extent of EM damage. The
analysis result is shown in Figure 7. As expected, temperature
affects the Sn conversion rate exponentially. A good portion
of the samples tested at 140oC did not show clearly definable
stage of resistance decay within 5200 hours of EM testing,
presumably due to slow rate of Cu6Sn5 and Cu3Sn growth.
This makes us unable to determine the average tP. The
activation energy for complete Sn conversion time based on tP
taken from 150 and 160oC is estimated to be ~0.9eV. This is
within the known range of activation energy for Cu diffusion
in Sn phase [21-23].
10
4
1000
t , hrs
P
100
o
160 C
o
150 C
10
0.0023 0.00232 0.00234 0.00236 0.00238 0.0024
Temperature, 1/K
Figure 7. A plot showing RP and tP as a function of
temperature under 7.0A.
Unlike in the case of current effect, the RP is found to
increase with more aggressive EM condition, that is, higher
temperature. The exact reason why RP behaves differently
with temperature is presently unknown. Our speculation is
that Sn EM rate increases much more rapidly with
temperature than Cu EM rate. Even if time for Sn conversion
is reduced at higher temperature, its effect may be outweighed
by increase in Sn EM rate. Also probable is the addition of
thermal voiding that is likely to be more active at higher
temperature.
Discussion
As is evidenced in our experimental result, the
mechanism of EM in solder joint with limited amount of Sn is
significantly complicated and poses considerable theoretical
and experimental challenges. Unlike in the conventional
solder joint, EM mechanism is not a simple function of Sn
EM resulting in void formation at the upstream end of atomic
flow. The growth of Cu6Sn5 phase interferes with void
formation by removing Sn and thus the competition between
the Cu-EM and Sn-EM determines the rate of joint failure by
EM. In an extreme case where Sn amount is limited compared
to the rate of Cu6Sn5 phase growth, the joint can be immune to
EM failure. There may be small amount of left-over voids as a
result of short-lived Sn EM, but their amount can be
negligibly small to create negative impact to the joint
reliability. This, a complete EM failure immunity of low-
profile solder joint, is what we found in this study and is
consistent with the results reported in previous studies [24-
27]. As demonstrated in this paper, the process of EM
induced voiding completely stops when the joint is fully
converted to Cu6Sn5 IMC. Our results further suggest that
such mechanism can be further exploited by designing a joint
structure or associated processes to induce quick conversion
of Sn to Cu6Sn5 phase. As long as structural reliability
against mechanically driven failure mechanism is ensured,
superior EM resistance in package interconnects can be
achieved by IMC joints. This is particularly attractive for
high power electronic devices because the current carrying
capability of the joint can be substantially increased.
While the benefit of low-profile solder joint is evident in
150 terms of EM resistance, it results in a challenge in conducting
EM reliability assessment. It is important to realize that the
critical amount of solder for EM immunity is not fixed but
varies with EM condition. For aggressive EM condition, the
100 EM immunity would require small amount of solder, while it
R , %
can be more for less aggressive EM condition. This means
P
that there is a possibility that EM failure kinetics do not scale
consistently with current and temperature. Also, EM failure
50
rate can show considerable scattering even within the samples
tested at the identical condition. This happens because small
o
140 C change in solder amount or variation in EM condition can
0 result in substantial difference in the Sn conversion rate and
0.00242 0.00244
thus EM failure rate. This may make EM test results to appear
chaotic and difficult to use. It is therefore necessary that more
extensive and careful EM testing would be done for the low-
profile solder joint.
The difficulty in conducting EM assessment is
compounded by the lack of reliable data on Cu EM and Sn
EM kinetics. Effective valence for Cu EM in Sn phase, for
example, is presently unknown, creating considerable
difficulty in analyzing the failure kinetics by the means of
computational analysis. Fundamental study on EM
mechanism is necessary and is highly recommended in order
to effectively resolve the challenges created by the complex
EM failure mechanism active in low-profile solder joint.
Finally, it should be mentioned that the considerable
scattering in tP is seen in our test (for example Figure 6),
which may be a result of the anisotropy in Sn EM rate. It is
well known that the rate of Cu EM as well as Cu diffusion in
Sn differs with the crystallographic orientation [28-29]. It was
our anticipation that the solder in our test structure would take
a polycrystalline structure due to a thin layer of solder in
lengthy Cu post. Although not included here, our electron-
back-scattered-diffraction (EBSD) analysis on limited number
of samples reveals that the number of grains in the joint is
surprisingly small. We believe that multiple reflow treatment
we employed is a probable cause of excessive Sn grain
growth. The joint to joint variation in crystallographic
orientation of such grains may be the main cause of the large
scattering in tP seen in our test. This finding suggests that
further enhancement in EM reliability is possible if Sn grain
orientation is controlled and made to be uniform. More
practical method may be the implementation of new assembly
process or alloys that can refine the grain structure. The
refinement does not necessarily make the joint to be more EM
immune but it would make tP to be more uniform to eliminate
other reliability issues caused by uneven physical properties
of solder joints within the assembly. Added benefit will be the
result of tightly distributed EM performance, which will make
EM assessment to be much more accurate.
Conclusions
EM testing conducted on the low-profile solder joints
consisting of long Cu-post, thin solder layer and thick LF
produced results suggesting that no complete joint failure
occurs because void growth is interrupted by the removal of
139
Sn due to the growth of Cu6Sn5 IMC. The interruption of 11. F.-Y. Ouyang, H. Hsu, Y.-P. Su, and T.-C. Chang,
voiding leaves EM damage in Cu6Sn5 phase in the form of Electromigration induced failure on lead-free micro
residual voids. The amount of the residual voids is found to bumps in three-dimensional integrated circuits
vary with EM condition because the Cu6Sn5 phase growth rate packaging, Journal of Applied Physics, vol. 112, p.
is affected by the Cu EM. The kinetic interplay between the 023505, 2012.
Cu EM, responsible for Cu6Sn5 growth, and Sn EM, 12. Y. C. Chan, and D. Yang, Failure mechanisms of solder
responsible for voiding, is found to be the factor that interconnects under current stressing in advanced
determines the degree of EM damage. This kinetic interplay electronic packages, Progress in Materials Science, vol.
between these two factors makes EM voiding kinetics of the 55, pp. 428-475, 2010.
low-profile solder joint to be more complex than what is 13. D.-Q. Yu, T. C. Chai, M. L. Thew, Y. Y. Ong, V. S. Rao,
found from the more conventional solder joint. L. C. Wai, and J. H. Lau, Electromigration study of 50
m pitch micro solder bumps using four-point kelvin
References
structure, in Proc. 2009 Electronic Components and
1. K. N. Tu, H. -Y. Hsiao, and C. Chen, Transition from flip
Technology Conference (ECTC), IEEE, 2009, pp. 930-
chip solder joint to 3D IC microbump: Its effect on
935.
microstructure anisotropy, Microelectronics Reliability,
14. K.-W. Moon, W. J. Boettinger, U. R. Kattner, F. S.
vol. 53, pp. 2-6, 2013.
Biancaniello, and C. A. Handwerker, Experimental and
2. H. Huebner , S. Penka, B. Barchmann, M. Eigner, W.
thermodynamic assessment of Sn-Ag-Cu solder alloys,
Gruber, M. Nobis, S. Janka, G. Kristen, and M.
Journal of Electronic Materials, vol. 29, pp. 1122-1136,
Schneegans, Microcontacts with sub-30 m pitch for 3D
2000.
chip-on-chip integration, Microelectronic Engineering,
15. M. Murugesan, Y. Ohara, T. Fukushima, T. Tanaka, and
vol. 83, pp. 21552162, 2006.
M. Koyanagi, Low-resistance Cu-Sn electroplated
3. C.-C. Lee, K.-S. Kao, R.-S. Cheng, C.-J. Zhan, and T.-C.
evaporated microbumps for 3D chip stacking, Journal of
Chang. Reliability enhancements of chip-on-chip
Electronic Materials, vol. 41, pp. 720-729, 2012.
package with layout designs of microbumps,
16. B. Chao, S.-H. Chae, X. Zhang, K.-H. Lu, J. Im, P.S. Ho,
Microelectronic Engineering, vol. 120, pp. 138-145, 2014.
Investigation of diffusion and electromigration parameters
4. O. M. Abdelhadi, and L. Ladani, Effect of joint size on
for CuSn intermetallic compounds in Pb-free solders
microstructure and growth kinetics of intermetallic
using simulated annealing, Acta Mater. vol. 55, pp. 2805-
compounds in solidliquid interdiffusion Sn-3.5Ag/Cu-
2814, (2009).
substrate solder joints, Journal of Electronic Packaging,
17. B. Chao, X. Zhang, S.-H. Chae, P.S. Ho, Recent
vol. 135, p. 021004. 2013.
advances on kinetic analysis of electromigration enhanced
5. C.-B. Lee, I.-Y. Lee, S.-B. Jung, and C.-C. Shur, Effect
intermetallic growth and damage formation in Pb-free
of surface finishes on ball shear strength in BGA joints
solder joints, Microelectronics Reliability vol. 49, pp.
with Sn-3.5 mass% Ag solder, Materials Transactions,
253-263, 2009.
vol. 43, pp. 751-756, 2002.
18. M. Li, Z. Li, Y. Xiao, and C. Wang, Rapid formation of
6. I. Shohji, F. Mori, and K. F. Kobayashi, Thermal fatigue
Cu/Cu3Sn/Cu joints using ultrasonic bonding process at
behavior of flip-chip joints with lead-free solders,
ambient temperature, Applied Physics Letters, vol. 102,
Materials Transactions, vol. 42, pp.790-793, 2001.
p. 094104, 2013.
7. M. Lee, M. Yoo, J. Cho, S. Lee, J. Kim, C. Lee, D. Kang,
20. K. Zeng, R. Stierman, T.-C. Chiu, D. Edwards, K. Ano,
C. Zwenger, and R. Lanzone, Study of interconnection
and K. N. Tu, Kirkendall void formation in eutectic SnPb
process for fine pitch flip chip, in Proc. 2009 Electronic
solder joints on bare Cu and its effect on joint reliability,
Components and Technology Conference (ECTC), IEEE,
Journal of Applied Physics, vol. 97, p. 024508, 2005.
2009, pp. 720-723.
21. Y. C. Chan, A. C. K. So, and J. K. L. Lai, Growth kinetic
8. H.-Y. Son, S.-K. Noh, H.-H.ee Jung, W.-S. Lee, J.-S. Oh,
studies of CuSn intermetallic compound and its effect on
and N.-S. Kim, Reliability studies on micro-bumps for 3-
shear strength of LCCC SMT solder joints, Materials
D TSV integration, in Proc. 2013 Electronic Components
Science and Engineering B, vol. 55, pp. 5-13, 1998.
and Technology Conference (ECTC), IEEE,2013 , pp.29-
22. N. Mookam, and K. Kanlayasiri, Evolution of
34.
intermetallic compounds between Sn0.3Ag0.7Cu low-
9. Y.-M. Lin, C.-J. Zhan, J.-Y. Juang, J. H. Lau, T.-H. Chen,
silver lead-free solder and Cu substrate during thermal
R. Lo, M. Kao, T. Tian, and K.-N. Tu, Electromigration
aging, Journal of Materials Science and Technology, vol.
in Ni/Sn intermetallic micro bump joint for 3D IC chip
28, pp. 53-59, 2012.
stacking, in Proc. 2011 Electronic Components and
23. Z. Mei, A. J. Sunwoo, J. W. Morris, Analysis of low-
Technology Conference (ECTC), IEEE, 2011, pp. 351-
temperature intermetallic growth in copper-tin diffusion
357.
couples, Metallurgical Transactions A, vol. 23, pp. 857-
10. J. Kim, J.A. Noquil, T. K. Tan, C.-L. Wu, and S.-Y. Choi,
864, 1992.
Multi-flip chip on lead frame overmolded IC package: a
24. R. Labie, W. Ruythooren, K. Baert, E. Beyne, and B.
novel packaging design to achieve high performance and
Swinnen, Resistance to electromigration of purely
cost effective module package, in Proc. 2005 Electronic
intermetallic micro-bump interconnections for 3D-device
Components and Technology Conference (ECTC), IEEE,
2005, pp. 1819-1821

140
 stacking, in Proc. 2008 Interconnect Technology
Conference (IITC), 2008, pp. 19-21.
25. Y. Wang, S.-H. Chae, R. Dunne, Y. Takahashi, K.
Mawatari, P. Steinmann, T. Bonifield, T. Jiang, J. Im, and
P. S. Ho, Effect of intermetallic formation on
electromigration reliability of TSV-microbump joints in
3D interconnect, in Proc. 2012 Electronic Components
and Technology Conference (ECTC), IEEE, 2012, pp.
319325.
26. C. C. Wei, C. H. Yu, C. H. Tung, R. Y. Huang, C. C.
Hsieh, C. C. Chiu, H. Y. Hsiao, Y. W. Chang, C. K. Lin,
Y. C. Liang, C. Chen, and T. C. Yeh, "Comparison of the
electromigration behaviors between micro-bumps and C4
solder bumps in Proc. 2011 Electronic Components and
Technology Conference (ECTC), IEEE, 2011, pp.706-710.
27. D.-Q. Yu, T.C. Chai, M.L. Thew, Y.Y. Ong, V.S. Rao,
L.C. Wai, and J.H. Lau, Electromigration study of 50 m
pitch micro solder bumps using four-point Kelvin
structure, in Proc. 2009 Electronic Components and
Technology Conference (ECTC), IEEE, 2009, pp. 930
935.
28.. Y. Wang, K. H. Lu, V. Gupta, L. Stiborek, D. Shirley, J.
Im, and P. S. Ho, Effect of Sn grain structure on
electromigration reliability of Pb-free solders, in Proc.
2011 Electronic Components and Technology Conference
(ECTC), 2011, pp. 711-716.
29. K. Lee, K.-S. Kim, Y. Tsukada, K. Suganuma, K.
Yamanaka, S. Kuritani, and M. Ueshima, Effects of the
crystallographic orientation of Sn on the electromigration
of Cu/SnAgCu/Cu ball joints, Journal of Materials
Research, vol. 26, pp. 467-474, 2011.

141