The goal of this project is to build circuits that communicate serially, one bit at a time with an even-parity check. A communication method that sends several data bits over separate wires at the same time is described as parallel. Some examples are the SCSI and IDE disk interfaces, the parallel port, and the PCI bus in your computer. Serial communication sends only one data bit at 1. Examples include, RS-232, USB, FireWire (IEEE 1394), Ethemet, and the public telephone system, Parallel communication systems can be made faster without inereasing the clock rate simply by adding more wires. For example 64-bit PCI can transfer twice as many data bits per bus transaction as 32-bit PCI running atthe same speed. While increasing the number of wires is 4an easy way to increase bandwidth, it gets expensive with large numbers of wires. Another problem is that long parallel wires tend to act like antennas and induce electrical signals in each other. This phenomenon, called cross-talk can cause problems for parallel ‘communication buses. Serial communication works better for longer distances, like across a room. Reducing the number of wires not only reduces cost, but also reduces cross-talk, the noise one data line induces in its neighboring data lines. For this lab we will also implement a simple parity check. A parity check is a very simple form of error checking where one bit of the data sent is reserved for the parity bit, and this bit can be used once the data is received to c ‘fone of the bits sent has been corrupted (i.e. the value sent is not the value received). Overview For this lab, you will implement a 4-bit serial sender and a 4-bit serial receiver circuit both on. ‘their own Basys 3 (3 data bits, and one parity bit). Both circuits will be based on a shift register to convert serial data to parallel or vice versa. A shift register is a sequential logic er in ‘the data serially left or right. Basically ‘Fegular register, except that the output nee dling on the input the shiftinte nthe output for the sender), sack isthe “receive acknowledgerent” signal (an input forthe sender). The sender and receiver are symmetric, The SROY, SACK, and SDA of the sender connect to RRDY, BACK, and ROKTA of the receiver respectively. SDATA The figure above shows how the transfer of 4 bits of data are implemented vi and RDY signals. When the sender has data to send it puts the most. c ren the sender sees SACK go low it. ‘register to put the next bit, bit 2, on the output and pulls sR0¥ high. ‘Sees SRY go high it shifts in the next bit and pulls sack high. The process J and 0. 1. Develop a state diagram model for both the sender and the receiver unit.