NATIONAL INSTITUTE OF TECHNOLOGY

JAMSHEDPUR
SPRING SEMESTER 2016-17
Department of Computer Science and Engineering
TEST-2
Course Code: CS602 (6th Sem) Course Title: Advanced Computer Architecture

Date: 31/03/2017 Course Instructor: Ansuman Mahapatra

Duration: 1 Hour Max. Marks: 20

All Questions are compulsory. Assume any missing data.

1. What is the use of critical word first and early restart policies? [2]
Ans: Refer Book Cache optimization chapter.
2. Given a fully associative cache having 3 lines. Processor accesses the block in following
sequence.
AB C AC D B F AB DA B C B F
How many misses will be there, if processor uses following block replacement policies; [3]
a. LRU
b. NMRU
c. PLRU

Ans: LRU 10

3. What is the use of Write Buffer. How write buffer can be optimized to help optimize cache? [3]
Ans: Write buffer is used for temporary storing data blocks which are to be written to the main
memory and are evicted from the cache.
Two Optimizations can be applied on write buffer: Merging Write buffer and Giving priority to
read misses over writes to reduce miss penalty.
4. There are dual core system executing a program having following instructions. [4]

Core 0 Core 1

Write A
Read A
Write A
Read B
Write B
Write B
Write A

How many times bus will be used by both cores with Write Update and Write Invalidate
Protocol?

Answer:
Write Update

Core 0 Core 1

1 (Write Miss)

1 (Data provided from Core 0)

1 (Write update core 0 value A)

1 (Read Miss)

0 (Write locally as it is not shared, so no bus access)

1 (Value shared from Core 0)

1 (Value updated to core 0)

Total: 6

Write Invalidate

Core 0 Core 1

1 (Write Miss)

1 (Data provided from Core 0)

1 (Invalidate core 0 value of A)

1 (Read Miss)

0 (Write locally as it is not shared, so no bus access)

1 (Value shared from Core 0, and core 0 data invalidated)

0 (locally read as data not shared)

Total: 5

5. Consider the same dual core system as above with MSI coherence protocol. Assume, initially all
the blocks are in main memory. What will be the state of the blocks in each core after each
instruction executed? [3]

Answer:

Core 0 Core 1
Write A
Modified Invalid
Shared Read A
Shared
Write A
Invalid Modified
Read B
Shared Invalid
Write B
Modified Invalid
Write B
Invalid Modified
Write A
Invalid Modified
6. What is the application of the following caches? [5]
a. VIPT Cache
b. Victim Cache
c. Trace Cache
d. Lookup-free Cache
e. Multi-banked Cache

Ans:

Refer Book Cache optimization chapter.

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