Schematic Diagrams

System Block Diagram

VDD3,VDD5
W150HRM/W170HR Huron River System Block Diagram W150HRM 7IN1 6-7P-W15R7-002
W150HRM MAIN BOARD
GPU NVDIDA N12x NVVDD 6-71-W15H0-D02

PCIE*8 AUDIO BOARD

5V,3V,5VS,3VS,1.5VS, PHONE JACK x3, USB x1
1.8VS,+1.5S_CPU Sandy Bridge RJ-11 6-71-W150A-D02

Nvidia 800/1067/1333 MHz SECOND HDD/ODD BOARD

1.8V, PEX_VDD,0.85VS PROCESSOR DDR3 / 1.5V 6-71-W150N-D01
Fermi N12E-GE-A1 DDRIII
rPGA988B SO-DIMM2 FINGER PRINTER BOARD
RAM SIZE:2GB SHEET 10 6-71-B510F-D02
1.5V,0.75VS(VTT_MEM)
FBVDDQ (128MX16) SYSTEM SMBUS DDRIII
1005 Balls 0.1"~13 CLICK BOARD
SO-DIMM1
B.Schematic Diagrams

FDI DMI*4 6-71-B5102-D04

SHEET 9
1.05VS_VTT 0.5"~5.5" <=8" AUDIO BOARD POWER SWITCH BOARD
6-71-B510S-D03
<8" W150HNM
LCD
CRT CONNECTOR
CONNECTOR <15" INT SPKER-R
VGFX_CORE SPDIF MIC HP LED & VGA S/W BOARD
OUT IN OUT 6-71-B5134-D01

Sheet 1 of 49 HDMI Connector CougarPoint USB PORT (USB8) W170HR 8IN1 6-7P-W1708-001
W150HNM (INT SPK R)
System Block SENTELIC
6-49-C4102-010
TOUCH PAD
Controller W150HN MAIN BOARD
6-71-W1500-D01
CLICK BOARD SPI Hub (PCH)
Diagram TPM 1.2 W150HNM AUDIO BOARD
Optional PHONE JACK x3, USB x1
INT SPKER-L
32.768 KHz Azalia Codec RJ-11 6-71-W170A-D01
EC LPC 27x27mm REALTAK
ITE 8518E 33 MHz 989 Ball FCBGA ALC269 SECOND HDD/ODD BOARD
0.5"~11" 6-71-W170N-D01
128pins LQFP
14 *1 4*1 .6m m INT MIC K/B TRANSFER BOARD
BIOS 6-71-B7117-D01
SPI 24 MHz AZALIA LINK
INT. K/B
EC SMBUS CLICK BOARD
25 6-71-B7112-D02
PCIE 100 MHz <12" MHz
THERMAL SMART SMART POWER SWITCH BOARD
SENSOR FAN BATTERY 6-71-B711S-D02
W83L771AWG AC-IN 32.768KHz
Mini PCIE Mini PCIE JMICRO LED & VGA S/W BOARD
SOCKET SOCKET JMC251_C 6-71-B7134-D01
SATA I/II 3.0Gb/s USB2.0 3G MSATA CARD WLAN CARD
<12" (USB2/SATA3) (USB2) DEBUG BOARD
USB3.0 LAN READER 6-71-W840TD-D03
480 Mbps VLI8012 (Optional)
1"~16" *NEC uPD720200

B5100 RJ-45 7IN1

SATA HDD SATA ODD eSATA SOCKET
(B4100M) USB PORT1 CCD FINGER PRINTER BOARD
(USB0) (USB5)
(USB4)
FingerPrint USB PORT2 USB PORT3

W150HNM (Optional) 12 MHz

SECOND HDD BOARD
USB3.0

B - 2 System Block Diagram

http://hobi-elektronika.net
 Schematic Diagrams

Sandy Bridge Processor 1/7

Sandy Bridge Processor 1/7 ( DMI,PEG,FDI )
1 . 05 V S _ V T T

CPU U4 9 A
J22 20 mil P E G_ I R C O M P _ R R1 3 3 2 4 . 9 _ 1% _ 0 4
P E G _ I C O MP I J21
B2 7 P E G_ I C OM P O H 22
20 DM I_ T X N0 B2 5 DM I_ RX # [0 ] P E G _ R C OM P O
H1 6 H 15 H 8
H 8 _ 0 D 4 _ 4 H 8 _0 D 4 _4 H 8 _ 0D 4 _ 4 20 DM I_ T X N1 A2 5 DM I_ RX # [1 ]
20 DM I_ T X N2 B2 4 DM I_ RX # [2 ] K3 3
20 DM I_ T X N3 DM I_ RX # [3 ] PE G _ RX# [0 ] PE G_ R X# 0 12
M 35
PE G _ RX# [1 ] PE G_ R X# 1 12
B2 8 L34
20 DM I_ T X P 0 B2 6 DM I_ RX [0 ] PE G _ RX# [2 ] J35 PE G_ R X# 2 12
20 DM I_ T X P 1 DM I_ RX [1 ] PE G _ RX# [3 ] PE G_ R X# 3 12
A2 4 J32
20 DM I_ T X P 2 DM I_ RX [2 ] PE G _ RX# [4 ] PE G_ R X# 4 12
B2 3 H 34

DMI
20 DM I_ T X P 3 DM I_ RX [3 ] PE G _ RX# [5 ] H 31 PE G_ R X# 5 12
PE G _ RX# [6 ] PE G_ R X# 6 12
G 21 G 33
20 DM I_ RX N 0 DM I _ T X# [ 0 ] PE G _ RX# [7 ] PE G_ R X# 7 12
E2 2 G 30
20 DM I_ RX N 1 F21 DM I _ T X# [ 1 ] PE G _ RX# [8 ] F35
20 DM I_ RX N 2 D 21 DM I _ T X# [ 2 ] PE G _ RX# [9 ] E3 4
20 DM I_ RX N 3 DM I _ T X# [ 3 ] P E G _ RX # [1 0 ] E3 2
G 22 P E G _ RX # [1 1 ] D 33

B.Schematic Diagrams
20 DM I_ RX P 0 D 22 DM I _ T X[ 0] P E G _ RX # [1 2 ] D 31
20 DM I_ RX P 1
F20 DM I _ T X[ 1] P E G _ RX # [1 3 ] B3 3
PEG Compensation Signal
20 DM I_ RX P 2 C 21 DM I _ T X[ 2] P E G _ RX # [1 4 ] C 32
20 DM I_ RX P 3 DM I _ T X[ 3] P E G _ RX # [1 5 ]

PCI EXPRESS* - GRAPHICS

J33
CAD NOTE: PEG_ICOMPI and RCOMPO signals
P E G _R X [ 0 ] L35 PE G_ R X0 12 should be shorted and routed with
P E G _R X [ 1 ] PE G_ R X1 12
K3 4
A2 1 P E G _R X [ 2 ] H 35
PE G_ R X2 12 - max length = 500 mils
20 F DI_ T X N0 H 19 FD I 0_ T X # [ 0 ] P E G _R X [ 3 ] H 32 PE G_ R X3 12
20 F DI_ T X N1 FD I 0_ T X # [ 1 ] P E G _R X [ 4 ] PE G_ R X4 12 - typical impedance = 43 mohms
E1 9 G 34
20 F DI_ T X N2 FD I 0_ T X # [ 2 ] P E G _R X [ 5 ] PE G_ R X5 12 PEG_ICOMPO signals should be routed with
F18 G 31
20 F DI_ T X N3 B2 1 FD I 0_ T X # [ 3 ] P E G _R X [ 6 ] F33 PE G_ R X6 12
PE G_ R X7 12 - max length = 500 mils

Intel(R ) FDI
20 F DI_ T X N4 C 20 FD I 1_ T X # [ 0 ] P E G _R X [ 7 ] F30
20 F DI_ T X N5 FD I 1_ T X # [ 1 ] P E G _R X [ 8 ]
20 F DI_ T X N6
D 18
FD I 1_ T X # [ 2 ] P E G _R X [ 9 ]
E3 5 - typical impedance = 14.5 mohms
E1 7 E3 3
20 F DI_ T X N7 FD I 1_ T X # [ 3 ] PE G _ RX[1 0 ] F32

20
20
F DI_ T X P 0
F DI_ T X P 1
A2 2
G 19 FD I 0_ T X [ 0 ]
PE G _ RX[1 1 ]
PE G _ RX[1 2 ]
PE G _ RX[1 3 ]
D 34
E3 1
C 33
Sheet 2 of 49
E2 0 FD I 0_ T X [ 1 ] PE G _ RX[1 4 ] B3 2
CAD NOTE: DP_COMPIO and ICOMPO signals
should be shorted near balls and routed with
20
20
20
F DI_ T X P 2
F DI_ T X P 3
F DI_ T X P 4
G 18
B2 0
C 19
FD
FD
FD
I 0_ T X [ 2 ]
I 0_ T X [ 3 ]
I 1_ T X [ 0 ]
PE G _ RX[1 5 ]

P E G_ T X # [ 0 ]
M 29
M 32
PE
PE
G_ T X # _0
G_ T X # _1
C
C
591
589
0.
0.
22 u _ 1 0 V _ X5 R
22 u _ 1 0 V _ X5 R
_ 04
_ 04
PE G_ T X #0 12
Sandy Bridge
- typical impedance < 25 mohms 20 F DI_ T X P 5 D 19 FD I 1_ T X [ 1 ] P E G_ T X # [ 1 ] M 31 PE G_ T X #1 12

1. 05 V S _V TT 1 .0 5 V S_ VT T
20
20
F DI_ T X P 6
F DI_ T X P 7
F17

J18
FD
FD
I 1_ T X [ 2 ]
I 1_ T X [ 3 ]
P E G_ T X # [ 2 ]
P E G_ T X # [ 3 ]
P E G_ T X # [ 4 ]
L32
L29
K3 1
PE
PE
PE
PE
G_ T X # _2
G_ T X # _3
G_ T X # _4
G_ T X # _5
C
C
C
C
594
596
598
601
0.
0.
0.
0.
22 u _ 1 0 V _ X5 R
22 u _ 1 0 V _ X5 R
22 u _ 1 0 V _ X5 R
22 u _ 1 0 V _ X5 R
_ 04
_ 04
_ 04
_ 04
PE
PE
PE
G_ T X #2
G_ T X #3
G_ T X #4
12
12
12
Processor 1/7
20 F D I_ F S Y N C 0 J17 F D I 0_ F S Y N C P E G_ T X # [ 5 ] K2 8 PE G_ T X # _6 PE G_ T X #5 12
C 606 0. 22 u _ 1 0 V _ X5 R _ 04 PE G_ T X #6 12
20 F D I_ F S Y N C 1 F D I 1_ F S Y N C P E G_ T X # [ 6 ] J30 PE G_ T X # _7 C 608 0. 22 u _ 1 0 V _ X5 R _ 04
H 20 P E G_ T X # [ 7 ] J28 PE G_ T X #7 12
20 F D I_ INT F D I _I N T P E G_ T X # [ 8 ] H 29
J19 P E G_ T X # [ 9 ] G 27
20 F D I _ LS Y N C 0 H 17 F D I 0_ L S Y N C P E G _T X # [ 1 0 ] E2 9
R 521 R5 1 9
20 F D I _ LS Y N C 1 F D I 1_ L S Y N C P E G _T X # [ 1 1 ] F27
1 K_ 1 % _ 0 4 2 4 . 9_ 1 % _ 0 4
P E G _T X # [ 1 2 ] D 28
ED P H P D Fu nc ti o n D is ab l e P E G _T X # [ 1 3 ] F26
ED P_ HP D : Pu ll -u p 10 K- D IS A BL ED H PD P E G _T X # [ 1 4 ] E2 5
E D P _ C OM P I O A1 8 P E G _T X # [ 1 5 ]
A1 7 e D P _ C OM P I O M 28
DP Compensation Signal PE G_ T X _ 0 C 587 0. 22 u _ 1 0 V _ X5 R _ 04
EDP _ H PD B1 6 e D P _ I C OM P O P E G_ T X [ 0 ] M 33 PE G_ T X _ 1 PE G_ T X 0 12
C 588 0. 22 u _ 1 0 V _ X5 R _ 04 PE G_ T X 1 12
e DP_ H P D P E G_ T X [ 1 ] M 30 PE G_ T X _ 2 C 593 0. 22 u _ 1 0 V _ X5 R _ 04
P E G_ T X [ 2 ] L31 PE G_ T X 2 12
PE G_ T X _ 3 C 595 0. 22 u _ 1 0 V _ X5 R _ 04
C 15 P E G_ T X [ 3 ] L28 PE G_ T X _ 4 PE G_ T X 3 12
11 DP _ A U X _ P C 597 0. 22 u _ 1 0 V _ X5 R _ 04 PE G_ T X 4 12
D 15 e DP_ AU X P E G_ T X [ 4 ] K3 0 PE G_ T X _ 5 C 602 0. 22 u _ 1 0 V _ X5 R _ 04
11 DP _ A U X _ N e DP_ AU X# P E G_ T X [ 5 ] K2 7 PE G_ T X 5 12
PE G_ T X _ 6 C 604 0. 22 u _ 1 0 V _ X5 R _ 04
P E G_ T X [ 6 ] J29 PE G_ T X _ 7 PE G_ T X 6 12
C 607 0. 22 u _ 1 0 V _ X5 R _ 04

eDP
P E G_ T X [ 7 ] PE G_ T X 7 12
C 17 J27
11 DP _ T XP _ 0 F16 e DP_ T X [0 ] P E G_ T X [ 8 ] H 28
11 DP _ T XP _ 1 C 16 e DP_ T X [1 ] P E G_ T X [ 9 ] G 28
11 DP _ T XP _ 2 e DP_ T X [2 ] P E G_ T X [ 1 0 ]
G 15 E2 8
e DP_ T X [3 ] P E G_ T X [ 1 1 ] F28
C 18 P E G_ T X [ 1 2 ] D 27 Q 26
11
11
DP _ T XN_ 0
DP _ T XN_ 1
E1 6 e DP_ T X # [0 ]
e DP_ T X # [1 ]
P E G_ T X [ 1 3 ]
P E G_ T X [ 1 4 ]
E2 6 5
G ND N C
1 SC70-5 & SC70-3
D 16 D 25 2
11 DP _ T XN_ 2 F15 e DP_ T X # [2 ] P E G_ T X [ 1 5 ] GN D Co-lay
e DP_ T X # [3 ] 4 3
VC C VO
3 .3 V
P Z 9 8 8 2 7- 36 4 B -0 1 F * T MP 2 0
Q 27
2 1
VC C O UT 1:2 (4mils:8mils) T H E R M _V OL T 3 4
C6 7 3 8/30
3 C6 7 2
G ND
0 . 1u _ 1 0 V _ X 7R _ 0 4 0 . 1 u_ 1 0 V _ X 7R _ 0 4
G 71 1 S T 9 U
1
3

2
PLACE NEAR U3

3 , 5 , 2 3 , 2 4, 25 , 3 5 , 3 9 1 . 0 5V S _ V T T
3 , 8, 11 , 1 2 , 1 6 , 1 8, 19 , 2 0 , 2 2 , 2 3, 24 , 2 5 , 2 7 , 2 8, 29 , 3 0 , 3 3 , 3 5, 37 , 3 8 , 3 9 3 . 3 V

Sandy Bridge Processor 1/7 B - 3

http://hobi-elektronika.net
 Schematic Diagrams

Sandy Bridge Processor 2/7

Sandy Bridge Processor 2/7 ( CLK,MISC,JTAG ) Processor Pullups/Pull downs
PU/PD for JTAG signals 1 .0 5 V S_ V T T
1. 0 5 V S _ V T T

H _ P R O C H OT # R1 1 0 62 _ 0 4
5 1_ 0 4 R5 1 0 XD P _ TM S
5 1_ 0 4 R5 0 6 XD P _ TD I _ R
* 5 1_ 0 4 R5 0 8 XD P _ P RE Q # U 49 B H _ C P U P W R GD _ R R 4 9 9 10 K _ 0 4
5 1_ 0 4 R5 1 1 XD P _ TD O_ R
5 1_ 0 4 R5 1 3 XD P _ TC L K
5 1_ 0 4 R5 0 5 XD P _ TR S T # TRACE WIDTH 10MIL, LENGTH <500MILS
A2 8
H _S N B _ I V B # C2 6 B C LK A2 7 CL K _ E X P _ P 1 9
2 3 H _ SNB _ IVB # P R OC _S E LE C T # BC L K# CL K _ E X P _ N 1 9

MISC

CLOCKS
3 . 3V S AN3 4
S K T OC C # A1 6
D P L L _R E F _ S S C LK CL K _ DP _ P 1 9
A1 5
R 4 94 1 K _0 4 X D P _D B R _R
DP L L _ RE F _ S SC L K# C L K _ D P _ N 19 DDR3 Compensation Signals
H _C A T E R R # AL 3 3 S M_ R C OM P _ 0 R5 3 1 14 0 _ 1 %_ 0 4
C A TE R R #
I f PR OC HO T# is n ot u se d, S M_ R C OM P _ 1 R5 2 8 25 . 5 _ 1 %_ 0 4
t he n it m us t b e te rm in at ed AN3 3 R8

THERMAL
B.Schematic Diagrams

C P UD RA M RS T # S M_ R C OM P _ 2 R5 2 9 20 0 _ 1 %_ 0 4
w it h a 56 -O +- 5% p ul l- up 2 3, 3 4 H_ P E CI PEC I S M_ D R A MR S T #

r es is to r to 1. 05 VS _V TT .

DDR3
MISC
H _ P R OC H O T# R1 0 9 56 _ 1 % _0 4 H _ P R O C H OT # _ D AL 3 2 AK1 S M _ R C O MP _0
3 9 H _ P R O C H OT # P R OC H OT # S M _ R C OM P [ 0] A5 S M _ R C O MP _1
S M _ R C OM P [ 1] A4 S M _ R C O MP _2
S M _ R C OM P [ 2]
AN3 2
2 3 H _ TH R M T R I P #

Sheet 3 of 49 T H E R MT R I P #

S3 circuit:- DRAM PWR GOOD logic

3 . 3V 3 .3 V

Sandy Bridge P R DY #
PREQ #
AP2 9
AP2 7
X D P _P R D Y #
X D P _P R E Q#
C 2 78
A R2 6 X D P _T C LK

Processor 2/7 T CK

*0 . 1 u_ 1 6 V _ Y 5V _0 4
A R2 7 X D P _T M S R 1 87 R1 8 8
A M3 4 T MS AP3 0 X D P _T R S T# 1 .5 V S _ CP U

PWR MANAGEMENT
2 0 H _ P M_ S Y N C

JTAG & BPM

P M _S Y N C TR S T #

* 2 00 _ 0 4

* 10 0 K _ 04
A R2 8 X D P _T D I _R
T DI AP2 6 X D P _T D O_ R
R4 9 8 *1 0 mi l _ sh o rt H _ C P U P W R GD _R AP3 3 T DO R 17 5
2 3 H _ C P U P W R GD U N C O R E P W R G OO D
2 0 0 _1 % _ 04

5
A L 35 X D P _D B R _ R 1
V8 DBR # 2 0 P M _D R A M_ P W R GD 4
P M S Y S _P W R G D _ B U F R1 7 4 13 0 _ 1% _ 0 4 V D D P W R G OO D _ R P MS Y S _ P W R G D _ B U F
S M _D R A M P W R OK 2
A T 28 2 0, 3 7 1 . 8 V S _ P W R G D
X DP _B P M0 _ R
1 . 05 V S _ V T T BPM # [ 0] A R2 9 X DP _B P M1 _ R U1 4
Buffered reset to CPU BPM # [ 1]

3
A R3 0 X DP _B P M2 _ R * MC 7 4V H C 1 G 08 D F T 1G R 16 8
B UF _ C P U_ RS T # AR3 3 BPM # [ 2] A T 30 X DP _B P M3 _ R * 39 _ 0 4
RE S ET # BPM # [ 3] AP3 2 X DP _B P M4 _ R
3 .3 VS BPM # [ 4] A R3 1 X DP _B P M5 _ R
R5 1 2
BPM # [ 5] A T 31 X DP _B P M6 _ R R1 8 6 0_04

D
7 5_ 0 4 BPM # [ 6] A R3 2 X DP _B P M7 _ R Q 13
BPM # [ 7]
R 6 58 G
3 5 , 3 7, 38 S U S B
R5 1 5 4 3 . 2_ 1 % _0 4 B U F _ C P U _ R S T# * MT N 7 0 0 2Z H S 3

S
3

1 0K _0 4 D P Z 9 8 8 2 7-3 6 4 B -0 1F
Q 3 7B
5G M T DN7 0 0 2 Z HS 6 R
S H _ P R O C H OT #
4
6

D
Q1 6
2G Q 37 A
1 2 , 22 , 2 8 P L T _R S T # S M TD N 7 0 0 2Z H S 6 R G C6 2 2
3 4 H _ P R OC H OT # _ E C
1

MT N 7 0 0 2 Z H S 3
S3 circuit:- DRAM_RST# to memory

S
R 20 3 47 p _ 50 V _ N P O_ 0 4

R 52 4 C 6 21
R5 1 8 *1 . 5 K _ 1% _ 0 4
1 0 0K _ 0 4
should be high during S3
R 51 7 1 .5 V
10 0 K _ 0 4 6 8 p _5 0 V _ N P O _ 04
* 75 0 _ 1% _ 0 4
CAD Note: Capacitor need to be placed R 2 30
close to buffer output pin R2 3 1 * 0 _0 4 1 K_ 0 4

Q1 7
MT N 7 0 0 2 Z H S 3
C P U D R A MR S T # S D R2 3 5 1 K _ 04
D D R 3 _ D R A MR S T # 9 , 1 0

D RA M RS T _ CN T RL 8 ,1 9

G
R 22 5 C3 1 5

4 . 9 9 K _1 % _ 0 4 0 . 0 47 u _ 10 V _ X 7 R _ 0 4

6 , 8 , 9 , 1 0, 2 5 , 2 9 , 35 , 3 7 , 3 8 1 . 5 V
6 ,3 5 ,3 8 1 .5 V S_ C PU
2 , 5 , 2 3 , 24 , 2 5 , 3 5, 3 9 1 . 0 5V S _V TT
2 , 8 , 1 1 , 12 , 1 6 , 1 8, 1 9 , 2 0 , 22 , 2 3 , 2 4, 2 5 , 2 7 , 28 , 2 9 , 3 0, 3 3 , 3 5, 37 , 3 8 , 3 9 3 . 3 V
9 , 1 0, 1 1 , 1 2, 18 , 1 9 , 20 , 2 1 , 2 2, 23 , 2 4 , 25 , 2 7 , 2 8, 2 9 , 3 0 , 31 , 3 2 , 3 3, 3 4 , 3 5 , 39 3 . 3 V S

B - 4 Sandy Bridge Processor 2/7

http://hobi-elektronika.net
 Schematic Diagrams

Sandy Bridge Processor 3/7

Sandy Bridge Processor 3/7 ( DDR3 )

U49
C U49D

AB6 AE2
9 M_A_DQ[63:0] SA_CLK[ 0] AA6 M_A_CLK_DDR0 9 10 M_B_DQ[ 63: 0] SB_CLK[0] AD2 M_B_CLK_DDR2 10
SA_CLK#[ 0] M_A_CLK_DDR#0 9 SB_CLK#[0] M_B_CLK_DDR#2 10
M_A_DQ0 C5 V9 M_B_DQ0 C9 R9
SA_DQ[0] SA_CKE[ 0] M_A_CKE0 9 SB_DQ[0] SB_CKE[0] M_B_CKE2 10
M_A_DQ1 D5 M_B_DQ1 A7
M_A_DQ2 D3 SA_DQ[1] M_B_DQ2 D10 SB_DQ[1]
M_A_DQ3 D2 SA_DQ[2] M_B_DQ3 C8 SB_DQ[2]
M_A_DQ4 D6 SA_DQ[3] AA5 M_B_DQ4 A9 SB_DQ[3] AE1
C6 SA_DQ[4] SA_CLK[ 1] AB5 M_A_CLK_DDR1 9 A8 SB_DQ[4] SB_CLK[1] AD1 M_B_CLK_DDR3 10
M_A_DQ5 M_B_DQ5
C2 SA_DQ[5] SA_CLK#[ 1] V10 M_A_CLK_DDR#1 9 D9 SB_DQ[5] SB_CLK#[1] R10 M_B_CLK_DDR#3 10
M_A_DQ6 M_A_CKE1 9 M_B_DQ6 M_B_CKE3 10
M_A_DQ7 C3 SA_DQ[6] SA_CKE[ 1] M_B_DQ7 D8 SB_DQ[6] SB_CKE[1]
M_A_DQ8 F10 SA_DQ[7] M_B_DQ8 G4 SB_DQ[7]
M_A_DQ9 F8 SA_DQ[8] M_B_DQ9 F4 SB_DQ[8]
M_A_DQ10 G10 SA_DQ[9] AB4 M_B_DQ10 F1 SB_DQ[9] AB2
M_A_DQ11 G9 SA_DQ[10] SA_CLK[ 2] AA4 M_B_DQ11 G1 SB_DQ[10] SB_CLK[2] AA2
M_A_DQ12 F9 SA_DQ[11] SA_CLK#[ 2] W9 M_B_DQ12 G5 SB_DQ[11] SB_CLK#[2] T9
F7 SA_DQ[12] SA_CKE[ 2] F5 SB_DQ[12] SB_CKE[2]

B.Schematic Diagrams
M_A_DQ13 M_B_DQ13
M_A_DQ14 G8 SA_DQ[13] M_B_DQ14 F2 SB_DQ[13]
M_A_DQ15 G7 SA_DQ[14] M_B_DQ15 G2 SB_DQ[14]
M_A_DQ16 K4 SA_DQ[15] AB3 M_B_DQ16 J7 SB_DQ[15] AA1
M_A_DQ17 K5 SA_DQ[16] SA_CLK[ 3] AA3 M_B_DQ17 J8 SB_DQ[16] SB_CLK[3] AB1
M_A_DQ18 K1 SA_DQ[17] SA_CLK#[ 3] W10 M_B_DQ18 K10 SB_DQ[17] SB_CLK#[3] T10
M_A_DQ19 J1 SA_DQ[18] SA_CKE[ 3] M_B_DQ19 K9 SB_DQ[18] SB_CKE[3]
J5 SA_DQ[19] J9 SB_DQ[19]
M_A_DQ20 M_B_DQ20
M_A_DQ21 J4 SA_DQ[20] M_B_DQ21 J10 SB_DQ[20]
M_A_DQ22 J2 SA_DQ[21] AK3 M_B_DQ22 K8 SB_DQ[21] AD3
SA_DQ[22] SA_CS#
[ 0] M_A_CS#0 9 SB_DQ[22] SB_CS#[0] M_B_CS#2 10
M_A_DQ23 K2 AL3 M_B_DQ23 K7 AE3
M_A_CS#1 9 M_B_CS#3 10

Sheet 4 of 49
M_A_DQ24 M8 SA_DQ[23] SA_CS#
[ 1] AG1 M_B_DQ24 M5 SB_DQ[23] SB_CS#[1] AD6
M_A_DQ25 N10 SA_DQ[24] SA_CS#
[ 2] AH1 M_B_DQ25 N4 SB_DQ[24] SB_CS#[2] AE6
M_A_DQ26 N8 SA_DQ[25] SA_CS#
[ 3] M_B_DQ26 N2 SB_DQ[25] SB_CS#[3]
M_A_DQ27 N7 SA_DQ[26] M_B_DQ27 N1 SB_DQ[26]
M_A_DQ
M_A_DQ
M_A_DQ
28
29
30
M10
M9
N9
SA_DQ[27]
SA_DQ[28]
SA_DQ[29] SA_ODT
[ 0]
AH3
AG3
M_A_ODT0 9
M
M
M
_B_DQ28
_B_DQ29
_B_DQ30
M4
N5
M2
SB_DQ[27]
SB_DQ[28]
SB_DQ[29] SB_ODT[0]
AE4
AD4
M_B_ODT2 10
Sandy Bridge
M_A_ODT1 9 M_B_ODT3 10
M_A_DQ
M_A_DQ
31
32
M
AG
7
6
SA_DQ[30]
SA_DQ[31]
SA_ODT
[ 1]
SA_ODT
[ 2]
AG2
AH2
M
M
_B_DQ31
_B_DQ32
M1
AM5
SB_DQ[30]
SB_DQ[31]
SB_ODT[1]
SB_ODT[2]
AD5
AE5 Processor 3/7

DDR SYSTEM MEMORY B

DDR SYSTEM MEMORY A

M_A_DQ33 AG5 SA_DQ[32] SA_ODT

[ 3] M_B_DQ33 AM6 SB_DQ[32] SB_ODT[3]
M_A_DQ34 AK6 SA_DQ[33] M_B_DQ34 AR3 SB_DQ[33]
AK5 SA_DQ[34] AP3 SB_DQ[34]
M_A_DQ35 M_B_DQ35
M_A_DQ36 AH5 SA_DQ[35] M_B_DQ36 AN3 SB_DQ[35]
M_A_DQ37 AH6 SA_DQ[36] C4 M_A_DQS#0 M_A_DQS#[ 7:0] 9 M_B_DQ37 AN2 SB_DQ[36] D7 M_B_DQS#0 M_B_DQS#[7:0] 10
M_A_DQ38 AJ5 SA_DQ[37] SA_DQS#[ 0] G6 M_A_DQS#1 M_B_DQ38 AN1 SB_DQ[37] SB_DQS#[0] F3 M_B_DQS#1
M_A_DQ39 AJ6 SA_DQ[38] SA_DQS#[ 1] J3 M_A_DQS#2 M_B_DQ39 AP2 SB_DQ[38] SB_DQS#[1] K6 M_B_DQS#2
M_A_DQ40 AJ8 SA_DQ[39] SA_DQS#[ 2] M6 M_A_DQS#3 M_B_DQ40 AP5 SB_DQ[39] SB_DQS#[2] N3 M_B_DQS#3
M_A_DQ41 AK8 SA_DQ[40] SA_DQS#[ 3] AL6 M_A_DQS#4 M_B_DQ41 AN9 SB_DQ[40] SB_DQS#[3] AN5 M_B_DQS#4
M_A_DQ42 AJ9 SA_DQ[41] SA_DQS#[ 4] AM 8 M_A_DQS#5 M_B_DQ42 AT5 SB_DQ[41] SB_DQS#[4] AP9 M_B_DQS#5
AK9 SA_DQ[42] SA_DQS#[ 5] AR12 AT6 SB_DQ[42] SB_DQS#[5] AK12
M_A_DQ43 M_A_DQS#6 M_B_DQ43 M_B_DQS#6
M_A_DQ44 AH8 SA_DQ[43] SA_DQS#[ 6] AM 15 M_A_DQS#7 M_B_DQ44 AP6 SB_DQ[43] SB_DQS#[6] AP15 M_B_DQS#7
M_A_DQ45 AH9 SA_DQ[44] SA_DQS#[ 7] M_B_DQ45 AN8 SB_DQ[44] SB_DQS#[7]
M_A_DQ46 AL9 SA_DQ[45] M_B_DQ46 AR6 SB_DQ[45]
M_A_DQ47 AL8 SA_DQ[46] M_B_DQ47 AR5 SB_DQ[46]
M_A_DQ48 AP11 SA_DQ[47] M_B_DQ48 AR9 SB_DQ[47]
AN11 SA_DQ[48] D4 M_A_DQS[ 7:0] 9 AJ11 SB_DQ[48] C7 M_B_DQS[7: 0] 10
M_A_DQ49 M_A_DQS0 M_B_DQ49 M_B_DQS0
AL12 SA_DQ[49] SA_DQS[ 0] F6 AT8 SB_DQ[49] SB_DQS[0] G3
M_A_DQ50 M_A_DQS1 M_B_DQ50 M_B_DQS1
M_A_DQ51 AM12 SA_DQ[50] SA_DQS[ 1] K3 M_A_DQS2 M_B_DQ51 AT9 SB_DQ[50] SB_DQS[1] J6 M_B_DQS2
M_A_DQ52 AM11 SA_DQ[51] SA_DQS[ 2] N6 M_A_DQS3 M_B_DQ52 AH11 SB_DQ[51] SB_DQS[2] M3 M_B_DQS3
M_A_DQ53 AL11 SA_DQ[52] SA_DQS[ 3] AL5 M_A_DQS4 M_B_DQ53 AR8 SB_DQ[52] SB_DQS[3] AN6 M_B_DQS4
M_A_DQ54 AP12 SA_DQ[53] SA_DQS[ 4] AM9 M_A_DQS5 M_B_DQ54 AJ12 SB_DQ[53] SB_DQS[4] AP8 M_B_DQS5
M_A_DQ55 AN12 SA_DQ[54] SA_DQS[ 5] AR11 M_A_DQS6 M_B_DQ55 AH12 SB_DQ[54] SB_DQS[5] AK11 M_B_DQS6
M_A_DQ56 AJ14 SA_DQ[55] SA_DQS[ 6] AM14 M_A_DQS7 M_B_DQ56 AT11 SB_DQ[55] SB_DQS[6] AP14 M_B_DQS7
AH14 SA_DQ[56] SA_DQS[ 7] AN14 SB_DQ[56] SB_DQS[7]
M_A_DQ57 M_B_DQ57
AL15 SA_DQ[57] AR14 SB_DQ[57]
M_A_DQ58 M_B_DQ58
M_A_DQ59 AK15 SA_DQ[58] M_B_DQ59 AT14 SB_DQ[58]
M_A_DQ60 AL14 SA_DQ[59] M_B_DQ60 AT12 SB_DQ[59]
SA_DQ[60] M_A_A[15:0] 9 SB_DQ[60] M_B_A[15:0] 10
M_A_DQ61 AK14 AD10 M_A_A0 M_B_DQ61 AN15 AA8 M_B_A0
M_A_DQ62 AJ15 SA_DQ[61] SA_MA[ 0] W1 M_A_A1 M_B_DQ62 AR15 SB_DQ[61] SB_MA[0] T7 M_B_A1
M_A_DQ63 AH15 SA_DQ[62] SA_MA[ 1] W2 M_A_A2 M_B_DQ63 AT15 SB_DQ[62] SB_MA[1] R7 M_B_A2
SA_DQ[63] SA_MA[ 2] W7 M_A_A3 SB_DQ[63] SB_MA[2] T6 M_B_A3
SA_MA[ 3] V3 SB_MA[3] T2
M_A_A4 M_B_A4
SA_MA[ 4] V2 M_A_A5 SB_MA[4] T4 M_B_A5
SA_MA[ 5] W3 M_A_A6 SB_MA[5] T3 M_B_A6
AE10 SA_MA[ 6] W6 M_A_A7 AA9 SB_MA[6] R2 M_B_A7
9 M_A_BS0 SA_BS[0] SA_MA[ 7] 10 M_B_BS0 SB_BS[0] SB_MA[7]
AF10 V1 M_A_A8 AA7 T5 M_B_A8
9 M_A_BS1 SA_BS[1] SA_MA[ 8] 10 M_B_BS1 SB_BS[1] SB_MA[8]
V6 W5 M_A_A9 R6 R3 M_B_A9
9 M_A_BS2 SA_BS[2] SA_MA[ 9] AD8 10 M_B_BS2 SB_BS[2] SB_MA[9] AB7
M_A_A10 M_B_A10
SA_MA[10] V4 SB_MA[ 10] R1
M_A_A11 M_B_A11
SA_MA[11] W4 SB_MA[ 11] T1
M_A_A12 M_B_A12
AE8 SA_MA[12] AF8 M_A_A13 AA10 SB_MA[ 12] AB10 M_B_A13
9 M_A_CAS# SA_CAS# SA_MA[13] 10 M_B_CAS# SB_CAS# SB_MA[ 13]
AD9 V5 M_A_A14 AB8 R5 M_B_A14
9 M_A_RAS# SA_RAS# SA_MA[14] 10 M_B_RAS# SB_RAS# SB_MA[ 14]
AF9 V7 M_A_A15 AB9 R4 M_B_A15
9 M_A_WE# SA_WE# SA_MA[15] 10 M_B_WE# SB_WE# SB_MA[ 15]

PZ9
8827-364B- 01
F PZ98827-364B-01F

Sandy Bridge Processor 3/7 B - 5

http://hobi-elektronika.net
 Schematic Diagrams

Sandy Bridge Processor 4/7

Sandy Bridge Processor 4/7 ( POWER )
U49F POWER
PRO CESSOR CORE POWER PRO CESSO R UNCO RE PO WER
VCORE
4 8A 1.05VS_VTT 8 .5A 1.05VS_VT
T
AG35
ICCMAX Maximum Processor SV 48 AG34 VCC1 AH13
AG33 VCC2 VCCIO1 AH10
AG32 VCC3 VCCIO2 AG10 C223 C222 C236 C230 C237 +C668
VCORE AG31 VCC4 VCCIO3 AC10
AG30 VCC5 VCCIO4 Y10 22u_6.3V_X5R_0
8 22u_6.3V_X5R_08 22u_6.3V_X5R_0
8 22u_6.3V_X5R_08 22u_6.3V_X5R_0
8 220u_6.3V_6.3*6. 3
*4.2
AG29 VCC6 VCCIO5 U10
AG28 VCC7 VCCIO6 P10
C61
5 C616 C165 C617 C618
AG27 VCC8 VCCIO7 L10

22u_6.3V_X5R_08
08

V_X5R_08

R_08

22u_6.3V_X5R_08
AG26 VCC9 VCCIO8 J14

. 3V_X5R_
AF35 VCC10 VCCIO9 J13 C231 C654 C650 C247 C652 +C639
VCC11 VCCIO10

22u_6.3V_X5
AF34 J12
AF33 VCC12 VCCIO11 J11 22u_6.3V_X5R_0
8 22u_6.3V_X5R_08 22u_6.3V_X5R_0
8 22u_6.3V_X5R_08 22u_6.3V_X5R_0
8 220u_6.3V_6.3*6. 3
*4.2
VCC13 VCCIO12

.3
AF32 H14

22u_6

*22u_6
AF31 VCC14 VCCIO13 H12
AF30 VCC15 VCCIO14 H11
AF29 VCC16 VCCIO15 G14
AF28 VCC17 VCCIO16 G13 C659 C647 C646 C645 C644
AF27 VCC18 VCCIO17 G12

PEG AND DD R
B.Schematic Diagrams

AF26 VCC19 VCCIO18 F14 22u_6.3V_X5R_0

8 22u_6.3V_X5R_08 22u_6.3V_X5R_0
8 22u_6.3V_X5R_08 22u_6.3V_X5R_0
8
AD35 VCC20 VCCIO19 F13
AD34 VCC21 VCCIO20 F12
C16
6 C619 C125 C161 C613
AD33 VCC22 VCCIO21 F11

22u_6.3V_X5R_08
2u_6.3V_X5R_08

V_X5R_08

2u_6.3V_X5R_08

X5R_08
AD32 VCC23 VCCIO22 E14
AD31 VCC24 VCCIO23 E12 C643 C642 C641 C640 C629
AD30 VCC25 VCCIO24
VCC26

22u_6.3V_
AD29 E11 *22u_6.3V_X5R_08 *22u_6.3V_X5R_08 *22u_6.3V_X5R_08 *22u_6.3V_X5R_08 *22u_6. 3V_X5R_08
VCC27 VCCIO25

.3
AD28 D14

Sheet 5 of 49

*22u_6
AD27 VCC28 VCCIO26 D13
AD26 VCC29 VCCIO27 D12

*2

2
AC35 VCC30 VCCIO28 D11
AC34 VCC31 VCCIO29 C14 C216 C194 C195 C226 C225

Sandy Bridge AC33 VCC32 VCCIO30 C13

AC32 VCC33 VCCIO31 C12 *22u_6.3V_X5R_08 *22u_6.3V_X5R_08 *22u_6.3V_X5R_08 *22u_6.3V_X5R_08 *22u_6. 3V_X5R_08
AC31 VCC34 VCCIO32 C11
C62
0 C627 C169 C162 C628 AC30 VCC35 VCCIO33 B14

Processor 4/7 V_X5R_08

AC29 VCC36 VCCIO34 B12
22u_6.3V_X5R_08

VCC37 VCCIO35
08

22u_6.3V_X5R_08
AC28 A14

*22u_6.3V_X5R_0
. 3V_X5R_

AC27 VCC38 VCCIO36 A13 C224 C227 C228 C229

AC26 VCC39 VCCIO37 A12
AA35 VCC40 VCCIO38 A11 *22u_6.3V_X5R_08 *22u_6.3V_X5R_08 *22u_6.3V_X5R_08 *22u_6.3V_X5R_08
VCC41 VCCIO39
*22u_6. 3

AA34
VCC42
22u_6

AA33 J23 1. 05VS_VCCP_F R129 *15

mil_short_06
VCC43 VCCIO40 1.05VS_VTT
AA32
AA31 VCC44
AA30 VCC45
AA29 VCC46
AA28 VCC47
AA27 VCC48
AA26 VCC49
Y35 VCC50
CAD Note: H_CPU_SVIDALRT# _R,H_CPU_SVIDDAT_R

CO RE SUP PLY
Y34 VCC51
Y33 VCC52 Place the PU resistors cl ose to CPU
VCORE Y32 VCC53
Y31 VCC54 SVID Signals
Y30 VCC55
C19
0 C191 C170 C172 C173 Y29 VCC56 1.05VS_VT
T
Y28 VCC57
0u_6.3V_X5R_06

*10u_6.3V_X5R_06

10u_6.3V_X5R_06

VCC58
R_06

_6.3V_X5R_06

Y27
Y26 VCC59 H_CPU_SVIDALRT# R118 75_04
V35 VCC60
10u_6.3V_X5

H_CPU_SVIDCLK R117 *54.9_1%_04

V34 VCC61 AJ29 H_CPU_SVIDALRT#_R R116 43.2_1%_04 H_CPU_SVIDDAT_R R122 130_1%_04

SV ID
V33 VCC62 VIDALERT# AJ30 H_CPU_SVIDCLK_R H_CPU_SVIDALRT
# 39
R114 0_04 H_CPU_SVIDCLK 39
V32 VCC63 VIDSCLK AJ28 H_CPU_SVIDDAT_R R120 0_04 H_CPU_SVIDDAT 39
VCC64 VIDSOUT
10u

V31
*1

V30 VCC65
V29 VCC66
V28 VCC67 CAD Note: H_CPU_SVIDCLK_R
V27 VCC68 Place the PU
V26 VCC69 VCORE
C17
4 C192 C193 C171 C175 U35 VCC70 resistors close to VR
U34 VCC71
X5R_06

V_X5R_06

VCC72
06

10u_6.3V_X5R_06

10u_6.3V_X5R_06

U33
. 3V_X5R_

U32 VCC73
R87
U31 VCC74
100_04
*10u_6.3V_

U30 VCC75
*10u_6. 3

U29 VCC76
VCC77
10u_6

U28
U27 VCC78
VCC79 VCORE_VCC_SENSE 39
U26
VCC80 VCORE_VSS_SENSE 39
R35
R34 VCC81 R94
R33 VCC82
VCC83 100_04
R32
R31 VCC84 1.05VS_VTT
R30 VCC85
R29 VCC86
R28 VCC87
SE NSE LIN ES

R27 VCC88 AJ35 R523

R26 VCC89 VCC_SENSE AJ34 1
0_04
P35 VCC90 VSS_SENSE
P34 VCC91
P33 VCC92
P32 VCC93 B10
VCC94 VCCIO_SENSE VCCP_SENSE 38
P31 A10
VCC95 VSSIO_SENSE VSSP_SENSE 38
P30
P29 VCC96
P28 VCC97
P27 VCC98
P26 VCC99
R526
VCC100 10_04

40 VCORE
2,3,23, 24
,25,35,39 1
.05VS_VTT
PZ98827-364B-01F

B - 6 Sandy Bridge Processor 4/7

http://hobi-elektronika.net
 Schematic Diagrams

Sandy Bridge Processor 5/7

Sandy Bridge Processor 5/7 ( GRAPHICS POWER )

1 .5 V

U 4 9G
POWER R 2 63
V G F X _ CO RE
33A Q1 8 1 K _ 1 % _0 4
AT2 4 A K 35 *A O 3 40 2 L

SENSE
LINES
AT2 3 VAXG 1 V A X G_ S E N S E A K 34 V C C _ G T_ S E N S E 3 9 S D
V _ S M_ V R E F V _ S M _V R E F _ C N T
AT2 1 VAXG 2 V S S A X G_ S E N S E V S S _G T _S E N S E 39
C 1 98 C 19 9 C2 2 1 C1 8 3 C1 6 8
AT2 0 VAXG 3 R 2 66
AT1 8 VAXG 4 10/22
2 2 u _ 6. 3 V _ X 5 R _ 0 8 2 2 u_ 6 . 3 V _ X 5R _ 08 2 2u _ 6 . 3 V _ X5 R _0 8 22 u _ 6 . 3V _X 5 R _ 0 8 2 2u _ 6 . 3 V _X 5 R _0 8 R 2 65 C3 5 5
VAXG 5

G
AT1 7 * 1 00 K _ 1 % _0 4
A R2 4 VAXG 6

0 . 1u _ 1 0 V _ X 5R _ 0 4
1 K _ 1 % _0 4
A R2 3 VAXG 7
A R2 1 VAXG 8 S US B # 2 0, 2 9 , 3 4 , 3 5
A R2 0 VAXG 9
C 6 56 C 21 1 C6 5 5 C1 8 5 C1 8 4 A R1 8 VAXG 10

VREF
A R1 7 VAXG 11
2 2 u _ 6. 3 V _ X 5 R _ 0 8 2 2 u_ 6 . 3 V _ X 5R _ 08 2 2u _ 6 . 3 V _ X5 R _0 8 22 u _ 6 . 3V _X 5 R _ 0 8 2 2u _ 6 . 3 V _X 5 R _0 8 AP2 4 VAXG 12 AL 1 V_ SM_ VR EF 0_04 R5 3 0 V _ SM _ V RE F _ C NT
AP2 3 VAXG 13 S M_ V R E F
AP2 1 VAXG 14

B.Schematic Diagrams
AP2 0 VAXG 15
AP1 8 VAXG 16
AP1 7 VAXG 17 CAD Note: +V_SM_VREF should
C 22 0 C2 1 2 C6 3 2 C6 2 4 A N2 4 VAXG 18 have 10 mil trace width
A N2 3 VAXG 19
2 2 u_ 6 . 3 V _ X 5R _ 08 2 2u _ 6 . 3 V _ X5 R _0 8 22 u _ 6 . 3V _X 5 R _ 0 8 2 2u _ 6 . 3 V _X 5 R _0 8 A N2 1 VAXG 20
A N2 0 VAXG 21 1. 5 V S _C P U
A N1 8 VAXG 22
12A

DDR3 -1.5V RAILS

A N1 7 VAXG 23
A M2 4 VAXG 24 AF 7

GRAPHICS
A M2 3 VAXG 25 V D D Q1 AF 4
A M2 1 VAXG 26 V D D Q2 AF 1
C1 8 9 C 6 78 C 679 C6 7 7 +C 6 83
+

22 0 u _ 6. 3 V _ 6 . 3 *6 . 3 *4 . 2
A M2 0
A M1 8
A M1 7
VAXG
VAXG
VAXG
VAXG
27
28
29
30
V D D Q3
V D D Q4
V D D Q5
V D D Q6
AC 7
AC 4
AC 1
1 0 u _6 . 3 V _ X 5 R _ 0 6 1 0 u _ 6. 3 V _ X 5 R _ 0 6 10 u _ 6 . 3V _X 5 R _ 0 6 5 6 0 u _2 . 5 V _ 6 . 6 *6 . 6 *5 . 9 Sheet 6 of 49
AL 2 4 Y 7
AL 2 3
AL 2 1
AL 2 0
VAXG
VAXG
VAXG
31
32
33
V D D Q7
V D D Q8
V D D Q9
Y 4
Y 1
U 7 C 6 80 C 681 C6 8 2
Sandy Bridge
AL 1 8 VAXG 34 V D D Q1 0 U 4
AL 1 7
AK2 4
AK2 3
VAXG
VAXG
VAXG
35
36
37
V D D Q1 1
V D D Q1 2
V D D Q1 3
U 1
P7
P4
1 0 u _6 . 3 V _ X 5 R _ 0 6 1 0 u _ 6. 3 V _ X 5 R _ 0 6 10 u _ 6 . 3V _X 5 R _ 0 6
Processor 5/7
AK2 1 VAXG 38 V D D Q1 4 P1
AK2 0 VAXG 39 V D D Q1 5
AK1 8 VAXG 40
AK1 7 VAXG 41
AJ 2 4 VAXG 42
AJ 2 3 VAXG 43
AJ 2 1 VAXG 44
AJ 2 0 VAXG 45
AJ 1 8 VAXG 46
AJ 1 7 VAXG 47
A H2 4 VAXG 48 0 . 85 V S
A H2 3 VAXG 49 6A

SA RAIL
A H2 1 VAXG 50 M 27
A H2 0 VAXG 51 V CC SA1 M 26
A H1 8 VAXG 52 V CC SA2 L26
A H1 7 VAXG 53 V CC SA3 J26 C 163 C1 6 4 C1 5 1 C 126
VAXG 54 V CC SA4 J25 +
V CC SA5 J24 1 0 u _ 6. 3 V _ X 5 R _ 0 8 10 u _ 6 . 3V _X 5 R _ 0 8 1 0u _ 6 . 3 V _X 5 R _0 6 * 3 30 U _ 2. 5 V _ D 2_ D
V CC SA6 H 26
V CC SA7 H 25
V CC SA8
1.8V RAIL

1 .0 5 V S
1 .8 V S 1.2A
B6 H 23 V CC S A _ S E N S E
V C CP L L 1 V CC SA _ S E N S E V C CS A _ S E NS E 37
A6 R 12 6 1 .5 V
MISC

+C 6 69 C 2 51 C 67 0 C 66 3 A2 V C CP L L 2
V C CP L L 3
R5 0 9 1 0 K _ 04 1 0 K _ 04
5 6 0 u _2 . 5 V _ 6 . 6 *6 . 6 *5 . 9 1 0 u _6 . 3 V _ X 5 R _ 0 6 1 u _6 . 3 V _ Y 5 V _ 0 4 1 u _ 6. 3 V _ X 5 R _ 0 4 C 2 2 R6 4 8 *0 _ 0 4
F C_ C2 2 C 24 V C CS A_ V ID 0 3 7
V C CS A _ V ID1 V CC S A _ V ID1 3 7

C3 0 8 C3 1 0
P Z 98 8 2 7 -36 4 B -0 1 F R 12 3

0 . 1 u_ 1 0 V _ X 5 R _ 0 4

0 . 1u _ 1 0 V _ X 5R _ 0 4
*1 0 K _ 0 4

1 .5 V S _ CP U

18 , 1 9 , 2 0, 24 , 2 5 , 2 9, 3 5 , 3 7 , 3 8, 3 9 1 . 0 5 V S
24 , 3 5 1 .5 V S
37 0 . 8 5V S
4 0 V GF X _ C O R E
3, 3 5 , 3 8 1 . 5V S _C P U
23 , 2 4 , 3 7 1. 8V S
3 , 8 , 9 , 1 0, 25 , 2 9 , 3 5, 3 7 , 3 8 1 . 5V
3, 9 , 1 0 , 1 1, 12 , 1 8 , 1 9, 2 0 , 2 1 , 2 2, 2 3 , 2 4 , 2 5, 2 7 , 2 8 , 29 , 3 0 , 3 1 , 32 , 3 3 , 3 4, 35 , 3 9 3 . 3 V S

Sandy Bridge Processor 5/7 B - 7

http://hobi-elektronika.net
 Schematic Diagrams

Sandy Bridge Processor 6/7

Sandy Bridge Processor 6/7 ( GND )

U4 9H U49I
AT35 AJ22
AT32 VSS1 VSS81 AJ19
AT29 VSS2 VSS82 AJ16 T35 F22
AT27 VSS3 VSS83 AJ13 T34 VSS161 VSS234 F19
AT25 VSS4 VSS84 AJ10 T33 VSS162 VSS235 E30
AT22 VSS5 VSS85 AJ7 T32 VSS163 VSS236 E27
AT19 VSS6 VSS86 AJ4 T31 VSS164 VSS237 E24
AT16 VSS7 VSS87 AJ3 T30 VSS165 VSS238 E21
AT13 VSS8 VSS88 AJ2 T29 VSS166 VSS239 E18
CAD Note: 0 ohm resistor AT10 VSS9 VSS89 AJ1 T28 VSS167 VSS240 E15
should be placed close AT7 VSS1 0 VSS90 AH35 T27 VSS168 VSS241 E13
AT4 VSS1 1 VSS91 AH34 T26 VSS169 VSS242 E10
B.Schematic Diagrams

to CPU AT3 VSS1 2 VSS92 AH32 P9 VSS170 VSS243 E9

AR25 VSS1 3 VSS93 AH30 P8 VSS171 VSS244 E8
AR22 VSS1 4 VSS94 AH29 P6 VSS172 VSS245 E7
AR19 VSS1 5 VSS95 AH28 P5 VSS173 VSS246 E6
AR16 VSS1 6 VSS96 AH26 P3 VSS174 VSS247 E5
AR13 VSS1 7 VSS97 AH25 P2 VSS175 VSS248 E4
AR10 VSS1 8 VSS98 AH22 N 35 VSS176 VSS249 E3
AR7 VSS1 9 VSS99 AH19 N 34 VSS177 VSS250 E2
AR4 VSS2 0 VSS100 AH16 N 33 VSS178 VSS251 E1
AR2 VSS2 1 VSS101 AH7 N 32 VSS179 VSS252 D3 5
VSS2 2 VSS102 VSS180 VSS253
Sheet 7 of 49 AP34
AP31
AP28
VSS2 3
VSS2 4
VSS103
VSS104
AH4
AG9
AG8
N 31
N 30
N 29
VSS181
VSS182
VSS254
VSS255
D3 2
D2 9
D2 6
AP25 VSS2 5 VSS105 AG4 N 28 VSS183 VSS256 D2 0
Sandy Bridge AP22
AP19
VSS2 6
VSS2 7
VSS2 8
VSS106
VSS107
VSS108
AF6
AF5
N 27
N 26
VSS184
VSS185
VSS186
VSS257
VSS258
VSS259
D1 7
C3 4
AP16 AF3 M34 C3 1
Processor 6/7 AP13
AP10
AP7
VSS2 9
VSS3 0
VSS3 1
VSS109
VSS110
VSS111
AF2
AE35
AE34
L 33
L 30
L 27
VSS187
VSS188
VSS189
VSS260
VSS261
VSS262
C2 8
C2 7
C2 5
AP4 VSS3 2 VSS112 AE33 L9 VSS190 VSS263 C2 3
AP1 VSS3 3 VSS113 AE32 L8 VSS191 VSS264 C1 0
AN30 VSS3 4 VSS114 AE31 L6 VSS192 VSS265 C1
AN27 VSS3 5 VSS115 AE30 L5 VSS193 VSS266 B22
AN25 VSS3 6 VSS116 AE29 L4 VSS194 VSS267 B19
AN22
AN19
AN16
VSS3 7
VSS3 8
VSS3 9
VSS VSS117
VSS118
VSS119
AE28
AE27
AE26
L3
L2
L1
VSS195
VSS196
VSS197
VSS VSS268
VSS269
VSS270
B17
B15
B13
AN13 VSS4 0 VSS120 AE9 K35 VSS198 VSS271 B11
AN10 VSS4 1 VSS121 AD7 K32 VSS199 VSS272 B9
AN7 VSS4 2 VSS122 AC9 K29 VSS200 VSS273 B8
AN4 VSS4 3 VSS123 AC8 K26 VSS201 VSS274 B7
AM29 VSS4 4 VSS124 AC6 J 34 VSS202 VSS275 B5
AM25 VSS4 5 VSS125 AC5 J 31 VSS203 VSS276 B3
AM22 VSS4 6 VSS126 AC3 H 33 VSS204 VSS277 B2
AM19 VSS4 7 VSS127 AC2 H 30 VSS205 VSS278 A35
AM16 VSS4 8 VSS128 AB35 H 27 VSS206 VSS279 A32
AM13 VSS4 9 VSS129 AB34 H 24 VSS207 VSS280 A29
AM10 VSS5 0 VSS130 AB33 H 21 VSS208 VSS281 A26
AM7 VSS5 1 VSS131 AB32 H 18 VSS209 VSS282 A23
AM4 VSS5 2 VSS132 AB31 H 15 VSS210 VSS283 A20
AM3 VSS5 3 VSS133 AB30 H 13 VSS211 VSS284 A3
AM2 VSS5 4 VSS134 AB29 H 10 VSS212 VSS285
AM1 VSS5 5 VSS135 AB28 H9 VSS213
AL34 VSS5 6 VSS136 AB27 H8 VSS214
AL31 VSS5 7 VSS137 AB26 H7 VSS215
AL28 VSS5 8 VSS138 Y9 H6 VSS216
AL25 VSS5 9 VSS139 Y8 H5 VSS217
AL22 VSS6 0 VSS140 Y6 H4 VSS218
AL19 VSS6 1 VSS141 Y5 H3 VSS219
AL16 VSS6 2 VSS142 Y3 H2 VSS220
AL13 VSS6 3 VSS143 Y2 H1 VSS221
AL10 VSS6 4 VSS144 W35 G 35 VSS222
AL7 VSS6 5 VSS145 W34 G 32 VSS223
AL4 VSS6 6 VSS146 W33 G 29 VSS224
AL2 VSS6 7 VSS147 W32 G 26 VSS225
AK33 VSS6 8 VSS148 W31 G 23 VSS226
AK30 VSS6 9 VSS149 W30 G 20 VSS227
AK27 VSS7 0 VSS150 W29 G 17 VSS228
AK25 VSS7 1 VSS151 W28 G 11 VSS229
AK22 VSS7 2 VSS152 W27 F34 VSS230
AK19 VSS7 3 VSS153 W26 F31 VSS231
AK16 VSS7 4 VSS154 U9 F29 VSS232
AK13 VSS7 5 VSS155 U8 VSS233
AK10 VSS7 6 VSS156 U6
AK7 VSS7 7 VSS157 U5
AK4 VSS7 8 VSS158 U3
AJ25 VSS7 9 VSS159 U2
VSS8 0 VSS160

PZ98827 -364B-0 1F PZ98 827-3 64B-01F

B - 8 Sandy Bridge Processor 6/7

http://hobi-elektronika.net
 Schematic Diagrams

Sandy Bridge Processor 7/7

Sandy Bridge Processor 7/7 ( RESERVED )

C FG S tr ap s fo r Pr oc ess or ? DIMM? ? ? & TRACE? ?
PEG Static Lane Reversal - CFG2 is for the 16x
1 .5 V

CF G2 1:(Default) Normal Operation; Lane # R6 4 2 *0 _ 0 4

definition matches socket pin map definition
U 4 9E R1 5 5
0:Lane Reversed
Q9 1K _ 1 % _0 4
L7 *A O 3 40 2 L
R S VD2 8 A G7 V R E F _ C H _A _D I MM S D M V R E F _D Q_ D I M 0
CF G 2 C F G0 AK2 8 R S VD2 9 AE7 M V R E F _D Q_ D I M MA 9
R5 0 3 * 1K _ 0 4
AK2 9 C F G[ 0 ] R S VD3 0 AK2
C F G2 A L2 6 C F G[ 1 ] R S VD3 1 W8 R 1 49 R1 5 0 C 3 57
A L2 7 C F G[ 2 ] R S VD3 2

G
*1 K _0 4
C F G4 AK2 6 C F G[ 3 ]
1K _ 1 % _0 4 0 . 1 u _1 0 V _ X 5R _0 4
C F G5 A L2 9 C F G[ 4 ] A T 26
C F G6 A L3 0 C F G[ 5 ] R S VD3 3 A M3 3
C F G7 A M3 1 C F G[ 6 ] R S VD3 4 A J 27

B.Schematic Diagrams
A M3 2 C F G[ 7 ] R S VD3 5
Display Port Presence Strap A M3 0 C F G[ 8 ]
C F G[ 9 ] D R A M R S T _ C N TR L 3, 1 9
A M2 8
1:(Default) Disabled; No Physical Display Port A M2 6 C F G[ 1 0 ]
CF G4 attached to Embedded Display Port A N2 8
A N3 1
C
C
F G[ 1 1 ]
F G[ 1 2 ] T8
1. 5 V

0:Enabled; An external Display Port device is A N2 6 C F G[ 1 3 ] R S VD3 7 J 16 R6 4 3 *0 _ 0 4

connected to the Embedded Display Port A M2 7 C F G[ 1 4 ] R S VD3 8 H1 6
AK3 1
A N2 9
C
C
C
F G[ 1 5 ]
F G[ 1 6 ]
F G[ 1 7 ]
R S VD3 9
R S VD4 0
G1 6

Q1 0
R 15 9 Sheet 8 of 49
*A O 3 40 2 L 1 K _ 1% _ 0 4
CF G 4 R4 9 3 * 1K _ 0 4

H_ C P U_ RS V D 1 A J3 1
V A X G_ V A L _ S E N S E
R
R
S VD4 1
S VD4 2
A R3 5
A T 34
V R E F _ C H _B _D I MM S D M V R E F _ D Q _ D I M1
M V R E F _D Q_ D I M MB 1 0
Sandy Bridge
H_ C P U_ RS V D 2 A H3 1 A T 33 R 1 53 R 16 0 C3 6 7
V S S A X G _V A L_ S E N S E R S VD4 3
Processor 7/7

G
H_ C P U_ RS V D 3 A J3 3 AP3 5 *1 K _0 4
H_ C P U_ RS V D 4 A H3 3 V C C _ V A L _S E N S E R S VD4 4 A R3 4 1 K _ 1% _ 0 4 0 . 1 u_ 1 0V _X 5 R _ 0 4
V SS _ VA L _ S ENSE R S VD4 5

A J2 6
R S V D5

RESERVED
B3 4
R S VD4 6 D R A MR S T_ C N T R L 3 , 1 9
V R E F _C H _ A _ D I M M B4 A3 3
V R E F _C H _ B _ D I M M D1 R S V D6 R S VD4 7 A3 4
R S V D7 R S VD4 8 B3 5
R S VD4 9 C3 5
R S VD5 0
PCIE Port Bifurcation Straps F25
F24 R S V D8
F23 R S V D9
11: (Default) x16 - Device 1 functions 1 and 2 disabled D2 4 R S V D1 0 A J 32
10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled G2 5 R S V D1 1 R S VD5 1 AK3 2
G2 4 R S V D1 2 R S VD5 2
C FG [ 6: 5] 01: Reserved - (Device 1 function 1 disabled ; function 2 enabled) E2 3
D2 3
R
R
S V D1 3
S V D1 4
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled R S V D1 5
C3 0 A H2 7
A3 1 R S V D1 6 V CC _ DIE _ S E NS E
B3 0 R S V D1 7
C F G5 R 49 2 *1 K _ 04 B2 9 R S V D1 8
D3 0 R S V D1 9 A N3 5
B3 1 R S V D2 0 R S VD5 4 A M3 5
C F G6 R 50 0 *1 K _ 04 A3 0 R S V D2 1 R S VD5 5
C2 9 R S V D2 2
R S V D2 3

R5 1 4 10 K _ 1 %_ 0 4 J2 0
3. 3 V B1 8 R S V D2 4 AT2
H _ S N B _I V B #_ P W R C T R L R5 1 6 *1 0 mi l _ sh o rt H _ S N B _ I V B # _ P W R C TR L _R A1 9 R S V D2 5 R S VD5 6 AT1
V C C I O _S E L R S VD5 7 A R1
R S VD5 8
J1 5
R S V D2 7
On CRB
H_SNB_IVB#_PWRCTRL = low, 1.0V KEY
B1
H_SNB_IVB#_PWRCTRL = high/NC, 1.05V

PEG DEFER TRAINING P Z 98 8 2 7-3 6 4 B -01 F

1: (Default) PEG Train immediately following xxRESETB de assertion

CF G 7 0: PEG Wait for BIOS for training

CF G 7 R4 9 1 * 1K _ 0 4

3, 6 , 9 , 1 0, 25 , 2 9 , 35 , 3 7 , 38 1 . 5 V
2, 3 , 1 1 , 12 , 1 6 , 1 8, 1 9 , 2 0, 2 2 , 2 3, 2 4 , 2 5, 2 7 , 2 8, 2 9 , 3 0, 33 , 3 5 , 37 , 3 8 , 39 3 . 3 V

Sandy Bridge Processor 7/7 B - 9

http://hobi-elektronika.net
 Schematic Diagrams

DDR3 SO-DIMM_0

SO-DIMM A
CHANGE TO STANDARD
C 35 4 *1 0 p_ 5 0 V _N P O_ 0 4
M_ A _ C L K _ D D R 0 M _ A _C L K _D D R # 0
JD I MM 1A
4 M_ A _ A [ 1 5 : 0 ] M _A _A 0 98 5 M _A _D Q0 M_ A _ D Q [ 63 : 0 ] 4
C 34 8 *1 0 p_ 5 0 V _N P O_ 0 4 J D I MM 1B
M_ A _ C L K _ D D R 1 M _ A _C L K _D D R # 1 M _A _A 1 97 A0 DQ 0 7 M _A _D Q1
M _A _A 2 96 A1 DQ 1 15 M _A _D Q2
M _A _A 3 95 A2 DQ 2 17 M _A _D Q3 1 .5 V
M _A _A 4 92 A3 DQ 3 4 M _A _D Q4
M _A _A 5 91 A4 DQ 4 6 M _A _D Q5 75 44
M _A _A 6 90 A5 DQ 5 16 M _A _D Q6 76 VD D1 VS S 16 48
M _A _A 7 86 A6 DQ 6 18 M _A _D Q7 81 VD D2 VS S 17 49
M _A _A 8 89 A7 DQ 7 21 M _A _D Q8 82 VD D3 VS S 18 54
La yout Note : M _A _A 9 85 A8 DQ 8 23 M _A _D Q9 87 VD D4 VS S 19 55
M _A _A 1 0 1 07 A9 DQ 9 33 M _A _D Q1 0 88 VD D5 VS S 20 60
si gna l/ spa ce /si gna l: M _A _A 1 1 84 A 1 0 /AP DQ 1 0 35 M _A _D Q1 1 93 VD D6 VS S 21 61
M _A _A 1 2 83 A1 1 DQ 1 1 22 M _A _D Q1 2 94 VD D7 VS S 22 65
8 / 4 /8 M _A _A 1 3 1 19 A 1 2 /BC # DQ 1 2 24 M _A _D Q1 3 3 .3 V S 99 VD D8 VS S 23 66
B.Schematic Diagrams

M _A _A 1 4 80 A1 3 DQ 1 3 34 M _A _D Q1 4 1 00 VD D9 VS S 24 71
M _A _A 1 5 78 A1 4 DQ 1 4 36 M _A _D Q1 5 2 0 mi ls 1 05 VD D1 0 VS S 25 72
A1 5 DQ 1 5 39 M _A _D Q1 6 1 06 VD D1 1 VS S 26 127
1 09 DQ 1 6 41 M _A _D Q1 7 C 3 59 C3 6 0 1 11 VD D1 2 VS S 27 128
4 M _ A _B S 0 1 08 BA 0 DQ 1 7 51 M _A _D Q1 8 1 12 VD D1 3 VS S 28 133
4 M _ A _B S 1 79 BA 1 DQ 1 8 53 1 17 VD D1 4 VS S 29 134
M _A _D Q1 9 1 u _ 6. 3V _ X 5 R _ 0 4 0 . 1 u_ 1 6 V _Y 5 V _0 4
4 M _ A _B S 2 1 14 BA 2 DQ 1 9 40 M _A _D Q2 0 1 18 VD D1 5 VS S 30 138
4 M _ A _C S # 0 1 21 S0 # DQ 2 0 42 1 23 VD D1 6 VS S 31 139
M _A _D Q2 1
4 M _ A _C S # 1 1 01 S1 # DQ 2 1 50 M _A _D Q2 2 1 24 VD D1 7 VS S 32 144

Sheet 9 of 49 4
4
4
4
M
M
M
M
_ A _C L K _D D R 0
_ A _C L K _D D R # 0
_ A _C L K _D D R 1
_ A _C L K _D D R # 1
1 03
1 02
1 04
C K0
C K0 #
C K1
C K1 #
DQ 2 2
DQ 2 3
DQ 2 4
DQ 2 5
52
57
59
M
M
M
_A
_A
_A
_D
_D
_D
Q2 3
Q2 4
Q2 5
1 99
VD D1 8

V D DS P D
VS
VS
VS
VS
S 33
S 34
S 35
S 36
145
150
151
73 67 M _A _D Q2 6 3 .3 V S 77 155

DDR3 SO-DIMM_0 4
4
4
M _ A _C K E 0
M _ A _C K E 1
M_ A _ C A S #
74
1 15
1 10
C KE0
C KE1
C AS#
DQ 2 6
DQ 2 7
DQ 2 8
69
56
58
M
M
M
_A
_A
_A
_D
_D
_D
Q2 7
Q2 8
Q2 9
R 2 51 1 0K _0 4
1 22
1 25
N C1
N C2
N CT E S T
VS
VS
VS
S 37
S 38
S 39
156
161
162
4 M_ A _ R A S # 1 13 R AS# DQ 2 9 68 M _A _D Q3 0 1 98 VS S 40 167
4 M_ A _ W E # SA 0 _ DIM 0 1 97 WE # DQ 3 0 70 M _A _D Q3 1 10 T S # _ D I MM 0 _1 30 EVEN T # VS S 41 168
SA 1 _ DIM 0 2 01 SA 0 DQ 3 1 12 9 M _A _D Q3 2 3 , 10 D D R 3_ D R A MR S T # R ESET # VS S 42 172
2 02 SA 1 DQ 3 2 13 1 M _A _D Q3 3 C 3 75 1 u_ 6 . 3 V _ X5 R _0 4 VS S 43 173
1 0, 1 9 S M B _C L K 2 00 SC L DQ 3 3 14 1 M _A _D Q3 4 M V R E F _ D Q_ D I M MA 1 VS S 44 178
C 3 74 0 . 1 u_ 1 6 V _Y 5 V _0 4
1 0, 1 9 S M B _D A T A SD A DQ 3 4 14 3 M _A _D Q3 5 1 26 V R E F _ DQ VS S 45 179
1 16 DQ 3 5 13 0 M _A _D Q3 6 V R E F _ CA VS S 46 184
4 M _ A _O D T 0 1 20 O DT 0 DQ 3 6 13 2 M _A _D Q3 7 8 M V R E F _ D Q_ D I M MA VS S 47 185
4 M _ A _O D T 1 O DT 1 DQ 3 7 14 0 M _A _D Q3 8 2 VS S 48 189
11 DQ 3 8 14 2 M _A _D Q3 9 M V R E F _ D I M0 3 VSS1 VS S 49 190
28 D M0 DQ 3 9 14 7 M _A _D Q4 0 8 VSS2 VS S 50 195
C 3 28 1 u_ 6 . 3 V _ X5 R _0 4
46 D M1 DQ 4 0 14 9 M _A _D Q4 1 C 3 25 0 . 1 u_ 1 6 V _Y 5 V _0 4 9 VSS3 VS S 51 196
63 D M2 DQ 4 1 15 7 M _A _D Q4 2 13 VSS4 VS S 52
1 36 D M3 DQ 4 2 15 9 M _A _D Q4 3 14 VSS5
1 53 D M4 DQ 4 3 14 6 M _A _D Q4 4 19 VSS6
1 70 D M5 DQ 4 4 14 8 M _A _D Q4 5 20 VSS7 V T T_ M E M
1 87 D M6 DQ 4 5 15 8 M _A _D Q4 6 25 VSS8
D M7 DQ 4 6 16 0 M _A _D Q4 7 CLOS E TO S O- DIM M _0 26 VSS9 203
4 M _A _D QS [ 7 : 0 ] 12 DQ 4 7 16 3 31 VSS1 0 V T T1 204
M _A _D QS 0 M _A _D Q4 8
M _A _D QS 1 29 D QS 0 DQ 4 8 16 5 M _A _D Q4 9 32 VSS1 1 V T T2
47 D QS 1 DQ 4 9 17 5 37 VSS1 2 G ND 1
M _A _D QS 2 M _A _D Q5 0
M _A _D QS 3 64 D QS 2 DQ 5 0 17 7 M _A _D Q5 1 R2 2 9 1 K _ 1 % _0 4 MV R E F _ D I M 0 38 VSS1 3 G1 G ND 2
1 37 D QS 3 DQ 5 1 16 4 1 . 5V 43 VSS1 4 G2
M _A _D QS 4 M _A _D Q5 2
M _A _D QS 5 1 54 D QS 4 DQ 5 2 16 6 M _A _D Q5 3 VSS1 5
1 71 D QS 5 DQ 5 3 17 4
M _A _D QS 6 M _A _D Q5 4 R 2 39 C 3 16 7 8 1 21 -0 0 11
3 .3 V S M _A _D QS 7 1 88 D QS 6 DQ 5 4 17 6 M _A _D Q5 5
D QS 7 DQ 5 5 18 1 M _A _D Q5 6 1 K _ 1 % _0 4 0 . 1 u _ 10 V _ X 5R _ 04
4 M _ A _ D QS #[ 7 : 0 ] M _A _D QS # 0 10 DQ 5 6 18 3 M _A _D Q5 7
RN 3 M _A _D QS # 1 27 D QS 0 # DQ 5 7 19 1 M _A _D Q5 8
10 K _ 8 P 4 R _ 0 4 M _A _D QS # 2 45 D QS 1 # DQ 5 8 19 3 M _A _D Q5 9
1 8 S A 1 _ D I M1 M _A _D QS # 3 62 D QS 2 # DQ 5 9 18 0 M _A _D Q6 0
2 7 S A 0 _ D I M1 S A 1 _ DIM 1 1 0 M _A _D QS # 4 1 35 D QS 3 # DQ 6 0 18 2 M _A _D Q6 1
3 6 S A 1 _ D I M0 S A 0 _ DIM 1 1 0 1 52 D QS 4 # DQ 6 1 19 2
M _A _D QS # 5 M _A _D Q6 2
4 5 S A 0 _ D I M0 M _A _D QS # 6 1 69 D QS 5 # DQ 6 2 19 4 M _A _D Q6 3
M _A _D QS # 7 1 86 D QS 6 # DQ 6 3
D QS 7 #
78 1 2 1-0 0 1 1

V T T _M E M

C3 3 4 C 37 6 C3 6 6 C 34 1 C3 4 0

10 u _ 10 V _ Y 5 V _ 0 8 1 u _6 . 3 V _ X 5R _0 4 1u _ 6 . 3V _X 5 R _ 0 4 1 u _6 . 3 V _ X5 R _0 4 1u _ 6 . 3V _ X 5 R _ 0 4

1. 5 V

C3 6 4 C 37 0 C3 3 3 C 33 7 C3 3 8 C 33 0 C3 7 1 C3 3 6 C 3 32 C3 3 9

0. 1 u _ 16 V _ Y 5 V _ 0 4 0 . 1 u_ 1 6 V _ Y 5 V _ 04 0. 1 u _ 16 V _ Y 5 V _ 0 4 0 . 1 u_ 1 6 V _Y 5 V _ 04 0. 1 u _ 16 V _ Y 5 V _ 0 4 0 . 1 u_ 1 6 V _Y 5 V _ 04 0. 1 u _ 16 V _ Y 5 V _ 0 4 0 . 1 u_ 1 6 V _Y 5 V _0 4 0. 1 u _ 16 V _ Y 5 V _ 0 4 0 . 1 u_ 1 6 V _Y 5 V _0 4
2 4, 3 5 1 .5 V S
1 0, 3 8 V T T _M E M
1 . 5V 3 , 6 , 8 , 1 0, 2 5 , 2 9, 3 5 , 3 7, 38 1 .5 V
3 , 10 , 1 1 , 12 , 1 8 , 1 9, 2 0 , 2 1, 2 2 , 2 3, 2 4 , 2 5 , 27 , 2 8 , 29 , 3 0 , 3 1, 3 2 , 3 3, 3 4 , 3 5, 39 3 .3 V S

+ C3 9 4 + C3 8 2 C3 3 5 C 36 1 C3 2 4 C 36 8 C3 6 9 C3 3 1 C 3 65 C3 6 3

22 0 u _6 . 3 V _ 6 . 3* 6. 3* 4. 2 *2 2 0u _ 6 . 3V _ 6 . 3 *6 . 3 *4 . 2 10 u _ 10 V _ Y 5 V _ 0 8 1 0 u_ 1 0 V _Y 5 V _0 8 10 u _ 6. 3 V _ X 5R _ 06 1 u _6 . 3 V _ X5 R _0 4 1u _ 6 . 3V _ X 5 R _ 0 4 1 u _6 . 3 V _ X5 R _0 4 1u _ 6 . 3V _ X 5 R _ 0 4 1 u _6 . 3 V _ X5 R _0 4

B - 10 DDR3 SO-DIMM_0

http://hobi-elektronika.net
 Schematic Diagrams

DDR3 SO-DIMM_1
SO-DIMM B CHANGE TO STANDARD

J D I M M2 B
C4 0 5 *1 0 p_ 5 0 V _ N P O _ 04
M _ B _C L K _ D D R 2 M _B _ C LK _D D R # 2
J D I M M2 A 1 . 5V
C4 0 1 *1 0 p_ 5 0 V _ N P O _ 04 4 M _ B _ A [ 1 5: 0] M _B _ A 0 98 5 M_ B _ D Q 0 M_ B _ D Q[ 6 3 : 0 ] 4
97 A0 DQ 0 7 75 44
M _ B _C L K _ D D R 3 M _B _ C LK _D D R # 3 M _B _ A 1 M_ B _ D Q 1
M _B _ A 2 96 A1 DQ 1 15 M_ B _ D Q 2 76 VD D1 VSS1 6 48
M _B _ A 3 95 A2 DQ 2 17 M_ B _ D Q 3 81 VD D2 VSS1 7 49
M _B _ A 4 92 A3 DQ 3 4 M_ B _ D Q 4 82 VD D3 VSS1 8 54
M _B _ A 5 91 A4 DQ 4 6 M_ B _ D Q 5 87 VD D4 VSS1 9 55
M _B _ A 6 90 A5 DQ 5 16 M_ B _ D Q 6 88 VD D5 VSS2 0 60
M _B _ A 7 86 A6 DQ 6 18 M_ B _ D Q 7 93 VD D6 VSS2 1 61
89 A7 DQ 7 21 94 VD D7 VSS2 2 65
M _B _ A 8 M_ B _ D Q 8
La y out N ot e : M _B _ A 9 85 A8 DQ 8 23 M_ B _ D Q 9 99 VD D8 VSS2 3 66
M _B _ A 1 0 107 A9 DQ 9 33 M_ B _ D Q 10 100 VD D9 VSS2 4 71
signa l/ spac e /si gna l : M _B _ A 1 1 84 A 1 0/ A P DQ 1 0 35 M_ B _ D Q 11 105 VD D1 0 VSS2 5 72
M _B _ A 1 2 83 A1 1 DQ 1 1 22 M_ B _ D Q 12 106 VD D1 1 VSS2 6 1 27
8/ 4 / 8 M _B _ A 1 3 119 A 1 2/ B C # DQ 1 2 24 M_ B _ D Q 13 111 VD D1 2 VSS2 7 1 28
M _B _ A 1 4 80 A1 3 DQ 1 3 34 M_ B _ D Q 14 112 VD D1 3 VSS2 8 1 33
M _B _ A 1 5 78 A1 4 DQ 1 4 36 M_ B _ D Q 15 117 VD D1 4 VSS2 9 1 34
A1 5 DQ 1 5 39 M_ B _ D Q 16 118 VD D1 5 VSS3 0 1 38
109 DQ 1 6 41 M_ B _ D Q 17 123 VD D1 6 VSS3 1 1 39
4 M _B _B S 0 108 BA0 DQ 1 7 51 M_ B _ D Q 18 124 VD D1 7 VSS3 2 1 44
4 M _B _B S 1 3. 3 V S
79 BA1 DQ 1 8 53 M_ B _ D Q 19 VD D1 8 VSS3 3 1 45
20 m ils

B.Schematic Diagrams
4 M _B _B S 2 114 BA2 DQ 1 9 40 M_ B _ D Q 20 199 VSS3 4 1 50
4 M _B _C S # 2 S0 # DQ 2 0 V D DS P D VSS3 5
121 42 M_ B _ D Q 21 1 51
4 M _B _C S # 3 101 S1 # DQ 2 1 50 M_ B _ D Q 22 77 VSS3 6 1 55
C4 1 8 C4 1 0
4 M_ B _ C L K _ D D R 2 103 CK 0 DQ 2 2 52 M_ B _ D Q 23 122 NC 1 VSS3 7 1 56
4 M_ B _ C L K _ D D R # 2 102 CK 0 # DQ 2 3 57 125 NC 2 VSS3 8 1 61
M_ B _ D Q 24 1u _ 6 . 3 V _ X5 R _0 4 0 . 1u _ 1 6V _Y 5 V _ 04
4 M_ B _ C L K _ D D R 3 104 CK 1 DQ 2 4 59 M_ B _ D Q 25 NC T ES T VSS3 9 1 62
4 M_ B _ C L K _ D D R # 3 73 CK 1 # DQ 2 5 67 198 VSS4 0 1 67
M_ B _ D Q 26
4 M_ B _ C K E 2 74 CK E 0 DQ 2 6 69 M_ B _ D Q 27 9 T S # _ D I M M0 _ 1 30 EVEN T # VSS4 1 1 68
4 M_ B _ C K E 3
4
4
4
M _ B _ CA S #
M _ B _ RA S #
M _ B_ W E#
115
110
113
CK E 1
CA S #
RA S #
W E#
DQ 2 7
DQ 2 8
DQ 2 9
DQ 3 0
56
58
68
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
28
29
30
C 416
C 415
3, 9 D D R 3 _D R A MR S T #

1 u _ 6. 3 V _ X 5 R _ 0 4
0 . 1 u _1 6 V _ Y 5 V _ 0 4 MV R E F _ D Q _ D I M MB 1
RE SET #

V R E F _ DQ
VSS4 2
VSS4 3
VSS4 4
VSS4 5
1 72
1 73
1 78
Sheet 10 of 49
197 70 126 1 79

DDR3 SO-DIMM_1
M_ B _ D Q 31
9 S A 0 _ D I M1 201 SA0 DQ 3 1 12 9 M_ B _ D Q 32 V R E F _ CA VSS4 6 1 84
9 S A 1 _ D I M1 202 SA1 DQ 3 2 13 1 8 MV R E F _ D Q _ D I M MB VSS4 7 1 85
M_ B _ D Q 33
9 , 1 9 S MB _C L K 200 S CL DQ 3 3 14 1 M_ B _ D Q 34 2 VSS4 8 1 89
9 , 1 9 S MB _D A T A S DA DQ 3 4 14 3 3 VSS1 VSS4 9 1 90
M_ B _ D Q 35 MV R E F _ D I M1
116 DQ 3 5 13 0 M_ B _ D Q 36 8 VSS2 VSS5 0 1 95
C 397 1 u _ 6. 3 V _ X 5 R _ 0 4
4 M _B _O D T 2 120 OD T 0 DQ 3 6 13 2 M_ B _ D Q 37 C 402 0 . 1 u _1 6 V _ Y 5 V _ 0 4 9 VSS3 VSS5 1 1 96
4 M _B _O D T 3 OD T 1 DQ 3 7 14 0 13 VSS4 VSS5 2
M_ B _ D Q 38
11 DQ 3 8 14 2 M_ B _ D Q 39 14 VSS5
28 DM 0 DQ 3 9 14 7 M_ B _ D Q 40 19 VSS6
46 DM 1 DQ 4 0 14 9 M_ B _ D Q 41 20 VSS7 V T T_ M E M
63 DM 2 DQ 4 1 15 7 M_ B _ D Q 42 25 VSS8
136 DM 3 DQ 4 2 15 9 M_ B _ D Q 43 CLO SE TO SO -DI MM 1 26 VSS9 2 03
153 DM 4 DQ 4 3 14 6 M_ B _ D Q 44 31 VSS1 0 VTT1 2 04
170 DM 5 DQ 4 4 14 8 M_ B _ D Q 45 32 VSS1 1 VTT2
187 DM 6 DQ 4 5 15 8 M_ B _ D Q 46 37 VSS1 2 GN D 1
DM 7 DQ 4 6 16 0 M_ B _ D Q 47 R2 7 0 1 K _1 % _ 0 4 M V R E F _ DIM 1 38 VSS1 3 G 1 GN D 2
4 M _B _ D QS [ 7 : 0 ] M _B _ D QS 0 12 DQ 4 7 16 3 M_ B _ D Q 48 1 .5 V 43 VSS1 4 G 2
M _B _ D QS 1 29 DQ S0 DQ 4 8 16 5 M_ B _ D Q 49 VSS1 5
M _B _ D QS 2 47 DQ S1 DQ 4 9 17 5 M_ B _ D Q 50 R 2 74 C3 8 4 7 8 19 2 -0 0 11
M _B _ D QS 3 64 DQ S2 DQ 5 0 17 7 M_ B _ D Q 51
M _B _ D QS 4 137 DQ S3 DQ 5 1 16 4 M_ B _ D Q 52 1 K _ 1 % _0 4 0 . 1u _ 1 0V _X 5 R _ 0 4
M _B _ D QS 5 154 DQ S4 DQ 5 2 16 6 M_ B _ D Q 53
171 DQ S5 DQ 5 3 17 4
M _B _ D QS 6 M_ B _ D Q 54
M _B _ D QS 7 188 DQ S6 DQ 5 4 17 6 M_ B _ D Q 55
DQ S7 DQ 5 5 18 1 M_ B _ D Q 56
4 M _ B _D QS #[ 7 : 0 ] M _B _ D QS # 0 10 DQ 5 6 18 3 M_ B _ D Q 57
M _B _ D QS # 1 27 DQ S0 # DQ 5 7 19 1 M_ B _ D Q 58
M _B _ D QS # 2 45 DQ S1 # DQ 5 8 19 3 M_ B _ D Q 59
M _B _ D QS # 3 62 DQ S2 # DQ 5 9 18 0 M_ B _ D Q 60
135 DQ S3 # DQ 6 0 18 2
M _B _ D QS # 4 M_ B _ D Q 61
M _B _ D QS # 5 152 DQ S4 # DQ 6 1 19 2 M_ B _ D Q 62
M _B _ D QS # 6 169 DQ S5 # DQ 6 2 19 4 M_ B _ D Q 63
M _B _ D QS # 7 186 DQ S6 # DQ 6 3
DQ S7 #
7 8 19 2 -0 0 11
V T T_ M E M

C 398 C4 1 7 C3 8 0 C3 8 5 C3 8 1

1 0 u _ 10 V _ Y 5V _0 8 1u _ 6 . 3 V _X 5 R _0 4 1u _ 6 . 3 V _ X5 R _0 4 1u _ 6 . 3 V _ X5 R _0 4 1 u_ 6 . 3 V _ X5 R _0 4

1. 5V

C 372 C4 0 3 C4 0 6 C3 9 0 C3 9 1 C4 0 8 C3 8 6 C3 8 8

1 0 u _ 10 V _ Y 5V _0 8 10 u _ 10 V _ Y 5V _0 8 10 u _ 1 0V _ Y 5 V _0 8 1u _ 6 . 3 V _ X5 R _0 4 1 u_ 6 . 3 V _ X5 R _0 4 1 u_ 6 . 3 V _ X5 R _ 04 1 u_ 6 . 3 V _ X 5R _ 04 1 u_ 6 . 3 V _ X 5R _ 04
9, 3 8 V T T _M E M
3 , 6 , 8 , 9 , 2 5, 2 9 , 3 5 , 37 , 3 8 1 .5 V
3, 9 , 1 1 , 1 2, 18 , 1 9 , 2 0, 2 1 , 2 2 , 23 , 2 4 , 2 5, 27 , 2 8 , 2 9, 3 0 , 3 1 , 3 2, 3 3 , 3 4 , 35 , 3 9 3 .3 V S
La yout Note : 24 , 3 5 1 .5 V S

1 .5 V
SO -D IM M_1 i s pl ac e d fa rthe r f rom t he GMCH tha n S O- DIMM _ 0

C 407 C3 8 7 C4 0 9 C4 0 0 C3 8 9 C4 0 4 C4 1 4 C4 1 3 C4 1 2 C 41 1

0 . 1 u _ 16 V _ Y 5V _0 4 0. 1 u _ 1 6V _ Y 5 V _0 4 0. 1 u _ 1 6V _Y 5 V _0 4 0. 1u _ 1 6V _Y 5 V _ 04 0 . 1u _ 1 6 V _Y 5 V _ 04 0 . 1u _ 1 6 V _Y 5 V _ 04 0 . 1u _ 1 6 V _ Y 5 V _ 0 4 0 . 1 u_ 1 6 V _ Y 5 V _ 0 4 0 . 1 u_ 1 6 V _ Y 5 V _ 0 4 0 . 1 u_ 1 6 V _ Y 5 V _ 0 4

DDR3 SO-DIMM_1 B - 11

http://hobi-elektronika.net
 Schematic Diagrams

Panel, Inverter, CRT

PANEL CONNECTOR (LED+EDP) 3. 3 V S

PANEL POWER
P LV DD
R2 8 R2 7 L VD S: 3. 3V 2 A

2 . 2K _0 4

2 . 2K _ 0 4
8 1
2 1 L V D S -U C L K N
R N8
7 2
0 _ 8P 4 R _0 4 L V D S -
L V DS -
U C L K N _C OM B O
U C L K P _ C OMB O 5V S
e DP 3 D: 5V 3 A Q3 0 P LV D D
2 1 L V D S -U C L K P 6 3 L V DS - U 1 N _ C O MB O J _L C D 1 PJ 2 0 A O 34 1 5

G1
G2
21 L V D S -U 1 N 5 4 L V DS - U 1 P _ C OM B O
>100 mil1 2
>100 mil S D
>100mil
21 L V D S -U1 P
R N1 0 8 1 0 _ 8P 4 R _0 4 L V D S - LC LK N _ C O MB O

Gn d 1
G nd 2
2 1 L V D S -LC L K N 7 2 L V DS - LC LK P _C OM B O L V D S -U C L K N _C OM B O 1 2 P _ DDC _ DA T A 2 1 O P E N_ 2 A C1 2 8 C2 4 8 C4 8 8
21 LV D S -L C L K P 6 3 3 4 P _ DDC _ CL K 2 1
L V DS - L1 N _ C OM B O L V D S -U C L K P _ C OMB O 3 .3 V S
21 LV D S - L 1 N 5 6

G
5 4 L V DS - L1 P _ C O MB O >100 mil1 PJ 3 3 C1 4 4 1 u_ 6 . 3 V _X 5 R _ 0 4
21 L V DS -L 1 P 7 8 LV D S -U 2N 2 1 2
L V D S -U 1 N _ C O MB O

0 . 1 u_ 1 6 V _Y 5 V _ 0 4

0 . 1u _ 1 6V _Y 5 V _ 0 4

1 0u _ 1 0V _ Y 5 V _ 0 8
L V D S -U 1 P _ C OM B O 9 10 LV D S -U 2P 2 1 R 22 3 R1 9 7 R 22 6
11 12
C 19 7 *0 . 1u _ 1 0V _X 7 R _ 0 4 L V D S - LC LK P _C OM B O O P E N_ 2 A
2 DP _ A UX _ P C 21 4 *0 . 1u _ 1 0V _X 7 R _ 0 4 L V D S - LC LK N _ C O MB O L V D S -LC LK N _ C O MB O 13 14 LV D S -U 0N 2 1 1 0 K _0 4 * 10 0 K _ 0 4 2 0 0_ 1 % _0 4
2 D P _ A UX _ N 15 16 LV D S -U 0P 2 1
C 17 8 *0 . 1u _ 1 0V _X 7 R _ 0 4 L V D S - U C L K P _ C OMB O L V D S -LC LK P _C OM B O R8 6 1 0 0 K _0 4
2 D P _ T XP _ 0 C 19 6 *0 . 1u _ 1 0V _X 7 R _ 0 4 L V D S - U 1 P _ C OM B O 17 18
2 D P _ T XP _ 1 19 20 LV D S -L 2 N 2 1
_X 7 R _ 0 4 L V D S - L1 P _ C O MB O L V D S -L1 N _ C OM B O

6
C 18 2 *0 . 1u _ 1 0V D
2 D P _ T XP _ 2 C 16 7 *0 . 1u _ 1 0V _X 7 R _ 0 4 L V D S - U C L K N _C OM B O L V D S -L1 P _ C O MB O 21 22 LV D S -L 2 P 2 1
2 D P _ TX N _ 0 23 24
C 18 6 *0 . 1u _ 1 0V _X 7 R _ 0 4 L V D S - U 1 N _ C O MB O
3 .3 V S
2G
2 D P _ TX N _ 1 25 26 2 1 , 34 N B _E N A V D D
B.Schematic Diagrams

C 17 9 *0 . 1u _ 1 0V _X 7 R _ 0 4 L V D S - L1 N _ C OM B O S
2 D P _ TX N _ 2 21 L V D S -L 0N 27 28 2A PL VD D

3
R 65 4 Q 22 A D
21 L V D S -L 0 P 29 30 I N V _ B L ON M TD N 7 0 02 Z H S 6R
10/29
31 32
P L V DD R4 6 0 *1 0K _0 4 B R I GH TN E S S _ R 1 0 0 K _0 4 Q2 2 B 5G
33 34 3 . 3V M T D N 7 0 0 2Z H S 6 R S

AC
35 36 L E D P L_ V I N

4
3 4 B R I GH T N E S S D2 4
37 38 3 .3 V
39 40
R 30 0 _ 04 *B A V 99 R E C T I F I E R
8 7 2 16 -4 0 06 C1 9 C1 6 R4 8 9 *1 00 K _ 0 4 U 4 5A

14
Sheet 11 of 49

A
D6 *C D B U 0 0 3 40 3 .3 V 7 4 L V C0 8 P W U4 5 B

14
V IN V IN L1 L E DP L _ V IN C A BKL _ EN 1 74 L V C 0 8 P W
C 21 34 B K L_ E N 3 B L ON 1 4 3 .3 V
* 0_ 0 6 0 . 1 u_ 1 6 V _Y 5 V _ 04 0 . 1u _ 1 6V _Y 5V _0 4
2 6 B L ON 2
. BL O N

Panel, Inverter,
21 BL O N
3
8
7 3 . 3V
P _G N D . 5
Q4 6 *0 . 1 u _1 6 V _ Y 5 V _ 04 L2 R4 9 0 10 0 K _ 04
3A

7
2 6 H C B 1 6 08 K F -1 2 1 T2 5 U 4 5C

14
1 5

7
R 5 78 P 2 00 3 E V G 7 4 L VC0 8 PW

CRT 1 M _0 4 4
R2 3 4

R2 2 8
C1 7 C 8 00 R4 8 8 *1 0 0 K _0 4 3 .3 V
10
9
8 I N V _B L O N

4 . 7 u _2 5 V _ X 5 R _ 0 8
*1 0 K _ 04 S B _B LO N 1 U4 5 D

0 . 1 u_ 5 0 V _Y 5 V _ 0 6
23 S B _ B L ON

14
*2 0 0_ 1 % _0 4 74 L V C 0 8 P W
12

7
C 15 1108 R 4 86 C5 8 4
28 , 3 4 L ID_ S W #
D

1 1 L I D _S W #1

3
D D
* 0. 1u _ 50 V _ Y 5 V _ 0 6 13 * 1M _ 04 0 . 1u _ 1 0V _ X 5 R _ 0 4
G NB _ E N A V DD 2G 5G 20 , 3 4 , 39 A L L _ S Y S _ P W R GD
Q4 5 Q 4 9A S Q4 9 B S

7
S

MT N 7 0 0 2Z H S 3 *M T D N 7 0 0 2Z H S 6 R *M TD N 7 0 02 Z H S 6 R

M1 M6 M3 M8 6-20-14X30-015
M-M A R K M-M A R K M- M A R K M-M A R K H4 H 21 H2 0 H 25
C 1 4 6 D 1 1 0 C 1 46 D 11 0 C 1 5 8 D 1 58 C 14 6 D 1 1 0 CRT J_ C R T 1
1 0 8A H 1 5F S T0 4 A 1 C C

D A C _R E D L45 . F C M1 00 5 MF - 60 0 T0 1 L43 . F C M1 0 05 MF - 60 0 T 01 FR ED 1
21 D A C _R E D 9
M1 0 M1 5 M7 M1 4 D A C _G R E E N L53 F C M1 00 5 MF - 60 0 T0 1 L42 F C M1 0 05 MF - 60 0 T 01 F G RN 2
M-M A R K M-M A R K M- M A R K M-M A R K H2 H 23 H1 H 22 21 D A C _ GR E E N
. . 10
24 mil
C 1 5 8 D 1 5 8 C 1 58 D 15 8 C 1 5 8 D 1 58 C 15 8 D 1 5 8 D A C _B L U E L56 . F C M1 00 5 MF - 60 0 T0 1 L41 . F C M1 0 05 MF - 60 0 T 01 F B L UE 3
21 D A C _B L U E 11
C6 9 7 C6 9 8 C6 6 1 C 56 3 C 56 0 C 55 8 C5 6 2 C5 6 1 C5 5 9 4
12 DD CD A T A
5

2 2p _ 5 0V _ N P O_ 0 4

2 2 p_ 5 0 V _ N P O_ 0 4

2 2 p_ 5 0 V _N P O_ 0 4

1 0p _ 5 0V _ N P O_ 0 4

1 0p _ 5 0V _ N P O_ 0 4

1 0p _ 5 0V _ N P O_ 0 4
R 4 34 R4 3 3 R4 3 2

10 p _ 50 V _ N P O_ 04

10 p _ 50 V _ N P O _ 04

10 p _ 50 V _ N P O _ 04
M2 M9 M4 M5 13 HS Y NC
M-M A R K M-M A R K M- M A R K M-M A R K 6

1 50 _ 1 %_ 0 4

1 50 _ 1 %_ 0 4

1 50 _ 1% _ 0 4
H1 9 H5 14 V S Y NC
H6 _ 0 D3 _ 7 MT H 7_ 0 D 2 _ 8_ O 7
15 DD CL K
8

1 00 0 p _5 0 V _ X 7 R _ 04

10 0 0 p_ 5 0 V _ X 7R _ 04
2 20 p _ 50 V _ N P O _ 04

2 20 p _ 50 V _ N P O _ 04
M1 1 M1 6 M1 2 M1 3

G ND 2
GN D 1
M-M A R K M-M A R K M- M A R K M-M A R K
3. 3 V S 5V S

8
7
6
5
RN 1

C4
C 3

C5

C1
2 . 2 K _8 P 4 R _ 0 4

1
2
3
4
H 27 H1 2 H1 8 H 26
2 9 2 9 2 9 2 9 U4 0
3 8 3 8 3 8 3 8 10 9 DDC DA T A
4 7 4 7 4 7 4 7 2 1 DA C _ DDC A DA T A DDC _ IN1 D D C _ OU T 1
1 1 1 1
5 6 5 6 5 6 5 6 11 12 D DCL K
2 1 DA C _ DDC A CL K DDC _ IN2 D D C _ OU T 2
M TH 7 _0 D 2_ 8 MT H 7 _ 0D 2 _8 MT H 7_ 0 D 2 _ 8 M T H 7 _0 D 2_ 8 13 14 H S Y N C _C R 1 3 3 3_ 0 4 H SYN C
2 1 D A C _H S Y N C S Y N C_ IN1 S Y N C _ OU T 1
G ND
H 17 GN D H6 G ND H2 8 G ND H 14 GN D 15 16 V S Y N C_ C R 1 3 3_ 0 4 VSYN C
2 9 2 9 2 9 2 9 2 1 D A C _V S Y N C S Y N C_ IN2 S Y N C _ OU T 2
3 8 3 8 3 8 3 8 R 4 1_ 0 4 1 3 FR ED
4 1 7 4 1 7 4 1 7 4 1 7 5 VS V C C _S Y N C V IDE O _ 1
5 6 5 6 5 6 5 6 2 4 F G RN 35 , 3 6 , 3 7, 3 8 , 3 9, 4 0 , 4 1, 4 2 V I N
3 .3 V S V C C _V I D E O V IDE O _ 2 1 8 , 2 4, 2 5 , 2 7, 2 8 , 3 1, 3 2 , 3 3, 3 5 , 3 9, 40 , 4 1 5V S
7 5 F B L UE 2 , 3 , 8, 1 2 , 1 6, 1 8 , 1 9, 20 , 2 2 , 23 , 2 4 , 25 , 2 7 , 28 , 2 9 , 30 , 3 3 , 3 5, 3 7 , 3 8, 3 9 3 . 3V
M TH 7 _0 D 2_ 8 MT H 7 _ 0D 2 _8 MT H 7_ 0 D 2 _ 8 M T H 7 _0 D 2_ 8 C2 C 6 3, 9 , 1 0 , 1 2, 1 8 , 1 9, 2 0 , 2 1, 2 2 , 2 3, 2 4 , 2 5, 27 , 2 8 , 29 , 3 0 , 31 , 3 2 , 33 , 3 4 , 35 , 3 9 3 . 3V S
V C C _D D C V IDE O _ 3
BY P 8 6

0 . 2 2u _ 1 0V _ Y 5 V _ 0 4

0 . 2 2 u_ 1 0 V _ Y 5V _ 0 4
G ND H 3 GN D H2 4 G ND H7 G ND GN D
2 9 2 9 2 9 BYP GN D
3 8 3 8 3 8 I P 4 77 2 C Z 1 6
4 1 7 4 1 7 4 1 7 C 5 57
5 6 5 6 5 6
0 . 2 2 u_ 1 0 V _Y 5 V _0 4
M TH 7 _0 D 2_ 8 MT H 7 _ 0D 2 _8 MT H 7_ 0 D 2 _ 8 CM2009-02QR PN:6-02-20090-B60
G ND GN D G ND G ND IP4772CZ16 PN:6-02-47721-B60

B - 12 Panel, Inverter, CRT

http://hobi-elektronika.net
 Schematic Diagrams

VGA PCI-E Interface

GP U
H9 H11 H 13
H 8_0D 4_4 H8_0 D4_ 4 H 8_0D 4_4

U46A
BGA_1
005_
P080
_29
0X29
0
3.3 V 3 V3_R U N
COMMON
P EX_ VD D Q4
1/ 16PC I_EXPR ESS AO 3415
AK1 6 S D
PEX_I OVD D AK1 7
PEX_I OVD D
AK2 1 C1 17 C1 06 C9 4 C 123 C4 0 C36 C 33
PEX_I OVD D AK2 4 C 46 C 34 R 769
PEX_I OVD D

G
AK2 7
PEX_I OVD D 0. 1u_16V _Y 5V_04 0. 1u_16V _Y 5V_04 1 u_6. 3V_X 5R_ 04 1u_6. 3V _X5R _04 4.7 u_6. 3V_ X5R_ 06 10u_6. 3V _X5R _06 2 2u_6. 3V_ X5R_ 08 d GP U_P WR_ EN _#2
3V 3_R UN 10 u_6. 3V_X 5R_0 6 47
. u _6. 3V_X5 R_06 10_0 4
C 39
3V3_ RU N PLA CE N EA R BA LLS PL AC E NE AR B GA 0. 022 u_16V _X7R _04 R37
AG 11
P EX_IO VDD Q AG 12 10K_0 4
P EX_IO VDD Q AG 13
P EX_IO VDD Q AG 15

dG PU _PWR _EN _#
C 69 R 45 R 48 100 K_04
P EX_IO VDD Q AG 16 D02 CHA NGE

D
P EX_IO VDD Q AG 17
U5 1u_6 .3V _X5R _04 100K _04 P EX_IO VDD Q AG 18 2 20 0 m A Q 50
MC74 VH C1G 08D FT2 G P EX_IO VDD Q MTN7 002ZH S3
5

AG 22 3.3 VS G
1 P EX_IO VDD Q AG 23
34 d GP U_R ST# 4 AM16 P EX_IO VDD Q AG 24

S
P ER STB # PE X_RST P EX_IO VDD Q P EX_ VD D
3, 22, 28 PLT_ RS T# 2
R 67 P EX_C LKR EQ # AR 13 AG 25
PE X_CLKRE Q P EX_IO VDD Q AG 26
3V 3_R UN P EX_IO VDD Q
3

100K _04 P EX_IO VDD Q

AJ14 C8 5 C7 8 C9 8 C 65 C1 38 C32 C 58
AJ15
P EX_IO VDD Q AJ19
R63 *0_ 04 P EX_IO VDD Q 0. 1u_16V _Y 5V_04 0. 1u_16V _Y 5V_04 1u _6. 3V_X5 R_04 1 u_6. 3V_X 5R_ 04 4. 7u_6. 3V _X5R _06 10u_6. 3V _X5R _06 2 2u_6. 3V_ X5R_ 08 R 49
G

AJ21
P EX_IO VDD Q

3
Q 39 AJ22 10 K_04 D
P EX_IO VDD Q

2
D S AJ24
1 9 PE G_ CLK RE Q# *MTN 7002Z HS 3 P EX_IO VDD Q PL AC E NE AR B ALLS P LAC E NE AR B GA Q 5B
AJ25 dGP U_P WR _EN _#0 5G PJ44
PEX_ TSTC LK _OU T A J17 P EX_IO VDD Q AJ27 S MTDN 7002 ZH S6R
PE X_TSTCLK O
_ UT P EX_IO VDD Q *6mil

4
R 68 *220 _1%_04 PEX_ TSTC LK _OU T# A J18 AK1 8
PE X_TSTCLK O
_ UT P EX_IO VDD Q

1
AK2 0

6
D
P EX_IO VDD Q

B.Schematic Diagrams
19 VG A_PE XC LK VG A_P EXC LK AR 16 AK2 3 Q5A R 58
VG A_P EXC LK # AR 17 PE X_REFC LK P EX_IO VDD Q AK2 6 2G
19 VG A_PE XC LK# PE X_REFC LK P EX_IO VDD Q AL16 2 2,3 4,3 7 dG PU _PWR _E N# S MTD N 7002Z HS 6R 1M_04
P EX_IO VDD Q

1
2 PEG _R X0 PE G_R X0 C71 0. 22u_ 10V_X 5R_ 04 P EX_ RX0 A L17
PE G_R X#0 PE X_TX0
2 PEG _R X#0 C75 0. 22u_ 10V_X 5R_ 04 P EX_ RX0# AM17
PE X_TX0

2 P EG _TX0 PE G_T X0 AP 17 AG 20 PE X_CA L_P U_G N D_N C 3V3 _RU N

PE G_T X#0 AN 17 PE X_RX0 G F10x PEX_PLL_HVD D_N C
2 P EG _TX#0 PE X_RX0 G T21X PEX_CA L
_P U_GN D_NC 16 mi l
dG PU _P WR_E N#
2 PEG _R X1 PE G_R X1
PE G_R X#1
C74
C82
0. 22u_ 10V_X 5R_ 04 P EX_ RX1
0. 22u_ 10V_X 5R_ 04 P EX_ RX1#
AM18
AM19 PE X_TX1 PEX_SVD D_3V3
AG 19
F7
PEX _VD D_ SVD D L5 . H CB 1005K F- 121T2 0
2 PEG _R X#1 PE X_TX1 GF10x PEX_SV DD_3V3_N C
C 55 C 104
D02 CH ANGE

Sheet 12 of 49
PE G_T X1 AN 19
2 P EG _TX1 PE G_T X#1 AP 19 PE X_RX1
PE X_RX1
GT21x PE X_SVDD _3V3
0. 1u_16 V_Y 5V_0 4 4. 7u_6. 3V _X5R _06 FOR NV VDD CV TES T
2 P EG _TX#1 P EX_V DD
2 PEG _R X2 PE G_R X2 C87 0. 22u_ 10V_X 5R_ 04 P EX_ RX2 A L19 A2 L3 H C B1005 KF- 121T 20 1 6m il
PE G_R X#2 C83 0. 22u_ 10V_X 5R_ 04 P EX_ RX2# AK 19 PE X_TX2 N C_1 A7 VI D_P LLVD D
2 PEG _R X#2 PE X_TX2 N C_2 AA2 8
.
AR 19 N C_3 AA4 P LAC E N EAR BA LLS

VGA PCI-E
2 P EG _TX2 PE G_T X2 PE X_RX2 N C_4 C 49 C41 C 42 C47 C 38 U 46P
2 P EG _TX#2 PE G_T X#2 AR 20 AA8
PE X_RX2 N C_5 AB4 BG_
A100
5_P0
80_
290
X290
A L20 N C_6 AB7 *4. 7u_6 .3V _X5R _06 10u_6. 3V _X5R _06 4700 p_50V _X7R _04 0. 1u_10V _X7R _04 0 .1u _10V_ X7R _04
COMMON
2 PEG _R X3 PE G_R X3 C86 0. 22u_ 10V_X 5R_ 04 P EX_ RX3 PE X_TX3 N C_7
2 PEG _R X#3 PE G_R X#3 C95 0. 22u_ 10V_X 5R_ 04 P EX_ RX3# AM20 AC 5
PE X_TX3 N C_8 AD 28 14/ 16XTA L
_P L
N C_9 1 2m il

Interface
PE G_T X3 AP 20 AD 6 AE9
2 P EG _TX3 PE G_T X#3 AN 20 PE X_RX3 N C_10 AF6 AE8 PLLVD D
2 P EG _TX#3 PE X_RX3 N C_11 AG 6 C37 C 45 A D8 PLLVD D
AM21 N C_12 AH 12 A D9 VI D_PLLVD D
2 PEG _R X4 PE G_R X4 C97 0. 22u_ 10V_X 5R_ 04 P EX_ RX4 PE X_TX4 N C_13 VI D_PLLVD D
2 PEG _R X#4 PE G_R X#4 C10 3 0. 22u_ 10V_X 5R_ 04 P EX_ RX4# AM22 AH 24 0. 1u_10V _X7R _04 0 .1u _10V_ X7R _04 AF8
PE X_TX4 N C_14 AH 25 AF9 SP _PLLVDD

2 P EG _TX4
PE G_T X4
PE G_T X#4
AN 22
AP 22
PE X_RX4
N C_15
N C_16
AH 26
AJ5
3V3_ RU N N1 2 P- GS P LAC E NE AR BG A PLA CE N EA R BA LLS
SP _PLLVDD

2 P EG _TX#4 PE X_RX4 N C_17 AK1 5

PE G_R X5 N C_18
2 PEG _R X5 C10 8 0. 22u_ 10V_X 5R_ 04 P EX_ RX5 A L22
PE X_TX5 N C_19
AL7 R 35 *20K _1%_04 VG A_ RO M_ SI R47 2 45. 3K_ 1%_04 X _SS IN D2 XT ALSSIN XTA L
O UTB UFF D1 X_O UT BU FF
2 PEG _R X#5 PE G_R X#5 C10 9 0. 22u_ 10V_X 5R_ 04 P EX_ RX5# AK 22 B7
PE X_TX5 N C_20 C7
PE G_T X5 AR 22 N C_21 D5 VG A_ RO M_ SO B1 B2
PE X_RX5 N C_22 R 450 *4. 99K _1%_04 R44 9 10K _1%_04 XT ALIN XTALO UT
2
2
P EG _TX5
P EG _TX#5 PE G_T X#5 AR 23
PE X_RX5 N C_23
D6 D02 CHA NGE R47 7 R 476
D7 N 12E- G E- A1 G F106 -70 0-A 1
PE G_R X6 C12 1 0. 22u_ 10V_X 5R_ 04 P EX_ RX6 A L23
PE X_TX6
N C_24
N C_25
E5 R 36 *34. 8K _1%_04 VG A_ RO M_ SC LK R47 3 15K _1%_04
R47 3 34 .8K FO R W / VB IOS RO M 10K_ 04 10 K_04
2 PEG _R X6 AM23 E7
2 PEG _R X#6 PE G_R X#6 C12 2 0. 22u_ 10V_X 5R_ 04 P EX_ RX6# PE X_TX6 N C_26
F4
R47 3 15 K FOR BI OS I NCL UDE VB IOS FS X8L_25M Hz? ? ? ? ?
N C_27
2 P EG _TX6
PE G_T X6 AP 23
AN 23 PE X_RX6 N C_28
G5
H10 R 41 45. 3K _1%_04 VG A_ STR AP 0 R42 *4. 99K_1 %_ 04 (R4 73 1 5K? U42 & C 569 ? ? ? ) 1
X11
2H SX84 0GA _27MHZ
2 P EG _TX#6 PE G_T X#6 PE X_RX6 N C_29 XT AL_I N XT AL_O U T
H11
PE G_R X7 C12 4 0. 22u_ 10V_X 5R_ 04 P EX_ RX7 AM24
PE X_TX7
N C_30
N C_31
H12 R 56 *34. 8K _1%_04 VG A_ STR AP 1 R55 34. 8K_ 1%_04 D 02 CHA NGE C 566 C56 7
2 PEG _R X7 PE G_R X#7 C13 9 0. 22u_ 10V_X 5R_ 04 P EX_ RX7# AM25 H15
2 PEG _R X#7 PE X_TX7 N C_32 X12
H21 20p_5 0V_N PO _04 20p_50 V_N PO _04
N C_33 4 3
PE G_T X7 AN 25 H24 R 54 34. 8K _1%_04 VG A_ STR AP 2 R53 *34. 8K_1 %_ 04
2 P EG _TX7 PE G_T X#7 AP 25 PE X_RX7 N C_34 H25
2 P EG _TX#7 PE X_RX7 N C_35 1 2
H26
A L25 N C_36 H32 *H SX32 1S_27 MH Z
AK 25 PE X_TX8 N C_37 L8
PE X_TX8 N C_38
P6
AR 25 N C_39 R28
AR 26 PE X_RX8
PE X_RX8
N C_40
N C_41
U7
V6
Cry st a l 8 0 4 5 & 32 2 5 C o-la y
A L26 N C_42 Y4
AM26 PE X_TX9 N C_43
PE X_TX9
AP 26
AN 26 PE X_RX9
PE X_RX9 3V3_R U N
D02 CH ANGE
AM27
PE X_TX10
B IOS R OM
AM28 U 46O 3 V3_R UN
PE X_TX10
1 6 mi l 3V3 _RU N
AN 28 R451
AP 28 PE X_RX10 J10 BG A_ 1005_P 080_2 90X290 U42
PE X_RX10 VD D33_1 C OMMON

7
J11 8
VD D33_2 10K_0 4 H OLD VC C
A L28 J12 C6 4 C48 C 35 C 59 C3 1 1 3
/ 1 6 M IS C 2 3
AK 28 PE X_TX11 VD D33_3 J13 J26 C3 V GA _RO M_CS # 1 WP C 569
PE X_TX11 VD D33_4 J9 J25 BBI ASN_N C R OM_
CS CS
VD D33_5 0. 1u_16V _Y 5V_04 0.1 u_16V _Y5 V_04 0 .1u _16V_ Y5V _04 1u_ 6.3 V_X5R _04 4. 7u_6. 3V _X5R _06 BBI ASP_NC
AR 28 D3 V GA _RO M_SI 5 *0. 1u_ 16V_Y 5V _04
AR 29 PE X_RX11 RO M_S I C4 V GA _RO M_SO 2 SI
PE X_RX11 R OM_SO SO
D4 V GA _RO M_SC LK 6 4
AK 29 P LAC E N EAR BAL LS P LAC E N EAR BG A RO M_S CLK S CK GN D
PE X_TX12
A L29 *M X25 L5121E MC - 20G
PE X_TX12 P7
AP 29 VD D_SEN SE R7 R767 *0_04
PE X_RX12 GN D_SEN SE V GA _ST RA P2 V7 STR AP2 3V3_R U N 6-04-25512-B71
AN 29 V GA _ST RA P1 W7
PE X_RX12 AD 20 PS1 _VD D_ SEN SE V GA _ST RA P0 W5 STR AP1 F6 I 2C _SC L
AM29 VD D_SEN SE AD 19 PS 1_VD D _SE NS E 41 STR AP0 I 2CH _SCL R 474 2.2 K_04 6-04-25512-B70
PE X_TX13 GN D_SEN SE PS1 _GN D _SE NS E PS 1_G ND _SE NS E 41 6-04-25512-B72
AM30 N12P- GS G6 I 2C _SD A R 475 2.2 K_04
PE X_TX13 D35 I 2CH_SD A
AN 31 VD D_SEN SE E35
6-04-25010-490
PE X_RX13 GN D_SEN SE R768 *0_04
AP 31 PEX_ VD D A5
PE X_RX13 L7 SPD IF_N C
AM31
PE X_TX14 1 6m il HC B1 005KF - 121T20
AM32
PE X_TX14 PEX_PLLVD D
AG 14
AH 15
P EX_P LLV DD . A B5 CEC
BUFR ST
A4
AR 31 PEX_PLLVD D
PE X_RX14 C 72 C96 C 70
AR 32 C5
PE X_RX14 AG 21 P EX_T ER MP R 82 2. 49K _1%_04 0. 1u_16 V_Y 5V_0 4 1u_6. 3V _X5R _04 4 .7u _6. 3V_X 5R_0 6 P GOO D_OU T
AN 32 PEX _
T ERMP AH 21
AP 32 PE X_TX15 PEX _
T ERMP N9 AK 14
PE X_TX15 R 64 40 .2K _1%_04 M_STR AP _RE F0 MULTI_S TRAP_R EF0_GN D GN D
P LAC E N EAR BAL LS PL AC E NE AR B GA R8
AR 34 M8 MULTI_S TRAP_R EF0_GN D K9
AP 34 PE X_RX15 AP3 5 M9 MULTI_S TRAP_R EF1_GN D GN D K8
PE X_RX15 TESTMOD E G PU _TES TMOD E R 507 10 K_04 1u->0.1u C990525 R 66 40 .2K _1%_04 M_STR AP _RE F1 MULTI_S TRAP_R EF1_GN D GN D
N1 2E- GE A
- 1 GF 106- 700- A1
N 12E- G E- A1 G F106- 700 -A 1

16, 41 3V3 _RU N

13, 37 PE X_VD D
2, 3, 8, 11, 16, 18, 19, 20, 22, 23, 24, 25, 27, 28, 29, 30, 33, 35, 37, 38, 39 3. 3V
3,9 ,10 ,11 ,18 ,19 ,20 ,21 ,22 ,23 ,24 ,25 ,27 ,28 ,29 ,30 ,31 ,32 ,33 ,34 ,35 ,39 3. 3VS

VGA PCI-E Interface B - 13

http://hobi-elektronika.net
 Schematic Diagrams

VGA Frame Buffer Interface

F ram e Buffer Int er face
U46B U46C

BGA_0
105
_P080
_29
0X29
0 BGA_
100
5_P0
80_2
90X2
90
COMMON COMMON

2/ 16FBA 3/16 FBB

FB C_D [ 63: 0] FB VD DQ

2727
F BA_ D[ 63: 0] F BV DD Q 15 FB C_ D[ 63: 0]

PN
1 4 F BA _D[ 63: 0]

7 J23
FBC _D 0 B13 FBB_D 0 FBVD DQ

2727
FB A_D 0 L 32 FBC _D 1 D13

2 J24
FBA _D0 FB VDD Q FBB_D 1 FBVD DQ

TR
N 33 A13

AJ29
FB A_D 1 FBC _D 2

U 27
FBA _D1 FB VDD Q FBB_D 2 FBVD DQ
FB A_D 2 L 33 C 134 C13 1 C 130 C 132 FBC _D 3 A14 C1 36 C 141 C99 C 133

2A9
FBA _D2 FB VDD Q FBB_D 3 FBVD DQ

2729
FB A_D 3 N 34 FBC _D 4 C16

3A1
FBA _D3 FB VDD Q