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Prepared by Approved by
Course Objectives:
At the end of this course, the students will be able to:
CO1:Write VHDL codes for combinational and sequential circuits and simulate.
CO5: Generate layouts for simple logic circuits using layout editor and analyze
to do post layout simulation.
CO6: Perform timing analysis with constraints and map it to the design.
CO7: Write test benches using VHDL codes for the given program.
CO8: Write VHDL code and implement circuits for some typical applications.
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Total =40
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1. You should first study the solved problems and then try to solve
all the exercise problems of the experiment in the lab.
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References:
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CONTENTS
Page No.
Sl. No. Title of the Experiment
01 INTRODUCTION TO MODELSIM 6
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EXPERIMENT NO. 01
INTRODUCTION TO MODELSIM
I. Starting ModelSim
1. Start ModelSim
3. The first thing to do is to create a project. Projects ease the interaction with ModelSim and
are
useful for organizing files and simulation settings.
5. A Create Project window pops up (See Figure 1). Select a suitable name for your project;
set the Project Location to D:/Name_reg_no, and leave the Default Library Name to work.
Hit Ok.
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6. After hitting OK, an Add items to the Project dialog pops out (See Figure 2).
If you have closed the Add items to the Project dialog, then select File Add to Project
New File.
2. A Create Project File dialog pops out. Select an appropriate file name for the file you want
to
add; choose VHDL as the add file as type option and Top level as the Folder option (See
Figure 3).
3. On the workspace section of the Main Window (See Figure 4), double-click on the file you
4. Type in your code in the new window. For our tutorial, we will use a simple D flip-flop
code
5. Save your code (File Save) and use compile compile option.
1. Click on the Library tab of the main window and then click on the (+) sign next to the
work
library. You should see the name of the entity of the code that we have just compiled DFF.
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2. Double-click on DFF to load the file. This should open a third tab sim in the main
window.
3. Now select view All Windows from the main window to open all ModelSim windows.
4. Locate the signals window and select the signals that you want to monitor for simulation
5. Drag the above signals using the left button of the mouse into the wave window. You can
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6. Do the same as in step 5 with the list window (i.e. drag selected signals into the list
window,
7. Now, select the wave window, and click on zoom full (see below). Your simulation
should
look as follows. Add binary values i.e 1 or 0 by selecting force value option by right-
clicking on the required signals.
Exercise problems
1. Repeat the same for combinational circuits.
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EXPERIMENT NO. 02
INTRODUCTION TO DATA FLOW AND BEHAVIORAL
MODELS
I. Solved Examples
1. Data flow model for all 2-i/p basic gate and universal operations.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity gates is
Port ( Ain : in std_logic;---- First Input
Bin : in std_logic; ---- Second Input
Op_not : out std_logic;
Op_or : out std_logic;
Op_and : out std_logic;
Op_nor : out std_logic;
Op_nand : out std_logic;
Op_xor : out std_logic;
Op_xnor : out std_logic);
end gates;
library ieee;
use ieee.std_logic_1164.all;
entity full_sub is
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process(a,b,c) is
variable temp1,temp2,temp3:std_logic;
begin
diff<= a xor b xor c;
temp1:= not(a) and b;
temp2:= not(a) and c;
temp3:= b and c;
borr<= temp1 or temp2 or temp3;
end process;
end behavioural;
B. Write the behavioral model for following blocks/functions. Simulate and synthesize
the same.
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EXPERIMENT NO. 03
INTRODUCTION TO SEQUENTIAL, BEHAVIORAL AND
MIXED-MODE MODELS
I. Solved Examples
1. Write a sequential VHDL code for mod-6 binary counter with positive edge triggered
clock and active-low clear.
entity mod6 is
port (clk: in std_logic;
signal s:std_logic_vector (2 downto 0);
c: out std_logic_vector(2 downto 0));
end mod6;
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end if;
end if;
if s=100 then
if clkevent and clk =1 then
c<=101;
end if;
end if;
if s=101 then
if clkevent and clk =1 then
c<=000;
end if;
end if;
s<=0;
end process;
end modcount;
a_input
output
b_input
alu_ctrl
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
entity asyn_alu is
generic(data_width : integer := 8);
port
( a_input,b_input : in std_logic_vector(data_width-1 downto 0);
asyn_output: out std_logic_vector(data_width-1 downto 0);
alu_ctrl : in std_logic_vector(1 downto 0)
);
end asyn_alu;
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begin
process(alu_ctrl,a_input, b_input)
begin
case alu_ctrl is
when "00" =>
asyn_output <= a_input and b_input;
1. 3-to-8 decoder with enable input and active-high output (Using concurrent signal
assignment statements).
2. 3-to-8 decoder with enable input and active high output (Using With..select.)
1. F(a,b,c,d)=MM(1,2,13,15)
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4. 3-to-8 decoder with enable input and active high output (Using If..then..else)
5. 8:1 Mux (Using case statement)
6. Clocked negative edge triggered 8:3 encoder with asynchronous reset facility (Using case
statement)
7.1:4 Demux with active-low inputs (Using case statement)
8.8-to-3 priority encoder with active high enable input and active high output (Using
If..then..else )
9.Mod-100 integer counter with a positive edge triggered clock , active high clear , parallel
load, up/down feature.
10. Write the mixed style VHDL model for full subtractor block. Model the difference and
borrow using data flow (behavioral) and structural style respectively.
11. 8-bit binary to gray and gray to binary code converter
12. Computing 1s complement and 2s complement of given 8-bit binary number
13.2-bit BCD to Excess-3 code converter
14.8-bit binary to 8-bit BCD code converter
15. To simulate the cosine of a real number.
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EXPERIMENT NO. 04
INTRODUCTION TO BEHAVIORAL MODELING OF
SEQUENTIAL CIRCUITS
I. Solved Examples
1. Write a sequential VHDL code for Ring Counter.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ring_counter is
port (
DAT_O : out unsigned(3 downto 0);
RST_I : in std_logic;
CLK_I : in std_logic
);
end ring_counter;
process(CLK_I)
begin
if( rising_edge(CLK_I) ) then
if (RST_I = '1') then
temp <= (0=> '1', others => '0');
else
temp(1) <= temp(0);
temp(2) <= temp(1);
temp(3) <= temp(2);
temp(0) <= temp(3);
end if;
end if;
end process;
end Behavioral;
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2. Write a sequential VHDL code for Sequential Arithmetic Logic Unit and Counter.
a_input
output
b_input
alu_ctrl
clock
reset
4
counter
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
entity syn_alu is
generic(data_width : integer := 8);
port
( clock,reset : in std_logic;
a_input,b_input : in std_logic_vector(data_width-1 downto 0);
output : out std_logic_vector(data_width-1 downto 0);
counter_out: out std_logic_vector(data_width-1 downto 0);
alu_ctrl : in std_logic_vector(1 downto 0)
);
end syn_alu;
begin
process(clock)
begin
if rising_edge(clock) then
if reset = '1' then
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process(clock)
begin
if rising_edge(clock) then
case alu_ctrl is
when "00" =>
output <= a_input and b_input;
end behavior;
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6. Write the sequential VHDL code for a Mealy synchronous sequential circuit for detection
10110 serial input sequences. The3 circuit has to produce a high on the output Q, whenever it
detects 10110 sequence on its serial input. The overlapping sequence must be detected.
Example
x 0 1 1 0 1 1 0 1 1 0 0
Q 0 0 0 0 0 0 1 0 0 1 0
7. Write the sequential VHDL code for a Mealy synchronous sequential circuit for detection
11011 serial input sequences. The3 circuit has to produce a high on the output Q, whenever
it detects 11011 sequence on its serial input. The overlapping sequence must be detected.
Simulate and synthesize the same.
Example
x 0 1 1 1 0 1 1 0 1 1
Q 0 0 0 0 0 0 1 0 0 1
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EXPERIMENT NO. 05
INTRODUCTION TO STRUCTURAL MODELING OF LOGIC
CIRCUITS
I. Solved Examples
1. Structural model of Full Adder using only NAND gates.
library ieee;
use ieee.std_logic_1164.all;
entity nand1 is
port(x: in std_logic; y: in std_logic; z: out std_logic);
end nand1;
architecture nand1 of nand1 is
begin
z<=x nand y;
end nand1;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity full_adder is
port( a : in STD_LOGIC;
b : in STD_LOGIC;
cin : in STD_LOGIC;
sum : out STD_LOGIC;
cout : out STD_LOGIC);
end full_adder;
component nand1
port(x: in std_logic; y :in std_logic; z:out std_logic);
end component;
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entity nor1 is
port(x,y: in std_logic; z:out std_logic);
end nor1;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity d_latch is
Port ( d : in STD_LOGIC; clk: in std_logic;
q : inout STD_LOGIC;
qbar : inout STD_LOGIC);
end d_latch;
component nor1
port(x,y: in std_logic; z: out std_logic);
end component;
signal dbar,e,f:std_logic;
begin
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end Behavioral;
library ieee;
use ieee.std_logic_1164.all;
entity xor1 is
port(u,v: in std_logic; w:out std_logic);
end xor1;
library ieee;
use ieee.std_logic_1164.all;
entity not1 is
port(x: in std_logic; y: out std_logic);
end not1;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity parity is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
d : in STD_LOGIC;
odd : buffer STD_LOGIC;
even : out STD_LOGIC);
end parity;
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component xor1
port(u,v: in std_logic; w: out std_logic);
end component;
component not1
port(x: in std_logic; y: out std_logic);
end component;
begin
Write the structural VHDL code for the following digital blocks. Simulate and synthesize the
same.
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EXPERIMENT NO. 06
INTRODUCTION TO SUBPROGRAMS IN VHDL
I. Solved Examples
1. Write a function for byte reversal in VHDL
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity byt is
port(
din:in std_logic_vector(3 downto 0);
dout:out std_logic_vector(3 downto 0));
end byt;
architecture byt of byt is
variable res:std_logic_vector(din'reverse_range);
begin
process(din)
begin
dout<=byte_reversal(din);
end process;
end byt;
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use ieee.std_logic_unsigned.all;
package mymux is
function MUX(signal in1,in2,sel:in std_logic) return std_logic;
end myMUX;
--Use of package
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.mymux.all;
entity FullAdd is
Port ( A,b,Ci : in std_logic;
sum, carry : out std_logic);
end FullAdd;
3. Write a VHDL program for full adder using half adder (Procedure) and OR gate
(Component).
library ieee;
use ieee.std_logic_1164.all;
entity or_2c is
port(in1,in2:in std_logic;
out1:out std_logic);
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end or_2c;
architecture dataflow of or_2c is
begin
out1<= in1 or in2;
end dataflow;
library ieee;
use ieee.std_logic_1164.all;
entity fulladder is
port(a,b,cin:in std_logic;
sum, carry:out std_logic);
end fulladder;
architecture FA of fulladder is
procedure HA (signal in1,in2:in std_logic; signal sum1,carry1:out std_logic)
is
begin
sum1<=(in1 xor in2);
carry1<=(in1 and in2);
end HA;
signal s1,c1,c2:std_logic;
begin
u1: ha(a,b,s1,c1);
u2: ha(s1,cin,sum,c2);
u3: entity or_2c port map (in1=>c1 ,in2=>c2, out1=>carry);
end fa;
A. Write the behavioral VHDL code for the following generic blocks:
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C. Write the behavioral VHDL code for following circuits using function and procedure
1. 4-bit gray code counter
2. To find cos2(x), where Cos(x) = 1 (x2/2!) + (x4/4!)-(x6/6!)+. Considering
first five terms.
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EXPERIMENT NO. 07
INTRODUCTION TO XILINX ISE TOOL
Getting Started
To start ISE, double-click the desktop icon,
Accessing Help
At any time during the tutorial, you can access online help for additional information about
the ISE software and related tools.
To open Help, do either of the following:
Press F1 to view Help for the specific tool or function that you have selected or
highlighted.
Launch the ISE Help Contents from the Help menu. It contains information about
creating and maintaining your complete design flow in ISE.
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When the table is complete, your project properties will look like the following AS SHOWN
IN FIG 1:
7. Click Next to proceed to the Create New Source window in the New Project Wizard. At
the end of the next section, your new project will be complete.
In this section, you will create the top-level HDL file for your design. Determine the
language that you wish to use for the tutorial. Then, continue either to the "Creating a VHDL
Source" section below, or skip to the "Creating a Verilog Source" section.
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7. Click Next, then Finish in the New Source Wizard - Summary dialog box to complete
the new source file template.
The source file containing the entity/architecture pair displays in the Workspace, and the
counter displays in the Source tab, as shown below in figure 3:
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FIG.3.
2. Customize the source file for the counter design by replacing the port and signal name
placeholders with the actual ones as follows:
replace all occurrences of <clock> with CLOCK
replace all occurrences of <count_direction> with DIRECTION
replace all occurrences of <count> with count_int
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter is
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You have now created the VHDL source for the tutorial project. Skip past the Verilog
sections below, and proceed to the Checking the Syntax of the New Counter
Modulesection.
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Verify that the counter design functions as you expect by performing behavior simulation
as follows:
1. Verify that Behavioral Simulation and counter_tbw are selected in the Sources
window.
2. In the Processes tab, click the + to expand the Xilinx ISE Simulator process and
double-click the Simulate Behavioral Model process.
The ISE Simulator opens and runs the simulation to the end of the test bench.
3. To view your simulation results, select the Simulation tab and zoom in on the
transitions.
The simulation waveform results will look like the following:
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Note: You can ignore any rows that start with TX.
4. Verify that the counter is counting up and down as expected.
5. Close the simulation view. If you are prompted with the following message, You have
an active simulation open. Are you sure you want to close it?, click Yes to continue.
You have now completed simulation of your design using the ISE Simulator.
Implement the design and verify that it meets the timing constraints specified in the
previous section.
1. Select the counter source file in the Sources window.
2. Open the Design Summary by double-clicking the View Design Summary process in the
Processes tab.
3. Double-click the Implement Design process in the Processes tab.
4. Notice that after Implementation is complete, the Implementation processes have a
green check mark next to them indicating that they completed successfully without
Errors or Warnings.
5. Locate the Performance Summary table near the bottom of the Design Summary.
6. Click the All Constraints Met link in the Timing Constraints field to view the Timing
Constraints report. Verify that the design meets the specified timing requirements.
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Specify the pin locations for the ports of the design so that they are connected correctly on
the board shown in fig 8.
To constrain the design ports to package pins, do the following:
1. Verify that counter is selected in the Sources window.
2. Double-click the Floorplan Area/IO/Logic - Post Synthesis process found in the
User Constraints process group. The Xilinx Pinout and Area Constraints Editor
(PACE) opens.
3. Select the Package View tab.
4. In the Design Object List window, enter a pin location for each pin in the Loc column
using the following information:
CLOCK input port connects to FPGA pin P80 (GCK0 signal on board)
COUNT_OUT<0> output port connects to FPGA pin P30 (LD0 signal on board)
COUNT_OUT<1> output port connects to FPGA pin P31 (LD1 signal on board)
COUNT_OUT<2> output port connects to FPGA pin P44 (LD2 signal on board)
COUNT_OUT<3> output port connects to FPGA pin P45 (LD3 signal on board)
DIRECTION input port connects to FPGA pin P3 (SW signal on board)
5. Select File Save. You are prompted to select the bus delimiter type based on the
synthesis tool you are using. Select XST Default <> and click OK.
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6. Close PACE.
Notice that the Implement Design processes have an orange question mark next to them,
indicating they are out-of-date with one or more of the design files. This is because the UCF
file has been modified.
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7. In the Welcome dialog box, select Configure devices using Boundary-Scan OR configure
device & select using slave serial mode.
8. Verify that Automatically connect to a cable.
9. Click Finish.
10. one window generate ,select counter.bit file
11. The Assign New Configuration File dialog box appears. To assign a configuration file to
the xc2s50 device in the JTAG chain, select the counter.bit file and click Open.
12. If you get a Warning message, click OK.
13. Select Bypass to skip any remaining devices.
14. Right-click on the xc3s400 device image, and select Program... The Programming
Properties dialog box opens
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EXPERIMENT NO. 08
I. Solved Examples
1. Simulate and synthesize 1-bit comparator using XILINX SPARTAN 3 chip.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity comparator is
Generic (N: integer := 3);--- Generalizing the Inputs
Port( A,B: in STD_LOGIC_VECTOR(N downto 0);
ALB,AGB,AEB: out STD_LOGIC);
end comparator;
process(A,B)
begin
if ( A < B ) then ALB <= '1';
else ALB <= '0';
end if;
if ( A > B ) then AGB <= '1';
else AGB <= '0';
end if;
if ( A = B ) then AEB <= '1';
else AEB <= '0';
end if;
end process;
end Comparator_arc;
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity exp2e_Demux1_4 is
port (
d_in: in STD_LOGIC; --Input For Demultiplexer
sel: in STD_LOGIC_VECTOR (1 downto 0); --Select Line of Demux
d_out: out STD_LOGIC_VECTOR (3 downto 0)); --Output Lines of Demux
end exp2e_Demux1_4;
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A. Write the behavioral VHDL code for realizing following counters, capable of
counting following counts repeatedly with a 1 sec delay at given OUTPUT LEDs (by
assigning proper pin numbers in the edit constraint file);
Use the available system clock of frequency 4 MHz and include an asynchronous active-high
reset input.
B. Write a behavioral VHDL code for generating a single digit counter, capable of
counting following counts repeatedly with a 1 sec delay at one of its seven segment
display digits(by assigning a proper pin number to display control in the trainer):
Use the available system clock of frequency 4 MHz and include an asynchronous active-high
reset input.
C. Write the behavioral VHDL code for a Mealy synchronous sequential circuit for
detecting 10110 serial input sequences. The circuit has to produce a high on the output
q, whenever it detects 10110 sequence on its serial input x. the overlapping sequence
must be detected.
Example:
Output q 00000010010
Synthesize the code and download the description on the SPARTAN 3 chip and demonstrate
the sequence detector action.
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EXPERIMENT NO. 09
SYNTHESIS AND EXECUTION OF STAIRCASE, RAMP AND
TRAINGULAR WAVEFORM IN SPARTAN 3 CHIP USING VHDL
I. Solved Examples
1. Synthesize and display the staircase waveform in CRO using SPARTAN 3 CHIP.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity staircase is
Port ( clk : in STD_LOGIC;
divider : inout STD_LOGIC_VECTOR(7 downto 0):="00000000");
end staircase;
process(clk)
begin
if clk' event and clk='1' then
count<=count +1;
end if;
end process;
clk1<=count(3);
process(clk1,divider)
begin
if clk1' event and clk1='1' then
divider<=divider + 25;
end if;
end process;
end Behavioral;
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2. Synthesize and display the ramp waveform in CRO using SPARTAN 3 CHIP.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity RAMPWAVE is
Port ( clk : in STD_LOGIC;
divider : inout STD_LOGIC_VECTOR(7 downto 0):="00000000");
end RAMPWAVE;
begin
process(clk)
begin
if clk' event and clk='1' then
count<=count +1;
end if;
end process;
clk1<=count(8);
process(clk1,divider)
begin
if clk1' event and clk1='1' then
divider<=divider + 1;
end if;
end process;
end Behavioral;
3. Synthesize and display the traingular waveform in CRO using SPARTAN 3 CHIP.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity traingle is
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end traingle;
process(temp(3))
begin
if rising_edge(temp(3)) then
counter<=counter +1;
if counter(8)= '1' then
divider<=counter(7 downto 0);
else
divider<=not(counter(7 downto 0));
end if;
end if;
end process;
end Behavioral;
1. Synthesize and display the ramp waveform with delay of 0.25 us.
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EXPERIMENT NO. 10
IMPLEMENTING STEPPER MOTOR CONTROL USING XILINX
SPARTAN 3 CHIP
I. SOLVED EXAMPLES
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity stepper is
port (clk, anticlk, slow, med, high1: in STD_LOGIC;
stepout: out STD_LOGIC_VECTOR (3 downto 0));
end stepper;
begin
process(clk)
begin
if rising_edge(clk) then
divider<=divider+1;
end if;
end process;
process(slow, med, high1)
begin
if slow=1 then clk1<=divider(20);
elsif med=1 then clk1<=divider(18);
elsif high=1 then clk1<=divider(15);
else clk1<=0;
end if;
end process;
process(anticlk, clk1)
begin
if rising_edge(clk1) then
if antclk=1 then
count<=count-1;
else
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Dept. of E&C Engg., MIT VLSI LAB
count<=count+1;
end if;
end if;
end process;
process(count)
begin
case count is
when 00=>stepout<=1100;
when 01=>stepout<=0110;
when 10=>stepout<=0011;
when 11=>stepout<=1001;
when others=>null;
end case;
end process;
end Behavioral;
1.Write a program to run the motor in the clockwise direction with a frequency of 10Hz.
2.Write a program to run the motor in the anti-clockwise direction with a frequency of 4MHz.
3.Write a program to run the motor in steps of 2 and 4 in one clock cycle (assume suitable
clock frequency).
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Dept. of E&C Engg., MIT VLSI LAB
EXPERIMENT NO. 11
INTRODUCTION TO MICROWIND SOFTWARE FOR LAYOUT
GENERATION
Microwind is a tool for designing and simulating circuits at layout level. The tool features
full editing facilities (copy, cut, past, duplicate, move), various views (MOS characteristics,
2D cross section, 3D process viewer), and an analog simulator.
When we open the file microwind, a window with grids and a palette consisting of different
fabrication materials will pop out as in the fig1.
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Dept. of E&C Engg., MIT VLSI LAB
: Delete tool, Erases some layout included in the given area or pointed by the mouse.
: Copy and paste tool, Copies the layout included in the given area.
: Stretch and move tool, Changes the size of one box, or moves the layout included in
the given area.
: Show palette
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Dept. of E&C Engg., MIT VLSI LAB
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Dept. of E&C Engg., MIT VLSI LAB
Step 1:
To create a pMOS transistor: Select N well from the palette. Click on the grid and
drag it to draw a box as shown in the fig2.
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Dept. of E&C Engg., MIT VLSI LAB
Step 2:
Select P+diffusion, and draw the box inside the N well as can be seen in fig 3.
The spacing between p+diffusion and the N well boundaries should not be less than 6
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Dept. of E&C Engg., MIT VLSI LAB
Step 3:
Now select polysilicon from the palette and draw the polysilicon gate as shown in the
fig 4.
The box width should not be less than 2, which is the minimum width of the polysilicon
box. And the extra polysilicon surrounding the p+diffusion should not be less than 3
Step 4:
To define the source and drain contacts: To build an electrical connection, a physical
contact is needed. The corresponding layer is called "contact".
Click on Metal 1 in the palette and then create the required rectangle on both the ends
of p diffusion.
Make the contacts between metal 1 and p+ diffusion by placing the contact
P+diffusion/metal1 from the palette on the layout as shown in the fig 5.
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Dept. of E&C Engg., MIT VLSI LAB
Step 5:
Similarly draw the nmos below the pmos by using N+diffusion, define the polysilicon
gate, source, drain and the contacts.
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Dept. of E&C Engg., MIT VLSI LAB
Step 6:
Once the design is over check the size constraints using the design rule checker.
If there are any changes to be made in the dimension of the layout, it will display the
errors as shown in fig 7.
It can be resized by clicking on the edges of the layout and dragging it.
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Dept. of E&C Engg., MIT VLSI LAB
Step 7:
Once the pmos and nmos transistors are drawn, connections between them is to be
done.
And connect the drains of each transistors with the metal 1 as it is show in fig 8.
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Dept. of E&C Engg., MIT VLSI LAB
Step 8:
As polysilicon is a poor conductor, metal is preferred to interconnect signals and
supplies.
Consequently, the input connection of the inverter is made with metal.
Metal and polysilicon are separated by an oxide which prevents electrical
connections.
Therefore, a box of metal drawn across a box of polysilicon does not allow an
electrical connection.
You may insert a metal-to-polysilicon contact in the layout using an icon situated in
the palette.
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Dept. of E&C Engg., MIT VLSI LAB
Step 9:
To define the inputs, outputs, ground and supply, select clock or pulse, a visible node,
ground and vdd supply respectively from the palette and place it on the appropriate
places of layout. (Fig 10).
Adding the VDD polarization in the n-well region is a very strict rule.
It is possible to define the rise time, fall time, time high and time low for the input
clock.
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Dept. of E&C Engg., MIT VLSI LAB
Step: 8
Once the design is over we can simulate it by clicking on the run simulation. The
timing diagrams of the cMOS device appears, as shown in fig 11
Depending on the input sequences assigned at the input the output is observed in the
simulation. The power value is also given.
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Dept. of E&C Engg., MIT VLSI LAB
EXPERIMENT NO. 12
INTRODUCTION TO PIN LAYOUT OF XILINX SPARTAN 3 CHIP
XC3S400-TQ144
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