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- Intra-Symbol Piecewise Equalization for OFDM Systems in Fast
- OFDM Report
- Agilent RF Testing of WLAN Products
- Coherent Optical – OFDM using 64QAM to high data rates 1.60 Tb/s over 4500 km
- Channel Estimation
- Performance Analysis of Adaptive Multi User OFDM
- Optimised Multiplication Architectures for Accelerating Fully Homomorphic Encryption.pdf
- PERFORMANCE ANALSIS OF CLIPPING TECHNIQUE FOR PAPR REDUCTION OF MB-OFDM UWB SIGNALS
- Improving the Signal Quality of Multistream Data Transmission in 4G Services
- Automatic Generation of Prime Length FFT Programs -1996.pdf
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- Analog
- Orthogonal Frequency Division Multiplexing
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CHAPTER 1

INTRODUCTION

Table of Contents

Page No.

1.0 INTRODUCTION 2

1.3 High-energy 4

2

CHAPTER 1

INTRODUCTION

The Discrete Fourier Transform decomposes a set of values into different components

manipulation of DFT. The algorithm of FFT was devised by Cooley and Tukey in

order to decrease the amount of complexity with respect to time and computations.

The memory architecture comprises a single processing element and various units

of memory. The merits of memory architecture include low power and low cost when

compared to that of other styles. The specific demerits are greater latency and lower

throughput. The above demerits of the memory architecture are totally eliminated by

various types of pipeline architecture include Single delay feedback (SDF), Single

delay commutator (SDC) and Multiple delay commutator (MDC). The pipeline

language in an easy manner. In the recent years, the communication systems need to

transmit voice and video signals of high quality in an efficient manner. Hence there is

3

The algorithms of FFT can be grouped into fixed-radix, mixed-radix and split-

with the input and output in reverse sequence and normal sequence respectively,

while DIF deals with input and output in normal sequence and reverse sequence

consideration.

The DFT is a technique used periodically for applications of signal and image

processing. Generally DFTs are computed using Fast Fourier Transform which

includes a variety of algorithms for manipulation. The FFT finds application in wide

emerge, the performance also increases in a parallel manner. But the consumption of

unfortunate manner. This rise in power has an impact in the current scenario where

important applications of FFT are restricted by available power budgets. This increase

applications. In the last decade, the field of low power electronics has been paid

versions. There were two major advancements in low-power electronics with respect

to performance and size. The initial advancement was the evolution of CMOS that

4

manufactured components having the characteristics of high power levels and low

dissipation of energy. The second advancement was the huge increase in demand for

the portable components such as laptops and mobile phones. Due to low power

electronics, there is a need for low power and low power dissipation due to energy

These portable circuits are constructed using CMOS due to its high performance,

efficiency, density etc. Other technologies such as Bipolar CMOS and Gallium

Arsenide have better performance, but they have restrictions in voltage or current

design. Energy is a factor used to measure the cost per work completed and hence it is

The processing of data with high performance is an important criteria required for

required for both regular and signal processing processors with regard to lower

latency. Hence, this work highlights high performance at the compromise of latency.

algorithms of FFT. Generally the algorithms are evaluated based on the number of

multiplications and additions. This work points out that other factors such as

complexity and regularity are also needed for the successful implementation of a FFT

5

The implementations of simple form of designs include less number of efforts and

small errors when compared to regular form of designs. Hence these simple designs

reduce the marketing time and their design time can be employed for simulating the

key design parameters. The regular forms of designs are generally constructed by the

basic building blocks and they include smaller number of components. But these

designs enjoy majority of the benefits attained by that of simple designs. Orthogonal

number of subcarriers are employed to express the data. The data is decomposed into

various channels with one channel for each sub-carrier. Every sub-carrier is subjected

to a traditional method of modulation at a lower symbol rate with respect to the same

bandwidth.

generated by selection of certain factors such as spectrum, the input and the method of

modulation. Initially, every carrier is allotted some amount of data for transmission.

Then phase and amplitude of the carrier is manipulated using the traditional method

converted to its time domain signal. The IFFT does this transformation in an efficient

6

The Fast Fourier Transform (FFT) converts a time based signal into its

components. The time based signal spectrum is indicated by the phase and amplitude

of those components. Inverse Fast Fourier Transform (IFFT) does the reverse process,

thus converting the spectrum back to time signal. Every point of data present in the

Each and every bin is set to generate the carrier signals for OFDM using IFFT. The

reverse process maintains the orthogonality between the carriers because each bin is

nothing but a group of orthogonal sinusoids. Figure 1.1 shows the schematic diagram

with the frequency of transmission in order to generate the Radio frequency signal.

The block diagram of a complete OFDM system is given in Figure 1.2. The

7

Data in

demodulator using the algorithms of FFT and inverse FFT on the receiver side and the

sender side respectively. Though the merits of OFDM are known earlier in the last

Initially, the input data in serial format is converted into parallel format. Then the

data travels in this format and it is subjected to differential encoding with previous

symbols and then converted into format of phase shift keying by concatenating an

extra symbol at the start of transmission. The data is then mapped on each symbol

8

depending upon the type of modulation used. In general, 0, 90, 180, and 270 degrees

of phase angles are employed for PSK. The method of phase shift keying (PSK) is

selected for the purpose of transmission because it reduces the fluctuations due to

the corresponding waveform can be obtained by using IFFT. The guard interval is

of guard period is done to recover the timing of the symbol by means of envelope

inserted between them. Once the guard period is concatenated, the symbols are

converted into serial format which forms the base band signal for transmission.

The signal from the transmitter enters the channel mode where it is subjected to

many factors amounting to noise and attenuation. The signal to noise ratio is

The spread of delay can be simulated to obtain the delay spread of multipath by using

a finite impulse response filter. The filter length and coefficient of amplitude indicate

spectrum of the baseband signal is obtained by removing the guard period and taking

FFT for each symbol. The phase angle of all symbols are manipulated and

9

The frequencies of the sub-carriers are orthogonal to each other and eliminate the

requirement of guard bands and the crosstalk between the channels in OFDM. This

reduces the complexity at the transmitting and receiving ends by which a standalone

filter for every channel is avoided. The idea of orthogonality needs the spacing of sub-

F (Hz) with M number of carriers. The better spectral efficiency is obtained with a

symbol rate almost equal to Nyquist rate for the baseband signal.

OFDM needs both the receiver and the transmitter to be synchronized to avoid the

interference between the carriers. Generally the offsets in frequency are created by

Doppler shift due to mismatch between the oscillators of transmitter and receiver.

restricting the application of OFDM for high-speed vehicles. The traditional methods

used for suppression of inter carrier interference are not appropriate and they may

implementation of the modulator and demodulator using FFT and inverse FFT on the

The receivers can benefit from the signals received from various transmitters in a

simultaneous manner and thereby improve the area of coverage for broadcasting. This

becomes the basis for the functioning of single-frequency networks (SFN) where

various transmitters send the same signal in a simultaneous manner using the same

multi-frequency networks (MFN). The merits of SFN over MFN include large gain

10

and coverage area because of increase in signal strength at the receiver. Some OFDM

systems employ a guard interval of longer period to space the transmitters in order to

In a SFN, the distance covered by the signal during the guard interval is used to

determine the maximum distance between transmitters. For example, a guard period

systems can be integrated with MIMO channels and antenna arrays using the

There are two types with respect to FFT algorithm devised by Cooley and Tukey -

approach. The input sequence x(n) of size N is decomposed into samples of odd and

even and the corresponding sub-sequences f1(n) and f2(n) are given by -

f1 (n ) x (2n)

N (1.1)

f 2 (n) x (2 n 1), n 0,1,... 1

2

subsequences of data f1 (n) and f2 (n). This type of FFT algorithm is called

( N / 2 ) 1 ( N / 2 ) 1

X (k ) f 1 ( m )W Nk m/ 2 W Nk f 2 ( m )W Nk m/ 2

m 0 m 0

F1 ( k ) W Nk F 2 ( k ) , k 0 , 1, .... N 1

(1.2)

11

where F1 (k) and F2 (k) are the sequences of DFT of size N/2 for the respective

obtain the given DFT as a set of 2-point subsequences of DFT. The butterfly

element is shown in Figure 1.3 and the process of computation for an 8-point DFT

12

lengths in a recursive manner and their outputs are employed to manipulate several

other outputs by which the cost of computation will be reduced. It integrates every

sample of fourth output into a sequence of small-length DFTs to decrease the count

data is disintegrated into four small sequences of x (4n + i) where n = 0, 1, ..., N/4-1

and i = 0, 1, 2, 3.

3

lq

X ( p, q) [W N . F ( l , q )]W 4lp

l0

( N / 4 ) 1

F (l , q ) x ( l , m )W Nm/q4

m 0

N (1.3)

p 0,1, 2, 3; l 0,1, 2, 3; q 0,1, 2, .. 1

4

and

x ( l , m ) x ( 4 m 1)

N

x( p, q) x( p q)

4

The four sub-sequences of DFT, F (l, q) of N/4-point arrived from the equation

(1.3) are integrated to obtain the DFT of N-point. The butterfly element is shown in

Figure 1.5 (a) and its compact form for Radix-4 is shown in Figure 1.5 (b). This

multiplications.

13

This type of FFT algorithm is used to manipulate the Discrete Fourier Transform.

into one subsequence of length N/2 and two subsequences of length N/4. It employs

least count of arithmetic manipulations needed for the calculation of DFT. This

14

N 1

X k xn wNnk (1.4)

n0

2 i

where k ranges from 0 to N 1 and wN e N

. The equation (1.4) is used to

summation with respect to even indices and a summation with respect to odd indices

Xk x2n2wNn2/2k wNk

n 20

x4n4 wNn4/4k wN3k

n 40

x

n 40

4n 4 3wNn4/4k (1.5)

In the above equation, the summations correspond to the components of Radix -2 and

Radix-4 respectively. These summations are obtained in a recursive manner and then

integrated. The butterfly element for split radix is shown in Figure 1.6.

15

The various types of pipeline architectures used to adopt processors of FFT with

their corresponding requirements are compared and listed in Table 1.1. These pipeline

architectures have different merits and requirements of various styles. The multiple

delay commutators using Radix-2 FFT (R2MDC) and Radix-4 FFT (R4MDC) are

frequently used for pipeline implementations but their resources of hardware are not

memory. In the table, among the approaches available, the SDF architecture using

Radix-22 FFT (R2 2SDF) needs the least number of multipliers and storage capacity.

But least number of both adders and multipliers are required for R4SDC architecture.

Hence single delay commutators using Radix-4 is generally utilized for the design of

16

The thesis is organized into eight chapters including this chapter. The contents of

implementation of power and area efficient pipeline FFT processors for OFDM

In the Third Chapter of the thesis, the problem statement and the proposed solution,

scope and objectives of the research, contributions of the thesis, design and

In the Fourth Chapter of the thesis, the implementation of low power and area

efficient 128 point pipeline FFT processor using Radix 2 algorithm based on Single

In the Fifth Chapter of the thesis, the implementation of low power and area efficient

128 point pipeline FFT processor has been achieved using Mixed Radix 4/2 algorithm

In the Sixth Chapter of the thesis, a low power and area efficient 128 point pipeline

FFT processor using Cache-memory architecture (CMA) and Mixed radix 4/2

(MDC), Single Delay Feedback (SDF) and Single Delay Commutator (SDC) using

the Mixed Radix 4/2 algorithm has also been arrived for the efficient design of 128-

point FFT processor with respect to memory size, area and power.

In the Seventh Chapter of the thesis, the application of 128 point pipeline FFT

17

algorithm, Delay feedback and Data scheduling approaches has been discussed.

Finally, the Eighth Chapter contains the summary of our work, contributions made

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