1st

You copy your verilog file and syn rtl script...

Open script file using text edit mode...

And check your library path

Also require to change my files name with basename

And if you have require to change period, in delay, out delay than you
change these values
Which show in next slide

Note
Not change any other data....
Make new folder in home folder
And give your own name...
And copy your verilog file and tcl script file
Go to destop
And right click & open terminal window
And write down below command

Csh
Sourece cshc
Go to command window

And
Run below command

rc gui f syn-rtl.tcl
In command window, some process is going
....

After that you check, there is no error come..

And

Check your floder, many new files is come

like
Name_RTL,sdc
Name_RTL.V
Name_RTL_cell.rep
Name_RTL_power.rep
Name_RTL_timimng.rep
In synthesis part
You check many parameter like power budget, timing report etc
Which show in below slide....

below figure is circuit design using library

check is design
mapped ??
In same window, also possible to available your
code...
Go to report > datapath >area
Go to report > timing > worst path

Which shows worst path delay with component

And also possible to check your require data.

Up to you are doing synthesis part...

After completion of synthesis part, start encounter

You are require to write below command in command window

encounter -32

Start Encounter RTL-to-GDSII system tool

New window is come....

Go to

File > Import Design >.....

New pop up window is

come...
like as.
In this popup window,

You are require some details

like as

Verilog file
Lef files
Power nets
And

Analysis configuration...
For verilog file.....
You are require to selected counter_rtl.v file which are generate in
synthesis process.
Click on selected verilog file and add file to add in file list

And
Also require to selected .lef file, which are available in your
library(show in below figure)
Click on add button and this come in lef files list
After that,

Write power nets...

VDD!

And Ground nets

GND!

Next,
Require to make
MMMC file

Click on create
analysis
configuration....

New popup is
come
New MMMC browser come.....

In MMMC objects

Double click on Library sets....

New popup small window is come

Give name as

timemin
And click on add
and select .lib file which are available in your library (use
same path which use in selection of .lef file)

Select .lib file and add

After that click on apply button

Next
Change name timemin to timemax and click on apply

Click on ok button
Here two library sets is come
Next double click on RC Corner
And popup window is come

Write name as rccorner

Next double click on Delay Corners

Name as
rccornermin

Select on chip variation type

And select rc corner attributes as

rccorner

And early library set is timemin &

late library set is timemax

Click on apply

Next change name rccornermin

to rccornermax

Click on apply

Click on ok
Next double click on Constraint
Modes

Here you are require to select .sdc

file which are generate in synthesis
process

1st
Name as Setup
And click on add button

Select sdc file and add...

Click on apply button only

Next
Change name Setup to Hold

And
Click on apply

Click on ok
Here all list are come which you are
make...
Require to select Analysis view list...

Double click on Analysis View

Name SetupView
Selected
constraint mode :Setup
Delay coener : rccornermin

Click on apply
Change Name SetupView to
HoldView
Selected
constraint mode :Hold
Delay coener : rccornermax
Next require to setup analysis view

Double click on setup analysis view

And

Select view as show in below figure

And
Same for Hold analysis view
Click on save & close button
And give file name as couter.view

Next,
Click on save
And save file as name as
counter.globals

And click on ok
Press F on your keyboard for full
layout preview. Amoeba view Physical
Floor plan view view
Next

Go to Floor Plan > specify floor plan

New popup window come

Fill mark details..

Ratio(h/w) = 0.70
Core utilization = 0.6(approximate)

Core to left 30...

Same as show in figure.
Click o tab Advanced
button

And fill row spacing = 18 um

And

Click ok
Go to Power > power planning > add
ring

New popup window is come...

Click on add nets

And
Add vdd! And gnd!

Next

Fill ring configuration data as show in

figure
And
Click on center in channel

Next window is show in next slide

Go to Power > power planning > add
stripes

New popup window is come...

Click on add nets

And
Add vdd! And gnd!

Next

Fill some data as show in figure

And

Click on advanced tab

Click on advanced tab

And

Change snap wire to

routing grid - grid
Show as below figure
Go to Route > Special Route

New popup window is come.

Next go to add nets (same as add ring

step)

Click on ok
Go to Place > place standard cell

New popup window is come.

Click on Mode button.

Mark Medium button in Congestion Effort

point.

Click on ok

Click on ok

Main window is come as next side.

Show as below figure

Standard cell
Go to Optimize > Optimize Design

New popup window is come.

Mark on Pre-CTS button

Click on ok

Some time taken....

Go to main command window

Some result is come which are show in next

slide
WNS means worst case
negative slake
Go to Clock > Synthesize clock tree

New popup window is come

Click on Gen spec button and

Select invx1, invx16, invx2, invx4,

invx8
And
Add

Click on ok

Click on ok
Go to Optimize > Optimize Design

New popup window is come.

Mark on Post-CTS button

Click on ok

Some time taken....

Go to main command window

Some result is come which are show in next

slide
Go to Route > NanoRoute > Route

New popup window is come

Click on ok
In below figure, some routing is change
Go to Place > Physical Cell > add filler

New popup window is come

Click on cell name select button

New popup is come and select all cell

list & add

Click on close

Click on ok
Filler cells
Go to Optimize > Optimize Design

New popup window is come.

Mark on Post-Route button

Click on ok

Some time taken....

Go to main command window

Some result is come which are show in next

slide
Go to Verify > Verify Geometry

New popup window is come

Demark cell overlap button

Click on ok
In pin and out pin in your design

Select particular area

using mouse and click
on Zoom In Button to
show in/out pin.
Up to this level, you are make complete chip planning....

Next, you are require to save all this file.

Go to File > Save >

Many option is available in that
Like as

Floorplan
I/O file
Place
Netlist

DEF
PDEF
GDS/OASIS

etc..

Requirement of your, save that file in your specified.

Here only showing, how to save GDSII file.

And other all are same.
Go to File > Save > GDS/OASIS

Give output file name

Click on ok
For above all are explain in __________ book

If you have require than read this book.

And
Try to optimize and explore other things in that tool......

Thank You