CHAPTER 1

INTRODUCTION

1.1 Background of the study

The development of wireless sensor network provides a low cost alternative for manual

monitoring and traditional infrastructure monitoring. Infrastructure based monitoring requires

physical medium to transfer data and power. A Wireless sensor network is a network that is

composed of wireless nodes scattered across an area. The nodes are equipped with a sensor to

gather data from the environment. Compared to traditional monitoring, advantages of WSN

are low cost, ability to self-organize, scalability and ease of deployment [Shahzad, 2014].

Wireless sensor nodes communicates with the other parts wireless while their means of

energy is built-in i.e. battery or ambient energy harvester The wireless sensor node is

composed of a controller, memory block, RF transceiver, sensor and power supply which can

either be a battery or ambient energy harvester.

The limited energy budget of a node in a WSN requires the use of ultra-low power

modules and efficient power consumption in order to prolong the life of the node in a WSN.

The tradeoff of using ultra-low power consumption is the performance capability of the node.

Different modules of the node has different response to the limited power supply, i.e. the

computational power of the microcontroller is limited in frequency and chip memory, low

powered transceivers lack bandwidth to transfer the whole data collected to the network.

The flash memory is a combination of the best features of the ROM and RAM. It is

electrically programmable, fast reading time, exhibit high density, and is non-volatile. The

flash memory retains the data even when there is no power unlike ROM and data can be
written like the RAM. The speed of read/write access of the core to the program memory

which can cause unwanted results.

Flash memory IP are component blocks by different foundries and semiconductor

companies that include all the necessary support and control circuitry, including all high-

voltage generation and distribution required programming. The advantage of using Flash

memory IPs than building one from scratch is that Flash memory uses floating gate

technology that is not available in standard CMOS process since it requires additional masks

to create the second additional polysilicon for the floating gate.

TinyOS is an open-source operating system designed for low-power wireless devices,

such a sensor networks, smart buildings and smart meters. TinyOS provides useful software

abstractions of the underlying device, providing useful well-designed and heavily tested

software abstractions greatly simplifies the job of application and system developers. TinyOS

is especially useful for microcontroller-based devices that have sensors and/or networking

capabilities. It's been designed for very reasource-constrained devices, such as

microcontrollers with a few kB of RAM and a few tens of kB of code space. It's also been

designed for devices that need to be very low power.

Wireless Network architectures affect the memory size needed by the nodes. A simple

star network needs less complex code than a multihop wireless mesh network hence a lower

memory requirement and computation resulting to lower energy consumption, but it requires

more nodes to cover an area due to the limited coverage of the central hub.
1.2 Statement of the Problem
Wireless sensor nodes are being employed in variety of scenarios and this diversity

translates into different memory requirements. Commercially available WSN are comprised

general purpose microcontroller and flash memory, both of which are not optimized for low

power applications. The trade-off between computational power, communication, and power

consumption are the main challenges that designer face in designing in building wireless

sensor networks. Different Wireless sensor architecture such as single hop and multi hop

network sensors have different communication protocols and memory requirements.

Understanding this requirements will improve the optimization of flash memory to WSN for

low power applications. Additionally there is a need for optimizing flash memory to the

expected amount of program memory used by the node.

1.3 Objective of the Study

The objective of this study is to integrate a flash memory to the controller while

alleviating the main concern of the node which is the power consumption and adjust the

of the behavior memory such that it wont affect the overall performance of the whole

system of the node.

Also understanding the memory requirements of individual wireless sensor network

architectures and power management techniques to determine the flash memory footprint

and minimize power consumption of the memory.

1.4 Significance of the Study

 This study will develop an optimized flash memory as the program memory for the

microcontroller core openMSP430 which is used in WSN. Different flash memory algorithm

will be tested for this application. Different techniques for managing the flash memory is

studied and compared with one another will allow the researchers to select the suitable

technique for the application of openMSP430 as a core for a wireless sensor node.
The program that will be stored in the memory block is another factor that can help

manage power consumption of the sensor node. Scaling memory size and optimized

algorithms can help manage power consumption.

1.5 Scope & Limitations
This study is focused on the program memory of the openMSP430 core which will be

used as the microcontroller for the node. The researchers are limited to the availability of

different flash memory IP that the researches find suitable for this Wireless Sensor Networks

application. The optimization of algorithms requires different programs to compile and verify

functionality. The researchers are limited to the available program that can be acquired with

no problems.
1.6 Definition of Terms

Wireless Sensor Networks Are spatially distributed autonomous sensors to monitor physical

or environmental conditions, such as temperature, sound, pressure, etc. and to cooperatively

pass their data through the network to a main location.

Wireless Sensor Node is a node in a sensor network that is capable of performing some

processing, gathering sensory information and communicating with other nodes connected to

the network. It is composed of a microcontroller, power supply, sensor and a transceiver.

Microcontroller it is a small computer on a single integrated circuit. In modern terminology,

it is a System on a chip or SoC. A microcontroller contains one or more CPUs (processor

cores) along with memory and programmable input/output peripherals.

Non-volatile memory a type of computer memory that can retrieve stored information even

after having been power cycled (turned off and on).

Verilog it is a hardware description language (HDL) used to model electronic systems. It is

most commonly used in the design and verification of digital circuits at the register-transfer

level of abstraction. It is also used in the verification of analog circuits and mixed-signal

circuits, as well as in the design of genetic circuits.

Single-hop a type of communications between nodes in a wireless sensor network. The node

communicates directly to the sink.

Multi-hop a type of communications between nodes in a wireless sensor network. The

sensor node passes the information to the neighboring node instead of directly connecting to

the sink.

Flash memory it is an electronic non-volatile memory storage medium that can be

electrically erased and can be re written.

1.7 Theoretical framework

The following sections explain the theories and principles behind the operations and

methodology utilized entirely in this study.

1.7.1 RTL Flash memory

The RTL codes for flash memory is available on the internet from different semiconductor

companies. Each company provides unique flash memory solution to different

microcontroller application. Comparing different Flash memory IP and determine which is

suitable for the application. Using ASIC design flow to implement the flash memory in to the

microcontroller core openMSP430.

 Figure 1.7.1.1 openMSP430 core
The flash memory cell in CMOS design uses the idea of floating gate. The floating gate is an

extra layer added to the gate node of the transistor. Data logic is based on the trapped

electrons/hole in the gate which can be considered as logic 1 or logic 0. The method of

injecting electrons in the gate is by the Fowler-Nordheim tunneling or through hot carrier

injection/hot hole injection.

1.7.2 ASIC DESIGN FLOW METHODOLOGY

The ASIC design flow breaks
Figure down theGate
2 Floating entire
Crosschip functionality
sectional view down to small pieces with

clear understanding about the block implementation. The ASIC design flow provides a

general method designing ASIC chips. Figure 1.7.2.1 shows the block diagram of the ASIC

design flow. Using the design flow in order to generate the custom IC ready for fabrication.

Using the tools that is easily accessible to the researchers.

 Figure 3.7.2.1 ASIC Design Flow

1.7.3 OTHER TOOLS

1.7.3.1 SYNOPSYS PRIMETIME
Primetime is a tools that can be used to analyze timing, signal integrity, power and

variation-aware analysis. PrimetimePX is a tool that is used to analyze static and

dynamic power. Dynamic power is dissipated any time the voltage on a net changes

due to some stimulus. The dynamic power consumed by the charging and discharging

of the output load external to the shell is classified as switching power, while the

dynamic power is dissipated within the cell is generally classified as the internal

power.
The static power is dissipated in several ways. Some are due to the reverse-biased

diode leakage from the diffusion layers and the substrate, but the largest percentage of

static power results from source-to-drain sub-threshold leakage current. This is caused

by reduced threshold voltage which prevent the gate from completely turning off and

allow leakage current. Switching power is determined by the capacitive load and the

frequency of the logic transitions on a cell output. Internal power is caused by the

charging of internal loads as well as by the short-circuit between the N and P

transistor of a gate when both are on.

 Chapter 2

REVIEW OF RELATED LITERATURE

An important parameter of a wireless sensor network is its energy requirement and

computing capabilities. In particular, WSNs are characterized by limited power storage, with

possible mitigation coming from power harvesting techniques. Many communication

protocols are designed for low power WSNs. This chapter presents studies that deals with the

energy management of wireless sensor networks.

WSN COMMUNICATION PROTOCOLS

2.1 AN ENERGY-EFFICIENT ANT-BASED ROUTING ALGORITHM FOR

WIRELESS SENSOR NETWORKS

Ant based routing protocols can add a significant contribution to assist in the

maximization of the network life-time, but this is only possible by means of an adaptable and

balanced algorithm that takes into account the Wireless Sensor Networks main restrictions.

The routing protocol is based on the Ant Colony Optimization meta heuristic. The protocol

was studied by simulation for several Wireless Sensor Network scenarios and the results

clearly show that it minimizes communication load and memory requirements and

maximizes energy savings.

 The paper proposes an improved Ant based routing for WSNs. The basic algorithm

sends the ant to no specific destination node, the sensor nodes should communicate with each

other and routing tables of each node must contain identification of all sensor nodes in the

network. In a larger systems, this can cause a problem since it would require big amounts of

memory to save all information to the other sensor nodes. The paper suggests that the

forward ants should be sent directly to the sink node. The routing table contents will only

save the neighbor nodes that are in the direction of the sink node. This reduces the size of

routing table, and decreases the memory needed by the nodes. Another suggestion made by

this paper is the energy efficient ant-based routing algorithm. According to the paper, tasks

performed by nodes spend much more energy to communicating with other nodes compared

to data processing and management.

The routing algorithm is required to perform as much processing possible rather than

sending them all to the sink and process there. This suggestion would save energy and helps

maximize lifetime of the nodes.

Figure 2.1.1 Performance in sensor network with different initial energy levels

The figure shown above shows the result of the paper. The graph on the left shows the

IABR (improved ant based routing) while the other one shows the EEABR (energy efficient

ant based routing). Both algorithms were energy aware but the difference between two shows
the EEABR performance is better since it significantly reduces the energy consumed in

communications.

2.2 Energy Efficient Routing Algorithms for Application to Agro-Food Wireless

Sensor Networks

Wireless Sensor Nodes have been used in precision agriculture to manage agro food

production. Dynamic flooding algorithm which is aware of the status of neighboring nodes

improves the network lifetime of the most solicited nodes without increasing complexity and

the core of the wireless sensor node is the processing unit, usually a microprocessor with a

limited amount of memory Specific nodes may integrate a location finding system that helps

the node to discover its position, relative to its neighbors or global. This unit is often

embedded on the transceiver module and requires the use of specific algorithms by the

processing unit. The routing schemes studied in this paper is the flooding and gossiping

protocols.

The flooding protocol broadcasts the packets to its neighboring nodes limited by the

number of hops. This technique is reactive and does not require costly topology maintenance.

However this technique has drawbacks such as implosion, resource blindness and

overlapping messages. The gossiping is a derivation of the previous protocol. The protocol

doesnt broadcast the packet but instead it selects random neighbor and send a single copy of

the message. The drawback in this is that it takes longer time to reach the destination.

Another approach is the direct diffusion, the sink sends out a description of the task called
interests to the network. If a source has the data, it traces back the path taken by the interest

in order to reach the sink. This method greatly reduces delivery latency.

The paper suggests to use gossiping and direct diffusion creating a hybrid protocol

based on the two suggested protocols. The process is described as that each idle node sense

the medium looking at the packets header which contains the information field: source ID,

coordinates, and available energy. Available energy is the tag used if it still able to transmit

and process packets. After reading the header, the nodes are able to select the next best hop

and update its routing table.

The paper simulates the worst case scenario where the traffic rate is constant bit rate

data flow with rate equal to one packet per slot and link capacity of exactly one pocket slot.

The simulation WSN is composed of 36 nodes, among which 35 of them are ordinary and 1

is the gateway. The results is shown on figure 2.2.1.

Figure 2.2.1.A
 Figure 2.2.1.B
Figure 2.2.1 power comparison [A] and throughput consumption [B]

2.3 Energetic sustainability of routing algorithms for energy-harvesting wireless

sensor networks

A new class of wireless sensor networks that harvest power from the environment is

emerging because of its intrinsic capability of providing unbounded lifetime. Many research

focuses on energy-aware routing schemes with battery operated networks. The objective of

this paper is to explore the routing schemes possible with energy harvesting wireless sensor

networks (EH-WSNs). Instead of extending network lifetime, the study aims to maximize the

workload that can be autonomously sustained by the network.

The paper states that most of the studies relating to wireless sensor networks aims at

prolonging battery life which is energy efficient algorithms were fabricated. On the other

hand energy harvesting WSNs are power constrained. The work introduces a new

methodology for assessing energetic sustainability of routing algorithms. The paper defines

new parameters, maximum energetically sustainable workload (MESW) of a given EH-WSN

(Net) with a given routing algorithm (rAlg) under given environmental power constraint

(Pmap) denoted with MESW (Net, rAlg, Pmap).

The model of their EH-WSN is a multihop WSN composed of sensor, routers and

base stations. The power model of the EH-WSN is modeled with packet energy and available
power. The packet energy is the energy spent by each nodes to process a packet and available

power refers to the environmental power available at each node to sustain the packet

processing. The network model of the EH-WSN is denoted with G = (V,E), associating

vertices ( v V with nodes and edges ( e E for the wireless link that connects

them. Single vertices are annotated with its available power Pv while each edges is annotated

with its Packet energy, pEe. The linking of edges with packet energy takes the distance-

dependence of transmission energy into account.

The workload model is classified into two sensor functionality. The monitoring and

event detection functions. The monitoring monitors periodic sampling of some physical

quantities while event detect reacts to special events. The paper focuses on the delivery of

data from the monitoring function. The delivery process called continuous delivery.

Energetic sustainability of the EH-WSN is entirely dependent on the power harvested

from the environment. According to the study, the energy sustained by a node cannot be

incremented without violating the energetic sustainability of other nodes. The paper then

proceeds to describe recovery time, channel capacity and flow networks. Recovery time is the

amount of time required by the energy scavenger to provide packet energy, channel capacity

is the maximum packet rate across an edge and flow network is a network annotated with

channel capacities. Node-constrained flow networks is a general class of flow network. The

flow across any edge e exiting from node n is limited by the maximum capacity and the

overall power budget of the node. The researchers of this study designed a methodology

integrating their specified variables into the program. MESW OPT is optimal energy

sustainable workload and is defined by the function G(V,E) Pn Ee. These variables are then
described furthermore in the proper paper The process flow of their methodology can be seen

on figure 2.3.1.

Figure 2.3.1 Tool flow

The Pmap is the power distribution map and OMNeT++ is the network simulator. The

paper outlines the mapping of the EH-WSN models into an executable specification for the

simulator and describes the implementation of the MESW algorithm. The routing algorithms

used for simulation is the minimum path (MP), Randomized weighted minimum path,

randomized minimum path energy, randomized minimum path recovery time, randomized

maxflow. The result is shown on figure 2.3.2. The paper presents different power maps but
will only show one for reference purposes. The results provided by the deterministic MP are

much worse compared to all other randomized algorithms. The accounting of environmental

power levels is shown on the R-MPRT and R-MPE. The optimal results of R-MF uses a

routing table constructed offline.

Figure2.3.1 routing algorithms applied to the EH-WSN

The study developed a tool that uses network simulation and graph algorithms with a

goal in mind of maximizing sustainable workload by using routing strategies applied to a

WSN with energy harvesting capabilities. Routing algorithms that do not account

environmental power distribution is found to provide poor results in terms of work

sustainability. The environmental power distribution has a strong impact on the routing

optimization.
 WSN POWER MANAGEMENT PROTOCOLS

2.4 HYBRID AUTONOMOUS TRANSCEIVERS

In recent year there has been a big effort in finding alternative solution to power such

nodes using the energy available on the node environment with good results. In a paper

entitled HYBRID AUTONOMOUS TRANSCEIVERS describes the methodology in

harvesting ambient power source solution that combines a PV cell and a piezoelectric

vibration energy harvester. A small photocell and a non-linear vibration energy harvester

have been used to power a low power wireless transceiver device. The device, a technology

demonstrator, is self-powered and works without any battery on board.

The power management regulates and manage energy coming from the generators. It

also has to find a way to store energy to be used when needed. The power management block

is composed of a voltage regulator or power conditioning, and by a voltage supervisor, power

supervisor. The RF transceiver uses a simple peer to peer protocol for transmission, peer to

peer protocol is simpler compared to ZigBee having a lower computational cost;

WSN MEMORY REQUIREMENTS

2.6 Memory Required for Wireless Sensor Nodes on the Basis of Characteristics and

Behavior when using TinyOS

The memory requirements of wireless sensor networks then depend on its

communication and power management protocols. Currently, Flash memories are used, they

have low cost and better storage capacity. Memory requirements are based on applications

used for sensor nodes. There are two categories of memory based on the purpose of storage

are: user memory used for storing application related or personal effective data, and program
memory used for programming the device. Program memory also contains identification data

of the device if it present in that location. A list of memory requirement is listed of common

sensor node name and EPIC mote base on MSP430 has an external memory of 48K Flash

using Tiny OS.

CHAPTER 3
METHODOLOGY

The procedure and methods of the proposed design to meet the targeted performance
will be presented in this chapter. The design methodology is briefly explained, and the design
is implemented on the Synopsys tool.

Start

Memory
Requirement
per WSNA &

Flash
RTL
No

Verilog Desired
Compiler output
Simulatio met?
n
Yes

DC &
ICC

Compare
Yes
No Output Power
met using Consumptio
UVM/ n to other
Primetime?
 Implementat

End

Figure 3.1 DESIGN FLOW

Figure 3.1 illustrates the flow of the study. An exhaustive study on related resources

will guide the researchers during the designing process. With sufficient information acquired

in these resources, researchers will proceed in designing and RTL coding. A simulation using

Synopsys tool will be used to check if the desired output are met and test benched using

Standard Universal Verification Methodology. Flash memory requirements for different

wireless network architectures and power management techniques have different flash

memory requirements. The power consumption of the nodes using the least amount of flash

memory cells will be compared.

MODELING FLASH MEMORY IN VERILOG

With the use of DesignWare library, and other free Verilog models of flash memory

from Free Model Foundry the Verilog codes can be instantiated directly to the MSP430

module. The model is compiled using Synopsys Verilog Compiler Simulator (VCS) and view

the generated waveforms.

Technology Optimization

Technology optimization takes a technology-independent description of a design, and

maps it to a library of logic circuits provided by an ASIC vendor, thereby making the design
technology-dependent. This phase seeks not just a correct mapping, but the most efcient one

in terms of the customer requirements. The optimization process is divided into subprocesses:

logic synthesis; and oorplanning; clock planning and insertion

LOGIC SYNTHESIS
Logic synthesis is the basic step that transforms the HDL representation of a design

into technology-specic logic circuits. An ASIC vendor provides the logic circuits in a form

called a synthesis library. As the synthesis tool breaks down high-level HDL statements

into more primitive functions, it searches this library to nd a match between the functions

required and those provided in the library. When a match is found, the synthesis tool copies

the function into the design (instantiates the circuit) and gives it a unique name (cell instance

name). This process continues until all statements are broken down and mapped

(synthesized) to logic circuits. There are potentially hundreds, or even thousands, of different

combinations of logic circuits that can implement the same logical function. The combination

chosen by a synthesis tool is determined by the synthesis constraints provided by the

designer. These constraints dene the designs performance, power, and area targets. A design

driven primarily by performance criteria may use larger, faster circuits than one driven to

minimize area or power consumption. The Model will be synthesized to hardware using

Synopsys Design Compiler. The gate level netlist output will generate area and timing report

of the system.

FLOOR & POWER PLANNING

Floor plan determines the size of the design cell (or die), creates the boundary and

core area, and creates wire tracks for placement of standard cells.
Power planning is a step in which power grid network is created to distribute power to each

part of the design equally.

CLOCK TREE SYNTHESIS

Is the process of insertion of buffers or inverters along the clock paths of ASIC design

in order to achieve zero/minimum skew or balanced skew. The goal of CTS is to minimize

skew and insertion delay. Apart from these, useful skew is also added in the design by means

of buffers and inverters.

ROUTING

After CTS, the routing process determines the precise paths for interconnections. This

includes the standard cell and macro pins, the pins on the block boundary or pads at the chip

boundary. After placement and CTS, the tool has information about the exact locations of

blocks, pins of blocks, and I/O pads at chip boundaries. The logical connectivity as defined

by the netlist is also available to the tool. In routing stage, metal and vias are used to create

the electrical connection in layout so as to complete all connections defined by the netlist.

VERIFICATION

After routing, the verification process checks that the ic follows the design rules. The

total chip area, timing and power is reported. The design will be test benched using the

Standard Universal Verification Methodology which automates the test bench process.
PRIMETIME

Primetime analysis is another tool that is used to analyze 90 nm technologies or

below because the Power, timing and signal integrity effects are all interdependent. Since this

flash memory will be applied in 65nm technology, the use of primetime is highly encouraged.

In order to achieve the highest accuracy power analysis, a timing engine is required to

perform accurate timing and slew calculations. Since timing parameters affect power

dissipation, the designers require a solution that takes advantage of these interdependencies.

Power analysis of a design when using PrimeTime PX requires that the designer consider the

Netlist data, cell library power models, signal activity, net parasitics / transition times.
References

[1] Camilo, Tiago, et al. An energy-efficient ant-based routing algorithm for

wireless sensor networks. Ant Colony Optimization and Swarm
Intelligence (2006): 49-59.

[2] Khurram Shahzad. Energy Efficient Wireless Sensor Node Architecture for Data and
Computation Intensive Applications Mid Sweden University, 2014

[3] Chiti, Francesco, et al. Energy efficient routing algorithms for application
to agro-food wireless sensor networks. Communications, 2005. ICC 2005.
2005 IEEE International Conference on. Vol. 5. IEEE, 2005.

[4] Lattanzi, Regini, et..al Energetic Sustainability of routing algorithms for

energy-harvesting wireless sensor networksInternation Journal of
Distributed Sensor Networks (2012)

[5] Orfei, F. et al. HYBRID AUTONOMOUS TRANSCEIVERS,

EDERC2012: 5th European DSP Education and Research Conference,
13/09/2012, Amsterdam, (2012)

[6] Texas Instruments, SimpliciTI Compliant Protocol Stack. 2009207210.

http://www.ti.com/tool/simpliciti Consulted December 2012.

[7] Memory Required for Wireless Sensor Nodes on the Basis of Characteristics
and Behaviour when using TinyOS

[8] KK Gautam, NK Gautam, PC Agrawal - Citeseer