A B C D E

1 1

QIQY6
2

Brandy3.0 (Y500) 2

LA-8692P Rev0.2 Schematic

3
Intel IVY Bridge Processor with DDRIII + Panther Point PCH 3

nVIDIA N13P GT-1 + 2nd VGA N13P GT-1

2012-02-05 Rev0.2

4 4

Security Classification LC Future Center Secret Data Title

Cover Page
Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-8692P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Tuesday, June 05, 2012 Sheet 1 of 66
A B C D E
 A B C D E

Chief River
PCI-Express 16X Gen3 Intel
PEG 8~15 PEG 0~7 IVY Bridge Memory BUS (DDRIII)
Processor Dual Channel DDR3-SO-DIMM X2
2nd VGA N13P-GT1 N13P-GT1 BANK 0, 1, 2, 3
1 1
Socket-rPGA989 1.5V DDRIII 1066/1333/1600 MT/s
VRAM 64*32 VRAM 64*32 UP TO 16G
37.5mm*37.5mm
GDDR5*8 GDDR5*8
Sub/B (SLI) Page 32 Page 23,24,25,26,27,28,29,30,31

FDI *8 DMI *4
2.7GT/s 5GT/s
USB 2.0 1x USB Left
5V 480MHz USB 3.0 Port 2 TV
USB 2.0 Port 12
HDMI Conn. CRT Conn. LVDS Conn. USB 2.0 3x USB 3.0 Port 3
Page 38
USB Charger
Page 37 Page 36 Page 34 5V 480MHz Page 48 PS8710BT
HDMI1.4b Intel USB 3.0 3x Int. Camera
Page 50
BT
2 Panther Point 5V 5GT/s USB 3.0 Port 0
USB 2.0 Port 0
Page 50
USB 2.0 Port 13
Page 47
2

PCH
Atheros USB Right
FCBGA 989 Balls USB 2.0 2x
PCIe Gen1 1x PCIeMini Card mSATA SSD USB 2.0 Port 9, Cha
RJ45 Conn. AR8161 1G 1.5V 5GT/s
5V 480MHz
WLAN SATA Port 0
Page 40
AR8151 1G 25mm*25mm PCIe Port 2 page 38 Sub/B Page 50
PCIe Gen1 2x page 38
PCIe port 1 Page 39 5V 480MHz PCIeMini Card
PCIeMini Card
TV PCIe Port 3
SATA Gen3 Port 0 WLAN
USB Port 10 USB Port 12
5V 6GHz(600MB/s) page 38 page 38
CardReader
PCIe Gen1 1x
JMB389 1.5V 5GT/s
SD/MMC/MS/XD
PCIe port 4 Page 44 SATA Gen3 Port 1 SATA HDD
5V 6GHz(600MB/s) SATA Port 1
page 41

3 SPI ROM SPI BUS SATA Gen1 Port2 SATA ODD

3

(4MB+2MB) 3.3V 33MHz 5V 3GHz(300MB/s) SATA Port 1

page 41
Page 14

HD Audio
LPC BUS
3.3V 33MHz
3.3V 24MHz

EC Codec
SPK Conn.
ITE IT8580E ALC269Q-VC3 Page 43
Page 43
Page 45

Power Circuit DC/DC

Page 54,55,56,57,58,59,
60,61,62,63,64
Thermal Sensor Int. MIC Conn.
Touch Pad Int.KBD Ext. MIC Conn. HP Conn.
DC/DC Interface CKT. RTC CKT. (JCMOS Conn.)
4

Page 53 Page 54
EMC 1403 Page 50 Page 49 Page 49
4

Page 46 Page 46 Page 41 Sub/B Sub/B

POWER/B Conn. AUDIO, USB/B Conn.

Page 51 Page 49 Security Classification LC Future Center Secret Data Title
MB Block Diagram
Issued Date 2012/07/01 Deciphered Date 2014/07/01

ODD/B Conn. NOVO/B Conn. THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
page 42 Page 51 DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-8692P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Tuesday, June 05, 2012 Sheet 2 of 66
A B C D E
 A B C D E

Voltage Rails
SIGNAL
+5VS STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
+3VS
Full ON HIGH HIGH HIGH HIGH ON ON ON ON
+1.5VS
power +VCCSA S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
plane +V1.5S_VCCP
S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
1
+CPU_CORE 1
+5VALW +1.5V
+VGA_CORE S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
+B
+GFX_CORE
+3VALW S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+1.8VS
+1.05VS
State
+0.75VS
+3.3VS_VGA
+1.5VS_VGA
+1.05VS_VGA

S0
O O O O

S3
O O O X
2 2
S5 S4/AC
O O X X USB Port Table
4 External BOM Structure Table
S5 S4/ Battery only USB 2.0 USB 3.0 Port
O X X X USB Port BOM Structure BTO Item
0 Camera HDMI@ HDMI part
S5 S4/AC & Battery
don't exist X X X X 1 Camera
TV@ TV module part
XHCI 1
2 CMOS@ CMOS Camera part

SMBUS Control Table EHCI1 3

2 USB Port (Left Side)
USB Port (Left Side)
8161@ AR8161 LAN part
8151@ AR8151 LAN part
Main 2nd WLAN
Thermal 3 USB Port (Left Side)
SOURCE VGA VGA BATT IT8580E SODIMM WWAN Sensor PCH 4 USB Port (Left Side) 8161S@ AR8161 LAN surge part
4 8151S@ AR8151 LAN surge part
SMB_EC_CK1
SMB_EC_DA1
IT8580E
+3VALW
X X V
+3VALW
X X X X X 5
6
SURGE@
X76@
AR8151&8161 LAN surge part
X76 Level part for VRAM
SMB_EC_CK2
SMB_EC_DA2
IT8580E X
+3VALW
X X X X X X V
+3VS
7
8
GC6@
NOGC6@
NV CG6 support part
NV no CG6 support part
EHCI2

3
SMBCLK
SMBDATA
PCH
+3VALW
X X X X V
+3VS
V
+3VS
X X 9
10
USB Port (Right Side)
Mini Card(WLAN)
AOAC@
KBL@
AOAC support part
K/B Light part 3

SML0CLK
SML0DATA
PCH
+3VALW
X X X X X X X X 11
12 Mini Card(TV)
ME@
OPT@
ME part
For optimus function part
SML1CLK
SML1DATA
PCH V
+3VALW +3VS
V
+3VS
X V
+3VS
X X V
+3VS
X 13 Blue Tooth SLI@
DS3@
For SLI function part
Deep S3 support part
PCIE PORT LIST GT@ NV chip part
Address Port Device @ Unpop
EC SM Bus1 address EC SM Bus2 address
1 LAN
Device Device Address
2 WLAN
Smart Battery 0001 011X b Thermal Sensor EMC1403-2 1001_101xb
3 TV
Master VGA 0x9E
Slave VGA 0x9C
4 Card Reader
5
PCH SM Bus address 6
7
Device Address
8
DDR DIMM0 1001 000Xb
4 DDR DIMM2 4
1001 010Xb

ZZZ

Security Classification LC Future Center Secret Data Title

Notes List
Issued Date 2012/07/01 Deciphered Date 2014/07/01
DA80000T20J THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-8692P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Tuesday, June 05, 2012 Sheet 3 of 66
A B C D E
 5 4 3 2 1

Hot plug detect for IFP link E

Performance Mode P0 TDP at Tj = 102 C* (GDDR5)
FBVDDQ PCI Express I/O and I/O and Other
VGA and GDDR5 Voltage Rails (N13Px GPIO) GPU Mem NVCLK FBVDD (GPU+Mem) (1.05V) PLLVDD PLLVDD
(4) (1,5) /MCLK NVVDD (1.35V) (1.35V) (6) (1.8V) (1.05V) (3.3V)
GPIO I/O ACTIVE Function Description Products (W) (W) (MHz) (V) (A) (W) (A) (W) (A) (W) (mA) (W) (mA) (W) (mA) (W) (mA) (W)

GPIO0 OUT - GPU VID4 N13X

128bit TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
D
1GB D
GPIO1 OUT - GPU VID3 GDDR5

GPIO2 OUT - VGA_BL_PWM Physical Logical Logical Logical Logical

Strapping pin Power Rail Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
GPIO3 OUT - VGA_ENVDD ROM_SCLK +3VS_VGA PCI_DEVID[4] SUB_VENDOR SLOT_CLK_CFG PEX_PLL_EN_TERM
GPIO4 OUT - VGA_ENBKL ROM_SI +3VS_VGA RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0]
ROM_SO +3VS_VGA FB[1] FB[0] SMB_ALT_ADDR VGA_DEVICE
GPIO5 OUT - GPU VID1
STRAP0 +3VS_VGA USER[3] USER[2] USER[1] USER[0]
GPIO6 OUT - GPU VID2 STRAP1 +3VS_VGA 3GIO_PAD_CFG_ADR[3] 3GIO_PAD_CFG_ADR[2] 3GIO_PAD_CFG_ADR[1] 3GIO_PAD_CFG_ADR[0]
STRAP2 +3VS_VGA PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]
GPIO7 OUT - DPRSLPVR_VGA
STRAP3 +3VS_VGA SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED
GPIO8 I/O - Thermal Catastrophic Over Temperature STRAP4 +3VS_VGA RESERVED PCIE_SPEED_ PCIE_MAX_SPEED DP_PLL_VDD33V
CHANGE_GEN3
GPIO9 OUT - GPIO9
Device ID setting I2C Slave addrees ID
GPIO10 OUT - Memory VREF Control N13P-GT SMB_ALT_ADDR
(28nm) 0x0FDB 0 0x9E
(ROM_SO Bit 1)
GPIO11 OUT - GPU VID0
C C
1 0x9C
GPIO12 IN AC Power Detect Input (10K pull High)

GPIO13 OUT - GPU VID5

GPIO14 OUT - FB_CLAMP_TOGGLE_REQ#

GPU ROM_SO ROM_SCLK STRAP0 STRAP1 STRAP2 STRAP3 STRAP4
GPIO15 IN N/A (100K pull low) PU 25K PU 5K
GC6@ SLI@
GPIO16 OUT - GPIO16 N13P-GT1
28nm PU 10K PU 45K PD 5K PD 10K PD 45K
PU 5K PD 5K
GPIO17 IN N/A GPIO17 OPT@
OPT@,SLI@
GPIO18 IN - dGPU_HDMI_HPD

GPIO19 IN - GPIO19
GPU N13P-GT

FB Memory (GDDR5) ROM_SI

Samsung K4G10325FD-FC04
B
+3VS_VGA 2500MHz B

32Mx32 PD 45K
+VGA_CORE
Hynix H5GQ1H24BFR-T2C
tNVVDD >0 2500MHz
+1.5VS_VGA 32Mx32 PD 35K
tFBVDDQ >0
Samsung K4G20325FD-FC04
+1.05VS_VGA 2500MHz
tPEX_VDD >0 64Mx32 PD 30K

1. all power rail ramp up time should be larger than 40us

Hynix H5GQ2H24AFR-T2C
2500MHz
64Mx32 PD 25K

Other Power rail

+3VS_VGA
A A

Tpower-off <10ms

Security Classification LC Future Center Secret Data Title

VGA Notes List
1.all GPU power rails should be turned off within 10ms
Issued Date 2012/07/01 Deciphered Date 2014/07/01
2. Optimus system VDD33 avoids drop down earlier than NVDD and FBVDDQ
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
LA-8692P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Thursday, June 07, 2012 Sheet 4 of 66
5 4 3 2 1
 5 4 3 2 1

D D
PEG_ICOMPI and RCOMPO signals should be
shorted and routed
with - max length = 500 mils - typical
+1.05VS impedance = 43 mohms
PEG_ICOMPO signals should be routed with -

1
max length = 500 mils
R1
24.9_0402_1%
- typical impedance = 14.5 mohms
JCPU1A

2
J22 PEG_COMP
PEG_ICOMPI J21
B27 PEG_ICOMPO H22
<16> DMI_CRX_PTX_N0 DMI_RX#[0] PEG_RCOMPO
B25
<16> DMI_CRX_PTX_N1 DMI_RX#[1]
A25
<16> DMI_CRX_PTX_N2 DMI_RX#[2] PCIE_CRX_GTX_N[0..15] <23,32>
B24 K33 PCIE_CRX_GTX_N0
<16> DMI_CRX_PTX_N3 DMI_RX#[3] PEG_RX#[0] M35 PCIE_CRX_GTX_N1
B28 PEG_RX#[1] L34 PCIE_CRX_GTX_N2
<16> DMI_CRX_PTX_P0 DMI_RX[0] PEG_RX#[2]
B26 J35 PCIE_CRX_GTX_N3 PEG Static Lane Reversal - CFG2 is for the 16x
<16> DMI_CRX_PTX_P1 DMI_RX[1] PEG_RX#[3]
A24 J32 PCIE_CRX_GTX_N4
<16> DMI_CRX_PTX_P2

DMI
B23 DMI_RX[2] PEG_RX#[4] H34 PCIE_CRX_GTX_N5
<16> DMI_CRX_PTX_P3 DMI_RX[3] PEG_RX#[5] H31 PCIE_CRX_GTX_N6 1: Normal Operation; Lane # definition matches
G21 PEG_RX#[6] G33 PCIE_CRX_GTX_N7
<16> DMI_CTX_PRX_N0 DMI_TX#[0] PEG_RX#[7] CFG2 socket pin map definition
E22 G30 PCIE_CRX_GTX_N8
<16> DMI_CTX_PRX_N1 F21 DMI_TX#[1] PEG_RX#[8] F35 PCIE_CRX_GTX_N9
<16> DMI_CTX_PRX_N2 D21 DMI_TX#[2] PEG_RX#[9] E34 PCIE_CRX_GTX_N10 0:Lane Reversed
<16>

<16>
DMI_CTX_PRX_N3

DMI_CTX_PRX_P0
G22
D22
DMI_TX#[3]

DMI_TX[0]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
E32
D33
D31
PCIE_CRX_GTX_N11
PCIE_CRX_GTX_N12 *
PCIE_CRX_GTX_N13
C <16> DMI_CTX_PRX_P1 F20 DMI_TX[1] PEG_RX#[13] B33 PCIE_CRX_GTX_N14 C
<16> DMI_CTX_PRX_P2 DMI_TX[2] PEG_RX#[14]

PCI EXPRESS* - GRAPHICS

C21 C32 PCIE_CRX_GTX_N15
<16> DMI_CTX_PRX_P3 DMI_TX[3] PEG_RX#[15]
PCIE_CRX_GTX_P[0..15] <23,32>
J33 PCIE_CRX_GTX_P0
PEG_RX[0] L35 PCIE_CRX_GTX_P1
PEG_RX[1] K34 PCIE_CRX_GTX_P2
A21 PEG_RX[2] H35 PCIE_CRX_GTX_P3
<16> FDI_CTX_PRX_N0 H19 FDI0_TX#[0] PEG_RX[3] H32 PCIE_CRX_GTX_P4
<16> FDI_CTX_PRX_N1 E19 FDI0_TX#[1] PEG_RX[4] G34 PCIE_CRX_GTX_P5
<16> FDI_CTX_PRX_N2 F18 FDI0_TX#[2] PEG_RX[5] G31 PCIE_CRX_GTX_P6
<16> FDI_CTX_PRX_N3 B21 FDI0_TX#[3] PEG_RX[6] F33

Intel(R) FDI
PCIE_CRX_GTX_P7
<16> FDI_CTX_PRX_N4 C20 FDI1_TX#[0] PEG_RX[7] F30 PCIE_CRX_GTX_P8
<16> FDI_CTX_PRX_N5 D18 FDI1_TX#[1] PEG_RX[8] E35 PCIE_CRX_GTX_P9
<16> FDI_CTX_PRX_N6 E17 FDI1_TX#[2] PEG_RX[9] E33 PCIE_CRX_GTX_P10
<16> FDI_CTX_PRX_N7 FDI1_TX#[3] PEG_RX[10] F32 PCIE_CRX_GTX_P11
PEG_RX[11] D34 PCIE_CRX_GTX_P12
A22 PEG_RX[12] E31 PCIE_CRX_GTX_P13
<16> FDI_CTX_PRX_P0 G19 FDI0_TX[0] PEG_RX[13] C33 PCIE_CRX_GTX_P14
<16> FDI_CTX_PRX_P1 E20 FDI0_TX[1] PEG_RX[14] B32 PCIE_CRX_GTX_P15
<16> FDI_CTX_PRX_P2 G18 FDI0_TX[2] PEG_RX[15]
<16> FDI_CTX_PRX_P3 B20 FDI0_TX[3] M29 PCIE_CTX_GRX_N[0..15] <23,32>
PCIE_CTX_GRX_C_N0 C1 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N0
<16> FDI_CTX_PRX_P4 C19 FDI1_TX[0] PEG_TX#[0] M32 PCIE_CTX_GRX_C_N1 C2 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N1
<16> FDI_CTX_PRX_P5 D19 FDI1_TX[1] PEG_TX#[1] M31 PCIE_CTX_GRX_C_N2 C3 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N2
<16> FDI_CTX_PRX_P6 F17 FDI1_TX[2] PEG_TX#[2] L32 PCIE_CTX_GRX_C_N3 C4 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N3
<16> FDI_CTX_PRX_P7 FDI1_TX[3] PEG_TX#[3] L29 PCIE_CTX_GRX_C_N4 C5 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N4
FDI_FSYNC0 J18 PEG_TX#[4] K31 PCIE_CTX_GRX_C_N5 C6 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N5
+1.05VS <16> FDI_FSYNC0 FDI0_FSYNC PEG_TX#[5]
FDI_FSYNC1 J17 K28 PCIE_CTX_GRX_C_N6 C7 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N6
<16> FDI_FSYNC1 FDI1_FSYNC PEG_TX#[6] J30 PCIE_CTX_GRX_C_N7 C8 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N7
FDI_INT H20 PEG_TX#[7] J28 PCIE_CTX_GRX_C_N8 SLI@C9
SLI@ C9 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N8
<16> FDI_INT FDI_INT PEG_TX#[8] H29 PCIE_CTX_GRX_C_N9 SLI@C10
SLI@ C10 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N9
PEG_TX#[9]
1

FDI_LSYNC0 J19 G27 PCIE_CTX_GRX_C_N10 SLI@C11 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N10

<16> FDI_LSYNC0 FDI0_LSYNC PEG_TX#[10]
R7 FDI_LSYNC1 H17 E29 PCIE_CTX_GRX_C_N11 SLI@C12
SLI@ C12 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N11
B <16> FDI_LSYNC1 FDI1_LSYNC PEG_TX#[11] B
24.9_0402_1% F27 PCIE_CTX_GRX_C_N12 SLI@C13
SLI@ C13 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N12
PEG_TX#[12] D28 PCIE_CTX_GRX_C_N13 SLI@C14 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N13
PEG_TX#[13] F26 PCIE_CTX_GRX_C_N14 SLI@C15
SLI@ C15 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N14
2

PEG_TX#[14] E25 PCIE_CTX_GRX_C_N15 SLI@C16

SLI@ C16 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N15
EDP_COMP A18 PEG_TX#[15]
A17 eDP_COMPIO M28 PCIE_CTX_GRX_P[0..15] <23,32>
eDP_COMPIO and ICOMPO signals PCIE_CTX_GRX_C_P0 C20 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P0
B16 eDP_ICOMPO PEG_TX[0] M33 PCIE_CTX_GRX_C_P1 C23 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P1
should be shorted near balls eDP_HPD eDP_HPD# PEG_TX[1] M30 PCIE_CTX_GRX_C_P2 C25 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P2
PEG_TX[2]
and routed with typical PEG_TX[3]
L31 PCIE_CTX_GRX_C_P3 C30 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P3
C15 L28 PCIE_CTX_GRX_C_P4 C18 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P4
impedance <25 mohms D15 eDP_AUX PEG_TX[4] K30 PCIE_CTX_GRX_C_P5 C22 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P5
eDP_AUX# PEG_TX[5] K27 PCIE_CTX_GRX_C_P6 C28 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P6
eDP

PEG_TX[6] J29 PCIE_CTX_GRX_C_P7 C32 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P7

C17 PEG_TX[7] J27 PCIE_CTX_GRX_C_P8 SLI@C19
SLI@ C19 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P8
F16 eDP_TX[0] PEG_TX[8] H28 PCIE_CTX_GRX_C_P9 C24 1
SLI@C24
SLI@ 2 0.22U_0402_10V6K PCIE_CTX_GRX_P9
C16 eDP_TX[1] PEG_TX[9] G28 PCIE_CTX_GRX_C_P10 SLI@C29
SLI@ C29 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P10
G15 eDP_TX[2] PEG_TX[10] E28 PCIE_CTX_GRX_C_P11 SLI@C17
SLI@ C17 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P11
eDP_TX[3] PEG_TX[11] F28 PCIE_CTX_GRX_C_P12 SLI@C21
SLI@ C21 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P12
C18 PEG_TX[12] D27 PCIE_CTX_GRX_C_P13 SLI@C27
SLI@ C27 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P13
E16 eDP_TX#[0] PEG_TX[13] E26 PCIE_CTX_GRX_C_P14 SLI@C26
SLI@ C26 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P14
D16 eDP_TX#[1] PEG_TX[14] D25 PCIE_CTX_GRX_C_P15 SLI@C31
SLI@ C31 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P15
F15 eDP_TX#[2] PEG_TX[15]
eDP_TX#[3]

TYCO_2013620-2_IVY BRIDGE

ME@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 PROCESSOR(1/7) DMI,FDI,PEG

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-8692P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Tuesday, June 05, 2012 Sheet 5 of 66
5 4 3 2 1
 5 4 3 2 1

JCPU1B
D D

A28 CLK_CPU_DMI
C26 BCLK A27 CLK_CPU_DMI <15>
CLK_CPU_DMI#

MISC

CLOCKS
<19> H_SNB_IVB# PROC_SELECT# BCLK# CLK_CPU_DMI# <15>

AN34
SKTOCC# A16 R12 2 1 1K_0402_5%
DPLL_REF_CLK A15 R13 2 1 1K_0402_5%
DPLL_REF_CLK# +1.05VS
+1.05VS
T14 PAD H_CATERR# AL33
CATERR#
R9 1 Reserve 43 Ohm resistor closs to EC(250~750mils)
62_0402_5%

THERMAL
H_PECI AN33 R8 H_DRAMRST#
<45> H_PECI PECI SM_DRAMRST# H_DRAMRST# <7>
2

R15

DDR3
MISC
56_0402_5%
H_PROCHOT# 1 2 H_PROCHOT#_R AL32 AK1 SM_RCOMP0 R16 2 1 140_0402_1%
<45,54> H_PROCHOT# PROCHOT# SM_RCOMP[0] A5 SM_RCOMP1 R17 2 1 25.5_0402_1% DDR3 Compensation Signals
SM_RCOMP[1] A4 SM_RCOMP2 R18 2 1 200_0402_1%
SM_RCOMP[2]
H_THRMTRIP# AN32
<19> H_THRMTRIP# THERMTRIP#

+1.05VS
AP29 XDP_PRDY# 1 R1499 2 0_0402_5% XDP_PRDY#_R PU/PD for JTAG signals
PRDY# AP27 XDP_PREQ# 1 R1500 2 0_0402_5% XDP_PREQ#_R
PREQ#
AR26 XDP_TCK 1 R1501 2 0_0402_5% XDP_TCK_R XDP_TMS R20 2 1 51_0402_5%
C TCK AR27 XDP_TMS 1 R1502 2 0_0402_5% XDP_TMS_R XDP_TDI R21 2 1 51_0402_5% C
R22 XDP_TDO 2 1

PWR MANAGEMENT
TMS R23 51_0402_5%

JTAG & BPM

1 2 H_PM_SYNC_R AM34 AP30 XDP_TRST# 1 R1503 2 0_0402_5% XDP_TRST#_R
<16> H_PM_SYNC PM_SYNC TRST# @
R_short 0_0402_5% AR28 1 R1504 2 0_0402_5% XDP_TDI_R XDP_TCK R24 2 1 51_0402_5%
XDP_TDI
TDI AP26 XDP_TDO 1 R1505 2 0_0402_5% XDP_TDO_R XDP_TRST# R25 2 1 51_0402_5%
1 R26 2 H_CPUPWRGD_R AP33 TDO
<19,6> H_CPUPWRGD UNCOREPWRGOOD
R_short 0_0402_5%
2

1 R29 AL35 XDP_DBRESET# R28 2 1 1K_0402_5%

DBR# +3VS
C550 R27 1 2 PM_DRAM_PWRGD_R V8
130_0402_5% SM_DRAMPWROK
100P_0402_50V8J 10K_0402_5% AT28 XDP_BPM#0 1 R1506 2 0_0402_5% XDP_BPM#0_R
2 BPM#[0] AR29 XDP_BPM#1 1 R1507 2 0_0402_5% XDP_BPM#1_R
1

BPM#[1] AR30 XDP_BPM#2 1 R1508 2 0_0402_5% XDP_BPM#2_R

BUF_CPU_RST# AR33 BPM#[2] AT30 XDP_BPM#3 1 R1509 2 0_0402_5% XDP_BPM#3_R
RESET# BPM#[3] AP32 XDP_BPM#4
9/23 ESD Request BPM#[4]
PAD T31
AR31 XDP_BPM#5 PAD T30
BPM#[5] AT31 XDP_BPM#6 PAD T33
BPM#[6] AR32 XDP_BPM#7 PAD T32
BPM#[7]

TYCO_2013620-2_IVY BRIDGE
ME@
XDP Connector
+3VS +3VALW JXDP1 @
Buffered reset to CPU
<16> SYS_PWROK XDP_PREQ#_R 1
+1.5V_CPU_VDDQ XDP_PRDY#_R 2
1 3
1

C33 +3VS
B XDP_BPM#0_R 4 B
R65 R338 0.1U_0402_16V4Z
XDP_BPM#1_R 5
1

0_0402_5% @ 10K_0402_5%
2 6
R30
+1.05VS XDP_BPM#2_R 7
U1 200_0402_5% 1
2

XDP_BPM#3_R 8
C34
9
5

0.1U_0402_16V4Z 1K_0402_5%
R1510 2 1 H_CPUPWRGD_R 10
2

1 <19,6> H_CPUPWRGD
P

B 4 PM_SYS_PWRGD_BUF 2 PBTN_OUT# 11
R32 <16,45> PBTN_OUT#
2 O R1511 2 1 CFG0_R 12
<16> PM_DRAM_PWRGD 1.05V 75_0402_5% This is NC pin <8> CFG0 1K_0402_5%
A VGATE 13
G

<16,60> VGATE
CLK_BCLK_ITP 14

5
74AHC1G09GW_TSSOP5 R34 U2 <15> CLK_BCLK_ITP
3V 15
3

1 CLK_BCLK_ITP#
43_0402_1% <15> CLK_BCLK_ITP#

P
BUF_CPU_RST# 1 2 BUFO_CPU_RST# 4 NC 16
Y +1.05VS PLT_RST# 17
2 PLT_RST# <18,23,32,38,39,44,45,6> PLT_RST#
A PLT_RST# <18,23,32,38,39,44,45,6> XDP_DBRESET# 18

G
1

SN74LVC1G07DCKR_SC70-5
19
20

3
XDP_TDO_R
R35 @
XDP_TRST#_R 21
0_0402_5%
XDP_TDI_R 22
2

XDP_TMS_R 23
24
25
XDP_TCK_R 26
27
28

MOLEX 52435-2671

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 PROCESSOR(2/7) PM,XDP,CLK

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-8692P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Tuesday, June 05, 2012 Sheet 6 of 66
5 4 3 2 1
 5 4 3 2 1

JCPU1C JCPU1D

AB6 AE2
<12> DDR_A_D[0..63] SA_CK[0] AA6 M_CLK_DDR0 <12>
<13> DDR_B_D[0..63] SB_CK[0] AD2 M_CLK_DDR2 <13>
C5 SA_CLK#[0] V9 M_CLK_DDR#0 <12> C9 SB_CLK#[0] R9 M_CLK_DDR#2 <13>
DDR_A_D0 DDR_B_D0
DDR_A_D1 D5 SA_DQ[0] SA_CKE[0] DDR_CKE0_DIMMA <12> DDR_B_D1 A7 SB_DQ[0] SB_CKE[0] DDR_CKE2_DIMMB <13>
DDR_A_D2 D3 SA_DQ[1] DDR_B_D2 D10 SB_DQ[1]
DDR_A_D3 D2 SA_DQ[2] DDR_B_D3 C8 SB_DQ[2]
DDR_A_D4 D6 SA_DQ[3] AA5 DDR_B_D4 A9 SB_DQ[3] AE1
D DDR_A_D5 C6 SA_DQ[4] SA_CK[1] AB5 M_CLK_DDR1 <12> DDR_B_D5 A8 SB_DQ[4] SB_CK[1] AD1 M_CLK_DDR3 <13> D
DDR_A_D6 C2 SA_DQ[5] SA_CLK#[1] V10 M_CLK_DDR#1 <12> DDR_B_D6 D9 SB_DQ[5] SB_CLK#[1] R10 M_CLK_DDR#3 <13>
DDR_A_D7 C3 SA_DQ[6] SA_CKE[1] DDR_CKE1_DIMMA <12> DDR_B_D7 D8 SB_DQ[6] SB_CKE[1] DDR_CKE3_DIMMB <13>
DDR_A_D8 F10 SA_DQ[7] DDR_B_D8 G4 SB_DQ[7]
DDR_A_D9 F8 SA_DQ[8] DDR_B_D9 F4 SB_DQ[8]
DDR_A_D10 G10 SA_DQ[9] AB4 DDR_B_D10 F1 SB_DQ[9] AB2
DDR_A_D11 G9 SA_DQ[10] SA_CK[2] AA4 DDR_B_D11 G1 SB_DQ[10] SB_CK[2] AA2
DDR_A_D12 F9 SA_DQ[11] SA_CLK#[2] W9 DDR_B_D12 G5 SB_DQ[11] SB_CLK#[2] T9
DDR_A_D13 F7 SA_DQ[12] SA_CKE[2] DDR_B_D13 F5 SB_DQ[12] SB_CKE[2]
DDR_A_D14 G8 SA_DQ[13] DDR_B_D14 F2 SB_DQ[13]
DDR_A_D15 G7 SA_DQ[14] DDR_B_D15 G2 SB_DQ[14]
DDR_A_D16 K4 SA_DQ[15] AB3 DDR_B_D16 J7 SB_DQ[15] AA1
DDR_A_D17 K5 SA_DQ[16] SA_CK[3] AA3 DDR_B_D17 J8 SB_DQ[16] SB_CK[3] AB1
DDR_A_D18 K1 SA_DQ[17] SA_CLK#[3] W10 DDR_B_D18 K10 SB_DQ[17] SB_CLK#[3] T10
DDR_A_D19 J1 SA_DQ[18] SA_CKE[3] DDR_B_D19 K9 SB_DQ[18] SB_CKE[3]
DDR_A_D20 J5 SA_DQ[19] DDR_B_D20 J9 SB_DQ[19]
DDR_A_D21 J4 SA_DQ[20] DDR_B_D21 J10 SB_DQ[20]
DDR_A_D22 J2 SA_DQ[21] AK3 DDR_B_D22 K8 SB_DQ[21] AD3
K2 SA_DQ[22] SA_CS#[0] AL3 DDR_CS0_DIMMA# <12> K7 SB_DQ[22] SB_CS#[0] AE3 DDR_CS2_DIMMB# <13>
DDR_A_D23 DDR_B_D23
DDR_A_D24 M8 SA_DQ[23] SA_CS#[1] AG1 DDR_CS1_DIMMA# <12> DDR_B_D24 M5 SB_DQ[23] SB_CS#[1] AD6 DDR_CS3_DIMMB# <13>
DDR_A_D25 N10 SA_DQ[24] SA_CS#[2] AH1 DDR_B_D25 N4 SB_DQ[24] SB_CS#[2] AE6
DDR_A_D26 N8 SA_DQ[25] SA_CS#[3] DDR_B_D26 N2 SB_DQ[25] SB_CS#[3]
DDR_A_D27 N7 SA_DQ[26] DDR_B_D27 N1 SB_DQ[26]
DDR_A_D28 M10 SA_DQ[27] DDR_B_D28 M4 SB_DQ[27]
DDR_A_D29 M9 SA_DQ[28] AH3 DDR_B_D29 N5 SB_DQ[28] AE4
N9 SA_DQ[29] SA_ODT[0] AG3 M_ODT0 <12> M2 SB_DQ[29] SB_ODT[0] AD4 M_ODT2 <13>
DDR_A_D30 DDR_B_D30
M_ODT1 <12> M_ODT3 <13>

DDR SYSTEM MEMORY B

DDR_A_D31 M7 SA_DQ[30] SA_ODT[1] AG2 DDR_B_D31 M1 SB_DQ[30] SB_ODT[1] AD5

DDR SYSTEM MEMORY A

DDR_A_D32 AG6 SA_DQ[31] SA_ODT[2] AH2 DDR_B_D32 AM5 SB_DQ[31] SB_ODT[2] AE5
DDR_A_D33 AG5 SA_DQ[32] SA_ODT[3] DDR_B_D33 AM6 SB_DQ[32] SB_ODT[3]
DDR_A_D34 AK6 SA_DQ[33] DDR_B_D34 AR3 SB_DQ[33]
DDR_A_D35 AK5 SA_DQ[34] DDR_B_D35 AP3 SB_DQ[34]
DDR_A_D36 AH5 SA_DQ[35] DDR_B_D36 AN3 SB_DQ[35]
C DDR_A_D37 AH6 SA_DQ[36] C4 DDR_A_DQS#0 DDR_A_DQS#[0..7] <12> DDR_B_D37 AN2 SB_DQ[36] D7 DDR_B_DQS#0 DDR_B_DQS#[0..7] <13> C
DDR_A_D38 AJ5 SA_DQ[37] SA_DQS#[0] G6 DDR_A_DQS#1 DDR_B_D38 AN1 SB_DQ[37] SB_DQS#[0] F3 DDR_B_DQS#1
DDR_A_D39 AJ6 SA_DQ[38] SA_DQS#[1] J3 DDR_A_DQS#2 DDR_B_D39 AP2 SB_DQ[38] SB_DQS#[1] K6 DDR_B_DQS#2
DDR_A_D40 AJ8 SA_DQ[39] SA_DQS#[2] M6 DDR_A_DQS#3 DDR_B_D40 AP5 SB_DQ[39] SB_DQS#[2] N3 DDR_B_DQS#3
DDR_A_D41 AK8 SA_DQ[40] SA_DQS#[3] AL6 DDR_A_DQS#4 DDR_B_D41 AN9 SB_DQ[40] SB_DQS#[3] AN5 DDR_B_DQS#4
DDR_A_D42 AJ9 SA_DQ[41] SA_DQS#[4] AM8 DDR_A_DQS#5 DDR_B_D42 AT5 SB_DQ[41] SB_DQS#[4] AP9 DDR_B_DQS#5
DDR_A_D43 AK9 SA_DQ[42] SA_DQS#[5] AR12 DDR_A_DQS#6 DDR_B_D43 AT6 SB_DQ[42] SB_DQS#[5] AK12 DDR_B_DQS#6
DDR_A_D44 AH8 SA_DQ[43] SA_DQS#[6] AM15 DDR_A_DQS#7 DDR_B_D44 AP6 SB_DQ[43] SB_DQS#[6] AP15 DDR_B_DQS#7
DDR_A_D45 AH9 SA_DQ[44] SA_DQS#[7] DDR_B_D45 AN8 SB_DQ[44] SB_DQS#[7]
DDR_A_D46 AL9 SA_DQ[45] DDR_B_D46 AR6 SB_DQ[45]
DDR_A_D47 AL8 SA_DQ[46] DDR_B_D47 AR5 SB_DQ[46]
DDR_A_D48 AP11 SA_DQ[47] DDR_B_D48 AR9 SB_DQ[47]
AN11 SA_DQ[48] D4 DDR_A_DQS[0..7] <12> AJ11 SB_DQ[48] C7 DDR_B_DQS[0..7] <13>
DDR_A_D49 DDR_A_DQS0 DDR_B_D49 DDR_B_DQS0
DDR_A_D50 AL12 SA_DQ[49] SA_DQS[0] F6 DDR_A_DQS1 DDR_B_D50 AT8 SB_DQ[49] SB_DQS[0] G3 DDR_B_DQS1
DDR_A_D51 AM12 SA_DQ[50] SA_DQS[1] K3 DDR_A_DQS2 DDR_B_D51 AT9 SB_DQ[50] SB_DQS[1] J6 DDR_B_DQS2
DDR_A_D52 AM11 SA_DQ[51] SA_DQS[2] N6 DDR_A_DQS3 DDR_B_D52 AH11 SB_DQ[51] SB_DQS[2] M3 DDR_B_DQS3
DDR_A_D53 AL11 SA_DQ[52] SA_DQS[3] AL5 DDR_A_DQS4 DDR_B_D53 AR8 SB_DQ[52] SB_DQS[3] AN6 DDR_B_DQS4
DDR_A_D54 AP12 SA_DQ[53] SA_DQS[4] AM9 DDR_A_DQS5 DDR_B_D54 AJ12 SB_DQ[53] SB_DQS[4] AP8 DDR_B_DQS5
DDR_A_D55 AN12 SA_DQ[54] SA_DQS[5] AR11 DDR_A_DQS6 DDR_B_D55 AH12 SB_DQ[54] SB_DQS[5] AK11 DDR_B_DQS6
DDR_A_D56 AJ14 SA_DQ[55] SA_DQS[6] AM14 DDR_A_DQS7 DDR_B_D56 AT11 SB_DQ[55] SB_DQS[6] AP14 DDR_B_DQS7
DDR_A_D57 AH14 SA_DQ[56] SA_DQS[7] DDR_B_D57 AN14 SB_DQ[56] SB_DQS[7]
DDR_A_D58 AL15 SA_DQ[57] DDR_B_D58 AR14 SB_DQ[57]
DDR_A_D59 AK15 SA_DQ[58] DDR_B_D59 AT14 SB_DQ[58]
DDR_A_D60 AL14 SA_DQ[59] DDR_B_D60 AT12 SB_DQ[59]
DDR_A_D61 AK14 SA_DQ[60] AD10 DDR_A_MA0 DDR_A_MA[0..15] <12> DDR_B_D61 AN15 SB_DQ[60] AA8 DDR_B_MA0 DDR_B_MA[0..15] <13>
DDR_A_D62 AJ15 SA_DQ[61] SA_MA[0] W1 DDR_A_MA1 DDR_B_D62 AR15 SB_DQ[61] SB_MA[0] T7 DDR_B_MA1
DDR_A_D63 AH15 SA_DQ[62] SA_MA[1] W2 DDR_A_MA2 DDR_B_D63 AT15 SB_DQ[62] SB_MA[1] R7 DDR_B_MA2
SA_DQ[63] SA_MA[2] W7 DDR_A_MA3 SB_DQ[63] SB_MA[2] T6 DDR_B_MA3
SA_MA[3] V3 DDR_A_MA4 SB_MA[3] T2 DDR_B_MA4
SA_MA[4] V2 DDR_A_MA5 SB_MA[4] T4 DDR_B_MA5
SA_MA[5] W3 DDR_A_MA6 SB_MA[5] T3 DDR_B_MA6
AE10 SA_MA[6] W6 DDR_A_MA7 AA9 SB_MA[6] R2 DDR_B_MA7
B <12> DDR_A_BS0 AF10 SA_BS[0] SA_MA[7] V1 <13> DDR_B_BS0 AA7 SB_BS[0] SB_MA[7] T5 B
DDR_A_MA8 DDR_B_MA8
<12> DDR_A_BS1 V6 SA_BS[1] SA_MA[8] W5 <13> DDR_B_BS1 R6 SB_BS[1] SB_MA[8] R3
DDR_A_MA9 DDR_B_MA9
<12> DDR_A_BS2 SA_BS[2] SA_MA[9] AD8 DDR_A_MA10 <13> DDR_B_BS2 SB_BS[2] SB_MA[9] AB7 DDR_B_MA10
SA_MA[10] V4 DDR_A_MA11 SB_MA[10] R1 DDR_B_MA11
SA_MA[11] W4 DDR_A_MA12 SB_MA[11] T1 DDR_B_MA12
AE8 SA_MA[12] AF8 DDR_A_MA13 AA10 SB_MA[12] AB10 DDR_B_MA13
<12> DDR_A_CAS# AD9 SA_CAS# SA_MA[13] V5 <13> DDR_B_CAS# AB8 SB_CAS# SB_MA[13] R5
DDR_A_MA14 DDR_B_MA14
<12> DDR_A_RAS# AF9 SA_RAS# SA_MA[14] V7 DDR_A_MA15 <13> DDR_B_RAS# AB9 SB_RAS# SB_MA[14] R4 DDR_B_MA15
<12> DDR_A_WE# SA_WE# SA_MA[15] <13> DDR_B_WE# SB_WE# SB_MA[15]

TYCO_2013620-2_IVY BRIDGE TYCO_2013620-2_IVY BRIDGE

ME@ +1.5V ME@

1

R37
1K_0402_5%

R38
2

1K_0402_5%
3 1 1 2
S

<6> H_DRAMRST# H_DRAMRST# DDR3_DRAMRST#_R

DDR3_DRAMRST# <12,13>
2

Q2
R39 BSS138_NL_SOT23-3
G
2

4.99K_0402_1%
1

A No DS3 to stuff R40 A

@
1 2 DRAMRST_CNTRL
<15> DRAMRST_CNTRL_PCH
R40 0_0402_5%
<10> DRAMRST_CNTRL
1 2 1
<45> DRAMRST_CNTRL_EC
R64 0_0402_5% Title
DS3@ C35 Security Classification LC Future Center Secret Data
0.047U_0402_16V4Z Issued Date 2014/07/01 PROCESSOR(3/7) DDRIII
2 2012/07/01 Deciphered Date
Module design used 0.047u THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-8692P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Tuesday, June 05, 2012 Sheet 7 of 66
5 4 3 2 1
 5 4 3 2 1

CFG Straps for Processor

CFG2

1
@ R41
1K_0402_1%

2
D D

PEG Static Lane Reversal - CFG2 is for the 16x

CFG2 * 1: Normal Operation; Lane #

socket pin map definition
definition matches

0:Lane Reversed

JCPU1E

AH27 PAD T13

CFG0 AK28 VCC_DIE_SENSE AH26
<6> CFG0 CFG[0] VSS
AK29
CFG2 AL26 CFG[1]
AL27 CFG[2]
CFG[3] Display Port Presence Strap
AK26 L7
CFG5 AL29 CFG[4] RSVD28 AG7
C CFG6 AL30 CFG[5] RSVD29 AE7 C
1 : Disabled; No Physical Display Port
CFG7 AM31
AM32
CFG[6]
CFG[7]
CFG[8]
RSVD30
RSVD31
AK2 CFG4 * attached to Embedded Display Port
AM30 W8

CFG
AM28 CFG[9] RSVD32
CFG[10] 0 : Enabled; An external Display Port device is
AM26
AN28 CFG[11] AT26 connected to the Embedded Display Port
AN31 CFG[12] RSVD33 AM33
AN26 CFG[13] RSVD34 AJ27
AM27 CFG[14] RSVD35
AK31 CFG[15] CFG6
AN29 CFG[16]
CFG[17] CFG5
11/24 Intel recommend to reserve test point

1
T8
RSVD37 J16 R43 @ R44
T56 PAD AJ31 RSVD38 H16 1K_0402_1% 1K_0402_1%
T57 PAD AH31 VAXG_VAL_SENSE RSVD39 G16
T58 PAD AJ33 VSSAXG_VAL_SENSE RSVD40

2
T59 PAD AH33 VCC_VAL_SENSE
VSS_VAL_SENSE

AJ26 AR35
RSVD5 RSVD_NCTF1 AT34
RSVD_NCTF2

RESERVED
AT33
RSVD_NCTF3 AP35
RSVD_NCTF4 AR34
RSVD_NCTF5
PCIE Port Bifurcation Straps
F25
F24 RSVD8
RSVD9 11: (Default) x16 - Device 1 functions 1 and 2 disabled
F23
RSVD10
*10: x8,
B D24 B34 B
RSVD11 RSVD_NCTF6 CFG[6:5] x8 - Device 1 function 1 enabled ; function 2
G25 A33
G24 RSVD12 RSVD_NCTF7 A34 disabled
E23 RSVD13 RSVD_NCTF8 B35
RSVD14 RSVD_NCTF9 01: Reserved - (Device 1 function 1 disabled ; function
D23 C35
C30 RSVD15 RSVD_NCTF10 2 enabled)
A31 RSVD16
RSVD17 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
B30
B29 RSVD18
D30 RSVD19 AJ32
B31 RSVD20 RSVD51 AK32
A30 RSVD21 RSVD52 CFG7
C29 RSVD22
RSVD23

1
AN35 @R45
@ R45
J20 BCLK_ITP AM35 1K_0402_1%
B18 RSVD24 BCLK_ITP#
RSVD25

2
J15 AT2
RSVD27 RSVD_NCTF11 AT1
RSVD_NCTF12 AR1
RSVD_NCTF13
PEG DEFER TRAINING
B1
KEY
1: (Default) PEG Train immediately following xxRESETB
CFG7 de assertion

A
0: PEG Wait for BIOS for training A
TYCO_2013620-2_IVY BRIDGE

ME@

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 PROCESSOR(4/7) RSVD,CFG

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-8692P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Tuesday, June 05, 2012 Sheet 8 of 66
5 4 3 2 1
 5 4 3 2 1

JCPU1F POWER
+VCC_CORE
+1.05VS
QC=94A
8.5A
DC=53A AG35
AG34 VCC1 AH13
AG33 VCC2 VCCIO1 AH10
AG32 VCC3 VCCIO2 AG10
AG31 VCC4 VCCIO3 AC10
D AG30 VCC5 VCCIO4 Y10 D
AG29 VCC6 VCCIO5 U10
AG28 VCC7 VCCIO6 P10
AG27 VCC8 VCCIO7 L10
AG26 VCC9 VCCIO8 J14
AF35 VCC10 VCCIO9 J13
AF34 VCC11 VCCIO10 J12
AF33 VCC12 VCCIO11 J11
AF32 VCC13 VCCIO12 H14
AF31 VCC14 VCCIO13 H12
AF30 VCC15 VCCIO14 H11
AF29 VCC16 VCCIO15 G14
AF28 VCC17 VCCIO16 G13
AF27 VCC18 VCCIO17 G12

PEG AND DDR

AF26 VCC19 VCCIO18 F14
AD35 VCC20 VCCIO19 F13
AD34 VCC21 VCCIO20 F12
AD33 VCC22 VCCIO21 F11
AD32 VCC23 VCCIO22 E14
AD31 VCC24 VCCIO23 E12
AD30 VCC25 VCCIO24
AD29 VCC26 E11
AD28 VCC27 VCCIO25 D14
AD27 VCC28 VCCIO26 D13
AD26 VCC29 VCCIO27 D12
AC35 VCC30 VCCIO28 D11
AC34 VCC31 VCCIO29 C14
AC33 VCC32 VCCIO30 C13
AC32 VCC33 VCCIO31 C12
AC31 VCC34 VCCIO32 C11
AC30 VCC35 VCCIO33 B14
AC29 VCC36 VCCIO34 B12
C AC28 VCC37 VCCIO35 A14 C
AC27 VCC38 VCCIO36 A13
AC26 VCC39 VCCIO37 A12
AA35 VCC40 VCCIO38 A11
AA34 VCC41 VCCIO39
AA33 VCC42 J23
AA32 VCC43 VCCIO40
AA31 VCC44
AA30 VCC45
AA29 VCC46
AA28 VCC47
AA27 VCC48
AA26 VCC49
Y35 VCC50 +1.05VS
Reserve 0.1u to avoid noise

CORE SUPPLY
Y34 VCC51
VCC52 Place the PU resistor close to CPU
Y33
Y32 VCC53
VCC54 @ 1

1
Y31
Y30 VCC55 C36 R46
Y29 VCC56 0.1U_0402_10V7K
VCC57 75_0402_5%
Y28 2
Y27 VCC58

2
Y26 VCC59
V35 VCC60
V34 VCC61 AJ29 H_CPU_SVIDALRT# R47 1 2 43_0402_5%

SVID
V33 VCC62 VIDALERT# AJ30 H_CPU_SVIDCLK VR_SVID_ALRT# <60>
R48 1 2 R_short 0_0402_5%
V32 VCC63 VIDSCLK AJ28 1 2 R_short 0_0402_5% VR_SVID_CLK <60>
H_CPU_SVIDDAT R49
V31 VCC64 VIDSOUT VR_SVID_DAT <60>
V30 VCC65
V29 VCC66 R50 2 1 130_0402_5%
VCC67 +1.05VS
V28
V27 VCC68
B V26 VCC69 B
U35 VCC70
VCC71 Place the PU resistor close to CPU
U34
U33 VCC72
U32 VCC73
U31 VCC74
U30 VCC75
U29 VCC76
U28 VCC77 VCC_SENCE 100ohm +-1% pull-up to VCC near processor
U27 VCC78
U26 VCC79
R35 VCC80 +VCC_CORE
R34 VCC81
R33 VCC82
VCC83

1
R32
R31 VCC84 R51
R30 VCC85
VCC86 100_0402_1%
R29
R28 VCC87
SENSE LINES

2
R27 VCC88 AJ35 VCCSENSE_R R52 1 2 R_short 0_0402_5%
R26 VCC89 VCC_SENSE AJ34 VSSSENSE_R R53 1 2 R_short 0_0402_5% VCCSENSE <60>
P35 VCC90 VSS_SENSE VSSSENSE <60>
P34 VCC91 R1294 2 1 10_0402_1%
VCC92 +1.05VS

1
P33
P32 VCC93 B10 VCCIO_SENSE R54
P31 VCC94 VCCIO_SENSE A10 VCCIO_SENSE <58>
VSSIO_SENSE 100_0402_1%
P30 VCC95 VSS_SENSE_VCCIO
VCC96

2
P29

2
P28 VCC97 R1297
P27 VCC98
VCC99 10_0402_1%
P26
VCC100

1
A A

VSS_SENCE 100ohm +-1% pull-down to GND near processor

TYCO_2013620-2_IVY BRIDGE Title

Security Classification LC Future Center Secret Data
ME@ Issued Date 2012/07/01 Deciphered Date 2014/07/01 PROCESSOR(5/7) PWR,BYPASS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-8692P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Tuesday, June 05, 2012 Sheet 9 of 66
5 4 3 2 1
 5 4 3 2 1

+1.5V +1.5V_CPU_VDDQ

C287
1 2
0.1U_0402_10V6K
C286 1 2
0.1U_0402_10V6K
C96 1 2
0.1U_0402_10V6K
AO4714 C95 1 2
Vgs=10V,Id=20A,Rds=6.7m ohm 0.1U_0402_10V6K
U3
+VSB AO4304L 1N SOIC-8
R56 check EVT 8 1
7 2

1
D D
+3VALW 6 3
5

1
1
R56 Place the PU/PD resistor close to CPU within 2 inch
R1537

4
100K_0402_5% R1487 (Reserve power side)

2
100K_0402_5% 470_0603_5%
@ R1349 @

32
RUN_ON_CPU1.5VS3 1 2

2
D
470K_0402_5% 1 +VCC_GFXCORE_AXG VCC_AXG_SENSE <60>

6
D Q4B 5 SUSP

0.01U 50V K X7R 0402

2 Q4A C97 G

2N7002KDWH_SOT363-6
Q156 R57 VSS_AXG_SENSE <60>

2
2N7002_SOT23 G

2N7002KDWH_SOT363-6
470K_0402_5% 2 R66

1
@ D S

4
2 S 100_0402_1%

1
<45> CPU1.5V_S3_GATE

2
G OPT@

1
S

3
R89 100_0402_1%

<38,52,56,58> SUSP
R1538 1 2 R_short 0_0402_5%
+VCC_GFXCORE_AXG
JCPU1G
POWER 2 1
OPT@

+1.5V_CPU_VDDQ
46A R1488 OPT@
AT24 AK35 VCC_AXG_SENSE_R 10_0402_5%2

SENSE
LINES
VAXG1 VAXG_SENSE

1
AT23 AK34 VSS_AXG_SENSE_R 1 2
VAXG2 VSSAXG_SENSE

1
AT21 0_0402_5% R77
AT20 VAXG3 R1489 1K_0402_1%
R1514 VAXG4 OPT@
AT18
0_0402_5% VAXG5
AT17

2
SLI@ AR24 VAXG6 +V_SM_VREF_CNT
VAXG7

2
AR23
VAXG8

1
C AR21 0.1U_0402_16V4Z 1 C
AR20 VAXG9 C114 R88
AR18 VAXG10 AL1 1K_0402_1%
AR17 VAXG11 SM_VREF
AP24 VAXG12 2

VREF

2
AP23 VAXG13
AP21 VAXG14
AP20 VAXG15 B4 +V_DDR_REFA_R
AP18 VAXG16 SA_DIMM_VREFDQ D1 +V_DDR_REFB_R
AP17 VAXG17 SB_DIMM_VREFDQ
AN24 VAXG18
AN23 VAXG19
AN21 VAXG20
AN20 VAXG21
<7> DRAMRST_CNTRL AN18 VAXG22
VAXG23 5A

DDR3 -1.5V RAILS

AN17 +1.5V_CPU_VDDQ
VAXG24
2

Q8 BSS138_SOT23 AM24 AF7

G

GRAPHICS
AM23 VAXG25 VDDQ1 AF4
VAXG26 VDDQ2

330U_D2_2.5VY_R9M
1 3 AM21 AF1 1
VAXG27 VDDQ3

C123
AM20 AC7
D

+VREF_DQ_DIMMA VAXG28 VDDQ4 1 1 1 1 1 1

10U_0603_6.3V6M
C117

10U_0603_6.3V6M
C118

10U_0603_6.3V6M
C119

10U_0603_6.3V6M
C120

10U_0603_6.3V6M
C121

10U_0603_6.3V6M
C122
AM18 AC4 +
AM17 VAXG29 VDDQ5 AC1
AL24 VAXG30 VDDQ6 Y7 @
+VREF_DQ_DIMMB @ AL23 VAXG31 VDDQ7 Y4 2 2 2 2 2 2 2
R74 1 2 0_0402_5% +V_DDR_REFA_R AL21 VAXG32 VDDQ8 Y1
R75 1 2 0_0402_5% +V_DDR_REFB_R AL20 VAXG33 VDDQ9 U7
@ AL18 VAXG34 VDDQ10 U4
AL17 VAXG35 VDDQ11 U1
VAXG36 VDDQ12
1

AK24 P7
AK23 VAXG37 VDDQ13 P4
R139 R132 AK21 VAXG38 VDDQ14 P1
1 3 1K_0402_1% 1K_0402_1% AK20 VAXG39 VDDQ15
D

B @ @ AK18 VAXG40 B
2

Q7 BSS138_SOT23 AK17 VAXG41

AJ24 VAXG42
G
2

DRAMRST_CNTRL AJ23 VAXG43

AJ21 VAXG44
AJ20 VAXG45 +VCCSA
6/8 Add M3 Circuit (Processor Generated SO-DIMM VREF_DQ) VAXG46 6A
AJ18
AJ17 VAXG47 M27 +VCCSA
AH24 VAXG48 VCCSA1 M26

SA RAIL
AH23 VAXG49 VCCSA2 L26
VAXG50 VCCSA3

330U_D2_2.5VY_R9M
AH21 J26 1 1 1 1 1
VAXG51 VCCSA4

10U_0805_6.3V6M
C124

10U_0805_6.3V6M
C125

10U_0805_6.3V6M
C126

10U_0805_6.3V6M
C127

C128
AH20 J25
AH18 VAXG52 VCCSA5 J24 @ + @
AH17 VAXG53 VCCSA6 H26
VAXG54 VCCSA7 H25 2 2 2 2
VCCSA8 2
1.8V RAIL

H23
+1.8VS VCCSA_SENSE +VCCSA_SENSE <57>
@
1 R67 2 +1.8VS_VCCPLL B6 1 2 0_0402_5%
R68
A6 VCCPLL1 C22
MISC

R_short 0_0805_5% 1 VCCPLL2 VCCSA_VID[0] H_VCCSA_VID0 <57>

10U_0805_6.3V6M
C130

1U_0402_6.3V6K
C131

1U_0402_6.3V6K
C132

A2 C24 6/3 modify for VCCSA 4-Level voltage

330U_B2_2.5VM_R15M

@ 1 1 VCCPLL3 VCCSA_VID[1] H_VCCSA_VID1 <57>

+ C279 1

2 2 2 A19
2 VCCIO_SEL

A TYCO_2013620-2_IVY BRIDGE A

ME@

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 PROCESSOR(6/7) PWR

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-8692P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Tuesday, June 05, 2012 Sheet 10 of 66
5 4 3 2 1
 5 4 3 2 1

JCPU1H JCPU1I
D AT35 AJ22 D
AT32 VSS1 VSS81 AJ19
AT29 VSS2 VSS82 AJ16 T35 F22
AT27 VSS3 VSS83 AJ13 T34 VSS161 VSS234 F19
AT25 VSS4 VSS84 AJ10 T33 VSS162 VSS235 E30
AT22 VSS5 VSS85 AJ7 T32 VSS163 VSS236 E27
AT19 VSS6 VSS86 AJ4 T31 VSS164 VSS237 E24
AT16 VSS7 VSS87 AJ3 T30 VSS165 VSS238 E21
AT13 VSS8 VSS88 AJ2 T29 VSS166 VSS239 E18
AT10 VSS9 VSS89 AJ1 T28 VSS167 VSS240 E15
AT7 VSS10 VSS90 AH35 T27 VSS168 VSS241 E13
AT4 VSS11 VSS91 AH34 T26 VSS169 VSS242 E10
AT3 VSS12 VSS92 AH32 P9 VSS170 VSS243 E9
AR25 VSS13 VSS93 AH30 P8 VSS171 VSS244 E8
AR22 VSS14 VSS94 AH29 P6 VSS172 VSS245 E7
AR19 VSS15 VSS95 AH28 P5 VSS173 VSS246 E6
AR16 VSS16 VSS96 AH25 P3 VSS174 VSS247 E5
AR13 VSS17 VSS98 AH22 P2 VSS175 VSS248 E4
AR10 VSS18 VSS99 AH19 N35 VSS176 VSS249 E3
AR7 VSS19 VSS100 AH16 N34 VSS177 VSS250 E2
AR4 VSS20 VSS101 AH7 N33 VSS178 VSS251 E1
AR2 VSS21 VSS102 AH4 N32 VSS179 VSS252 D35
AP34 VSS22 VSS103 AG9 N31 VSS180 VSS253 D32
AP31 VSS23 VSS104 AG8 N30 VSS181 VSS254 D29
AP28 VSS24 VSS105 AG4 N29 VSS182 VSS255 D26
AP25 VSS25 VSS106 AF6 N28 VSS183 VSS256 D20
AP22 VSS26 VSS107 AF5 N27 VSS184 VSS257 D17
AP19 VSS27 VSS108 AF3 N26 VSS185 VSS258 C34
AP16 VSS28 VSS109 AF2 M34 VSS186 VSS259 C31
AP13 VSS29 VSS110 AE35 L33 VSS187 VSS260 C28
AP10 VSS30 VSS111 AE34 L30 VSS188 VSS261 C27
AP7 VSS31 VSS112 AE33 L27 VSS189 VSS262 C25
C AP4 VSS32 VSS113 AE32 L9 VSS190 VSS263 C23 C
AP1 VSS33 VSS114 AE31 L8 VSS191 VSS264 C10
AN30 VSS34 VSS115 AE30 L6 VSS192 VSS265 C1
AN27 VSS35 VSS116 AE29 L5 VSS193 VSS266 B22
AN25 VSS36 VSS117 AE28 L4 VSS194 VSS267 B19
AN22
AN19
VSS37
VSS38
VSS39
VSS VSS118
VSS119
VSS120
AE27
AE26
L3
L2
VSS195
VSS196
VSS197
VSS VSS268
VSS269
VSS270
B17
B15
AN16 AE9 L1 B13
AN13 VSS40 VSS121 AD7 K35 VSS198 VSS271 B11
AN10 VSS41 VSS122 AC9 K32 VSS199 VSS272 B9
AN7 VSS42 VSS123 AC8 K29 VSS200 VSS273 B8
AN4 VSS43 VSS124 AC6 K26 VSS201 VSS274 B7
AM29 VSS44 VSS125 AC5 J34 VSS202 VSS275 B5
AM25 VSS45 VSS126 AC3 J31 VSS203 VSS276 B3
AM22 VSS46 VSS127 AC2 H33 VSS204 VSS277 B2
AM19 VSS47 VSS128 AB35 H30 VSS205 VSS278 A35
AM16 VSS48 VSS129 AB34 H27 VSS206 VSS279 A32
AM13 VSS49 VSS130 AB33 H24 VSS207 VSS280 A29
AM10 VSS50 VSS131 AB32 H21 VSS208 VSS281 A26
AM7 VSS51 VSS132 AB31 H18 VSS209 VSS282 A23
AM4 VSS52 VSS133 AB30 H15 VSS210 VSS283 A20
AM3 VSS53 VSS134 AB29 H13 VSS211 VSS284 A3
AM2 VSS54 VSS135 AB28 H10 VSS212 VSS285
AM1 VSS55 VSS136 AB27 H9 VSS213
AL34 VSS56 VSS137 AB26 H8 VSS214
AL31 VSS57 VSS138 Y9 H7 VSS215
AL28 VSS58 VSS139 Y8 H6 VSS216
AL25 VSS59 VSS140 Y6 H5 VSS217
AL22 VSS60 VSS141 Y5 H4 VSS218
AL19 VSS61 VSS142 Y3 H3 VSS219
AL16 VSS62 VSS143 Y2 H2 VSS220
AL13 VSS63 VSS144 W35 H1 VSS221
B AL10 VSS64 VSS145 W34 G35 VSS222 B
AL7 VSS65 VSS146 W33 G32 VSS223
AL4 VSS66 VSS147 W32 G29 VSS224
AL2 VSS67 VSS148 W31 G26 VSS225
AK33 VSS68 VSS149 W30 G23 VSS226
AK30 VSS69 VSS150 W29 G20 VSS227
AK27 VSS70 VSS151 W28 G17 VSS228
AK25 VSS71 VSS152 W27 G11 VSS229
AK22 VSS72 VSS153 W26 F34 VSS230
AK19 VSS73 VSS154 U9 F31 VSS231
AK16 VSS74 VSS155 U8 F29 VSS232
AK13 VSS75 VSS156 U6 VSS233
AK10 VSS76 VSS157 U5
AK7 VSS77 VSS158 U3
AK4 VSS78 VSS159 U2
AJ25 VSS79 VSS160
VSS80

TYCO_2013620-2_IVY BRIDGE TYCO_2013620-2_IVY BRIDGE

ME@ ME@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 PROCESSOR(7/7) VSS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-8692P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Tuesday, June 05, 2012 Sheet 11 of 66
5 4 3 2 1
 5 4 3 2 1

<7> DDR_A_D[0..63]
+1.5V
+VREF_DQ_DIMMA <7> DDR_A_DQS[0..7]
+1.5V +1.5V

1
3A@1.5V
<7> DDR_A_DQS#[0..7]
R78
1K_0402_1% DDR3 SO-DIMM A <7> DDR_A_MA[0..15]

0.047U_0402_16V4Z
0.047U_0402_16V4Z
JDIMM1

0.047U_0402_16V4Z

For RF request
2
+VREF_DQ_DIMMA 1 2 1 1 1
3 VREF_DQ VSS1 4 DDR_A_D4

C1066
C1064

C1065
VSS2 DQ4

0.1U_0402_10V6K

2.2U_0603_6.3V6K
DDR_A_D0 5 6 DDR_A_D5
DQ0 DQ5 @

1
@ @

C140

C141
1 1 DDR_A_D1 7 8 2
D DQ1 VSS3 2 2 D
9 10 DDR_A_DQS#0
R79 11 VSS4 DQS#0 12 DDR_A_DQS0
1K_0402_1% 13 DM0 DQS0 14
2 2 DDR_A_D2 15 VSS5 VSS6 16 DDR_A_D6
2 DDR_A_D3 17 DQ2 DQ6 18 DDR_A_D7
19 DQ3 DQ7 20
DDR_A_D8 21 VSS7 VSS8 22 DDR_A_D12
DDR_A_D9 23 DQ8 DQ12 24 DDR_A_D13
25 DQ9 DQ13 26
DDR_A_DQS#1 27 VSS9 VSS10 28
DDR_A_DQS1 29 DQS#1 DM1 30 DDR3_DRAMRST#
DQS1 RESET# DDR3_DRAMRST# <13,7>
31 32
DDR_A_D10 33 VSS11 VSS12 34 DDR_A_D14
DDR_A_D11 35 DQ10 DQ14 36 DDR_A_D15
37 DQ11 DQ15 38
DDR_A_D16 39 VSS13 VSS14 40 DDR_A_D20
DDR_A_D17 41 DQ16 DQ20 42 DDR_A_D21
43 DQ17 DQ21 44
DDR_A_DQS#2 45 VSS15 VSS16 46
DDR_A_DQS2 47 DQS#2 DM2 48
49 DQS2 VSS17 50 DDR_A_D22
DDR_A_D18 51 VSS18 DQ22 52 DDR_A_D23
DDR_A_D19 53 DQ18 DQ23 54
55 DQ19 VSS19 56 DDR_A_D28
DDR_A_D24 57 VSS20 DQ28 58 DDR_A_D29
DDR_A_D25 59 DQ24 DQ29 60
61 DQ25 VSS21 62 DDR_A_DQS#3
63 VSS22 DQS#3 64 DDR_A_DQS3
65 DM3 DQS3 66
DDR_A_D26 67 VSS23 VSS24 68 DDR_A_D30
DDR_A_D27 69 DQ26 DQ30 70 DDR_A_D31
71 DQ27 DQ31 72
C VSS25 VSS26 C

<7> DDR_CKE0_DIMMA DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA

CKE0 CKE1 DDR_CKE1_DIMMA <7>
75 76
77 VDD1 VDD2 78 DDR_A_MA15
DDR_A_BS2 79 NC1 A15 80 DDR_A_MA14
<7> DDR_A_BS2 BA2 A14
81 82
DDR_A_MA12 83 VDD3 VDD4 84 DDR_A_MA11
DDR_A_MA9 85 A12/BC# A11 86 DDR_A_MA7
87 A9 A7 88
DDR_A_MA8 89 VDD5 VDD6 90 DDR_A_MA6
DDR_A_MA5 91 A8 A6 92 DDR_A_MA4
93 A5 A4 94
DDR_A_MA3 95 VDD7 VDD8 96 DDR_A_MA2 OSCON (220uF_6.3V_4.2L_ESR17m)*1=(SF000002Y00)
DDR_A_MA1 97 A3 A2 98 DDR_A_MA0
99 A1 A0 100
<7> M_CLK_DDR0 M_CLK_DDR0 101 VDD9 VDD10 102 M_CLK_DDR1
Layout Note: (10uF_0603_6.3V)*8
CK0 CK1 M_CLK_DDR1 <7>
<7> M_CLK_DDR#0 M_CLK_DDR#0 103 104 M_CLK_DDR#1
M_CLK_DDR#1 <7>
Place near DIMM
105 CK0# CK1# 106
DDR_A_MA10 107 VDD11 VDD12 108 DDR_A_BS1 (0.1uF_402_10V)*4
A10/AP BA1 DDR_A_BS1 <7>
<7> DDR_A_BS0 DDR_A_BS0 109 110 DDR_A_RAS# +1.5V
BA0 RAS# DDR_A_RAS# <7>
111 112
DDR_A_WE# 113 VDD13 VDD14 114 DDR_CS0_DIMMA#
<7> DDR_A_WE# WE# S0# DDR_CS0_DIMMA# <7>

1
DDR_A_CAS# 115 116 M_ODT0
<7> DDR_A_CAS# CAS# ODT0 M_ODT0 <7>
117 118 R80 +1.5V
DDR_A_MA13 119 VDD15 VDD16 120 M_ODT1 1K_0402_1%
A13 ODT1 M_ODT1 <7>
<7> DDR_CS1_DIMMA# DDR_CS1_DIMMA# 121 122
S1# NC2

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
123 124

2
VDD17 VDD18

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K
125 126 +VREF_CA 1
NCTEST VREF_CA

C151

C142

C143

C152

C144

C145

C153

C146

C154

C155

C147

C156
127 128 1 1 1 1 1 1 1 1 1 1 1 1
VSS27 VSS28

0.1U_0402_10V6K

2.2U_0603_6.3V6K
DDR_A_D32 129 130 DDR_A_D36 + C148
DQ32 DQ36

1
C149

C150
B DDR_A_D33 131 132 DDR_A_D37 1 1 220U_6.3V_M B
133 DQ33 DQ37 134 @ @
DDR_A_DQS#4 135 VSS29 VSS30 136 R81 2 2 2 2 2 2 2 2 2 2 2 2 2
DDR_A_DQS4 137 DQS#4 DM4 138 1K_0402_1%
139 DQS4 VSS31 140 DDR_A_D38 2 2

2
DDR_A_D34 141 VSS32 DQ38 142 DDR_A_D39
DDR_A_D35 143 DQ34 DQ39 144
145 DQ35 VSS33 146 DDR_A_D44
DDR_A_D40 147 VSS34 DQ44 148 DDR_A_D45
DDR_A_D41 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDR_A_DQS#5
153 VSS36 DQS#5 154 DDR_A_DQS5
155 DM5 DQS5 156
DDR_A_D42 157 VSS37 VSS38 158 DDR_A_D46
DDR_A_D43 159 DQ42 DQ46 160 DDR_A_D47
Layout Note:
161 DQ43 DQ47 162 Place near DIMM
DDR_A_D48 163 VSS39 VSS40 164 DDR_A_D52
DDR_A_D49 165 DQ48 DQ52 166 DDR_A_D53
167 DQ49 DQ53 168
DDR_A_DQS#6 169 VSS41 VSS42 170
DDR_A_DQS6 171 DQS#6 DM6 172 +0.75VS
173 DQS6 VSS43 174 DDR_A_D54
DDR_A_D50 175 VSS44 DQ54 176 DDR_A_D55
DDR_A_D51 177 DQ50 DQ55 178
179 DQ51 VSS45 180 DDR_A_D60
VSS46 DQ60

C288

1U_0402_6.3V6K
C158

1U_0402_6.3V6K
C159

1U_0402_6.3V6K
C160

1U_0402_6.3V6K
DDR_A_D56 181 182 DDR_A_D61
DDR_A_D57 183 DQ56 DQ61 184
DQ57 VSS47 1 1 1 1
185 186 DDR_A_DQS#7
187 VSS48 DQS#7 188 DDR_A_DQS7
189 DM7 DQS7 190
DDR_A_D58 191 VSS49 VSS50 192 DDR_A_D62 2 2 2 2
DDR_A_D59 193 DQ58 DQ62 194 DDR_A_D63
A 1 R82 2 195 DQ59 DQ63 196 A
10K_0402_5% 197 VSS51 VSS52 198
199 SA0 EVENT# 200 SMB_DATA_S3
+3VS VDDSPD SDA SMB_DATA_S3 <13,15,38,46>
2.2U_0603_6.3V6K

0.1U_0402_10V6K

201 202 SMB_CLK_S3

SA1 SCL SMB_CLK_S3 <13,15,38,46>
C290

C162

1 203 204 +0.75VS

VTT1 VTT2
1
10K_0402_5%
R83

1
205 206 0.65A@0.75V
G1 G2
2 Security Classification LC Future Center Secret Data Title
LCN_DAN06-K4806-0103
2
Issued Date 2012/07/01 Deciphered Date 2014/07/01 DDRIII-SODIMM SLOT1
2

ME@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
LA-8692P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Tuesday, June 05, 2012 Sheet 12 of 66
5 4 3 2 1
 5 4 3 2 1

+1.5V <7> DDR_B_D[0..63]

<7> DDR_B_DQS[0..7]
3A@1.5V

1
+1.5V
+VREF_DQ_DIMMB <7> DDR_B_DQS#[0..7]
R84
1K_0402_1% +1.5V
<7> DDR_B_MA[0..15]
JDIMM2

0.047U_0402_16V4Z
0.047U_0402_16V4Z

0.047U_0402_16V4Z
2

For RF request
+VREF_DQ_DIMMB 1 2 1
3 VREF_DQ VSS1 4 DDR_B_D4 1 1
VSS2 DQ4

C1068
C1069
2.2U_0603_6.3V6K

0.1U_0402_10V6K

C1067
DDR_B_D0 5 6 DDR_B_D5
DQ0 DQ5

1
1 1 DDR_B_D1 7 8 @ @ @
DQ1 VSS3 2

C289
9 10 DDR_B_DQS#0 2 2
VSS4 DQS#0

C157
D R85 11 12 DDR_B_DQS0 D
1K_0402_1% 13 DM0 DQS0 14
2 2 DDR_B_D2 15 VSS5 VSS6 16 DDR_B_D6
2 DDR_B_D3 17 DQ2 DQ6 18 DDR_B_D7
19 DQ3 DQ7 20
DDR_B_D8 21 VSS7 VSS8 22 DDR_B_D12
DDR_B_D9 23 DQ8 DQ12 24 DDR_B_D13
25 DQ9 DQ13 26
DDR_B_DQS#1 27 VSS9 VSS10 28
DDR_B_DQS1 29 DQS#1 DM1 30 DDR3_DRAMRST#
DQS1 RESET# DDR3_DRAMRST# <12,7>
31 32
DDR_B_D10 33 VSS11 VSS12 34 DDR_B_D14
DDR_B_D11 35 DQ10 DQ14 36 DDR_B_D15
37 DQ11 DQ15 38
DDR_B_D16 39 VSS13 VSS14 40 DDR_B_D20
DDR_B_D17 41 DQ16 DQ20 42 DDR_B_D21
43 DQ17 DQ21 44
DDR_B_DQS#2 45 VSS15 VSS16 46
DDR_B_DQS2 47 DQS#2 DM2 48
49 DQS2 VSS17 50 DDR_B_D22
DDR_B_D18 51 VSS18 DQ22 52 DDR_B_D23
DDR_B_D19 53 DQ18 DQ23 54
55 DQ19 VSS19 56 DDR_B_D28
DDR_B_D24 57 VSS20 DQ28 58 DDR_B_D29
DDR_B_D25 59 DQ24 DQ29 60
61 DQ25 VSS21 62 DDR_B_DQS#3
63 VSS22 DQS#3 64 DDR_B_DQS3
65 DM3 DQS3 66
DDR_B_D26 67 VSS23 VSS24 68 DDR_B_D30
DDR_B_D27 69 DQ26 DQ30 70 DDR_B_D31
71 DQ27 DQ31 72
VSS25 VSS26
C C

<7> DDR_CKE2_DIMMB DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB

CKE0 CKE1 DDR_CKE3_DIMMB <7>
75 76
77 VDD1 VDD2 78 DDR_B_MA15
DDR_B_BS2 79 NC1 A15 80 DDR_B_MA14
<7> DDR_B_BS2 BA2 A14
81 82
DDR_B_MA12 83 VDD3 VDD4 84 DDR_B_MA11
DDR_B_MA9 85 A12/BC# A11 86 DDR_B_MA7
87 A9 A7 88
DDR_B_MA8 89 VDD5 VDD6 90 DDR_B_MA6
DDR_B_MA5 91 A8 A6 92 DDR_B_MA4
93 A5 A4 94
DDR_B_MA3 95 VDD7 VDD8 96 DDR_B_MA2
DDR_B_MA1 97 A3 A2 98 DDR_B_MA0
99 A1 A0 100
M_CLK_DDR2 101 VDD9 VDD10 102 M_CLK_DDR3
<7>
<7>
M_CLK_DDR2
M_CLK_DDR#2 M_CLK_DDR#2 103 CK0 CK1 104 M_CLK_DDR#3
M_CLK_DDR3 <7> Layout Note: (10uF_0603_6.3V)*8
CK0# CK1# M_CLK_DDR#3 <7>
105 106 Place near DIMM
DDR_B_MA10 107 VDD11 VDD12 108 DDR_B_BS1
<7> DDR_B_BS0 DDR_B_BS0 109 A10/AP BA1 110 DDR_B_RAS#
DDR_B_BS1 <7> +1.5V (0.1uF_402_10V)*4
BA0 RAS# DDR_B_RAS# <7>
111 112
DDR_B_WE# 113 VDD13 VDD14 114 DDR_CS2_DIMMB#
<7> DDR_B_WE# WE# S0# DDR_CS2_DIMMB# <7>

1
<7> DDR_B_CAS# DDR_B_CAS# 115 116 M_ODT2
CAS# ODT0 M_ODT2 <7>
117 118 R86
DDR_B_MA13 119 VDD15 VDD16 120 M_ODT3 1K_0402_1% +1.5V
A13 ODT1 M_ODT3 <7>
<7> DDR_CS3_DIMMB# DDR_CS3_DIMMB# 121 122
123 S1# NC2 124

2
VDD17 VDD18

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
125 126 +VREF_CB
NCTEST VREF_CA

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K
127 128
VSS27 VSS28

2.2U_0603_6.3V6K

C161

C282

C163

C164

C165

C166

C167

C168

C169

C170

C171

C172
DDR_B_D32 129 130 DDR_B_D36 1 1 1 1 1 1 1 1 1 1 1 1
DQ32 DQ36

1
C280
DDR_B_D33 131 132 DDR_B_D37 1 1
DQ33 DQ37

C281
B 133 134 B
DDR_B_DQS#4 135 VSS29 VSS30 136 R87 @ @
DDR_B_DQS4 137 DQS#4 DM4 138 1K_0402_1% 2 2 2 2 2 2 2 2 2 2 2 2
139 DQS4 VSS31 140 DDR_B_D38 2 2

2
DDR_B_D34 141 VSS32 DQ38 142 DDR_B_D39
DDR_B_D35 143 DQ34 DQ39 144
145 DQ35 VSS33 146 DDR_B_D44
DDR_B_D40 147 VSS34 DQ44 148 DDR_B_D45
DDR_B_D41 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDR_B_DQS#5
153 VSS36 DQS#5 154 DDR_B_DQS5
155 DM5 DQS5 156
DDR_B_D42 157 VSS37 VSS38 158 DDR_B_D46
DDR_B_D43 159 DQ42 DQ46 160 DDR_B_D47
Layout Note:
161 DQ43 DQ47 162 Place near DIMM
DDR_B_D48 163 VSS39 VSS40 164 DDR_B_D52
DDR_B_D49 165 DQ48 DQ52 166 DDR_B_D53
167 DQ49 DQ53 168
DDR_B_DQS#6 169 VSS41 VSS42 170
DDR_B_DQS6 171 DQS#6 DM6 172 +0.75VS
173 DQS6 VSS43 174 DDR_B_D54
DDR_B_D50 175 VSS44 DQ54 176 DDR_B_D55
DDR_B_D51 177 DQ50 DQ55 178
179 DQ51 VSS45 180 DDR_B_D60
VSS46 DQ60

C173

1U_0402_6.3V6K
C174

1U_0402_6.3V6K
C175

1U_0402_6.3V6K
C176

1U_0402_6.3V6K
DDR_B_D56 181 182 DDR_B_D61
DDR_B_D57 183 DQ56 DQ61 184
DQ57 VSS47 1 1 1 1
185 186 DDR_B_DQS#7
187 VSS48 DQS#7 188 DDR_B_DQS7
189 DM7 DQS7 190
DDR_B_D58 191 VSS49 VSS50 192 DDR_B_D62 2 2 2 2
DDR_B_D59 193 DQ58 DQ62 194 DDR_B_D63
195 DQ59 DQ63 196
A 1 R95 2 197 VSS51 VSS52 198 A
10K_0402_5% 199 SA0 EVENT# 200 SMB_DATA_S3
VDDSPD SDA SMB_DATA_S3 <12,15,38,46>
1 2 201 202 SMB_CLK_S3
+3VS SA1 SCL SMB_CLK_S3 <12,15,38,46>
2.2U_0603_6.3V6K

0.1U_0402_10V6K

R97 10K_0402_5% 203 204 +0.75VS

VTT1 VTT2 0.65A@0.75V
C178

1 1
C177

205 206
G1 G2
TYCO_2-2013287-1 Title
2 2 Security Classification LC Future Center Secret Data
ME@ Issued Date 2012/07/01 Deciphered Date 2014/07/01 DDRIII-SODIMM SLOT2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
LA-8692P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Tuesday, June 05, 2012 Sheet 13 of 66
5 4 3 2 1
 5 4 3 2 1

PCH_RTCX1

W=20mils W=20mils 1 2 PCH_RTCX2

R98 10M_0402_5%
+RTCVCC +RTCBATT
Y1
R99 1 2
1K_0402_5%
1 2 32.768KHZ_12.5PF_CM31532768DZFT

18P_0402_50V8J
1
C179 1 1
1U_0603_10V6K C181
C180 18P_0402_50V8J
2
D 2 2 D

CMOS
+RTCVCC
U4A
R101 1 2 1M_0402_5% SM_INTRUDER#
+RTCVCC PCH_RTCX1 A20 C38 LPC_AD0
1 RTCX1 FWH0 / LAD0 LPC_AD0 <38,45>

1
R102 1 2 330K_0402_5% PCH_INTVRMEN A38 LPC_AD1
FWH1 / LAD1 LPC_AD1 <38,45>

LPC
C183 JCMOS PCH_RTCX2 C20 B37 LPC_AD2 EC and Mini card debug port
RTCX2 FWH2 / LAD2 C37 LPC_AD3 LPC_AD2 <38,45>
1U_0603_10V6K SHORT PADS
LPC_AD3 <38,45>

2
1 2 2 PCH_RTCRST# D20 FWH3 / LAD3
R103 20K_0402_5% RTCRST# D36 LPC_FRAME#
INTVRMEN FWH4 / LFRAME# LPC_FRAME# <38,45>
Integrated
1 2 PCH_SRTCRST# G22
SRTCRST#
* HL Integrated VRM enable R100 20K_0402_5% 1 LDRQ0#
E36

1
SM_INTRUDER# K22 K36

RTC
VRM disable INTRUDER# LDRQ1# / GPIO23
C182 JME +3VS
(INTVRMEN should always be pull high.) 1U_0603_10V6K PCH_INTVRMEN
SHORT PADS C17 V5 R104 2 1 10K_0402_5%

2
2 INTVRMEN SERIRQ
SERIRQ
SERIRQ <45>
AM3 SATA_DTX_C_IRX_N0
+3VS SATA0RXN SATA_DTX_C_IRX_N0 <38>
HDA_BIT_CLK N34 AM1 SATA_DTX_C_IRX_P0
HDA_BCLK SATA0RXP SATA_DTX_C_IRX_P0 <38>
AP7 SATA_ITX_C_DRX_N0 0.01U_0402_16V7K 2 1 C184 SATA_ITX_DRX_N0 SSD

SATA 6G
SATA0TXN SATA_ITX_DRX_N0 <38>
R105 1 @ 2 1K_0402_5% HDA_SPKR HDA_SYNC L34 AP5 SATA_ITX_C_DRX_P0 0.01U_0402_16V7K 2 1 C185 SATA_ITX_DRX_P0 SATA_ITX_DRX_P0 <38>
HDA_SYNC SATA0TXP
HIGH= Enable ( No Reboot ) HDA_SPKR T10 AM10 SATA_DTX_C_IRX_N1
<43> HDA_SPKR SPKR SATA1RXN SATA_DTX_C_IRX_N1 <42>
LOW= Disable (Default) AM8 SATA_DTX_C_IRX_P1
* HDA_RST# K34
HDA_RST#
SATA1RXP
SATA1TXN
AP11 SATA_ITX_C_DRX_N1 0.01U_0402_16V7K 2 1 C273 SATA_ITX_DRX_N1
SATA_DTX_C_IRX_P1
SATA_ITX_DRX_N1
<42>
<42> HDD
AP10 SATA_ITX_C_DRX_P1 0.01U_0402_16V7K 2 1 C272 SATA_ITX_DRX_P1
SATA1TXP SATA_ITX_DRX_P1 <42>
C +3V_PCH HDA_SDIN0 E34 AD7 SATA_DTX_C_IRX_N2 C
<43> HDA_SDIN0 HDA_SDIN0 SATA2RXN SATA_DTX_C_IRX_N2 <42>
AD5 SATA_DTX_C_IRX_P2
SATA2RXP SATA_DTX_C_IRX_P2 <42>
R106 2 @ 1 1K_0402_5% HDA_SDOUT G34 AH5 SATA_ITX_C_DRX_N2 0.01U_0402_16V7K 2 1 C186 SATA_ITX_DRX_N2_CONN
HDA_SDIN1 SATA2TXN AH4 SATA_ITX_DRX_N2_CONN <42>ODD
SATA_ITX_C_DRX_P2 0.01U_0402_16V7K 2 1 C187 SATA_ITX_DRX_P2_CONN SATA_ITX_DRX_P2_CONN <42>
C34 SATA2TXP
Low = Disabled (Default)
* HDA_SDIN2 AB8

IHDA
High = Enabled [Flash Descriptor Security Overide] A34 SATA3RXN AB10
HDA_SDIN3 SATA3RXP AF3
SATA3TXN AF1
ME_FLASH 1 R109 2 HDA_SDOUT A36 SATA3TXP
+3V_PCH <45> ME_FLASH HDA_SDO Y7

SATA
R_short 0_0402_5% SATA4RXN Y5
R108 2 1 1K_0402_5% HDA_SYNC R107 1 @ 2 1K_0402_1% PCH_GPIO33 C36 SATA4RXP AD3
HDA_DOCK_EN# / GPIO33 SATA4TXN AD1
R317 2 1 10K_0402_5% PCH_GPIO13 N32 SATA4TXP
This signal has a weak internal pull-down +3V_PCH HDA_DOCK_RST# / GPIO13 Y3
SATA5RXN Y1
@

2MB P/N : SA00003FO10

On Die PLL VR Select is supplied by SATA5RXP AB3
1.5V when smapled high 2 1 PCH_JTAG_TCK J3 SATA5TXN AB1
* 1.8V when sampled low
JTAG_TCK SATA5TXP
51_0402_5% PCH_JTAG_TMS H7 Y11 R111 +3VS
Needs to be pulled High for Chief River platfrom JTAG_TMS SATAICOMPO 37.4_0402_1% +1.05VS_VCC_SATA

JTAG
R110
PCH_JTAG_TDI K5 Y10 SATA_COMP 1 2
JTAG_TDI SATAICOMPI
R112 PCH_JTAG_TDO H1
+5VS JTAG_TDO +1.05VS_SATA3 R292 1 2 SPI_WP#_1
33_0402_5% AB12 R113
SATA3RCOMPO 3.3K_0402_5%
1 2 HDA_BIT_CLK 49.9_0402_1%
43> HDA_BITCLK_AUDIO
2
G

R114 Q10 AB13 SATA3_COMP 1 2 +3VS

SATA3COMPI R246 1 2 SPI_HOLD#_1
33_0402_5% BSS138_NL_SOT23-3 3.3K_0402_5%
1 2 HDA_SYNC_R 3 1 HDA_SYNC
<43> HDA_SYNC_AUDIO C275
R116 SPI_CLK_PCH T3 AH1 RBIAS_SATA3 R115 1 2 750_0402_1%
S

SPI_CLK SATA3RBIAS 1 2
1

1M_0402_5%

33_0402_5% R303
B 1 2 HDA_RST# SPI_SB_CS0# Y14 B
<43> HDA_RST_AUDIO# SPI_CS0# R_short 0_0402_5% U9 0.1U_0402_16V4Z
R118 HDD_LED# SPI_CS1# 1 2 SPI_CS1#_R 1 8
HDD_LED# <47> R299
R1353

33_0402_5% SPI_CS1# T1 1 2 SPI_SO_L1 2 CS# VCC 7

SPI_CS1# SPI_SO_R SPI_HOLD#_1 33_0402_5%
SPI

1 2 HDA_SDOUT P3 2 R120 1 SPI_WP#_1 3 DO(IO1) HOLD#(IO3) 6 SPI_CLK_PCH_1 1 2SPI_CLK_PCH

43> HDA_SDOUT_AUDIO +3VS
2

SATALED# 10K_0402_5% WP#(IO2) CLK

33_0402_5% 4 5 SPI_SI_R1 1 2 SPI_SI
SPI_SI V4 V14 PCH_GPIO21 2 R119 1 R294 GND DI(IO0)
SPI_MOSI SATA0GP / GPIO21 +3VS
10K_0402_5% W25Q16BVSSIG_SO8 33_0402_5%
SPI_SO_R U3 P1 SATA_DET# R204
+3V_PCH +3V_PCH +3V_PCH SPI_MISO SATA1GP / GPIO19 SATA_DET# <38>

4MB P/N : SA00003K800

PANTHER-POINT_FCBGA989 R316 2 1 10K_0402_5%
+3VS
1

@ R121 @ R122 @ R123

200_0402_5% 200_0402_5% 200_0402_5% SPI_CLK_PCH
+3VS
2

PCH_JTAG_TDO PCH_JTAG_TMS PCH_JTAG_TDI

1
1

R127 1 2 SPI_WP# R124

R125 R126 R128 3.3K_0402_5% 33_0402_5%
100_0402_1% 100_0402_1% 100_0402_1% @
R129 1 2 SPI_HOLD# +3VS

2
@ @ @ 3.3K_0402_5%
2

C191
1 2 C190
R130
22P_0402_50V8J
R_short 0_0402_5% U5 0.1U_0402_16V4Z @
SPI_SB_CS0# 1 2 SPI_SB_CS0#_R 1 8 R298
SPI_SO_R 1 2 SPI_SO_L 2 CS# VCC 7 SPI_HOLD# 33_0402_5%
SPI_WP# 3 DO HOLD# 6 SPI_CLK_PCH_0 1 2 SPI_CLK_PCH
33_0402_5% 4 WP# CLK 5 SPI_SI_R 1 2 SPI_SI
GND DI
R131
A W25Q32BVSSIG_SO8 33_0402_5% A
R133

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 PCH (1/9) SATA,HDA,SPI, LPC, XDP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-8692P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Tuesday, June 05, 2012 Sheet 14 of 66
5 4 3 2 1
 5 4 3 2 1

2N7002KDWH Q60A
Vth= min 1V, max 2.5V 2N7002KDWH_SOT363-6
U4B
ESD 2KV
6 1 SMB_CLK_S3

S
D
SMB_CLK_S3 <12,13,38,46>
PCIE_PRX_DTX_N1 BG34 10K_0402_5%
<39> PCIE_PRX_DTX_N1 PERN1
LAN PCIE_PRX_DTX_P1 BJ34 E12 PCH_GPIO11 2 1
<39> PCIE_PRX_DTX_P1 PERP1 SMBALERT# / GPIO11 +3V_PCH
C192 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_N1 AV32 2.2K_0402_5% 2.2K_0402_5%
<39> PCIE_PTX_C_DRX_N1 PETN1 DIMM1

G
C193 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_P1 AU32 H14 PCH_SMBCLK R134 1 R136 2 1 2 R137

2
<39> PCIE_PTX_C_DRX_P1 PETP1 SMBCLK

<38> PCIE_PRX_DTX_N2 PCIE_PRX_DTX_N2 BE34

PERN2 SMBDATA
C9 PCH_SMBDATA
+3V_PCH
1
R135
2
+3VS
1 2 DIMM2
PCIE_PRX_DTX_P2 BF34 R138
MINI CARD

5
D <38> PCIE_PRX_DTX_P2 PERP2 D
2.2K_0402_5% 2.2K_0402_5%

G
WLAN C194 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_N2 BB32
<38> PCIE_PTX_C_DRX_N2 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_P2 AY32 PETN2
C195
<38> PCIE_PTX_C_DRX_P2 PETP2 A12

SMBUS
DRAMRST_CNTRL_PCH
PCIE_PRX_DTX_N3 BG36 SML0ALERT# / GPIO60 DRAMRST_CNTRL_PCH <7> 3 4 SMB_DATA_S3
<38> PCIE_PRX_DTX_N3 PERN3 SMB_DATA_S3 <12,13,38,46>
TV@ PCIE_PRX_DTX_P3 BJ36 C8 SML0CLK 1 2

S
<38> PCIE_PRX_DTX_P3 PERP3 SML0CLK Q60B
TV <38> PCIE_PTX_C_DRX_N3
C292 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_N3 AV34
PETN3
R335 2.2K_0402_5% 2 R329 1
+3V_PCH 2N7002KDWH_SOT363-6
<38> PCIE_PTX_C_DRX_P3 C285 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_P3 AU34 G12 SML0DATA 1 2
+3V_PCH 1K_0402_5%
PETP3 SML0DATA R336 2.2K_0402_5%
TV@ Q61A
PCIE_PRX_DTX_N4 BF36
<44> PCIE_PRX_DTX_N4 PERN4 2N7002KDWH_SOT363-6
PCIE_PRX_DTX_P4 BE36
<44> PCIE_PRX_DTX_P4 PERP4
Card Reader C277 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_N4 AY34 C13 PCH_HOT# 2 1
<44> PCIE_PTX_C_DRX_N4 PETN4 SML1ALERT# / PCHHOT# / GPIO74 +3V_PCH 6 1 EC_SMB_CK2

S
D
C276 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_P4 BB34 R140 10K_0402_5% EC_SMB_CK2 <23,32,41,45>
<44> PCIE_PTX_C_DRX_P4 PETP4 E14 SML1CLK
BG37 SML1CLK / GPIO58

PCI-E*
BH37 PERN5 M16 SML1DATA 2.2K_0402_5%
AY36 PERP5 SML1DATA / GPIO75 1 R141 2 VGA

G
2
BB36 PETN5
PETP5 +3V_PCH
1 2
+3VS EC

5
BJ38 R142
thermal sensor

G
BG38 PERN6 2.2K_0402_5%
AU36 PERP6 M7

Controller
AV36 PETN6 CL_CLK1
PETP6 3 4 EC_SMB_DA2
EC_SMB_DA2 <23,32,41,45>

S
Link
BG40 T11
BJ40 PERN7 CL_DATA1
PERP7 2N7002KDWH_SOT363-6
AY40
PETN7 Q61B
BB40 P10
PETP7 CL_RST1#
BE38
BC38 PERN8
AW38 PERP8 CLK_REQ_GPU#_R <23>
AY38 PETN8
C PETP8 C
10K_0402_5% R202
M10 CLK_REQ_GPU#_R 1 2
PEG_A_CLKRQ# / GPIO47 +3V_PCH
CLK_PCIE_LAN# Y40
<39> CLK_PCIE_LAN# Y39 CLKOUT_PCIE0N
LAN CLK_PCIE_LAN
<39> CLK_PCIE_LAN CLKOUT_PCIE0P AB37 CLK_PCIE_VGA#
J2 CLKOUT_PEG_A_N AB38 CLK_PCIE_VGA# <23>
CLKREQ_LAN# CLK_PCIE_VGA

CLOCKS
<39> CLKREQ_LAN# 2 1 10K_0402_5% PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P CLK_PCIE_VGA <23>
+3V_PCH R152

CLK_PCIE_WLAN1# AB49 AV22 CLK_CPU_DMI#

<38> CLK_PCIE_WLAN1# CLK_PCIE_WLAN1 AB47 CLKOUT_PCIE1N CLKOUT_DMI_N AU22 CLK_CPU_DMI CLK_CPU_DMI# <6>
<38> CLK_PCIE_WLAN1 CLKOUT_PCIE1P CLKOUT_DMI_P CLK_CPU_DMI <6>
WLAN
WLAN_CLKREQ1# M1
<38> WLAN_CLKREQ1# PCIECLKRQ1# / GPIO18
R158 2 1 10K_0402_5% AM12
+3VS CLKOUT_DP_N AM13
CLK_PCIE_TV# AA48 CLKOUT_DP_P
<38> CLK_PCIE_TV# AA47 CLKOUT_PCIE2N
CLK_PCIE_TV
<38> CLK_PCIE_TV CLKOUT_PCIE2P
TV CLKIN_DMI_N
BF18 CLK_BUF_CPU_DMI# R155 1 2 10K_0402_5%
<38> CLKREQ_TV# CLKREQ_TV# V10 BE18 CLK_BUF_CPU_DMI R157 1 2 10K_0402_5%
2 1 10K_0402_5% PCIECLKRQ2# / GPIO20 CLKIN_DMI_P
+3VS R308
CLK_PCIE_CARD_PCH# Y37 BJ30 CLKIN_DMI2# R159 1 2 10K_0402_5%
<44> CLK_PCIE_CARD_PCH# Y36 CLKOUT_PCIE3N CLKIN_GND1_N BG30
CLK_PCIE_CARD_PCH CLKIN_DMI2 R160 1 2 10K_0402_5%
<44> CLK_PCIE_CARD_PCH CLKOUT_PCIE3P CLKIN_GND1_P
Card Reader
R168 2 1 10K_0402_5% PCH_GPIO25 A8
+3V_PCH PCIECLKRQ3# / GPIO25 G24 CLK_BUF_DREF_96M# R162 1 2 10K_0402_5%
CLKIN_DOT_96N E24 CLK_BUF_DREF_96M R163 1 2 10K_0402_5%
Y43 CLKIN_DOT_96P
Y45 CLKOUT_PCIE4N Change C196, C197 value of Cap from 10pF to 27pF
CLKOUT_PCIE4P AK7 CLK_BUF_PCIE_SATA# R164 1 2 10K_0402_5%
R165 2 1 10K_0402_5% PCH_GPIO26 L12 CLKIN_SATA_N AK5 CLK_BUF_PCIE_SATA R166 1 2 10K_0402_5%
+3V_PCH PCIECLKRQ4# / GPIO26 CLKIN_SATA_P
B XTAL25_IN B
V45 K45 CLK_BUF_ICH_14M R167 1 2 10K_0402_5%
V46 CLKOUT_PCIE5N REFCLK14IN
CLKOUT_PCIE5P XTAL25_OUT 1 2
2 1 10K_0402_5% PCH_GPIO44 L14 H45 CLK_PCI_LPBACK R169 1M_0402_5%
+3V_PCH R147
PCIECLKRQ5# / GPIO44 CLKIN_PCILOOPBACK CLK_PCI_LPBACK <18> Y2
4 3
NC OSC
CLK_PCIE_2VGA# AB42 V47 XTAL25_IN
<32> CLK_PCIE_2VGA# CLKOUT_PEG_B_N XTAL25_IN 1 1 2 1
CLK_PCIE_2VGA AB40 V49 XTAL25_OUT OSC NC
<32> CLK_PCIE_2VGA CLKOUT_PEG_B_P XTAL25_OUT
2 1 10K_0402_5% E6 +1.05VS_VCCDIFFCLKN C196 C197
R170 CLK2_REQ_GPU#_R R171
+3V_PCH PEG_B_CLKRQ# / GPIO56 27P_0402_50V8J 25MHZ_12PF_X3G025000DC1H~D 27P_0402_50V8J
90.9_0402_1% 2 2
2nd VGA Y47 XCLK_RCOMP 1 2
<32> CLK2_REQ_GPU#_R V40 XCLK_RCOMP
V42 CLKOUT_PCIE6N
CLKOUT_PCIE6P
S_DGPU_GC6_EN
R172 2 1 10K_0402_5% PCH_GPIO45 T13 S_DGPU_GC6_EN <32>
+3V_PCH PCIECLKRQ6# / GPIO45
V38 K43
V37 CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64
FLEX CLOCKS

CLKOUT_PCIE7P F47 @R175

@ R175 @C198
@ C198
CLKOUTFLEX1 / GPIO65 R1592 1 2 10K_0402_5% 33_0402_5% 22P_0402_50V8J
R174 2 1 10K_0402_5% PCH_GPIO46 K12 +3VS
+3V_PCH PCIECLKRQ7# / GPIO46 CLK_BUF_ICH_14M 2 1 1 2
H47 S_DGPU_RST_R R1593 1 2 R_short 0_0402_5%
CLK_BCLK_ITP# AK14 CLKOUTFLEX2 / GPIO66 S_DGPU_RST <18,32>
<6> CLK_BCLK_ITP# AK13 CLKOUT_ITPXDP_N K49
CLK_BCLK_ITP PCH_GPIO67
<6> CLK_BCLK_ITP CLKOUT_ITPXDP_P CLKOUTFLEX3 / GPIO67 PCH_GPIO67 <19> Reserve for EMI please close to PCH

PANTHER-POINT_FCBGA989
for XDP BIOS Request SKU ID
@ R176 @ C199
33_0402_5% 22P_0402_50V8J
CLK_PCI_LPBACK 2 1 1 2
A A

Reserve for EMI please close to PCH

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 PCH (2/9) PCIE, SMBUS, CLK
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-8692P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Tuesday, June 05, 2012 Sheet 15 of 66
5 4 3 2 1
 5 4 3 2 1

D D

U4C

DMI_CTX_PRX_N0 BC24 BJ14 FDI_CTX_PRX_N0

<5> DMI_CTX_PRX_N0 DMI0RXN FDI_RXN0 FDI_CTX_PRX_N0 <5>
DMI_CTX_PRX_N1 BE20 AY14 FDI_CTX_PRX_N1
<5> DMI_CTX_PRX_N1 DMI1RXN FDI_RXN1 FDI_CTX_PRX_N1 <5>
DMI_CTX_PRX_N2 BG18 BE14 FDI_CTX_PRX_N2
<5> DMI_CTX_PRX_N2 DMI2RXN FDI_RXN2 FDI_CTX_PRX_N2 <5>
DMI_CTX_PRX_N3 BG20 BH13 FDI_CTX_PRX_N3
<5> DMI_CTX_PRX_N3 DMI3RXN FDI_RXN3 FDI_CTX_PRX_N3 <5>
BC12 FDI_CTX_PRX_N4
FDI_RXN4 FDI_CTX_PRX_N4 <5>
DMI_CTX_PRX_P0 BE24 BJ12 FDI_CTX_PRX_N5
<5> DMI_CTX_PRX_P0 DMI0RXP FDI_RXN5 FDI_CTX_PRX_N5 <5>
DMI_CTX_PRX_P1 BC20 BG10 FDI_CTX_PRX_N6
<5> DMI_CTX_PRX_P1 DMI1RXP FDI_RXN6 FDI_CTX_PRX_N6 <5>
DMI_CTX_PRX_P2 BJ18 BG9 FDI_CTX_PRX_N7
<5> DMI_CTX_PRX_P2 DMI2RXP FDI_RXN7 FDI_CTX_PRX_N7 <5>
DMI_CTX_PRX_P3 BJ20
<5> DMI_CTX_PRX_P3 DMI3RXP
+3VS BG14 FDI_CTX_PRX_P0
FDI_RXP0 FDI_CTX_PRX_P0 <5>
DMI_CRX_PTX_N0 AW24 BB14 FDI_CTX_PRX_P1
<5> DMI_CRX_PTX_N0 DMI0TXN FDI_RXP1 FDI_CTX_PRX_P1 <5>
DMI_CRX_PTX_N1 AW20 BF14 FDI_CTX_PRX_P2
<5> DMI_CRX_PTX_N1 DMI1TXN FDI_RXP2 FDI_CTX_PRX_P2 <5>
1 DMI_CRX_PTX_N2 BB18 BG13 FDI_CTX_PRX_P3
C1060 <5> DMI_CRX_PTX_N2 DMI2TXN FDI_RXP3 FDI_CTX_PRX_P3 <5>
DMI_CRX_PTX_N3 AV18 BE12 FDI_CTX_PRX_P4
0.1U_0402_16V4Z <5> DMI_CRX_PTX_N3 DMI3TXN FDI_RXP4 FDI_CTX_PRX_P4 <5>

DMI
FDI
BG12 FDI_CTX_PRX_P5
FDI_RXP5 FDI_CTX_PRX_P5 <5>
DMI_CRX_PTX_P0 AY24 BJ10 FDI_CTX_PRX_P6
2 <5> DMI_CRX_PTX_P0 DMI0TXP FDI_RXP6 FDI_CTX_PRX_P6 <5>
U6 DMI_CRX_PTX_P1 AY20 BH9 FDI_CTX_PRX_P7
<5> DMI_CRX_PTX_P1 DMI1TXP FDI_RXP7 FDI_CTX_PRX_P7 <5>
DMI_CRX_PTX_P2 AY18
<5> DMI_CRX_PTX_P2 DMI2TXP
5

MC74VHC1G08DFT2G SC70 5P DMI_CRX_PTX_P3 AU18

<5> DMI_CRX_PTX_P3 DMI3TXP
VGATE 2 AW16 FDI_INT
P

60> VGATE B FDI_INT FDI_INT <5>

4
PCH_PWROK 1 Y SYS_PWROK <6> +1.05VS BJ24 AV12 FDI_FSYNC0
A DMI_ZCOMP FDI_FSYNC0 FDI_FSYNC0 <5>
G

+RTCVCC
1 2 DMI_IRCOMP BG25 BC10 FDI_FSYNC1
FDI_FSYNC1 <5>
3

DMI_IRCOMP FDI_FSYNC1
1

R177 49.9_0402_1%

1
R180 1 2 RBIAS_CPY BH21 AV14 FDI_LSYNC0
C DMI2RBIAS FDI_LSYNC0 FDI_LSYNC0 <5> C
100K_0402_1% R178 750_0402_1% R179
4mil width and place BB10 FDI_LSYNC1 330K_0402_5%
@ FDI_LSYNC1 FDI_LSYNC1 <5>
within 500mil of the PCH
2

2
For Deep S3 DSWODVREN - On Die DSW VR Enable
DSWVRMEN
A18 DSWODVREN * H Enable
L Disable
R1457 0_0402_5% 0_0402_5%

System Power Management

1
2 1 SUSACK#_R C12 E22 PCH_DPWROK_R 1 2 DPWROK_EC
<45> SUSACK# SUSACK# DPWROK DPWROK_EC <45>
DS3@ R185 R181 R183
0_0402_5% 330K_0402_5%
For Deep S3 2 1 SYS_RST# K3 B9 WAKE# 1 2
+3VS SYS_RESET# WAKE# PCIE_WAKE# <19,38,39> @
R184 10K_0402_5% 1 2 10K_0402_5%
+3V_PCH

2
R186
SYS_PWROK P12 N3 PM_CLKRUN# 1 2
SYS_PWROK CLKRUN# / GPIO32 R253 10K_0402_5%

<45> PCH_PWROK R190 1 2 0_0402_5% PWROK L22 G8 SUS_STAT# PAD T76

PWROK SUS_STAT# / GPIO61

2 1 APWROK L10 N14 SUSCLK PAD T77

R191 0_0402_5% APWROK SUSCLK / GPIO62

PM_DRAM_PWRGD B13 D10 PM_SLP_S5# PAD T78

<6> PM_DRAM_PWRGD DRAMPWROK SLP_S5# / GPIO63

1 2
PCH_RSMRST#_R C21 H4 PM_SLP_S4#
<45> EC_RSMRST# RSMRST# SLP_S4# PM_SLP_S4# <45>
R193 0_0402_5%
R1455 0_0402_5%
2 1 SUSWARN#_R K16 F4 PM_SLP_S3#
+3V_PCH <45> SUSWARN# SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3# PM_SLP_S3# <45>
DS3@ Can be left NC
B
For Deep S3 when IAMT is not
B
1 2 PBTN_OUT#_R E20 G10 support on the
<45,6> PBTN_OUT# PWRBTN# SLP_A#
R198 0_0402_5%
R192 2 1 200_0402_5% PM_DRAM_PWRGD R1447 0_0402_5%
platfrom
1 2 AC_PRESENT_R H20 G16 PM_SLP_SUS#_R2 1
2 1 10K_0402_5% <45> AC_PRESENT ACPRESENT / GPIO31 SLP_SUS# PM_SLP_SUS# <45,52>
R194 SUSWARN# R208 0_0402_5% DS3@
For Deep S3
1 R200 2 PCH_GPIO72 E10 AP14 H_PM_SYNC
BATLOW# / GPIO72 PMSYNCH H_PM_SYNC <6>
8.2K_0402_5%
R201
R197 2 1 10K_0402_5% PCH_RSMRST#_R 2 1 RI# A10 K14 PCH_GPIO29 PAD T74 Can be left NC if no use
+3V_PCH RI# SLP_LAN# / GPIO29
10K_0402_5% integrated LAN.
PANTHER-POINT_FCBGA989
10/06 Test point request

+3VALW

R195 2 1 200K_0402_5% AC_PRESENT_R

+3VS
A A

@
R1290 2 1 200_0402_5% PM_DRAM_PWRGD

7/28 Modify follow Module Design.

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 PCH (3/9) DMI,FDI,PM,

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-8692P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Tuesday, June 05, 2012 Sheet 16 of 66
5 4 3 2 1
 5 4 3 2 1

D D

U4D

+3VS PCH_ENBKL J47 AP43

<34> PCH_ENBKL PCH_ENVDD M45 L_BKLTEN SDVO_TVCLKINN AP45 +3VS
<34> PCH_ENVDD L_VDD_EN SDVO_TVCLKINP
P45 AM42
<34> PCH_PWM L_BKLTCTL SDVO_STALLN AM40
R836 R835 SDVO_STALLP

1
2.2K_0402_5% EDID_CLK T40
2.2K_0402_5% <34> EDID_CLK L_DDC_CLK
EDID_DATA K47 AP39 R267 R203
OPT@ OPT@ <34> EDID_DATA L_DDC_DATA SDVO_INTN AP40 2.2K_0402_5% 2.2K_0402_5%
R205 1 OPT@ 2 2.2K_0402_5% CTRL_CLK T45 SDVO_INTP OPT@ OPT@
+3VS L_CTRL_CLK
R261 1 2 2.2K_0402_5% CTRL_DATA P39

2
2.37K_0402_1% L_CTRL_DATA
OPT@
EDID_DATA R257 2 1 LVDS_IBG AF37 P38 HDMICLK
LVD_IBG SDVO_CTRLCLK HDMICLK <37>
OPT@ AF36 M39 HDMIDAT
LVD_VBG SDVO_CTRLDATA HDMIDAT <37>
EDID_CLK AE48
AE47 LVD_VREFH AT49
Remove netname LVD_REF LVD_VREFL DDPB_AUXN AT47
DDPB_AUXP AT40
AK39 DDPB_HPD TMDS_B_HPD <37>
<34> LVDS_ACLK# LVDSA_CLK#

LVDS
AK40 AV42 TMDS_B_DATA2#_PCH
<34> LVDS_ACLK LVDSA_CLK DDPB_0N AV40 TMDS_B_DATA2_PCH TMDS_B_DATA2#_PCH <37>
AN48 DDPB_0P AV45 TMDS_B_DATA1#_PCH TMDS_B_DATA2_PCH <37>
<34> LVDS_A0# AM47 LVDSA_DATA#0 DDPB_1N AV46 TMDS_B_DATA1_PCH TMDS_B_DATA1#_PCH <37>
<34> LVDS_A1# LVDSA_DATA#1 DDPB_1P TMDS_B_DATA1_PCH <37>

Digital Display Interface

C AK47 AU48 TMDS_B_DATA0#_PCH C
<34> LVDS_A2# AJ48 LVDSA_DATA#2 DDPB_2N AU47 TMDS_B_DATA0_PCH TMDS_B_DATA0#_PCH <37>
LVDSA_DATA#3 DDPB_2P AV47 TMDS_B_CLK#_PCH TMDS_B_DATA0_PCH <37>
AN47 DDPB_3N AV49 TMDS_B_CLK_PCH TMDS_B_CLK#_PCH <37>
<34> LVDS_A0 AM49 LVDSA_DATA0 DDPB_3P TMDS_B_CLK_PCH <37>
<34> LVDS_A1 AK49 LVDSA_DATA1
<34> LVDS_A2 AJ47 LVDSA_DATA2 P46
LVDSA_DATA3 DDPC_CTRLCLK P42
DDPC_CTRLDATA
AF40
<34> LVDS_BCLK# AF39 LVDSB_CLK# AP47
<34> LVDS_BCLK LVDSB_CLK DDPC_AUXN AP49
AH45 DDPC_AUXP AT38
<34> LVDS_B0# AH47 LVDSB_DATA#0 DDPC_HPD
<34> LVDS_B1# AF49 LVDSB_DATA#1 AY47
<34> LVDS_B2# AF45 LVDSB_DATA#2 DDPC_0N AY49
LVDSB_DATA#3 DDPC_0P AY43
AH43 DDPC_1N AY45
<34> LVDS_B0 AH49 LVDSB_DATA0 DDPC_1P BA47
DAC_BLU
<36> DAC_BLU <34> LVDS_B1 LVDSB_DATA1 DDPC_2N
R266 2 1 150_0402_1% AF47 BA48
<34> LVDS_B2 AF43 LVDSB_DATA2 DDPC_2P BB47
DAC_GRN LVDSB_DATA3 DDPC_3N BB49
<36> DAC_GRN OPT@ DDPC_3P
R264 2 1 150_0402_1%

OPT@ DAC_RED N48 M43

<36> DAC_RED CRT_BLUE DDPD_CTRLCLK
R262 2 1 150_0402_1% P49 M36
T49 CRT_GREEN DDPD_CTRLDATA
CRT_RED
OPT@
AT45
DDPD_AUXN

CRT
CRT_DDC_CLK T39 AT43
<36> CRT_DDC_CLK CRT_DDC_DATA M40 CRT_DDC_CLK DDPD_AUXP BH41
+3VS <36> CRT_DDC_DATA CRT_DDC_DATA DDPD_HPD
B BB43 B
M47 DDPD_0N BB45
<36> CRT_HSYNC M49 CRT_HSYNC DDPD_0P BF44
<36> CRT_VSYNC CRT_VSYNC DDPD_1N
1

BE44
DDPD_1P BF42
R848 R849
CRT_IREF T43 DDPD_2N BE42
2.2K_0402_5% 2.2K_0402_5%
T42 DAC_IREF DDPD_2P BJ42
OPT@ OPT@
CRT_IRTN DDPD_3N BG42
DDPD_3P
2

CRT_DDC_DATA
R211 PANTHER-POINT_FCBGA989
1K_0402_1%
2

CRT_DDC_CLK

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 PCH (4/9) LVDS,CRT,DP,HDMI

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-8692P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Tuesday, June 05, 2012 Sheet 17 of 66
5 4 3 2 1
 5 4 3 2 1

+3VS
RP2
8 1 PCI_PIRQA#
7 2 PCI_PIRQD# U4E
6 3 PCI_PIRQC# AY7
5 4 PCI_PIRQB# RSVD1 AV7
BG26 RSVD2 AU3
8.2K_0804_8P4R_5% BJ26 TP1 RSVD3 BG4
BH25 TP2 RSVD4
RP1 BJ16 TP3 AT10
8 1 PCH_GPIO2 BG16 TP4 RSVD5 BC8
7 2 DGPU_PWR_EN AH38 TP5 RSVD6
6 3 PCH_GPIO4 AH37 TP6 AU2
5 4 ODD_DA#_R AK43 TP7 RSVD7 AT4
D AK45 TP8 RSVD8 AT3 D
8.2K_0804_8P4R_5% C18 TP9 RSVD9 AT1
N30 TP10 RSVD10 AY3
@
PPT EDS DOC#474146 H3 TP11 RSVD11 AT5
R305 1 2 8.2K_0402_5% PCH_GPIO51 AH12 TP12 RSVD12 AV3
@ AM4 TP13 RSVD13 AV1
R297 1 2 8.2K_0402_5% DGPU_GC6_EN USB30 AM5 TP14
TP15
RSVD14
RSVD15
BB1
Y13 BA3
OPT@ 2 8.2K_0402_5% TP16 RSVD16
R213 1 HDMI_HPD PORT1 Camera USB K24
TP17 RSVD17
BB5
L24 BB3
R225 1 2 8.2K_0402_5% PCH_WL_OFF# AB46 TP18 RSVD18 BB7
AB45 TP19 RSVD19 BE8
PORT2 TP20 RSVD20
1 2 8.2K_0402_5% BD4

RSVD
R212 NVDD_PWR_EN
RSVD21 BF6
1 2 8.2K_0402_5% DGPU_HOLD_RST# RSVD22
R252 PORT3 LEFT USB B21 AV5
M20 TP21 RSVD23 AV10
R306 1 2 8.2K_0402_5% DGPU_GC6_EN AY16 TP22 RSVD24
PORT4 LEFT USB TP23
@ BG46 AT8
R214 1 2 8.2K_0402_5% DGPU_HOLD_RST# TP24 RSVD25
AY5
@ RSVD26 BA2
USB30_RX_N1 BE28 RSVD27
<50> USB30_RX_N1 BC30 USB3Rn1 AT12
USB30_RX_N3 BE32 USB3Rn2 RSVD28 BF3
<48> USB30_RX_N3 BJ32 USB3Rn3 RSVD29
USB30_RX_N4
PCH_WL_OFF# 1 2 1K_0402_5% <48> USB30_RX_N4 USB30_RX_P1 BC28 USB3Rn4
R215 @
<50> USB30_RX_P1 BE30 USB3Rp1
USB30_RX_P3 BF32 USB3Rp2 USB DEBUG=PORT1 AND PORT9
<48> USB30_RX_P3 BG32 USB3Rp3 C24
USB30_RX_P4 USB20_N0
<48> USB30_RX_P4 USB3Rp4 USBP0N USB20_N0 <50>
A16 swap overide Strap/Top-Block <50> USB30_TX_N1
USB30_TX_N1 AV26
USB3Tn1 USBP0P
A24 USB20_P0
USB20_P0 Camera
<50>
Swap Override jumper BB26 C25
C USB30_TX_N3 AU28 USB3Tn2 USBP1N B25 C
<48> USB30_TX_N3 USB30_TX_N4 AY30 USB3Tn3 USBP1P C26 USB20_N2
Low=A16 swap <48> USB30_TX_N4 USB3Tn4 USBP2N USB20_N2 <48>
override/Top-Block USB30_TX_P1 AU26 A26 USB20_P2
<50> USB30_TX_P1 AY26 USB3Tp1 USBP2P K28 USB20_P2 <48> LEFT USB
PCI_GNT3# Swap Override enabled USB20_N3
USB30_TX_P3 AV28 USB3Tp2 USBP3N H28 USB20_P3 USB20_N3 <48>
High=Default * <48> USB30_TX_P3 USB3Tp3 USBP3P USB20_P3 <48> LEFT USB
USB30_TX_P4 AW30 E28
<48> USB30_TX_P4 USB3Tp4 USBP4N D28
USBP4P C28
USBP5N A28
USBP5P C29
USBP6N B29
PCI_PIRQA# K40 USBP6P N28
PCI_PIRQB# K38 PIRQA# USBP7N M28
Some PCH config not support USB port 6 & 7.
PIRQB# USBP7P

PCI
PCI_PIRQC# H38 L30
PCI_PIRQD# G38 PIRQC# USBP8N K30
<23> DGPU_HOLD_RST# PIRQD# USBP8P G30 USB20_N9
2 0_0402_5% C46 USBP9N E30 USB20_N9 <49> +3V_PCH
R1591 @1
@ DGPU_HOLD_RST# USB20_P9
<15,32> S_DGPU_RST REQ1# / GPIO50 USBP9P USB20_P9 <49> RIGHT USB 1 (SUB/B)

USB
NVDD_PWR_EN C44 C30 USB20_N10
<59> NVDD_PWR_EN E40 REQ2# / GPIO52 USBP10N A30 USB20_N10 <38>
DGPU_PWR_EN USB20_P10 RP3
<23,52> DGPU_PWR_EN REQ3# / GPIO54 USBP10P L32 USB20_P10 <38>WLAN USB_OC5# 4 5
PCH_GPIO51 D47 USBP11N K32 USB_OC2# 3 6
DGPU_GC6_EN E42 GNT1# / GPIO51 USBP11P G32 USB20_N12 USB_OC7# 2 7
<27> DGPU_GC6_EN PCH_WL_OFF# F46 GNT2# / GPIO53 USBP12N E32 USB20_P12 USB20_N12 <38> TV USB_OC0# 1 8
<38> PCH_WL_OFF# GNT3# / GPIO55 USBP12P C32 USB20_P12 <38>
USB20_N13
USBP13N USB20_N13 <47>
GPIO53=This Signal has a weak internal pull-up. USBP13P
A32 USB20_P13
USB20_P13 <47> BT 10K_1206_8P4R_5%
PCH_GPIO2 G42
NOTE: The internal pull-up is disabled after ODD_DA#_R G40 PIRQE# / GPIO2
<42> ODD_DA#_R
PCH_GPIO4 C42 PIRQF# / GPIO3 C33 USBRBIAS
Within
1
500 2mils
PLTRST# deasserts. HDMI_HPD D44 PIRQG# / GPIO4 USBRBIAS# R218 22.6_0402_1% RP4
<37> HDMI_HPD PIRQH# / GPIO5 USB_OC6# 4 5
B33 USB_OC1# 3 6
K10 USBRBIAS USB_OC4# 2 7
B PME# USB_OC3# 1 8 B
PLT_RST# C6 A14 USB_OC0#
<23,32,38,39,44,45,6> PLT_RST# PLTRST# OC0# / GPIO59 K20 USB_OC1# 10K_1206_8P4R_5%
OC1# / GPIO40 B17 USB_OC2# USB_OC1# <48>
22_0402_5% 1 2 R219 CLK_PCI_LPBACK_R H49 OC2# / GPIO41 C16 USB_OC3#
<15> CLK_PCI_LPBACK CLKOUT_PCI0 OC3# / GPIO42
22_0402_5% 1 2 R220 CLK_PCI_EC_R H43 L16 USB_OC4#
<45> CLK_PCI_EC CLKOUT_PCI1 OC4# / GPIO43 USB_OC4# <49>
22_0402_5% 2 1 R173 CLK_PCI_DB_R J48 A16 USB_OC5#
<38> CLK_PCI_DB K42 CLKOUT_PCI2 OC5# / GPIO9 D14 USB_OC6#
@
H40 CLKOUT_PCI3 OC6# / GPIO10 C14 USB_OC7#
PCH_GPIO51 R221 1 @ 2 1K_0402_5% CLKOUT_PCI4 OC7# / GPIO14

PANTHER-POINT_FCBGA989
PLT_RST#

Boot BIOS Strap bit1 BBS1

1

Boot BIOS
R223
Bit11 Bit10 Destination 100K_0402_5%
2

0 1 Reserved
GNT1#/
GPIO51 1 0 Reserved
1 1 * SPI (Default)
0 0 LPC

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 PCH (5/9) PCI, USB
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-8692P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Tuesday, June 05, 2012 Sheet 18 of 66
5 4 3 2 1
 5 4 3 2 1

SKU ID +3VS
Function PCH_GPIO38 PCH_GPIO67 PCH_GPIO70

Optimus 0 0 X R711 R708 R704

2
10K_0402_5%

10K_0402_5%

10K_0402_5%
Reserve 0 1 X SLI@

DIS @
1 0 X

1
(SLI) PCH_GPIO38

Reserve 1 1 X <15> PCH_GPIO67

PCH_GPIO67

D PCH_GPIO70 D
+3VS
14" X X 0
10K_0402_5% 2 1 R1493 EC_SCI# R712 R709 R706
15" X X 1

2
10K_0402_5%

10K_0402_5%

10K_0402_5%
+3V_PCH
OPT@
GC6_EVENT# @
R235 2 1 10K_0402_5% EC_SMI# <23> GC6_EVENT#

1
R233 1 2 10K_0402_5%
+3VS
U4F

T7 C40 S_DGPU_PWROK
BMBUSY# / GPIO0 TACH4 / GPIO68 S_DGPU_PWROK <32>
R227 1 2 10K_0402_5% PCH_GPIO1 A42 B41 S_DGPU_PWR_EN +3VS
TACH1 / GPIO1 TACH5 / GPIO69 S_DGPU_PWR_EN <32,52>
R228 1 2 10K_0402_5% PCH_GPIO6 H36 C41 PCH_GPIO70 9/18 Reseve for SKU ID S_DGPU_PWR_EN R1589 1 2 10K_0402_5%
+3VS TACH2 / GPIO6 TACH6 / GPIO70
EC_SCI# E38 A40 S_NVDD_PWR_EN S_NVDD_PWR_EN R1590 1 2 10K_0402_5%
<45> EC_SCI# TACH3 / GPIO7 TACH7 / GPIO71 S_NVDD_PWR_EN <32>
GPIO28
On-Die PLL Voltage Regulator EC_SMI# C10
<45> EC_SMI# GPIO8
This signal has a weak internal pull up

* H
L

On-Die voltage regulator enable
On-Die PLL Voltage Regulator disable
+3V_PCH R229

R230
1

1
@ 2 10K_0402_5%

2 10K_0402_5%
PCH_GPIO12

EC_LID_OUT#
C4

G2
LAN_PHY_PWR_CTRL / GPIO12
P4
R236 2 1 10K_0402_5%
+3VS

GPIO15 A20GATE GATEA20 <45>

1 2 1K_0402_5% PCH_GPIO28 <45> EC_LID_OUT# AU16
R240 @
<32> S_Toggle_REQ# 1 2 10K_0402_5% U2 PECI
+3VS R231
R232 1 2 10K_0402_1% SATA4GP / GPIO16 P5 KBRST#
RCIN# KBRST# <45>
@
C D40 AY11 C

GPIO
DGPU_PWROK
<27,56,59> DGPU_PWROK TACH0 / GPIO17 PROCPWRGD H_CPUPWRGD <6>

CPU/MISC
R238 1 2 10K_0402_5% PCH_BT_DISABLE# T5 AY10 PCH_THRMTRIP#_R 1 2 H_THRMTRIP#
+3VS SCLOCK / GPIO22 THRMTRIP# H_THRMTRIP# <6>
R239 390_0402_5%
<38> PCH_BT_DISABLE# ODD_EN E8 T14
* PCH_GPIO27 (Have internal Pull-High) <42> ODD_EN GPIO24 INIT3_3V#
@
High: VCCVRM VR Enable 0_0402_5% 2 1 R224 DS3_WAKE#_R E16 AY1 NV_CLE
PCH_THRMTRIP#_R <23,32>
Low: VCCVRM VR Disable <16,38,39> PCIE_WAKE# GPIO27 DF_TVS

+3V_PCH R241 1 2 10K_0402_5% PCH_GPIO28 P8

GPIO28 AH8
<38,47> PCH_BT_ON# TS_VSS1
INIT3_3V
1 2 10K_0402_5% PCH_BT_ON# K1 +3VS
+3VS STP_PCI# / GPIO34
R242 AK11 This signal has weak internal
+3VALW 1 2 10K_0402_5% PCH_GPIO35 K4 TS_VSS2 S_DGPU_PWROK R255 1 2 10K_0402_5%
GPIO35 PU, can't pull low
R243 AH10
ODD_DETECT# V8 TS_VSS3 KBRST# R226 1 2 10K_0402_5%
<42> ODD_DETECT# SATA2GP / GPIO36 AK10
AOAC@
R207 2 1 10K_0402_5% PCH_GPIO37 M5 TS_VSS4 PCH_THRMTRIP#_R R244 1 2 10K_0402_5%
SATA3GP / GPIO37
PCH_GPIO38 N2 P37
1 2 10K_0402_5% DS3_WAKE#_R SLOAD / GPIO38 NC_1
R245 @ Intel schematic reviwe recommand.
R247 1 2 10K_0402_5% PCH_GPIO39 M3
+3VS SDATAOUT0 / GPIO39
R248 1 2 10K_0402_5% PCH_GPIO48 V13 BG2
SDATAOUT1 / GPIO48 VSS_NCTF_15
R249 1 2 10K_0402_5% PCH_GPIO49 V3 BG48
+3VS SATA5GP / GPIO49 / TEMP_ALERT# VSS_NCTF_16
SLAVE_PRESENT# D6 BH3
<32> SLAVE_PRESENT# GPIO57 VSS_NCTF_17
200K_0402_5% 1 2 R250 ODD_DETECT# BH47
+3VS VSS_NCTF_18
A4 BJ4
VSS_NCTF_1 VSS_NCTF_19
B A44 BJ44 H : Sandy Bridge B
R251 1 2 10K_0402_5% SLAVE_PRESENT# VSS_NCTF_2 VSS_NCTF_20
+3V_PCH PROC_SEL
A45 BJ45 L : Ivy Bridge
VSS_NCTF_3 VSS_NCTF_21

NCTF
A46 BJ46
VSS_NCTF_4 VSS_NCTF_22 +1.8VS
R259 1 2 10K_0402_5% PCH_GPIO37 A5 BJ5
VSS_NCTF_5 VSS_NCTF_23
A6 BJ6
VSS_NCTF_6 VSS_NCTF_24 R216
B3 C2 2.2K_0402_5%
VSS_NCTF_7 VSS_NCTF_25
B47 C48
VSS_NCTF_8 VSS_NCTF_26 NV_CLE 1 2
H_SNB_IVB# <6>
BD1 D1 R217 1K_0402_5%
VSS_NCTF_9 VSS_NCTF_27
BD49 D49 CLOSE TO THE BRANCHING POINT
VSS_NCTF_10 VSS_NCTF_28
BE1 E1
VSS_NCTF_11 VSS_NCTF_29
BE49 E49
VSS_NCTF_12 VSS_NCTF_30
BF1 F1
VSS_NCTF_13 VSS_NCTF_31
BF49 F49
VSS_NCTF_14 VSS_NCTF_32

PANTHER-POINT_FCBGA989

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 PCH (6/9) GPIO, CPU, MISC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-8692P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Tuesday, June 05, 2012 Sheet 19 of 66
5 4 3 2 1
 5 4 3 2 1

L1 change to 1 ohm P/N

S RES 1/10W 1 +-1% 0603
+1.05VS U4G POWER +3VS PCH Power Rail Table
J17 @ 1700mA L1 1_0603_1% Refer to CPU EDS R1.5
2 1 +1.05VS_PCH AA23 U48 +VCCADAC 2 1
2 1 AC23 VCCCORE[1] 63mA VCCADAC
S0 Iccmax

10U_0603_6.3V6M
VCCCORE[2] 1 1 1

1U_0402_6.3V6K
C210

1U_0402_6.3V6K
C211

1U_0402_6.3V6K
C212

C215
JUMP_43X118 1 1 1 AD21 Voltage Rail Voltage Current (A)
1

CRT
AD23 VCCCORE[3] U47

10U_0603_6.3V6M
C209
C213 C214
AF21 VCCCORE[4] VSSADAC 0.01U_0402_16V7K 0.1U_0402_10V7K

VCC CORE
AF23 VCCCORE[5] 2 2 2
VCCCORE[6]
V_PROC_IO 1.05 0.001
D 2 2 2 2 AG21 +3VS D
AG23 VCCCORE[7] R295
AG24 VCCCORE[8] AK36 +VCCA_LVDS 2 1
VCCCORE[9] 1mA VCCALVDS
V5REF 5 0.001
AG26
VCCCORE[10] 0_0603_5%
AG27 AK37
AG29 VCCCORE[11] VSSALVDS
VCCCORE[12]
V5REF_Sus 5 0.001
AJ23 +1.8VS
AJ26 VCCCORE[13] AM37

LVDS
L2
AJ27 VCCCORE[14] VCCTX_LVDS[1]
VCCCORE[15]
0.1UH_MLF1608DR10KT_10%_1608 Vcc3_3 3.3 0.228
AJ29 AM38 +VCCTX_LVDS 2 1
AJ31 VCCCORE[16] VCCTX_LVDS[2] 0.1uH inductor, 200mA
VCCCORE[17] 1 1 1
+1.05VS AP36 VccADAC 3.3 0.063
40mA VCCTX_LVDS[3] C216 C217 C218
AP37 0.01U_0402_16V7K 0.01U_0402_16V7K 22U_0805_6.3V6M
2 1 +1.05VS_VCCDPLLEXP AN19 VCCTX_LVDS[4] 2 2 2
R254 0_0603_5%
VCCIO[28]
VccADPLLA 1.05 0.08

PAD T47 @ +VCCAPLLEXP BJ22 +3VS VccADPLLB 1.05 0.08

VCCAPLLEXP
This pin can be left as no connect in V33 +3VS_VCC3_3_6 2 R256 1
AN16 VCC3_3[6]

HVCMOS
0_0603_5% VccCore 1.05 1.7
On-Die VR enabled mode (default). VCCIO[15]
1
AN17
VCCIO[16] V34
VCC3_3[7]
C219 VccDMI 1.05 0.047
0.1U_0402_10V7K
AN21 2
VCCIO[17]
VccIO 1.05 3.711
AN26
VCCIO[18]
AN27 3711mA AT16 +VCCAFDI_VRM VccASW 1.05 0.903
VCCIO[19] VCCVRM[3]
+1.05VS AP21 +VCCP_VCCDMI +1.05VS
C VCCIO[20] C
VccSPI 3.3 0.01
AP23 AT20 +VCCP_VCCDMI 2 R258 1
VCCIO[21] VCCDMI[1] 0_0603_5%
1
+1.05VS
1U_0402_6.3V6K
C222

1U_0402_6.3V6K
C223

1U_0402_6.3V6K
C224

1U_0402_6.3V6K
C225

DMI
1 1 1 1 1 AP24 VccDSW 3.3 0.001
VCCIO[22]
10U_0603_6.3V6M
C221

VCCIO
C220
AP26 AB36 +1.05VS_VCC_DMI_CCI 2 R300 1 1U_0402_6.3V6K
VCCIO[23] 70mA VCCCLKDMI 2
1 0_0603_5% VccDFTERM 1.8 0.002
2 2 2 2 2 AT24
VCCIO[24] C226
1U_0402_6.3V6K VccRTC 3.3 6 uA
AN33 2
VCCIO[25]
AN34 AG16 VccSus3_3 3.3 0.095
+3VS VCCIO[26] VCCDFTERM[1]

1 R260 2 +3VS_VCCA3GBG BH29 AG17 +VCCPNAND +1.8VS VccSusHDA 3.3 / 1.5 0.01
0_0603_5% VCC3_3[3] 190mA VCCDFTERM[2]

DFT / SPI
1
C227
0.1U_0402_10V7K AJ16 2 R293 1 VccVRM 1.8 / 1.5 0.167
VCCDFTERM[3] 0_0603_5%
2 +VCCAFDI_VRM AP16
VCCVRM[2] 1
AJ17 C228 VccCLKDMI 1.05 0.07
VCCDFTERM[4] 0.1U_0402_10V7K
PAD T48 @ +1.05VS_VCCAPLL_FDI BG6
VccAFDIPLL 2 +3VS VccSSC 1.05 0.095
1 R263 2 +1.05VS_VCCDPLL_FDI AP17 R399
+1.05VS VCCIO[27]
0_0603_5% V1 +3V_VCCPSPI 2 1 VccDIFFCLKN 1.05 0.055
FDI

10mA VCCSPI 0_0603_5%

AU20 1
+VCCP_VCCDMI VCCDMI[2]
VccALVDS 3.3 0.001
C230
B PANTHER-POINT_FCBGA989 1U_0402_6.3V6K B
2 VccTX_LVDS 1.8 0.04

+VCCAFDI_VRM
+1.5VS

R265 2 1 0_0603_5% +VCCAFDI_VRM

Intel recommand VCCVRM==>1.5V FOR MOBILE

stuff R265 and unstuff R266 VCCVRM==>1.8V FOR DESKTOP
VCCVRM = 160mA detal waiting for newest spec

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 PCH (7/9) PWR

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-8692P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Tuesday, June 05, 2012 Sheet 20 of 66
5 4 3 2 1
 5 4 3 2 1

Have internal VRM

+3VS
VCC3_3 = 266mA detal waiting for newest spec
VCCDMI = 42mA detal waiting for newest spec
R280
0_0603_5%
2 1 +3VS_VCC_CLKF33 +3VALW R269
1 1 0_0603_5% U4J POWER +1.05VS

10U_0805_10V4Z
C231

1U_0402_6.3V6K
C232
2 1 +VCCPDSW
1 AD49 N26 +1.05VS_VCCUSBCORE 2 R270 1
VCCACLK VCCIO[29] 0_0603_5%
2 2 1
C234 P26
0.1U_0402_10V7K T16 VCCIO[30] C233
D 2 VCCDSW3_3 1mA P28 1U_0402_6.3V6K D
VCCIO[31] 2
V12 T27
DCPSUSBYP VCCIO[32]
T29
+3VS_VCC_CLKF33 T38 VCCIO[33] +3V_PCH
VCC3_3[5]

H On-Die PLL voltage regulator enable

On-Die PLL Voltage Regulator
BH23
VCCAPLLDMI2
228mA VCCSUS3_3[7]
T23 +3V_VCCPUSB 2 R272 1
0_0603_5%
+3V_PCH

0.1U_0402_10V7K
C236
T24 1 +5V_PCH
2 R271 1 +VCCDPLL_CPY AL29 VCCSUS3_3[8] +3V_PCH
VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2 +1.05VS VCCIO[14]
0_0603_5% V23 +3V_VCCAUBG 2 R273 1
,VCCAPLLSATA VCCSUS3_3[9]

USB
1 0_0603_5%

2
+VCCSUS1 AL24 V24 2

1
DCPSUS[3] VCCSUS3_3[10] C238 D1
1 R275
P24 0.1U_0402_10V7K CH751H-40PT_SOD323-2
@ C239 VCCSUS3_3[6] 2 +1.05VS 10_0402_5%
1U_0402_6.3V6K AA19

1
2 VCCASW[1] T26 +1.05VS_VCCAUPLL 2 R276 1 +PCH_V5REF_SUS

2
+1.05VS AA21 VCCIO[34]
VCCASW[2]
903mA 0_0603_5% 1
1 R277 2 +1.05VM_VCCASW AA24 M26 +PCH_V5REF_SUS C240
0_0805_5% VCCASW[3] 1mA V5REF_SUS 0.1U_0603_25V7K
1 1 2

22U_0805_6.3V6M
C241

22U_0805_6.3V6M
C242
AA26

Clock and Miscellaneous

VCCASW[4] AN23 +VCCA_USBSUS C243 @1
@ 2 1U_0402_6.3V6K
AA27 DCPSUS[4]
2 2 VCCASW[5] AN24 +3V_VCCPSUS
AA29 VCCSUS3_3[1]
VCCASW[6]
+5VS +3VS
+1.05VS AA31
VCCASW[7]
AC26 P34 +PCH_V5REF_RUN +3V_PCH

1
VCCASW[8] 1mA V5REF

2
C C
1 1 1 R279

1U_0402_6.3V6K
C244

1U_0402_6.3V6K
C245

1U_0402_6.3V6K
C246
L5 AC27 2 R278 1 D2
1 2 +1.05VS_VCCA_A_DPL VCCASW[9] N20 +3V_VCCPSUS 0_0603_5% 10_0402_5% CH751H-40PT_SOD323-2
VCCSUS3_3[2] 1
AC29

PCI/GPIO/LPC
BLM18PG181SN1D_0603
2 2 2 VCCASW[10] N22 C247

1
AC31 VCCSUS3_3[3] 1U_0402_6.3V +PCH_V5REF_RUN
VCCASW[11] P20 2 +3VS
VCCSUS3_3[4] 1
L6 AD29
1 2 +1.05VS_VCCA_B_DPL VCCASW[12] P22 2 R281 1 C248
BLM18PG181SN1D_0603 AD31 VCCSUS3_3[5] 0_0603_5% 1U_0603_10V6K
VCCASW[13] 1 2
C249
W21 AA16 +3VS_VCCPCORE 0.1U_0402_10V7K
VCCASW[14] VCC3_3[1]
2 +3VS
1U_0402_6.3V6K
C251

1U_0402_6.3V6K
C253

1 1 W23 W16
VCCASW[15] VCC3_3[8]
22U_0805_6.3V6M
C250

22U_0805_6.3V6M
C252

1 1
W24 T34 +3VS_VCCPPCI 2 R282 1
VCCASW[16] VCC3_3[4] 0_0603_5%
2 2 1
W26
2 2 VCCASW[17] C254
W29 +3VS 0.1U_0402_10V7K
VCCASW[18] 2
W31 AJ2 +VCC3_3_2 2 R283 1
VCCASW[19] VCC3_3[2] 0_0603_5% +1.05VS_SATA3 +1.05VS
1
Before gerber out change to 22u_0805 W33
VCCASW[20] AF13 2 R285 1
VCCIO[5] C255 0_0603_5%
2 0.1U_0402_10V7K 1
+VCCRTCEXT N16
DCPRTC AH13 C257
1 VCCIO[12]
C258 1U_0402_6.3V6K
0.1U_0402_10V7K +VCCAFDI_VRM Y49 AH14 +1.05VS_SATA3 2
VCCVRM[4] VCCIO[13]
2
B AF14 B
2 R274 1 +1.05VS_VCCA_A_DPL BD47 VCCIO[6]

On-Die PLL voltage regulator enable

+1.05VS VCCADPLLA 80mA AK1

SATA
0_0603_5%
VCCAPLLSATA On-Die PLL Voltage Regulator
1 +1.05VS_VCCA_B_DPL BF47 H
C256 VCCADPLLB 80mA +VCCAFDI_VRM
1U_0402_6.3V6K AF11 +VCCAFDI_VRM VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2
+1.05VS_VCCDIFFCLKN +VCCDIFFCLK AF17 VCCVRM[1] +1.05VS_VCC_SATA +1.05VS
2 AF33 VCCIO[7] ,VCCAPLLSATA
AF34 VCCDIFFCLKN[1] AC16 +1.05VS_VCC_SATA 2 R288 1
55mA
VCCDIFFCLKN[2] VCCIO[2]
2 R304 1 +1.05VS_VCCDIFFCLKN AG34 0_0603_5%
+1.05VS VCCDIFFCLKN[3]
0_0603_5% 1 AC17 1
VCCIO[3] C261
C259 +1.05VS_SSCVCC AG33 AD17 1U_0402_6.3V6K
1U_0402_6.3V6K VCCSSC 95mA VCCIO[4]
2 2
+VCCSST V16 +1.05VS
DCPSST
1
2 R284 1 C263
+1.05VS
0_0603_5% 1 0.1U_0402_10V7K T17 T21
V19 DCPSUS[1] VCCASW[22]
C262 2 DCPSUS[2]
MISC

1U_0402_6.3V6K +1.05VS V21

2 VCCASW[23]
CPU

2 R286 1 +V_CPU_IO BJ8

0_0603_5% V_PROC_IO 1mA T19
VCCASW[21]
1 1 1
+RTCVCC +3V_PCH
4.7U_0603_6.3V6K
C265

0.1U_0402_10V7K
C266

0.1U_0402_10V7K
C267

A22 P32 +VCCSUSHDA 2 R287 1

RTC

2 2 2 VCCRTC 10mA VCCSUSHDA

HDA

@ 0_0603_5%
1U_0402_6.3V6K
C268

0.1U_0402_10V7K
C269

0.1U_0402_10V7K
C270

1 1 1 1
PANTHER-POINT_FCBGA989 C271
A 0.1U_0402_16V4Z A
@
2 2 2 2

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 PCH (8/9) PWR

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-8692P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Tuesday, June 05, 2012 Sheet 21 of 66
5 4 3 2 1
 5 4 3 2 1

U4I

AY4 H46
AY42 VSS[159] VSS[259] K18
AY46 VSS[160] VSS[260] K26
AY8 VSS[161] VSS[261] K39
B11 VSS[162] VSS[262] K46
D U4H B15 VSS[163] VSS[263] K7 D
H5 B19 VSS[164] VSS[264] L18
VSS[0] B23 VSS[165] VSS[265] L2
AA17 AK38 B27 VSS[166] VSS[266] L20
AA2 VSS[1] VSS[80] AK4 B31 VSS[167] VSS[267] L26
AA3 VSS[2] VSS[81] AK42 B35 VSS[168] VSS[268] L28
AA33 VSS[3] VSS[82] AK46 B39 VSS[169] VSS[269] L36
AA34 VSS[4] VSS[83] AK8 B7 VSS[170] VSS[270] L48
AB11 VSS[5] VSS[84] AL16 F45 VSS[171] VSS[271] M12
AB14 VSS[6] VSS[85] AL17 BB12 VSS[172] VSS[272] P16
AB39 VSS[7] VSS[86] AL19 BB16 VSS[173] VSS[273] M18
AB4 VSS[8] VSS[87] AL2 BB20 VSS[174] VSS[274] M22
AB43 VSS[9] VSS[88] AL21 BB22 VSS[175] VSS[275] M24
AB5 VSS[10] VSS[89] AL23 BB24 VSS[176] VSS[276] M30
AB7 VSS[11] VSS[90] AL26 BB28 VSS[177] VSS[277] M32
AC19 VSS[12] VSS[91] AL27 BB30 VSS[178] VSS[278] M34
AC2 VSS[13] VSS[92] AL31 BB38 VSS[179] VSS[279] M38
AC21 VSS[14] VSS[93] AL33 BB4 VSS[180] VSS[280] M4
AC24 VSS[15] VSS[94] AL34 BB46 VSS[181] VSS[281] M42
AC33 VSS[16] VSS[95] AL48 BC14 VSS[182] VSS[282] M46
AC34 VSS[17] VSS[96] AM11 BC18 VSS[183] VSS[283] M8
AC48 VSS[18] VSS[97] AM14 BC2 VSS[184] VSS[284] N18
AD10 VSS[19] VSS[98] AM36 BC22 VSS[185] VSS[285] P30
AD11 VSS[20] VSS[99] AM39 BC26 VSS[186] VSS[286] N47
AD12 VSS[21] VSS[100] AM43 BC32 VSS[187] VSS[287] P11
AD13 VSS[22] VSS[101] AM45 BC34 VSS[188] VSS[288] P18
AD19 VSS[23] VSS[102] AM46 BC36 VSS[189] VSS[289] T33
AD24 VSS[24] VSS[103] AM7 BC40 VSS[190] VSS[290] P40
AD26 VSS[25] VSS[104] AN2 BC42 VSS[191] VSS[291] P43
AD27 VSS[26] VSS[105] AN29 BC48 VSS[192] VSS[292] P47
AD33 VSS[27] VSS[106] AN3 BD46 VSS[193] VSS[293] P7
AD34 VSS[28] VSS[107] AN31 BD5 VSS[194] VSS[294] R2
C AD36 VSS[29] VSS[108] AP12 BE22 VSS[195] VSS[295] R48 C
AD37 VSS[30] VSS[109] AP19 BE26 VSS[196] VSS[296] T12
AD38 VSS[31] VSS[110] AP28 BE40 VSS[197] VSS[297] T31
AD39 VSS[32] VSS[111] AP30 BF10 VSS[198] VSS[298] T37
AD4 VSS[33] VSS[112] AP32 BF12 VSS[199] VSS[299] T4
AD40 VSS[34] VSS[113] AP38 BF16 VSS[200] VSS[300] W34
AD42 VSS[35] VSS[114] AP4 BF20 VSS[201] VSS[301] T46
AD43 VSS[36] VSS[115] AP42 BF22 VSS[202] VSS[302] T47
AD45 VSS[37] VSS[116] AP46 BF24 VSS[203] VSS[303] T8
AD46 VSS[38] VSS[117] AP8 BF26 VSS[204] VSS[304] V11
AD8 VSS[39] VSS[118] AR2 BF28 VSS[205] VSS[305] V17
AE2 VSS[40] VSS[119] AR48 BD3 VSS[206] VSS[306] V26
AE3 VSS[41] VSS[120] AT11 BF30 VSS[207] VSS[307] V27
AF10 VSS[42] VSS[121] AT13 BF38 VSS[208] VSS[308] V29
AF12 VSS[43] VSS[122] AT18 BF40 VSS[209] VSS[309] V31
AD14 VSS[44] VSS[123] AT22 BF8 VSS[210] VSS[310] V36
AD16 VSS[45] VSS[124] AT26 BG17 VSS[211] VSS[311] V39
AF16 VSS[46] VSS[125] AT28 BG21 VSS[212] VSS[312] V43
AF19 VSS[47] VSS[126] AT30 BG33 VSS[213] VSS[313] V7
AF24 VSS[48] VSS[127] AT32 BG44 VSS[214] VSS[314] W17
AF26 VSS[49] VSS[128] AT34 BG8 VSS[215] VSS[315] W19
AF27 VSS[50] VSS[129] AT39 BH11 VSS[216] VSS[316] W2
AF29 VSS[51] VSS[130] AT42 BH15 VSS[217] VSS[317] W27
AF31 VSS[52] VSS[131] AT46 BH17 VSS[218] VSS[318] W48
AF38 VSS[53] VSS[132] AT7 BH19 VSS[219] VSS[319] Y12
AF4 VSS[54] VSS[133] AU24 H10 VSS[220] VSS[320] Y38
AF42 VSS[55] VSS[134] AU30 BH27 VSS[221] VSS[321] Y4
AF46 VSS[56] VSS[135] AV16 BH31 VSS[222] VSS[322] Y42
AF5 VSS[57] VSS[136] AV20 BH33 VSS[223] VSS[323] Y46
AF7 VSS[58] VSS[137] AV24 BH35 VSS[224] VSS[324] Y8
AF8 VSS[59] VSS[138] AV30 BH39 VSS[225] VSS[325] BG29
AG19 VSS[60] VSS[139] AV38 BH43 VSS[226] VSS[328] N24
B AG2 VSS[61] VSS[140] AV4 BH7 VSS[227] VSS[329] AJ3 B
AG31 VSS[62] VSS[141] AV43 D3 VSS[228] VSS[330] AD47
AG48 VSS[63] VSS[142] AV8 D12 VSS[229] VSS[331] B43
AH11 VSS[64] VSS[143] AW14 D16 VSS[230] VSS[333] BE10
AH3 VSS[65] VSS[144] AW18 D18 VSS[231] VSS[334] BG41
AH36 VSS[66] VSS[145] AW2 D22 VSS[232] VSS[335] G14
AH39 VSS[67] VSS[146] AW22 D24 VSS[233] VSS[337] H16
AH40 VSS[68] VSS[147] AW26 D26 VSS[234] VSS[338] T36
AH42 VSS[69] VSS[148] AW28 D30 VSS[235] VSS[340] BG22
AH46 VSS[70] VSS[149] AW32 D32 VSS[236] VSS[342] BG24
AH7 VSS[71] VSS[150] AW34 D34 VSS[237] VSS[343] C22
AJ19 VSS[72] VSS[151] AW36 D38 VSS[238] VSS[344] AP13
AJ21 VSS[73] VSS[152] AW40 D42 VSS[239] VSS[345] M14
AJ24 VSS[74] VSS[153] AW48 D8 VSS[240] VSS[346] AP3
AJ33 VSS[75] VSS[154] AV11 E18 VSS[241] VSS[347] AP1
AJ34 VSS[76] VSS[155] AY12 E26 VSS[242] VSS[348] BE16
AK12 VSS[77] VSS[156] AY22 G18 VSS[243] VSS[349] BC16
AK3 VSS[78] VSS[157] AY28 G20 VSS[244] VSS[350] BG28
VSS[79] VSS[158] G26 VSS[245] VSS[351] BJ28
PANTHER-POINT_FCBGA989 G28 VSS[246] VSS[352]
G36 VSS[247]
G48 VSS[248]
H12 VSS[249]
H18 VSS[250]
H22 VSS[251]
H24 VSS[252]
H26 VSS[253]
H30 VSS[254]
H32 VSS[255]
H34 VSS[256]
F3 VSS[257]
VSS[258]
A A

PANTHER-POINT_FCBGA989

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 PCH (9/9) VSS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-8692P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Tuesday, June 05, 2012 Sheet 22 of 66
5 4 3 2 1
 5 4 3 2 1

DPRSLPVR_VGA 1 2 GPIO16
RV234 @ 0_0402_5%
UV1A
PCIE_CTX_GRX_N[0..15] +VDD33MISC
<32,5> PCIE_CTX_GRX_N[0..15] PCIE_CTX_GRX_P7 AN12 +VDD33MISC
Part 1 of 7
PCIE_CTX_GRX_P[0..15] PCIE_CTX_GRX_N7 AM12 PEX_RX0 P6 GPU_VID4
<32,5> PCIE_CTX_GRX_P[0..15] PCIE_CTX_GRX_P6 AN14 PEX_RX0_N GPIO0 M3 GPU_VID3 GPU_VID4 <59>
PEX_RX1 GPIO1 GPU_VID3 <59>

10K_0402_5%
PCIE_CRX_GTX_N[0..15] PCIE_CTX_GRX_N6 AM14 L6 VGA_BL_PWM PCH_THRMTRIP#_R
<32,5> PCIE_CRX_GTX_N[0..15] PEX_RX1_N GPIO2 VGA_BL_PWM <34> PCH_THRMTRIP#_R <19,32>

1
PCIE_CTX_GRX_P5 AP14 P5 VGA_ENVDD
PEX_RX2 GPIO3 VGA_ENVDD <34>

RV65
PCIE_CRX_GTX_P[0..15] PCIE_CTX_GRX_N5 AP15 P7 VGA_ENBKL RV208
<32,5> PCIE_CRX_GTX_P[0..15] PEX_RX2_N GPIO4 VGA_ENBKL <34>

3
PCIE_CTX_GRX_P4 AN15 L7 GPU_VID1 10K_0402_5%
PCIE_CTX_GRX_N4 AM15 PEX_RX3 GPIO5 M7 GPU_VID2 GPU_VID1 <59>
@ QV7B
PCIE_CTX_GRX_P3 AN17 PEX_RX3_N GPIO6 N8 DPRSLPVR_VGA_R 1 GPU_VID22 <59>
DMN66D0LDW-7 2N_SOT363-6

2
PCIE_CTX_GRX_N3 AM17 PEX_RX4 GPIO7 M1 OVERT# DPRSLPVR_VGA <59> 5
RV235 0_0402_5%
PCIE_CTX_GRX_P2 AP17 PEX_RX4_N GPIO8 M2 GPIO9 @
Under GPU(below 150mils) PEX_RX5 GPIO9

6
D
150mA PCIE_CTX_GRX_N2 AP18 L1 D

4
PCIE_CTX_GRX_P1 AN18 PEX_RX5_N GPIO10 M5 GPU_VID0 MEM_VREF <28,29,30,31>
LV1 BLM18PG181SN1D_2P QV7A

GPIO
1 2 +SP_PLLVDD PCIE_CTX_GRX_N1 AM18 PEX_RX6 GPIO11 N3 GPU_VID0 <59> VGA_AC_DET
+1.05VS_VGA PEX_RX6_N GPIO12 VGA_AC_DET <32,45,59> DMN66D0LDW-7 2N_SOT363-6

10K_0402_5%
22U_0805_6.3V6M

4.7U_0402_6.3V6M

0.1U_0402_10V7K

0.1U_0402_10V7K
PCIE_CTX_GRX_P0 AN20 M4 GPU_VID5 OVERT# 2
PEX_RX7 GPIO13 GPU_VID5 <59>

1
CV112

CV113

CV4

CV5
180ohms (ESR=0.2) Bead 1 1 1 1 PCIE_CTX_GRX_N0 AM20 N4 FB_CLAMP_TOGGLE_REQ#
PEX_RX7_N GPIO14

RV223
AP20 P2 GPIO15
GPIO15 <27>

1
AP21 PEX_RX8 GPIO15 R8 GPIO16
AN21 PEX_RX8_N GPIO16 M6
2 2 2 2 AM21 PEX_RX9 GPIO17 R1 DGPU_HDMI_HPD
DGPU_HDMI_HPD <37>

2
+VDD33MISC +3VS AN23 PEX_RX9_N GPIO18 P3
PEX_RX10 GPIO19

1
AM23 P4 D
AP23 PEX_RX10_N GPIO20 P1 PLT_RST_VGA# 2
Add QV17, C38 has abnormal shutdown issue
PEX_RX11 GPIO21
1

AP24 G QV17
RV237 RV238 AN24 PEX_RX11_N 2N7002KW_SOT323-3
S

3
AM24 PEX_RX12
0_0402_5% 0_0402_5% PEX_RX12_N
AN26 Vendor recommand reserve PU/PD resistor
@ @ PEX_RX13
AM26
2

AP26 PEX_RX13_N
AP27 PEX_RX14
PEX_RX14_N
2

AN27 AK9 VGA_CRT_R

AM27 PEX_RX15 DACA_RED AL10 VGA_CRT_G VGA_CRT_R <36>
RV24 RV25 RV170 GC6@
PEX_RX15_N DACA_GREEN AL9 VGA_CRT_B VGA_CRT_G <36>
2.2K_0402_5% 2.2K_0402_5%
DACA_BLUE VGA_CRT_B <36> 2 1
@ @

DACs
@ <19> GC6_EVENT#
5

PCIE_CRX_GTX_P7 CV24 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_P7 AK14 0_0402_5% RV52 @ +VDD33MISC +3VS

1

QV1B PCIE_CRX_GTX_N7 CV26 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_N7 AJ14 PEX_TX0 AM9 VGA_CRT_HSYNC

VGA_SMB_CK2 4 3 PCIE_CRX_GTX_P6 1 2 PCIE_CRX_C_GTX_P6 AH14 PEX_TX0_N DACA_HSYNC AN9 VGA_CRT_VSYNC VGA_CRT_HSYNC <36> FB_CLAMP_TOGGLE_REQ# 1 2
CV21 0.22U_0402_10V6K
EC_SMB_CK2 <15,32,41,45> PCIE_CRX_GTX_N6 1 2 PCIE_CRX_C_GTX_N6 AG14 PEX_TX1 DACA_VSYNC VGA_CRT_VSYNC <36>
CV23 0.22U_0402_10V6K 10K_0402_5%
2N7002DW-T/R7_SOT363-6 PCIE_CRX_GTX_P5 CV25 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_P5 AK15 PEX_TX1_N OVERT# 1 2
PEX_TX2

1
1
1 2 PCIE_CRX_GTX_N5 CV27 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_N5 AJ15 AG10 +DACA_VDD RV1 10K_0402_5%
PEX_TX2_N DACA_VDD

PCI EXPRESS
RV126 R_short 0_0402_5% PCIE_CRX_GTX_P4 CV29 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_P4 AL16 AP9 +DACA_VREF RV239
PCIE_CRX_GTX_N4 CV31 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_N4 AK16 PEX_TX3 DACA_VREF AP8 DACA_RSET RV240
PEX_TX3_N DACA_RSET

0.1U_0402_10V7K
PCIE_CRX_GTX_P3 CV33 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_P3 AK17 R_short 0_0402_5%
PEX_TX4
2

0_0402_5%

@
CV130
C
@ PCIE_CRX_GTX_N3 CV28 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_N3 AJ17 1
C

2
PEX_TX4_N

2
QV1A PCIE_CRX_GTX_P2 CV30 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_P2 AH17 RV107
VGA_SMB_DA2 1 6 PCIE_CRX_GTX_N2 CV32 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_N2 AG17 PEX_TX5 124_0402_1%
EC_SMB_DA2 <15,32,41,45> PCIE_CRX_GTX_P1 1 2 PCIE_CRX_C_GTX_P1 AK18 PEX_TX5_N SLI@ GPIO9 1 2
CV36 0.22U_0402_10V6K SLI@
2N7002DW-T/R7_SOT363-6 PCIE_CRX_GTX_N1 CV41 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_N1 AJ18 PEX_TX6 2 RV15 2.2K_0402_5%

2
1 2 PCIE_CRX_GTX_P0 CV34 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_P0 AL19 PEX_TX6_N VGA_EDID_CLK 1 2
PCIE_CRX_GTX_N0 CV35 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_N0 AK19 PEX_TX7 R4 VGA_CRT_CLK RV4 2.2K_0402_5%
RV137 R_short 0_0402_5% PEX_TX7_N I2CA_SCL VGA_CRT_CLK <36>
AK20 R5 VGA_CRT_DATA VGA_EDID_DATA 1 2
AJ20 PEX_TX8
PEX_TX8_N
I2CA_SDA VGA_CRT_DATA <36> CRT SLI@ RV7 2.2K_0402_5%
AH20 R7 I2CB_SCL VGA_BL_PWM 2 1 VGA_CRT_DATA 1 2
AG20 PEX_TX9 I2CB_SCL R6 I2CB_SDA RV16 10K_0402_5% RV10 2.2K_0402_5%
AK21 PEX_TX9_N I2CB_SDA VGA_CRT_CLK 1 2

I2C
AJ21 PEX_TX10 R2 VGA_EDID_CLK VGA_ENBKL 1 2 RV11 2.2K_0402_5%
VGA_EDID_CLK <34>
AL22 PEX_TX10_N
PEX_TX11
I2CC_SCL
I2CC_SDA
R3 VGA_EDID_DATA
VGA_EDID_DATA <34>
LVDS RV17 100K_0402_5% I2CB_SCL 1 2
AK22 SLI@ RV12 2.2K_0402_5%
AK23 PEX_TX11_N T4 VGA_SMB_CK2 I2CB_SDA 1 2
+3VS AJ23 PEX_TX12 I2CS_SCL T3 VGA_SMB_DA2 RV13 2.2K_0402_5%
AH23 PEX_TX12_N I2CS_SDA
AG23 PEX_TX13 Close to GPU
1 AK24 PEX_TX13_N VGA_AC_DET 1 2
C1061 PEX_TX14 SLI@
AJ24 VGA_CRT_R 1 2 RV2 10K_0402_5%
0.1U_0402_16V4Z PEX_TX14_N
AL25 60mA RV106 150_0402_1%
2 AK25 PEX_TX15 +PLLVDD VGA_CRT_G 1 SLI@ 2
PEX_TX15_N RV108 150_0402_1%
AD8 1 2 VGA_CRT_B 1 SLI@ 2
PLLVDD
5

UV2 AJ11 45mA RV112 @ 0_0402_5% RV109 150_0402_1%

PLT_RST# 2 PEX_WAKE_N AE8
P

<18,32,38,39,44,45,6> PLT_RST# B SP_PLLVDD

4 PLT_RST_VGA# CLK_PCIE_VGA AL13 45mA
Y <15> CLK_PCIE_VGA PEX_REFCLK
DGPU_HOLD_RST# 1 CLK_PCIE_VGA# AK13 AD7 +SP_PLLVDD
<18> DGPU_HOLD_RST# A <15> CLK_PCIE_VGA# PEX_REFCLK_N VID_PLLVDD
G

CLK_REQ_GPU# AK12

CLK
2

PEX_CLKREQ_N
3

RV111 1 @ 2 PEX_TSTCLK_OUT AJ26 H3 XTAL_IN

B NC7SZ08P5X_NL_SC70-5 10K_0402_5% Differential signal RV20 200_0402_1% PEX_TSTCLK_OUT# AK26 PEX_TSTCLK_OUT XTAL_IN H2 XTAL_OUT B
PEX_TSTCLK_OUT_N XTAL_OUT
PLT_RST_VGA# AJ12 J4 XTALOUT 220 ohms @100MHz (ESR=0.05)
1

AP29 PEX_RST_N XTAL_OUTBUFF H1 XTALSSIN 1 2

PEX_TERMP XTAL_SSIN 120mA

1
1 2 PEX_TERMP 10K_0402_5% RV26 LV5
RV22 2.49K_0402_1% RV27 +DACA_VDD
Under GPU Near GPU 2 1
+3VS_VGA

0.1U_0402_10V7K

0.1U_0402_10V7K

4.7U_0603_6.3V6K
0.1U_0402_10V7K

0.1U_0402_10V7K
10K_0402_5% BLM18PG181SN1D_0603

CV139

CV122

CV127

CV128
1U_0402_6.3V4Z
@ CV125

@ CV126
R1495 @ 0_0402_5% 1 1 1 1 1 1
+3VS_VGA
1 2 SLI@

2
N13P-GT1-A2_FCBGA908 Internal Thermal Sensor
2 2 2 2 2 2 SLI@
2

GT@ CV126
RV230
10K_0402_5% SLI@ SLI@ SLI@
@
RV231
1

2 1 +3VS_VGA
<18,52> DGPU_PWR_EN 1 2 10K_0402_5%
RV23 10M_0402_5% OPT@
10K_0402_5%
2

RV30 YV1
10K_0402_5% 4 3 XTAL_OUT +PLLVDD 1 2
NC OSC +1.05VS_VGA
2

22U_0805_6.3V6M
0.1U_0402_10V7K
G

LV7 0_0402_5%
XTAL_IN 1 2

CV131
QV16 1 1
OSC NC
1

1 3

CV40
CLK_REQ_GPU#
<15> CLK_REQ_GPU#_R
1 27MHZ 16PF +-30PPM X3G027000FG1H-HX 1
D

2N7002H 1N_SOT23-3 CV37 CV38 2 2

@ RV232
@RV232 15P_0402_50V8J 15P_0402_50V8J
10K_0402_5% 2 2
A @ A
1 2
Under GPU Near GPU
1

RV233 0_0402_5%

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 N13P-PCIE/DAC/GPIO
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size
R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-8692P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Tuesday, June 05, 2012 Sheet 23 of 66
5 4 3 2 1
 5 4 3 2 1

UV1D

Part 4 of 7
<34> VGA_TXCLK+ VGA_TXCLK+ AM6
VGA_TXCLK- AN6 IFPA_TXC P8
<34> VGA_TXCLK- IFPA_TXC_N NC
<34> VGA_TXOUT0+ VGA_TXOUT0+ AP3 AC6
VGA_TXOUT0- AN3 IFPA_TXD0 NC AJ28
<34> VGA_TXOUT0- IFPA_TXD0_N NC
<34> VGA_TXOUT1+ VGA_TXOUT1+ AN5 AJ4
VGA_TXOUT1- AM5 IFPA_TXD1 NC AJ5
<34> VGA_TXOUT1- IFPA_TXD1_N NC
<34> VGA_TXOUT2+ VGA_TXOUT2+ AL6 AL11
VGA_TXOUT2- AK6 IFPA_TXD2 NC C15
<34> VGA_TXOUT2- IFPA_TXD2_N NC

NC
AJ6 D19
AH6 IFPA_TXD3 NC D20
D IFPA_TXD3_N NC D23 D
NC D26
VGA_TZCLK+ AJ9 NC H31
<34> VGA_TZCLK+ IFPB_TXC NC
<34> VGA_TZCLK- VGA_TZCLK- AH9 T8
VGA_TZOUT0+ AP6 IFPB_TXC_N NC V32
<34> VGA_TZOUT0+ IFPB_TXD4 NC
<34> VGA_TZOUT0- VGA_TZOUT0- AP5
for 15" dual channel VGA_TZOUT1+ AM7 IFPB_TXD4_N
<34> VGA_TZOUT1+ IFPB_TXD5
<34> VGA_TZOUT1- VGA_TZOUT1- AL7
VGA_TZOUT2+ AN8 IFPB_TXD5_N
<34> VGA_TZOUT2+ IFPB_TXD6
<34> VGA_TZOUT2- VGA_TZOUT2- AM8
AK8 IFPB_TXD6_N
AL8 IFPB_TXD7
IFPB_TXD7_N L4 VCCSENSE_VGA
VDD_SENSE VCCSENSE_VGA <59>
AK1
AJ1 IFPC_L0
AJ3 IFPC_L0_N L5 VSSSENSE_VGA
IFPC_L1 GND_SENSE VSSSENSE_VGA <59>
AJ2
AH3 IFPC_L1_N
IFPC_L2 trace width: 16mils
AH4
AG5 IFPC_L2_N differential voltage sensing.
IFPC_L3
AG4
IFPC_L3_N differential signal routing.
TEST
AM1 AK11 TESTMODE
AM2 IFPD_L0 TESTMODE
AM3 IFPD_L0_N AM10
IFPD_L1 JTAG_TCK TV2

1
AM4 AM11
IFPD_L1_N JTAG_TDI TV3
AL3 AP12
IFPD_L2 JTAG_TDO TV4 10K_0402_5%
C AL4 AP11 C
IFPD_L2_N JTAG_TMS TV5
AK4 AN11 1 2 RV33
AK5 IFPD_L3 JTAG_TRST_N RV34 10K_0402_5%

2
IFPD_L3_N

LVDS/TMDS
<37> VGA_HDMI_TX2+ VGA_HDMI_TX2+ AD2
VGA_HDMI_TX2- AD3 IFPE_L0
<37> VGA_HDMI_TX2- IFPE_L0_N
VGA_HDMI_TX1+ AD1
<37>
<37>
VGA_HDMI_TX1+
VGA_HDMI_TX1- VGA_HDMI_TX1- AC1 IFPE_L1 SERIAL
VGA_HDMI_TX0+ AC2 IFPE_L1_N H6 ROM_CS#
<37> VGA_HDMI_TX0+ IFPE_L2 ROM_CS_N
<37> VGA_HDMI_TX0- VGA_HDMI_TX0- AC3 H4 ROM_SCLK ROM_SCLK <33>
VGA_HDMI_CLK+ AC4 IFPE_L2_N ROM_SCLK H5 ROM_SI
<37> VGA_HDMI_CLK+ IFPE_L3 ROM_SI ROM_SI <33>
<37> VGA_HDMI_CLK- VGA_HDMI_CLK- AC5 H7 ROM_SO ROM_SO <33>
IFPE_L3_N ROM_SO

AE3
AE4 IFPF_L0
AF4 IFPF_L0_N
AF5 IFPF_L1
AD4 IFPF_L1_N GENERAL RV35 10K_0402_5%
AD5 IFPF_L2 L2 2 1
AG1 IFPF_L2_N BUFRST_N
AF1 IFPF_L3 L3
IFPF_L3_N CEC
J1 1 2
MULTI_STRAP_REF0_GND RV38 40.2K_0402_1%
AG3
AG2 IFPC_AUX_I2CW _SCL
IFPC_AUX_I2CW _SDA_N J2 STRAP0
STRAP0 STRAP0 <33>
J7 STRAP1 STRAP1 <33>
B
AK3 STRAP1 J6 STRAP2 B
+VDD33MISC IFPD_AUX_I2CX_SCL STRAP2 STRAP2 <33>
AK2 J5 STRAP3 STRAP3 <33>
IFPD_AUX_I2CX_SDA_N STRAP3 J3 STRAP4
STRAP4 STRAP4 <33>
SLI@
1 2 VGA_HDMI_CLK VGA_HDMI_CLK AB3
RV113 4.7K_0402_5% HDMI <37> VGA_HDMI_CLK
VGA_HDMI_DATA AB4 IFPE_AUX_I2CY_SCL
<37> VGA_HDMI_DATA IFPE_AUX_I2CY_SDA_N K3
1 2 VGA_HDMI_DATA THERMDP K4
RV114 4.7K_0402_5% AF3 THERMDN
SLI@ IFPF_AUX_I2CZ_SCL
AF2
IFPF_AUX_I2CZ_SDA_N

1MB SPI ROM FOR VBIOS ROM (SLI)

N13P-GT1-A2_FCBGA908
+3VS_VGA
CV295 GC6@
2 1 20mils

1
0.1U_0402_16V4Z GC6@
RV229 RV225
10K_0402_5% 10K_0402_5%
GC6@ GC6@

2
RV224 0_0402_5% UV15 GC6@
ROM_CS#1 2 ROM_CS#_R 1 8
ROM_SO 1 2 ROM_SO_R 2 CS# VCC 7 ROM_HOLD#
RV226 0_0402_5% 3 DO HOLD# 6
A W P# CLK A
GC6@ 4 5 RV228 0_0402_5%
GND DIO ROM_SCLK_R1 GC6@2 ROM_SCLK
MX25L1005AMC-12G SOP ROM_SI_R 1 2 ROM_SI
RV227 0_0402_5%
GC6@

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 N13P-LVDS/HDMI/DP/THM

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
LA-8692P 0.2

Date: Tuesday, June 05, 2012 Sheet 24 of 66

5 4 3 2 1
 5 4 3 2 1

UV1E
Near GPU
+1.5VS_VGA
For GDDR5 setting. Near GPU Part 5 of 7 2000mA +1.05VS_VGA
3.5A
AA27 AG19
FBVDDQ_0 PEX_IOVDD_0

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
CV273

CV274

CV275

CV276

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
AA30 AG21
FBVDDQ_1 PEX_IOVDD_1

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
CV263

CV264

CV265

CV266

CV267

CV268

CV269

CV270

CV271

CV272

CV43

CV44

CV45

CV46

CV47

CV48

CV49

CV50

CV51

CV52
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
1 1 1 1 1 1 2 2 2 2 1 1 1 1 AB27 AG22 1 1 1 1 1 1 2 2 2 2
AB33 FBVDDQ_2 PEX_IOVDD_2 AG24
AC27 FBVDDQ_3 PEX_IOVDD_3 AH21
AD27 FBVDDQ_4 PEX_IOVDD_4 AH25
2 2 2 2 2 2 1 1 1 1 2 2 2 2 AE27 FBVDDQ_5 PEX_IOVDD_5 2 2 2 2 2 2 1 1 1 1
AF27 FBVDDQ_6
AG27 FBVDDQ_7 AG13
B13 FBVDDQ_8 PEX_IOVDDQ_0 AG15
FBVDDQ_9 PEX_IOVDDQ_1 Under GPU(below 150mils) +1.05VS_VGA For N13P-GT
D B16 AG16 D
FBVDDQ_10 PEX_IOVDDQ_2

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
Under GPU(below 150mils) B19 AG18
+1.5VS_VGA FBVDDQ_11 PEX_IOVDDQ_3

CV54

CV53

CV56

CV55
E13 AG25 1 1 1 1
E16 FBVDDQ_12 PEX_IOVDDQ_4 AH15
FBVDDQ_13 PEX_IOVDDQ_5 <52> DGPU_PWR_EN#

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
E19 AH18
FBVDDQ_14 PEX_IOVDDQ_6 +3VS_VGA
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
CV277

CV281

CV282

CV278

CV279

CV280

CV292

CV287

CV294

CV284

CV285

CV286
1 1 1 1 1 1 1 1 1 1 1 1 H10 AH26 +VDD33MISC
FBVDDQ_15 PEX_IOVDDQ_7

2
2 2 2 2

G
H11 AH27 AO3413_SOT23 QV8
H12 FBVDDQ_16 PEX_IOVDDQ_8 AJ27
H13 FBVDDQ_17 PEX_IOVDDQ_9 AK27 +VDD33MISC 3 1
2 2 2 2 2 2 2 2 2 2 2 2 FBVDDQ_18 PEX_IOVDDQ_10

0.1U_0402_10V7K

0.1U_0402_10V7K
H14 AL27

D
POWER
FBVDDQ_19 PEX_IOVDDQ_11

CV72

CV105
H15 AM28 1 1
H16 FBVDDQ_20 PEX_IOVDDQ_12 AN28
H18 FBVDDQ_21 PEX_IOVDDQ_13
H19 FBVDDQ_22 +3VS_VGA
H20 FBVDDQ_23 2 2
H21 FBVDDQ_24 AH12
FBVDDQ_25 PEX_PLL_HVDD

0.1U_0402_10V7K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
H22
FBVDDQ_26

CV70

CV74

CV73
H23 1 1 1
H24 FBVDDQ_27
H8 FBVDDQ_28 AG12
H9 FBVDDQ_29 PEX_SVDD_3V3
L27 FBVDDQ_30 2 2 2
M27 FBVDDQ_31
N27 FBVDDQ_32 AG26 +PEX_PLLVDD
P27 FBVDDQ_33 PEX_PLLVDD
R27 FBVDDQ_34 +VDD33MISC
FBVDDQ_35 Under GPU(below 150mils)
T27
T30 FBVDDQ_36 J8
T33 FBVDDQ_37 VDD33_0 K8 +3VS_VGA
FBVDDQ_38 VDD33_1 Place near balls Place near GPU
V27 L8
FBVDDQ_39 VDD33_2 RV5
W27 M8 +VDD33 2 1
FBVDDQ_40 VDD33_3

0.1U_0402_10V7K

0.1U_0402_10V7K

4.7U_0603_6.3V6K
W30
FBVDDQ_41 R_short 0_0603_5%

1U_0402_6.3V6K
CV109

CV111

CV293

CV75
W33 1 1 1 1
Y27 FBVDDQ_42
FBVDDQ_43 AH8 +IFPAB_PLLVDD
C IFPAB_PLLVDD AJ8 2 1 C
RV141 IFPAB_RSET 2 2 2 2
1 2 FB_VDDQ_SENSE 1K_0402_1% RV40
<56> VDDQ_SENSE
AG8 +IFPAB_IOVDD @
R_short 0_0402_5% IFPA_IOVDD AG9
RV142 IFPB_IOVDD
1 2 FB_VSS_SENSE F1
FB_VDDQ_SENSE
R_short 0_0402_5%
AF7 +IFPC_PLLVDD 1 2
+1.5VS_VGA F2 IFPC_PLLVDD AF8 10K_0402_5% RV42 2 1 S3 GC6
FB_GND_SENSE IFPC_RSET 1K_0402_1% RV43
AF6 +IFPC_IOVDD 1 2 @ +3VS Off On
1 2 J27 IFPC_IOVDD 10K_0402_5% RV44
RV6 40.2_0402_1% FB_CAL_PD_VDDQ IFPAB & IFPEF have to use
CALIBRATION PIN GDDR5 +3VS_VGA Off Off
AG7 +IFPD_PLLVDD 1 2
1 2 H27 IFPD_PLLVDD AN2 10K_0402_5% RV45 2 1
FB_CAL_PU_GND IFPD_RSET +VDD33MISC Off Off
RV8 40.2_0402_1% 1K_0402_1% RV46
FB_CAL_x_PD_VDDQ 40.2Ohm AG6 +IFPD_IOVDD 1 2 @
1 2 H25 IFPD_IOVDD 10K_0402_5% RV47
RV9 60.4_0402_1% FB_CAL_TERM_GND
FB_CAL_x_PU_GND 40.2Ohm AB8 +IFPEF_PLLVDD
IFPEF_PLVDD AD6 2 1
IFPEF_RSET 1K_0402_1% RV50
FB_CAL_xTERM_GND 60.4Ohm AC7 +IFPE_IOVDD SLI@
IFPE_IOVDD AC8
Place near balls IFPF_IOVDD

LV2 +1.05VS_VGA
120mA 0_0603_5%
+PEX_PLLVDD 2 1

1U_0603_10V6K

4.7U_0805_25V6-K
0.1U_0402_10V7K
N13P-GT1-A2_FCBGA908

CV65

CV3

CV66
1 1 1

2 2 2
B 300ohms @100MHz (ESR=0.25) B

P/N: SM010031680 120ohms @100MHz (ESR=0.18)

+3VS_VGA
LV9 220mA +1.05VS_VGA P/N:SM01000BZ00
2 1 +IFPEF_PLLVDD LV6 200mA Place near balls
0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

BLM18PG181SN1D_0603 2 1 +IFPAB_PLLVDD
1U_0402_6.3V6K
CV149

CV147

CV171

CV173

CV150
4.7U_0603_6.3V6K

1 1 1 1 1 BLM18PG181SN1D_0603
0.1U_0402_10V7K

SLI@
1U_0402_6.3V6K
CV146

CV140

CV141

SLI@ 1 1 1
CV147 CV140
2 2 2 2 2
4.7U_0603_6.3V6K

2 2 2
SLI@ SLI@ SLI@ SLI@ SLI@
SLI@ SLI@
10K_0402_5% Place near balls 10K_0402_5% SLI@
OPT@ OPT@
Place near balls
180ohms @100MHz (ESR=0.2)
220ohms @100MHz (ESR=0.05) P/N: SM010030710
+1.05VS_VGA +3VS_VGA
LV10 570mA LV4
0.1U_0402_10V7K

0.1U_0402_10V7K

2 1 +IFPE_IOVDD 2 1 +IFPAB_IOVDD
0.1U_0402_10V7K

0.1U_0402_10V7K
1U_0402_6.3V6K
CV152

CV172

CV153

CV158

BLM18PG181SN1D_0603 1 1 1 1 BLM18PG181SN1D_0603 IFPA_IOVDD and

1U_0402_6.3V6K
CV156

CV176

CV216

CV197

1 1 1 1
SLI@ SLI@
IFPB_IOVDD combined
4.7U_0603_6.3V6K

CV172 2 2 2 2
4.7U_0603_6.3V6K

2 2 2 2
CV176
SLI@ SLI@
SLI@ SLI@ SLI@ SLI@
SLI@ SLI@
A A
Place near balls
10K_0402_5%
OPT@
10K_0402_5%
OPT@ Place near balls

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 N13P-POWER

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
LA-8692P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Tuesday, June 05, 2012 Sheet 25 of 66
5 4 3 2 1
 5 4 3 2 1

UV1F

Part 6 of 7
A2 D2
AA17 GND_0 GND_100 D31
AA18 GND_1 GND_101 D33
AA20 GND_2 GND_102 E10
AA22 GND_3 GND_103 E22
UV1G +VGA_CORE AB12 GND_4 GND_104 E25
+VGA_CORE AB14 GND_5 GND_105 E5
AB16 GND_6 GND_106 E7
Part 7 of 7 V17 AB19 GND_7 GND_107 F28
AA12 VDD_56 V18 AB2 GND_8 GND_108 F7
AA14 VDD_0 VDD_57 V20 AB21 GND_9 GND_109 G10
D
AA16 VDD_1 VDD_58 V22 A33 GND_10 GND_110 G13 D

AA19 VDD_2 VDD_59 W12 AB23 GND_11 GND_111 G16

AA21 VDD_3 VDD_60 W14 AB28 GND_12 GND_112 G19
AA23 VDD_4 VDD_61 W16 AB30 GND_13 GND_113 G2
AB13 VDD_5 VDD_62 W19 AB32 GND_14 GND_114 G22
AB15 VDD_6 VDD_63 W21 AB5 GND_15 GND_115 G25
AB17 VDD_7 VDD_64 W23 AB7 GND_16 GND_116 G28
AB18 VDD_8 VDD_65 Y13 AC13 GND_17 GND_117 G3
AB20 VDD_9 VDD_66 Y15 AC15 GND_18 GND_118 G30
AB22 VDD_10 VDD_67 Y17 AC17 GND_19 GND_119 G32
AC12 VDD_11 VDD_68 Y18 AC18 GND_20 GND_120 G33
AC14 VDD_12 VDD_69 Y20 AA13 GND_21 GND_121 G5
AC16 VDD_13 VDD_70 Y22 AC20 GND_22 GND_122 G7
AC19 VDD_14 VDD_71 AC22 GND_23 GND_123 K2
AC21 VDD_15 AE2 GND_24 GND_124 K28
AC23 VDD_16 U1 AE28 GND_25 GND_125 K30
M12 VDD_17 XVDD_1 U2 AE30 GND_26 GND_126 K32
M14 VDD_18 XVDD_2 U3 AE32 GND_27 GND_127 K33
VDD_19 XVDD_3 GND_28 GND_128
POWER
M16 U4 AE33 K5
M19 VDD_20 XVDD_4 U5 AE5 GND_29 GND_129 K7
M21 VDD_21 XVDD_5 U6 AE7 GND_30 GND_130 M13
M23 VDD_22 XVDD_6 U7 AH10 GND_31 GND_131 M15
N13 VDD_23 XVDD_7 U8 AA15 GND_32 GND_132 M17
N15 VDD_24 XVDD_8 AH13 GND_33 GND_133 M18
N17 VDD_25 AH16 GND_34 GND_134 M20
N18 VDD_26 V1 AH19 GND_35 GND_135 M22
N20 VDD_27 XVDD_9 V2 AH2 GND_36 GND_136 N12
N22 VDD_28 XVDD_10 V3 AH22 GND_37 GND_137 N14
P12 VDD_29 XVDD_11 V4 AH24 GND_38 GND_138 N16
C P14 VDD_30 XVDD_12 V5 AH28 GND_39 GND_139 N19 C
P16 VDD_31 XVDD_13 V6 AH29 GND_40 GND_140 N2
P19 VDD_32 XVDD_14 V7 AH30 GND_41 GND_141 N21
P21 VDD_33 XVDD_15 V8 AH32 GND_42 GND_142 N23

GND
P23 VDD_34 XVDD_16 AH33 GND_43 GND_143 N28
R13 VDD_35 AH5 GND_44 GND_144 N30
R15 VDD_36 W2 AH7 GND_45 GND_145 N32
R17 VDD_37 XVDD_17 W3 AJ7 GND_46 GND_146 N33
R18 VDD_38 XVDD_18 W4 AK10 GND_47 GND_147 N5
R20 VDD_39 XVDD_19 W5 AK7 GND_48 GND_148 N7
R22 VDD_40 XVDD_20 W7 AL12 GND_49 GND_149 P13
T12 VDD_41 XVDD_21 W8 AL14 GND_50 GND_150 P15
T14 VDD_42 XVDD_22 AL15 GND_51 GND_151 P17
T16 VDD_43 AL17 GND_52 GND_152 P18
T19 VDD_44 Y1 AL18 GND_53 GND_153 P20
T21 VDD_45 XVDD_23 Y2 AL2 GND_54 GND_154 P22
T23 VDD_46 XVDD_24 Y3 AL20 GND_55 GND_155 R12
U13 VDD_47 XVDD_25 Y4 AL21 GND_56 GND_156 R14
U15 VDD_48 XVDD_26 Y5 AL23 GND_57 GND_157 R16
U17 VDD_49 XVDD_27 Y6 AL24 GND_58 GND_158 R19
U18 VDD_50 XVDD_28 Y7 AL26 GND_59 GND_159 R21
U20 VDD_51 XVDD_29 Y8 AL28 GND_60 GND_160 R23
U22 VDD_52 XVDD_30 AL30 GND_61 GND_161 T13
V13 VDD_53 AL32 GND_62 GND_162 T15
V15 VDD_54 AA1 AL33 GND_63 GND_163 T17
VDD_55 XVDD_31 AA2 AL5 GND_64 GND_164 T18
XVDD_32 AA3 AM13 GND_65 GND_165 T2
XVDD_33 AA4 AM16 GND_66 GND_166 T20
XVDD_34 AA5 AM19 GND_67 GND_167 T22
XVDD_35 AA6 AM22 GND_68 GND_168 AG11
B XVDD_36 AA7 AM25 GND_69 GND_169 T28 B
XVDD_37 AA8 AN1 GND_70 GND_170 T32
XVDD_38 AN10 GND_71 GND_171 T5
AN13 GND_72 GND_172 T7
AN16 GND_73 GND_173 U12
AN19 GND_74 GND_174 U14
N13P-GT1-A2_FCBGA908 AN22 GND_75 GND_175 U16
AN25 GND_76 GND_176 U19
AN30 GND_77 GND_177 U21
AN34 GND_78 GND_178 U23
AN4 GND_79 GND_179 V12
AN7 GND_80 GND_180 V14
AP2 GND_81 GND_181 V16
AP33 GND_82 GND_182 V19
B1 GND_83 GND_183 V21
B10 GND_84 GND_184 V23
B22 GND_85 GND_185 W13
B25 GND_86 GND_186 W15
B28 GND_87 GND_187 W17
B31 GND_88 GND_188 W18
B34 GND_89 GND_189 W20
B4 GND_90 GND_190 W22
B7 GND_91 GND_191 W28
C10 GND_92 GND_192 Y12
C13 GND_93 GND_193 Y14
C19 GND_94 GND_194 Y16
C22 GND_95 GND_195 Y19
C25 GND_96 GND_196 Y21
C28 GND_97 GND_197 Y23
A C7 GND_98 GND_198 AH11 A
GND_99 GND_199 C16
GND_OPT W32
GND_OPT

Security Classification LC Future Center Secret Data Title

N13P-GT1-A2_FCBGA908
Issued Date 2012/07/01 Deciphered Date 2014/07/01 N13P-VGA CORE, GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom
LA-8692P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Tuesday, June 05, 2012 Sheet 26 of 66
5 4 3 2 1
 5 4 3 2 1

FBC_D[0..63]
FBA_D[0..63] <30,31> FBC_D[0..63]
<28,29> FBA_D[0..63]

30ohms (ESR=0.01) Bead

UV1B PU for X16 mode PU for X16 mode
P/N;SM010007W00 UV1C
Part 2 of 7
+1.05VS_VGA +FB_PLLAVDD FBA_D0 L28 U30 FBA_CS#_L Part 3 of 7
FBA_D1 M29 FBA_D0 FBA_CMD0 T31 FBA_MA3_BA3_L FBA_CS#_L <28> FBC_D0 G9 D13 FBC_CS#_L
200mA FBA_D2 L29 FBA_D1 FBA_CMD1 U29 FBA_MA2_BA0_L FBA_MA3_BA3_L <28> FBC_D1 E9 FBB_D0 FBB_CMD0 E14 FBC_MA3_BA3_L FBC_CS#_L <30>
FBMA-L11-160808300LMA25T_2P
1 2 +FB_PLLAVDD FBA_D3 M28 FBA_D2
FBA_D3
FBA_CMD2
FBA_CMD3
R34 FBA_MA4_BA2_L FBA_MA2_BA0_L
FBA_MA4_BA2_L
<28>
<28>
FBC_D2 G8 FBB_D1
FBB_D2
FBB_CMD1
FBB_CMD2
F14 FBC_MA2_BA0_L FBC_MA3_BA3_L
FBC_MA2_BA0_L
<30>
<30>
GDDR5
D FBA_D4 N31 R33 FBA_MA5_BA1_L FBC_D3 F9 A12 FBC_MA4_BA2_L D
LV3 FBA_D5 P29
R29
FBA_D4
FBA_D5
FBA_CMD4
FBA_CMD5
U32
U33
FBA_WE#_L FBA_MA5_BA1_L
FBA_WE#_L <28>
<28>
+1.5VS_VGA FBC_D4 F11
G11
FBB_D3
FBB_D4
FBB_CMD3
FBB_CMD4
B12
C14
FBC_MA5_BA1_L FBC_MA4_BA2_L
FBC_MA5_BA1_L
<30>
<30>
+1.5VS_VGA
Mode H - Mirror Mode Mapping
Place close to BGA FBA_D6
FBA_D6 FBA_CMD6
FBA_MA7_MA8_L
FBA_MA7_MA8_L <28>
FBC_D5
FBB_D5 FBB_CMD5
FBC_WE#_L
FBC_WE#_L <30>
FBA_D7 P28 U28 FBA_MA6_MA11_L FBC_D6 F12 B14 FBC_MA7_MA8_L
FBA_D7 FBA_CMD7 FBA_MA6_MA11_L <28> FBB_D6 FBB_CMD6 FBC_MA7_MA8_L <30>

1
FBA_D8 J28 V28 FBA_ABI#_L FBC_D7 G12 G15 FBC_MA6_MA11_L DATA Bus
FBA_D8 FBA_CMD8 FBA_ABI#_L <28> FBB_D7 FBB_CMD7 FBC_MA6_MA11_L <30>

1
FBA_D9 H29 V29 FBA_MA12_RFU_L RV209 FBC_D8 G6 F15 FBC_ABI#_L
FBA_D10 J29 FBA_D9 FBA_CMD9 V30 FBA_MA0_MA10_L FBA_MA12_RFU_L <28> FBC_D9 F5 FBB_D8 FBB_CMD8 E15 FBC_MA12_RFU_L FBC_ABI#_L <30>
FBA_D10 FBA_CMD10 FBA_MA0_MA10_L <28> 10K_0402_5% FBB_D9 FBB_CMD9 FBC_MA12_RFU_L <30>
RV210 Address 0..31 32..63
FBA_D11 H28 U34 FBA_MA1_MA9_L FBC_D10 E6 D15 FBC_MA0_MA10_L 10K_0402_5%
FBA_D12 G29 FBA_D11 FBA_CMD11 U31 FBA_RAS#_L FBA_MA1_MA9_L <28> FBC_D11 F6 FBB_D10 FBB_CMD10 A14 FBC_MA1_MA9_L FBC_MA0_MA10_L <30>
FBx_CMD0 CS#

2
FBA_D13 E31 FBA_D12 FBA_CMD12 V34 FBA_RST#_L FBA_RAS#_L <28> FBC_D12 F4 FBB_D11 FBB_CMD11 D14 FBC_RAS#_L FBC_MA1_MA9_L <30>

2
FBA_D14 E32 FBA_D13 FBA_CMD13 V33 FBA_CKE_L FBA_RST#_L <28> FBC_D13 G4 FBB_D12 FBB_CMD12 A15 FBC_RST#_L FBC_RAS#_L <30>
FBA_D14 FBA_CMD14 FBA_CKE_L <28> FBB_D13 FBB_CMD13 FBC_RST#_L <30> FBx_CMD1 A3_BA3
FBA_D15 F30 Y32 FBA_CAS#_L FBC_D14 E2 B15 FBC_CKE_L
FBA_D16 C34 FBA_D15 FBA_CMD15 AA31 FBA_CS#_H FBA_CAS#_L <28> FBC_D15 F3 FBB_D14 FBB_CMD14 C17 FBC_CAS#_L FBC_CKE_L <30>
FBA_D16 FBA_CMD16 FBA_CS#_H <29> FBB_D15 FBB_CMD15 FBC_CAS#_L <30> FBx_CMD2 A2_BA0
FBA_D17 D32 AA29 FBA_MA3_BA3_H FBC_D16 C2 D18 FBC_CS#_H
FBA_D18 B33 FBA_D17 FBA_CMD17 AA28 FBA_MA2_BA0_H FBA_MA3_BA3_H <29> FBC_D17 D4 FBB_D16 FBB_CMD16 E18 FBC_MA3_BA3_H FBC_CS#_H <31>
FBA_D18 FBA_CMD18 FBA_MA2_BA0_H <29> FBB_D17 FBB_CMD17 FBC_MA3_BA3_H <31> FBx_CMD3 A4_BA2
FBA_D19 C33 AC34 FBA_MA4_BA2_H FBC_D18 D3 F18 FBC_MA2_BA0_H
FBA_D20 F33 FBA_D19 FBA_CMD19 AC33 FBA_MA5_BA1_H FBA_MA4_BA2_H <29> FBC_D19 C1 FBB_D18 FBB_CMD18 A20 FBC_MA4_BA2_H FBC_MA2_BA0_H <31>
FBA_D20 FBA_CMD20 FBA_MA5_BA1_H <29>
+1.5VS_VGA FBB_D19 FBB_CMD19 FBC_MA4_BA2_H <31> FBx_CMD4 A5_BA1
FBA_D21 F32 AA32 FBA_WE#_H FBC_D20 B3 B20 FBC_MA5_BA1_H
FBA_D22 H33 FBA_D21 FBA_CMD21 AA33 FBA_MA7_MA8_H FBA_WE#_H <29> FBC_D21 C4 FBB_D20 FBB_CMD20 C18 FBC_WE#_H FBC_MA5_BA1_H <31>
+1.5VS_VGA
FBA_D22 FBA_CMD22 FBA_MA7_MA8_H <29> FBB_D21 FBB_CMD21 FBC_WE#_H <31> FBx_CMD5 WE#
FBA_D23 H32 Y28 FBA_MA6_MA11_H FBC_D22 B5 B18 FBC_MA7_MA8_H
FBA_D23 FBA_CMD23 FBA_MA6_MA11_H <29> FBB_D22 FBB_CMD22 FBC_MA7_MA8_H <31>

MEMORY INTERFACE

1
FBA_D24 P34 Y29 FBA_ABI#_H FBC_D23 C5 G18 FBC_MA6_MA11_H FBx_CMD6 A7_A8
FBA_D24 FBA_CMD24 FBA_ABI#_H <29> FBB_D23 FBB_CMD23 FBC_MA6_MA11_H <31>

1
FBA_D25 P32 W31 FBA_MA12_RFU_H RV221 FBC_D24 A11 G17 FBC_ABI#_H
FBA_D26 P31 FBA_D25 FBA_CMD25 Y30 FBA_MA0_MA10_H FBA_MA12_RFU_H <29> FBC_D25 C11 FBB_D24 FBB_CMD24 F17 FBC_MA12_RFU_H FBC_ABI#_H <31>
10K_0402_5% RV222 FBx_CMD7 A6_A11

MEMORY INTERFACE B
FBA_D27 P33 FBA_D26 FBA_CMD26 AA34 FBA_MA1_MA9_H FBA_MA0_MA10_H <29> FBC_D26 D11 FBB_D25 FBB_CMD25 D16 FBC_MA0_MA10_H FBC_MA12_RFU_H <31>
FBA_D27 FBA_CMD27 FBA_MA1_MA9_H <29> FBB_D26 FBB_CMD26 FBC_MA0_MA10_H <31> 10K_0402_5%
FBA_D28 L31 Y31 FBA_RAS#_H FBC_D27 B11 A18 FBC_MA1_MA9_H FBx_CMD8 ABI#

2
FBA_D29 L34 FBA_D28 FBA_CMD28 Y34 FBA_RST#_H FBA_RAS#_H <29> FBC_D28 D8 FBB_D27 FBB_CMD27 D17 FBC_RAS#_H FBC_MA1_MA9_H <31>

2
FBA_D30 L32 FBA_D29 FBA_CMD29 Y33 FBA_CKE_H FBA_RST#_H <29> FBC_D29 A8 FBB_D28 FBB_CMD28 A17 FBC_RST#_H FBC_RAS#_H <31>
FBA_D30 FBA_CMD30 FBA_CKE_H <29> FBB_D29 FBB_CMD29 FBC_RST#_H <31> FBx_CMD9 A12_RFU
FBA_D31 L33 V31 FBA_CAS#_H FBC_D30 C8 B17 FBC_CKE_H
FBA_D32 AG28 FBA_D31 FBA_CMD31 FBA_CAS#_H <29> FBC_D31 B8 FBB_D30 FBB_CMD30 E17 FBC_CAS#_H FBC_CKE_H <31>
FBA_D32 FBB_D31 FBB_CMD31 FBC_CAS#_H <31> FBx_CMD10 A0_A10
FBA_D33 AF29 FBC_D32 F24
FBA_D34 AG29 FBA_D33 FBC_D33 G23 FBB_D32
FBA_D34 FBB_D33 FBx_CMD11 A1_A9
FBA_D35 AF28 R32 FBC_D34 E24
C FBA_D36 AD30 FBA_D35 FBA_CMD_RFU0 AC32 FBC_D35 G24 FBB_D34 C12 C
FBA_D36 FBA_CMD_RFU1 FBB_D35 FBB_CMD_RFU0 FBx_CMD12 RAS#
FBA_D37 AD29 FBC_D36 D21 C20
FBA_D38 AC29 FBA_D37 FBC_D37 E21 FBB_D36 FBB_CMD_RFU1
FBA_D38 FBB_D37 FBx_CMD13 RST#
FBA_D39 AD28 @ FBC_D38 G21
FBA_D39 FBB_D38

A
FBA_D40 AJ29 R28 60.4_0402_1%
1 2RV58 FBC_D39 F21 @ FBx_CMD14 CKE#
FBA_D40 FBA_DEBUG0 +1.5VS_VGA FBB_D39
FBA_D41 AK29 AC28 60.4_0402_1%
1 2RV59 FBC_D40 G27 G14 60.4_0402_1%
1 2RV60
FBA_D41 FBA_DEBUG1 FBB_D40 FBB_DEBUG0 +1.5VS_VGA
FBA_D42 AJ30 FBC_D41 D27 G20 60.4_0402_1%
1 2RV61 FBx_CMD15 CAS#
FBA_D43 AK28 FBA_D42 FBC_D42 G26 FBB_D41 FBB_DEBUG1
FBA_D43 @ FBB_D42
FBA_D44 AM29 FBC_D43 E27 @ FBx_CMD16 CS#
FBA_D45 AM31 FBA_D44 R30 FBA_CLK0 FBC_D44 E29 FBB_D43
FBA_D46 AN29 FBA_D45 FBA_CLK0 R31 FBA_CLK0# FBA_CLK0 <28> FBC_D45 F29 FBB_D44 D12 FBC_CLK0
FBA_D46 FBA_CLK0_N FBA_CLK0# <28> FBB_D45 FBB_CLK0 FBC_CLK0 <30> FBx_CMD17 A3_BA3
FBA_D47 AM30 AB31 FBA_CLK1 FBC_D46 E30 E12 FBC_CLK0#
FBA_D48 AN31 FBA_D47 FBA_CLK1 AC31 FBA_CLK1# FBA_CLK1 <29> FBC_D47 D30 FBB_D46 FBB_CLK0_N E20 FBC_CLK1 FBC_CLK0# <30>
FBA_D48 FBA_CLK1_N FBA_CLK1# <29> FBB_D47 FBB_CLK1 FBC_CLK1 <31> FBx_CMD18 A2_BA0
FBA_D49 AN32 FBC_D48 A32 F20 FBC_CLK1#
FBA_D50 AP30 FBA_D49 FBC_D49 C31 FBB_D48 FBB_CLK1_N FBC_CLK1# <31>
FBA_D50 FBB_D49 FBx_CMD19 A4_BA2
FBA_D51 AP32 FBC_D50 C32
FBA_D52 AM33 FBA_D51 K31 FBA_WCK0 FBC_D51 B32 FBB_D50
FBA_D52 FBA_WCK01 FBA_WCK0 <28> FBB_D51 FBx_CMD20 A5_BA1
FBA_D53 AL31 L30 FBA_WCK0_N FBC_D52 D29 F8 FBC_WCK0
FBA_D54 AK33 FBA_D53 FBA_WCK01_N H34 FBA_WCK1 FBA_WCK0_N <28> FBC_D53 A29 FBB_D52 FBB_WCK01 E8 FBC_WCK0_N FBC_WCK0 <30>
FBA_D54 FBA_WCK23 FBA_WCK1 <28> FBB_D53 FBB_WCK01_N FBC_WCK0_N <30> FBx_CMD21 WE#
FBA_D55 AK32 J34 FBA_WCK1_N FBC_D54 C29 A5 FBC_WCK1
FBA_D56 AD34 FBA_D55 FBA_WCK23_N AG30 FBA_WCK2 FBA_WCK1_N <28> FBC_D55 B29 FBB_D54 FBB_WCK23 A6 FBC_WCK1_N FBC_WCK1 <30>
FBA_D56 FBA_WCK45 FBA_WCK2 <29> FBB_D55 FBB_WCK23_N FBC_WCK1_N <30> FBx_CMD22 A7_A8
FBA_D57 AD32 AG31 FBA_WCK2_N FBC_D56 B21 D24 FBC_WCK2
FBA_D58 AC30 FBA_D57 FBA_WCK45_N AJ34 FBA_WCK3 FBA_WCK2_N <29> FBC_D57 C23 FBB_D56 FBB_WCK45 D25 FBC_WCK2_N FBC_WCK2 <31>
FBA_D58 FBA_WCK67 FBA_WCK3 <29> FBB_D57 FBB_WCK45_N FBC_WCK2_N <31> FBx_CMD23 A6_A11
FBA_D59 AD33 AK34 FBA_WCK3_N FBC_D58 A21 B27 FBC_WCK3
FBA_D60 AF31 FBA_D59 FBA_WCK67_N FBA_WCK3_N <29> FBC_D59 C21 FBB_D58 FBB_WCK67 C27 FBC_WCK3_N FBC_WCK3 <31>
FBA_D60 FBB_D59 FBB_WCK67_N FBC_WCK3_N <31> FBx_CMD24 ABI#
FBA_D61 AG34 FBC_D60 B24
FBA_D62 AG32 FBA_D61 FBC_D61 C24 FBB_D60
FBA_D62 FBB_D61 FBx_CMD25 A12_RFU
FBA_D63 AG33 J30 FBC_D62 B26
FBA_D63 FBA_WCKB01 J31 FBC_D63 C26 FBB_D62 D6
FBA_WCKB01_N FBB_D63 FBB_WCKB01 FBx_CMD26 A0_A10
FBA_DBI0# P30 J32 D7
<28> FBA_DBI0# FBA_DBI1# F31 FBA_DQM0 FBA_WCKB23 J33 FBC_DBI0# E11 FBB_WCKB01_N C6
<28> FBA_DBI1# FBA_DQM1 FBA_WCKB23_N GC6 support on 15" <30> FBC_DBI0# FBB_DQM0 FBB_WCKB23 FBx_CMD27 A1_A9
FBA_DBI2# F34 AH31 FBC_DBI1# E3 B6
B <28> FBA_DBI2# FBA_DBI3# M32 FBA_DQM2 FBA_WCKB45 AJ31 <30> FBC_DBI1# FBC_DBI2# A3 FBB_DQM1 FBB_WCKB23_N F26 B
<28> FBA_DBI3# FBA_DQM3 FBA_WCKB45_N FB_CLAMP <30> FBC_DBI2# FBB_DQM2 FBB_WCKB45 FBx_CMD28 RAS#
FBA_DBI4# AD31 AJ32 FBC_DBI3# C9 E26
<29> FBA_DBI4# FBA_DBI5# AL29 FBA_DQM4 FBA_WCKB67 AJ33 <30> FBC_DBI3# FBC_DBI4# F23 FBB_DQM3 FBB_WCKB45_N A26
<29> FBA_DBI5# FBA_DQM5 FBA_WCKB67_N <31> FBC_DBI4# FBB_DQM4 FBB_WCKB67 FBx_CMD29 RST#
FBA_DBI6# AM32 FBC_DBI5# F27 A27
<29> FBA_DBI6# FBA_DBI7# AF34 FBA_DQM6 <31> FBC_DBI5# FBC_DBI6# C30 FBB_DQM5 FBB_WCKB67_N
<29> FBA_DBI7# FBA_DQM7 <31> FBC_DBI6# FBB_DQM6 FBx_CMD30 CKE#
RV66 NOGC6@ 10K_0402_5% FBC_DBI7# A24
FBA_EDC0 M31 E1 2 1 <31> FBC_DBI7# FBB_DQM7
FBA_DQS_WP0 FB_CLAMP FBx_CMD31 CAS#
FBA_EDC1 G31 FBC_EDC0 D10
<28> FBA_EDC[3..0] FBA_DQS_WP1 +FB_PLLAVDD FBB_DQS_WP0
FBA_EDC2 E33 FBC_EDC1 D5
FBA_EDC3 M33 FBA_DQS_WP2 CV106 0.1U_0402_10V7K FBC_EDC2 C3 FBB_DQS_WP1
<29> FBA_EDC[7..4] FBA_EDC4 AE31 FBA_DQS_WP3 K27 1 2 FBC_EDC3 B9 FBB_DQS_WP2
FBA_EDC5 AK30 FBA_DQS_WP4 FB_DLL_AVDD FBC_EDC4 E23 FBB_DQS_WP3 H17
FBA_DQS_WP5 FBB_DQS_WP4 FBB_PLL_AVDD +FB_PLLAVDD

0.1U_0402_10V7K
FBA_EDC6 AN33 Place close to ball FBC_EDC5 E28
FBA_DQS_WP6 FBB_DQS_WP5

CV108
FBA_EDC7 AF33 FBC_EDC6 B30 1
FBA_DQS_WP7 U27 FBC_EDC7 A23 FBB_DQS_WP6
FBA_PLL_AVDD +FB_PLLAVDD FBB_DQS_WP7

22U_0805_6.3V6M
0.1U_0402_10V7K

M30
FBA_DQS_RN0
CV107

CV110
1U_0402_6.3V6K

H30 1 1 1 D9
FBA_DQS_RN1 <30> FBC_EDC[3..0] FBB_DQS_RN0 2

CV39
For N13P-GT GC6 support E34 E4
M34 FBA_DQS_RN2 H26 B2 FBB_DQS_RN1
AF30 FBA_DQS_RN3 FB_VREF <31> FBC_EDC[7..4] A9 FBB_DQS_RN2
AK31 FBA_DQS_RN4 2 2 2 D22 FBB_DQS_RN3
+3VS AM34 FBA_DQS_RN5 D28 FBB_DQS_RN4
FBA_DQS_RN6 FBB_DQS_RN5
Place close to ball
AF32 A30
FBA_DQS_RN7 B23 FBB_DQS_RN6 FBC_RST#_L
FBB_DQS_RN7
1

D @ Place close to ball Place close to BGA FBC_RST#_H

2 QV4
<18> DGPU_GC6_EN
G 2N7002_SOT23

1
S For GC6 test N13P-GT1-A2_FCBGA908
3
1

GC6@ N13P-GT1-A2_FCBGA908 RV74 RV73

@ FBA_RST#_L 10K_0402_5% 10K_0402_5%
0_0402_5% 1 2 GPIO15 FBA_RST#_H
RV169 GPIO15 <23>
RV241 0_0402_5%

2
A A
2

2 1 FB_CLAMP
RV18 1K_0402_1% DV3 RV71 RV72
GC6@ DAN202UT106_SC70-3 10K_0402_5% 10K_0402_5%
GC6_EN 2
1
2

FBVDDQ_PWR_EN <56>
1

3
RV68 Title
Security Classification LC Future Center Secret Data
1

10K_0402_5% GC6@
RV29 N13P-MEM Interface
GC6@
1 2 Issued Date 2012/07/01 Deciphered Date 2014/07/01
200K_0402_5%
2

<19,56,59> DGPU_PWROK
RV156 0_0402_5% THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
NOGC6@ GC6@ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size
R&D Document Number Rev
LA-8692P
2

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Tuesday, June 05, 2012 Sheet 27 of 66
5 4 3 2 1
 5 4 3 2 1

Memory - Lower 32 bits UV3 UV4

MF=0 MF=1 MF=1 MF=0 MF=0 MF=1 MF=1 MF=0

A4 FBA_D0 A4 FBA_D24
FBA_EDC0 C2 DQ24 DQ0 A2 FBA_D1 FBA_EDC3 C2 DQ24 DQ0 A2 FBA_D25
C13 EDC0 EDC3 DQ25 DQ1 B4 FBA_D2 C13 EDC0 EDC3 DQ25 DQ1 B4 FBA_D26
R13 EDC1 EDC2 DQ26 DQ2 B2 R13 EDC1 EDC2 DQ26 DQ2 B2
<27> FBA_D[0..31]
FBA_EDC2
EDC2 EDC1 DQ27 DQ3
FBA_D3 BYTE0 FBA_EDC1
EDC2 EDC1 DQ27 DQ3
FBA_D27
R2 E4 FBA_D4 R2 E4 FBA_D28 BYTE3
EDC3 EDC0 DQ28 DQ4 E2 FBA_D5 EDC3 EDC0 DQ28 DQ4 E2 FBA_D29
DQ29 DQ5 F4 FBA_D6 DQ29 DQ5 F4 FBA_D30
<27> FBA_EDC[3..0] DQ30 DQ6 DQ30 DQ6
FBA_DBI0# D2 F2 FBA_D7 FBA_DBI3# D2 F2 FBA_D31
<27> FBA_DBI0# DBI0# DBI3# DQ31 DQ7 <27> FBA_DBI3# DBI0# DBI3# DQ31 DQ7
D13 A11 D13 A11
FBA_DBI2# P13 DBI1# DBI2# DQ16 DQ8 A13 FBA_DBI1# P13 DBI1# DBI2# DQ16 DQ8 A13
<27> FBA_DBI2# DBI2# DBI1# DQ17 DQ9 <27> FBA_DBI1# DBI2# DBI1# DQ17 DQ9
D
P2 B11 P2 B11 D
DBI3# DBI0# DQ18 DQ10 B13 DBI3# DBI0# DQ18 DQ10 B13
FBA_CLK0 J12 DQ19 DQ11 E11 FBA_CLK0 J12 DQ19 DQ11 E11
<27> FBA_CLK0 CK DQ20 DQ12 CK DQ20 DQ12
FBA_CLK0# J11 E13 FBA_CLK0# J11 E13
<27> FBA_CLK0# CK# DQ21 DQ13 CK# DQ21 DQ13
FBA_CKE_L J3 F11 FBA_CKE_L J3 F11
<27> FBA_CKE_L CKE# DQ22
DQ23
DQ14
DQ15
F13 CKE# DQ22
DQ23
DQ14
DQ15
F13 GDDR5
U11 FBA_D16 U11 FBA_D8
<27> FBA_MA2_BA0_L
FBA_MA2_BA0_L H11
K10 BA0/A2 BA2/A4
DQ8
DQ9
DQ16
DQ17
U13
T11
FBA_D17 FBA_MA4_BA2_L H11
K10 BA0/A2 BA2/A4
DQ8
DQ9
DQ16
DQ17
U13
T11
FBA_D9 Mode H - Mirror Mode Mapping
FBA_MA5_BA1_L FBA_D18 FBA_MA3_BA3_L FBA_D10
<27> FBA_MA5_BA1_L BA1/A5 BA3/A3 DQ10 DQ18 BA1/A5 BA3/A3 DQ10 DQ18
FBA_MA4_BA2_L K11 T13 FBA_D19 FBA_MA2_BA0_L K11 T13 FBA_D11 BYTE1
<27> FBA_MA4_BA2_L BA2/A4 BA0/A2 DQ11 DQ19 BA2/A4 BA0/A2 DQ11 DQ19
FBA_MA3_BA3_L H10 N11 FBA_D20 BYTE2 FBA_MA5_BA1_L H10 N11 FBA_D12 DATA Bus
<27> FBA_MA3_BA3_L BA3/A3 BA1/A5 DQ12 DQ20 BA3/A3 BA1/A5 DQ12 DQ20
N13 FBA_D21 N13 FBA_D13
DQ13 DQ21 M11 DQ13 DQ21 M11 Address
DQ14 DQ22
FBA_D22
DQ14 DQ22
FBA_D14 0..31 32..63
FBA_MA7_MA8_L K4 M13 FBA_D23 FBA_MA0_MA10_L K4 M13 FBA_D15
<27> FBA_MA7_MA8_L A8/A7 A10/A0 DQ15 DQ23 A8/A7 A10/A0 DQ15 DQ23
FBA_MA1_MA9_L H5 U4 FBA_MA6_MA11_L H5 U4 FBx_CMD0 CS#
<27> FBA_MA1_MA9_L A9/A1 A11/A6 DQ0 DQ24 A9/A1 A11/A6 DQ0 DQ24
FBA_MA0_MA10_L H4 U2 FBA_MA7_MA8_L H4 U2
<27> FBA_MA0_MA10_L A10/A0 A8/A7 DQ1 DQ25 A10/A0 A8/A7 DQ1 DQ25
FBA_MA6_MA11_L K5 T4 FBA_MA1_MA9_L K5 T4 FBx_CMD1 A3_BA3
<27> FBA_MA6_MA11_L A11/A6 A9/A1 DQ2 DQ26 A11/A6 A9/A1 DQ2 DQ26
FBA_MA12_RFU_L J5 T2 FBA_MA12_RFU_L J5 T2
<27> FBA_MA12_RFU_L A12/RFU/NC DQ3 DQ27 A12/RFU/NC DQ3 DQ27
N4 N4 FBx_CMD2 A2_BA0
A5 DQ4 DQ28 N2 A5 DQ4 DQ28 N2
U5 VPP/NC DQ5 DQ29 M4 +1.5VS_VGA U5 VPP/NC DQ5 DQ29 M4
VPP/NC DQ6 DQ30 VPP/NC DQ6 DQ30
FBx_CMD3 A4_BA2
2 RV115 1 M2 2 RV116 1 M2
DQ7 DQ31 DQ7 DQ31
1K_0402_1%
+1.5VS_VGA
1K_0402_1%
+1.5VS_VGA
FBx_CMD4 A5_BA1
J1 J1
2 RV117 1 J10 MF 2 RV118 1 J10 MF
SEN SEN FBx_CMD5 WE#
2 RV119 1 1K_0402_1% J13 B1 2 RV120 1 1K_0402_1% J13 B1
ZQ VDDQ D1 ZQ VDDQ D1
121_0402_1%
VDDQ
121_0402_1%
VDDQ
FBx_CMD6 A7_A8
F1 F1
J4 VDDQ M1 J4 VDDQ M1
Follow DG <27> FBA_ABI#_L
FBA_ABI#_L
ABI# VDDQ
FBA_ABI#_L
ABI# VDDQ
FBx_CMD7 A6_A11
FBA_RAS#_L G3 P1 FBA_CAS#_L G3 P1
<27> FBA_RAS#_L RAS# CAS# VDDQ RAS# CAS# VDDQ
FBA_CS#_L G12 T1 FBA_WE#_L G12 T1 FBx_CMD8 ABI#
<27> FBA_CS#_L CS# WE# VDDQ CS# WE# VDDQ
FBA_CLK0 1 2 FBA_CAS#_L L3 G2 FBA_RAS#_L L3 G2
<27> FBA_CAS#_L CAS# RAS# VDDQ CAS# RAS# VDDQ
RV21 40.2_0402_1% FBA_WE#_L L12 L2 FBA_CS#_L L12 L2 FBx_CMD9 A12_RFU
<27> FBA_WE#_L WE# CS# VDDQ WE# CS# VDDQ
B3 B3
2

VDDQ D3 VDDQ D3
VDDQ VDDQ FBx_CMD10 A0_A10
RV123 F3 F3
D5 VDDQ H3 D5 VDDQ H3
160_0402_1% <27> FBA_WCK0_N
FBA_WCK0_N
WCK01# WCK23# VDDQ
FBA_WCK1_N
WCK01# WCK23# VDDQ
FBx_CMD11 A1_A9
C @ FBA_WCK0 D4 K3 FBA_WCK1 D4 K3 C
<27> FBA_WCK0 WCK01 WCK23 VDDQ WCK01 WCK23 VDDQ
M3 M3 FBx_CMD12 RAS#
1

FBA_CLK0# 1 2 FBA_WCK1_N P5 VDDQ P3 FBA_WCK0_N P5 VDDQ P3

<27> FBA_WCK1_N WCK23# WCK01# VDDQ WCK23# WCK01# VDDQ
RV28 40.2_0402_1% FBA_WCK1 P4 T3 FBA_WCK0 P4 T3 FBx_CMD13 RST#
<27> FBA_WCK1 WCK23 WCK01 VDDQ WCK23 WCK01 VDDQ
E5 E5
VDDQ N5 VDDQ N5
VDDQ VDDQ
FBx_CMD14 CKE#
A10 E10 A10 E10
CV155

+FBA_VREFD_L +FBA_VREFD_L
0.01U_0402_25V7K

1 VREFD VDDQ VREFD VDDQ

U10 N10 U10 N10 FBx_CMD15 CAS#
+FBA_VREFC0 J14 VREFD VDDQ B12 +FBA_VREFC0 J14 VREFD VDDQ B12
VREFC VDDQ D12 VREFC VDDQ D12
2 VDDQ VDDQ
FBx_CMD16 CS#
F12 F12
VDDQ H12 VDDQ H12
VDDQ VDDQ FBx_CMD17 A3_BA3
FBA_RST#_L J2 K12 FBA_RST#_L J2 K12
<27> FBA_RST#_L RESET# VDDQ RESET# VDDQ
M12 M12 FBx_CMD18 A2_BA0
VDDQ P12 VDDQ P12
+1.5VS_VGA VDDQ T12 VDDQ T12
VDDQ VDDQ
FBx_CMD19 A4_BA2
G13 G13
H1 VDDQ L13 H1 VDDQ L13
VSS VDDQ VSS VDDQ FBx_CMD20 A5_BA1
1

K1 B14 K1 B14
B5 VSS VDDQ D14 B5 VSS VDDQ D14
RV127
VSS VDDQ VSS VDDQ
FBx_CMD21 WE#
549_0402_1% G5 F14 G5 F14
L5 VSS VDDQ M14 L5 VSS VDDQ M14
VSS VDDQ VSS VDDQ
FBx_CMD22 A7_A8
T5 P14 T5 P14
RV212
2

B10 VSS VDDQ T14 B10 VSS VDDQ T14

VSS VDDQ VSS VDDQ
FBx_CMD23 A6_A11
1 2 +FBA_VREFC0 D10 D10
G10 VSS G10 VSS
931_0402_1% FBx_CMD24 ABI#
820P_0402_25V7

VSS VSS
1

L10 A1 L10 A1
CV42

1 16 mil VSS VSSQ VSS VSSQ

RV128 P10 C1 P10 C1 FBx_CMD25 A12_RFU
1.33K_0402_1% T10 VSS VSSQ E1 T10 VSS VSSQ E1
H14 VSS VSSQ N1 H14 VSS VSSQ N1
2 VSS VSSQ VSS VSSQ FBx_CMD26 A0_A10
K14 R1 K14 R1
2

+1.5VS_VGA VSS VSSQ U1 +1.5VS_VGA VSS VSSQ U1

VSSQ VSSQ FBx_CMD27 A1_A9
H2 H2
G1 VSSQ K2 G1 VSSQ K2
VDD VSSQ VDD VSSQ
FBx_CMD28 RAS#
L1 A3 L1 A3
G4 VDD VSSQ C3 G4 VDD VSSQ C3
VDD VSSQ VDD VSSQ
FBx_CMD29 RST#
L4 E3 L4 E3
C5 VDD VSSQ N3 C5 VDD VSSQ N3
B
+1.5VS_VGA VDD VSSQ VDD VSSQ FBx_CMD30 CKE# B
R5 R3 R5 R3
C10 VDD VSSQ U3 C10 VDD VSSQ U3
VDD VSSQ VDD VSSQ
FBx_CMD31 CAS#
R10 C4 R10 C4
VDD VSSQ VDD VSSQ
1

D11 R4 D11 R4
RV129 G11 VDD VSSQ F5 G11 VDD VSSQ F5
549_0402_1% L11 VDD VSSQ M5 L11 VDD VSSQ M5
P11 VDD VSSQ F10 P11 VDD VSSQ F10
RV213 VDD VSSQ VDD VSSQ
G14 M10 G14 M10
2

1 2 +FBA_VREFD_L L14 VDD VSSQ C11 L14 VDD VSSQ C11

931_0402_1% VDD VSSQ R11 VDD VSSQ R11
820P_0402_25V7

VSSQ VSSQ
1

A12 A12
CV58

1 VSSQ VSSQ
RV130 C12 C12
VSSQ VSSQ
1

D 1.33K_0402_1% E12 E12

2 VSSQ N12 VSSQ N12
<23,29,30,31> MEM_VREF G 2 VSSQ R12 VSSQ R12
2

QV9 170-BALL VSSQ U12 170-BALL VSSQ U12

S
3

2N7002W-T/R7_SOT323-3 VSSQ H13 VSSQ H13

SGRAM GDDR5 VSSQ K13 SGRAM GDDR5 VSSQ K13
VSSQ A14 VSSQ A14
VSSQ C14 VSSQ C14
VSSQ E14 VSSQ E14
VSSQ N14 VSSQ N14
VSSQ R14 VSSQ R14
VSSQ U14 VSSQ U14
VSSQ VSSQ
X76@ X76@

H5GQ1H24AFR-T2L_BGA170 H5GQ1H24AFR-T2L_BGA170
+1.5VS_VGA UV3 SIDE +1.5VS_VGA UV4 SIDE
1U_0603_10V6K

1U_0603_10V6K

1U_0603_10V6K

1U_0603_10V6K

1U_0603_10V6K

1U_0603_10V6K

1U_0603_10V6K

1U_0603_10V6K
10U_0603_6.3V6M

10U_0603_6.3V6M
0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
CV68

CV69

CV77

CV78

CV71

CV76

CV79

CV80
CV166

CV129

CV132

CV133

CV174

CV134

CV135

CV136
2 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1

1 2 2 2 2 2 2 2 1 2 2 2 2 2 2 2
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 N13P-VRAM A Lower
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom
LA-8692P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Tuesday, June 05, 2012 Sheet 28 of 66
5 4 3 2 1
 5 4 3 2 1

Memory - Upper 32 bits UV6

UV5
MF=0 MF=1 MF=1 MF=0
MF=0 MF=1 MF=1 MF=0
A4 FBA_D56
A4 FBA_D32 FBA_EDC7 C2 DQ24 DQ0 A2 FBA_D57
FBA_EDC4 C2 DQ24 DQ0 A2 FBA_D33 C13 EDC0 EDC3 DQ25 DQ1 B4 FBA_D58
C13 EDC0 EDC3 DQ25 DQ1 B4 FBA_D34 FBA_EDC5 R13 EDC1 EDC2 DQ26 DQ2 B2 FBA_D59
FBA_EDC6 R13 EDC1 EDC2 DQ26 DQ2 B2 FBA_D35 R2 EDC2 EDC1 DQ27 DQ3 E4 FBA_D60
<27> FBA_D[63..32] EDC2 EDC1 DQ27 DQ3 BYTE4 EDC3 EDC0 DQ28 DQ4 BYTE7
R2 E4 FBA_D36 E2 FBA_D61
EDC3 EDC0 DQ28 DQ4 E2 FBA_D37 DQ29 DQ5 F4 FBA_D62
DQ29 DQ5 F4 FBA_D38 FBA_DBI7# D2 DQ30 DQ6 F2 FBA_D63
<27> FBA_EDC[7..4] DQ30 DQ6 <27> FBA_DBI7# DBI0# DBI3# DQ31 DQ7
FBA_DBI4# D2 F2 FBA_D39 D13 A11
<27> FBA_DBI4# DBI0# DBI3# DQ31 DQ7 DBI1# DBI2# DQ16 DQ8
D13 A11 FBA_DBI5# P13 A13
DBI1# DBI2# DQ16 DQ8 <27> FBA_DBI5# DBI2# DBI1# DQ17 DQ9
D FBA_DBI6# P13 A13 P2 B11 D
<27> FBA_DBI6# DBI2# DBI1# DQ17 DQ9 DBI3# DBI0# DQ18 DQ10
P2 B11 B13
DBI3# DBI0# DQ18 DQ10 B13 FBA_CLK1 J12 DQ19 DQ11 E11
FBA_CLK1 J12 DQ19 DQ11 E11 FBA_CLK1# J11 CK DQ20 DQ12 E13
<27> FBA_CLK1 CK DQ20 DQ12 CK# DQ21 DQ13
FBA_CLK1# J11 E13 FBA_CKE_H J3 F11
<27> FBA_CLK1# CK# DQ21 DQ13 CKE# DQ22 DQ14
FBA_CKE_H J3 F11 F13
<27> FBA_CKE_H CKE# DQ22 DQ14 DQ23 DQ15
F13 U11 FBA_D40
DQ23 DQ15 U11 FBA_D48 FBA_MA4_BA2_H H11 DQ8 DQ16 U13 FBA_D41
FBA_MA2_BA0_H H11 DQ8 DQ16 U13 FBA_D49 FBA_MA3_BA3_H K10 BA0/A2 BA2/A4 DQ9 DQ17 T11 FBA_D42
<27> FBA_MA2_BA0_H BA0/A2 BA2/A4 DQ9 DQ17 BA1/A5 BA3/A3 DQ10 DQ18
FBA_MA5_BA1_H K10 T11 FBA_D50 FBA_MA2_BA0_H K11 T13 FBA_D43 BYTE5
<27> FBA_MA5_BA1_H BA1/A5 BA3/A3 DQ10 DQ18 BA2/A4 BA0/A2 DQ11 DQ19
FBA_MA4_BA2_H K11 T13 FBA_D51 FBA_MA5_BA1_H H10 N11 FBA_D44
<27>
<27>
FBA_MA4_BA2_H
FBA_MA3_BA3_H
FBA_MA3_BA3_H H10 BA2/A4
BA3/A3
BA0/A2
BA1/A5
DQ11
DQ12
DQ19
DQ20
N11 FBA_D52 BYTE6 BA3/A3 BA1/A5 DQ12
DQ13
DQ20
DQ21
N13 FBA_D45 GDDR5
N13 FBA_D53 M11 FBA_D46

K4
DQ13
DQ14
DQ21
DQ22
M11
M13
FBA_D54 FBA_MA0_MA10_H K4
H5 A8/A7 A10/A0
DQ14
DQ15
DQ22
DQ23
M13
U4
FBA_D47 Mode H - Mirror Mode Mapping
FBA_MA7_MA8_H FBA_D55 FBA_MA6_MA11_H
<27> FBA_MA7_MA8_H A8/A7 A10/A0 DQ15 DQ23 A9/A1 A11/A6 DQ0 DQ24
FBA_MA1_MA9_H H5 U4 FBA_MA7_MA8_H H4 U2
<27> FBA_MA1_MA9_H A9/A1 A11/A6 DQ0 DQ24 A10/A0 A8/A7 DQ1 DQ25
FBA_MA0_MA10_H H4 U2 FBA_MA1_MA9_H K5 T4 DATA Bus
<27> FBA_MA0_MA10_H A10/A0 A8/A7 DQ1 DQ25 A11/A6 A9/A1 DQ2 DQ26
FBA_MA6_MA11_H K5 T4 FBA_MA12_RFU_H J5 T2
<27> FBA_MA6_MA11_H A11/A6 A9/A1 DQ2 DQ26 A12/RFU/NC DQ3 DQ27
FBA_MA12_RFU_H J5 T2 N4 Address 0..31 32..63
<27> FBA_MA12_RFU_H A12/RFU/NC DQ3 DQ27 DQ4 DQ28
N4 A5 N2
A5 DQ4 DQ28 N2 +1.5VS_VGA U5 VPP/NC DQ5 DQ29 M4
VPP/NC DQ5 DQ29 VPP/NC DQ6 DQ30
FBx_CMD0 CS#
U5 M4 2 RV132 1 M2
2 RV131 1 VPP/NC DQ6 DQ30 M2 DQ7 DQ31
DQ7 DQ31
1K_0402_1%
+1.5VS_VGA
FBx_CMD1 A3_BA3
1K_0402_1% J1
J1 +1.5VS_VGA 2 RV134 1 J10 MF
MF SEN FBx_CMD2 A2_BA0
2 RV133 1 J10 2 RV136 1 1K_0402_1% J13 B1
2 RV135 1 J13 SEN B1 ZQ VDDQ D1
1K_0402_1%
ZQ VDDQ
121_0402_1%
VDDQ
FBx_CMD3 A4_BA2
121_0402_1% D1 F1
VDDQ F1 J4 VDDQ M1
Follow DG VDDQ
FBA_ABI#_H
ABI# VDDQ
FBx_CMD4 A5_BA1
FBA_ABI#_H J4 M1 FBA_CAS#_H G3 P1
<27> FBA_ABI#_H ABI# VDDQ RAS# CAS# VDDQ
FBA_RAS#_H G3 P1 FBA_WE#_H G12 T1 FBx_CMD5 WE#
<27> FBA_RAS#_H RAS# CAS# VDDQ CS# WE# VDDQ
FBA_CS#_H G12 T1 FBA_RAS#_H L3 G2
<27> FBA_CS#_H CS# WE# VDDQ CAS# RAS# VDDQ
FBA_CLK1 1 2 FBA_CAS#_H L3 G2 FBA_CS#_H L12 L2 FBx_CMD6 A7_A8
<27> FBA_CAS#_H CAS# RAS# VDDQ WE# CS# VDDQ
RV31 40.2_0402_1% FBA_WE#_H L12 L2 B3
<27> FBA_WE#_H WE# CS# VDDQ VDDQ
B3 D3 FBx_CMD7 A6_A11
VDDQ VDDQ
2

D3 F3
VDDQ F3 D5 VDDQ H3
RV139
VDDQ
FBA_WCK3_N
WCK01# WCK23# VDDQ
FBx_CMD8 ABI#
C 160_0402_1% FBA_WCK2_N D5 H3 FBA_WCK3 D4 K3 C
<27> FBA_WCK2_N WCK01# WCK23# VDDQ WCK01 WCK23 VDDQ
@ FBA_WCK2 D4 K3 M3 FBx_CMD9 A12_RFU
<27> FBA_WCK2 WCK01 WCK23 VDDQ VDDQ
M3 FBA_WCK2_N P5 P3
1

1 2 P5 VDDQ P3 P4 WCK23# WCK01# VDDQ T3

FBA_CLK1#
<27> FBA_WCK3_N
FBA_WCK3_N
WCK23# WCK01# VDDQ
FBA_WCK2
WCK23 WCK01 VDDQ
FBx_CMD10 A0_A10
RV36 40.2_0402_1% FBA_WCK3 P4 T3 E5
<27> FBA_WCK3 WCK23 WCK01 VDDQ VDDQ
E5 N5 FBx_CMD11 A1_A9
VDDQ N5 +FBA_VREFD_H A10 VDDQ E10
A10 VDDQ E10 U10 VREFD VDDQ N10
CV175

+FBA_VREFD_H FBx_CMD12 RAS#

0.01U_0402_25V7K

1 VREFD VDDQ VREFD VDDQ

U10 N10 +FBA_VREFC1 J14 B12
J14 VREFD VDDQ B12 VREFC VDDQ D12
+FBA_VREFC1
VREFC VDDQ VDDQ
FBx_CMD13 RST#
D12 F12
2 VDDQ F12 VDDQ H12
VDDQ VDDQ FBx_CMD14 CKE#
H12 FBA_RST#_H J2 K12
J2 VDDQ K12 RESET# VDDQ M12
<27> FBA_RST#_H
FBA_RST#_H
RESET# VDDQ VDDQ FBx_CMD15 CAS#
M12 P12
VDDQ P12 VDDQ T12
VDDQ VDDQ
FBx_CMD16 CS#
T12 G13
VDDQ G13 H1 VDDQ L13
VDDQ VSS VDDQ FBx_CMD17 A3_BA3
H1 L13 K1 B14
+1.5VS_VGA K1 VSS VDDQ B14 B5 VSS VDDQ D14
VSS VDDQ VSS VDDQ
FBx_CMD18 A2_BA0
B5 D14 G5 F14
G5 VSS VDDQ F14 L5 VSS VDDQ M14 FBx_CMD19 A4_BA2
1

L5 VSS VDDQ M14 T5 VSS VDDQ P14

T5 VSS VDDQ P14 B10 VSS VDDQ T14
RV143
VSS VDDQ VSS VDDQ
FBx_CMD20 A5_BA1
549_0402_1% B10 T14 D10
D10 VSS VDDQ G10 VSS
RV214 VSS VSS FBx_CMD21 WE#
G10 L10 A1
2

1 2 +FBA_VREFC1 L10 VSS A1 P10 VSS VSSQ C1

VSS VSSQ VSS VSSQ FBx_CMD22 A7_A8
931_0402_1% 16 mil P10 C1 T10 E1
820P_0402_25V7

VSS VSSQ VSS VSSQ

1

T10 E1 H14 N1
CV59

1 VSS VSSQ VSS VSSQ

FBx_CMD23 A6_A11
RV144 H14 N1 K14 R1
K14 VSS VSSQ R1 +1.5VS_VGA VSS VSSQ U1
1.33K_0402_1%
+1.5VS_VGA VSS VSSQ VSSQ
FBx_CMD24 ABI#
U1 H2
2 VSSQ H2 G1 VSSQ K2 FBx_CMD25 A12_RFU
2

G1 VSSQ K2 L1 VDD VSSQ A3

L1 VDD VSSQ A3 G4 VDD VSSQ C3
VDD VSSQ VDD VSSQ
FBx_CMD26 A0_A10
G4 C3 L4 E3
L4 VDD VSSQ E3 C5 VDD VSSQ N3
B VDD VSSQ VDD VSSQ FBx_CMD27 A1_A9 B
C5 N3 R5 R3
R5 VDD VSSQ R3 C10 VDD VSSQ U3
VDD VSSQ VDD VSSQ
FBx_CMD28 RAS#
C10 U3 R10 C4
R10 VDD VSSQ C4 D11 VDD VSSQ R4
+1.5VS_VGA VDD VSSQ VDD VSSQ
FBx_CMD29 RST#
D11 R4 G11 F5
G11 VDD VSSQ F5 L11 VDD VSSQ M5
VDD VSSQ VDD VSSQ
FBx_CMD30 CKE#
L11 M5 P11 F10
VDD VSSQ VDD VSSQ
1

P11 F10 G14 M10 FBx_CMD31 CAS#

RV145 G14 VDD VSSQ M10 L14 VDD VSSQ C11
549_0402_1% L14 VDD VSSQ C11 VDD VSSQ R11
VDD VSSQ R11 VSSQ A12
RV215 VSSQ VSSQ
A12 C12
2

1 2 +FBA_VREFD_H VSSQ C12 VSSQ E12

931_0402_1% VSSQ E12 VSSQ N12
820P_0402_25V7
1

VSSQ N12 VSSQ R12

CV60

1 VSSQ VSSQ
RV146 R12 170-BALL U12
VSSQ VSSQ
1

D 1.33K_0402_1% 170-BALL U12 H13

2 VSSQ H13 SGRAM GDDR5 VSSQ K13
<23,28,30,31> MEM_VREF G 2 SGRAM GDDR5 VSSQ K13 VSSQ A14
2

QV11 VSSQ A14 VSSQ C14

S
3

2N7002W-T/R7_SOT323-3 VSSQ C14 VSSQ E14

VSSQ E14 VSSQ N14
VSSQ N14 VSSQ R14
VSSQ R14 VSSQ U14
VSSQ U14 VSSQ
VSSQ X76@
X76@
+1.5VS_VGA UV5 SIDE H5GQ1H24AFR-T2L_BGA170
H5GQ1H24AFR-T2L_BGA170
+1.5VS_VGA UV6 SIDE
1U_0603_25V6

1U_0603_25V6

1U_0603_25V6

1U_0603_25V6
10U_0603_6.3V6M

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
CV84

CV81

CV82

CV83
CV179

CV138

CV142

CV137

2 1 1 1 1 1 1 1
1U_0603_25V6

1U_0603_25V6

1U_0603_25V6

1U_0603_25V6
10U_0603_6.3V6M

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
CV187

CV87

CV88

CV85

CV86

CV145

CV143

CV144
2 1 1 1 1 1 1 1
1 2 2 2 2 2 2 2
A A
1 2 2 2 2 2 2 2

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 N13P-VRAM A Upper
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom
LA-8692P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Tuesday, June 05, 2012 Sheet 29 of 66
5 4 3 2 1
 5 4 3 2 1

Memory Partition C - Lower 32 bits

UV7 UV8

MF=0 MF=1 MF=1 MF=0 MF=0 MF=1 MF=1 MF=0

A4 FBC_D0 A4 FBC_D24
FBC_EDC0 C2 DQ24 DQ0 A2 FBC_D1 FBC_EDC3 C2 DQ24 DQ0 A2 FBC_D25
C13 EDC0 EDC3 DQ25 DQ1 B4 FBC_D2 C13 EDC0 EDC3 DQ25 DQ1 B4 FBC_D26
FBC_EDC2 R13 EDC1 EDC2 DQ26 DQ2 B2 FBC_D3 FBC_EDC1 R13 EDC1 EDC2 DQ26 DQ2 B2 FBC_D27
<27> FBC_D[0..31] R2 EDC2 EDC1 DQ27 DQ3 E4
BYTE0 R2 EDC2 EDC1 DQ27 DQ3 E4
FBC_D4 FBC_D28 BYTE3
EDC3 EDC0 DQ28 DQ4 E2 FBC_D5 EDC3 EDC0 DQ28 DQ4 E2 FBC_D29
DQ29 DQ5 F4 FBC_D6 DQ29 DQ5 F4 FBC_D30
<27> FBC_EDC[3..0] FBC_DBI0# D2 DQ30 DQ6 F2 FBC_D7 FBC_DBI3# D2 DQ30 DQ6 F2 FBC_D31
D <27> FBC_DBI0# DBI0# DBI3# DQ31 DQ7 <27> FBC_DBI3# DBI0# DBI3# DQ31 DQ7 D
D13 A11 D13 A11
FBC_DBI2# P13 DBI1# DBI2# DQ16 DQ8 A13 FBC_DBI1# P13 DBI1# DBI2# DQ16 DQ8 A13
<27> FBC_DBI2# P2 DBI2# DBI1# DQ17 DQ9 B11 <27> FBC_DBI1# P2 DBI2# DBI1# DQ17 DQ9 B11
DBI3# DBI0# DQ18 DQ10 B13 DBI3# DBI0# DQ18 DQ10 B13
FBC_CLK0 J12 DQ19 DQ11 E11 FBC_CLK0 J12 DQ19 DQ11 E11
<27> FBC_CLK0 FBC_CLK0# J11 CK DQ20 DQ12 E13 FBC_CLK0# J11 CK DQ20 DQ12 E13
<27>
<27>
FBC_CLK0#
FBC_CKE_L
FBC_CKE_L J3 CK#
CKE#
DQ21
DQ22
DQ13
DQ14
F11 FBC_CKE_L J3 CK#
CKE#
DQ21
DQ22
DQ13
DQ14
F11 GDDR5
F13 F13

FBC_MA2_BA0_L H11
DQ23
DQ8
DQ15
DQ16
U11
U13
FBC_D16
FBC_D17 FBC_MA4_BA2_L H11
DQ23
DQ8
DQ15
DQ16
U11
U13
FBC_D8
FBC_D9
Mode H - Mirror Mode Mapping
<27> FBC_MA2_BA0_L FBC_MA5_BA1_L K10 BA0/A2 BA2/A4 DQ9 DQ17 T11 FBC_D18 FBC_MA3_BA3_L K10 BA0/A2 BA2/A4 DQ9 DQ17 T11 FBC_D10
<27> FBC_MA5_BA1_L FBC_MA4_BA2_L K11 BA1/A5 BA3/A3 DQ10 DQ18 T13 FBC_D19 FBC_MA2_BA0_L K11 BA1/A5 BA3/A3 DQ10 DQ18 T13 FBC_D11
<27> FBC_MA4_BA2_L BA2/A4 BA0/A2 DQ11 DQ19 BA2/A4 BA0/A2 DQ11 DQ19 BYTE1 DATA Bus
FBC_MA3_BA3_L H10 N11 FBC_D20 BYTE2 FBC_MA5_BA1_L H10 N11 FBC_D12
<27> FBC_MA3_BA3_L BA3/A3 BA1/A5 DQ12 DQ20 N13 FBC_D21 BA3/A3 BA1/A5 DQ12 DQ20 N13 FBC_D13
DQ13 DQ21 DQ13 DQ21
Address 0..31 32..63
M11 FBC_D22 M11 FBC_D14
FBC_MA7_MA8_L K4 DQ14 DQ22 M13 FBC_D23 FBC_MA0_MA10_L K4 DQ14 DQ22 M13 FBC_D15
<27> FBC_MA7_MA8_L A8/A7 A10/A0 DQ15 DQ23 A8/A7 A10/A0 DQ15 DQ23 FBx_CMD0 CS#
FBC_MA1_MA9_L H5 U4 FBC_MA6_MA11_L H5 U4
<27> FBC_MA1_MA9_L FBC_MA0_MA10_L H4 A9/A1 A11/A6 DQ0 DQ24 U2 FBC_MA7_MA8_L H4 A9/A1 A11/A6 DQ0 DQ24 U2
<27> FBC_MA0_MA10_L A10/A0 A8/A7 DQ1 DQ25 A10/A0 A8/A7 DQ1 DQ25 FBx_CMD1 A3_BA3
FBC_MA6_MA11_L K5 T4 FBC_MA1_MA9_L K5 T4
<27> FBC_MA6_MA11_L FBC_MA12_RFU_L J5 A11/A6 A9/A1 DQ2 DQ26 T2 FBC_MA12_RFU_L J5 A11/A6 A9/A1 DQ2 DQ26 T2
<27> FBC_MA12_RFU_L A12/RFU/NC DQ3 DQ27 A12/RFU/NC DQ3 DQ27 FBx_CMD2 A2_BA0
N4 N4
A5 DQ4 DQ28 N2 A5 DQ4 DQ28 N2
VPP/NC DQ5 DQ29 +1.5VS_VGA VPP/NC DQ5 DQ29 FBx_CMD3 A4_BA2
U5 M4 U5 M4
2 RV147 1 VPP/NC DQ6 DQ30 M2 2 RV148 1 VPP/NC DQ6 DQ30 M2
DQ7 DQ31 DQ7 DQ31 FBx_CMD4 A5_BA1
1K_0402_1% 1K_0402_1%
J1 +1.5VS_VGA J1 +1.5VS_VGA FBx_CMD5 WE#
2 RV149 1 J10 MF 2 RV150 1 J10 MF
2 RV151 1 J13 SEN B1 2 RV152 1 J13 SEN B1
1K_0402_1%
ZQ VDDQ
1K_0402_1%
ZQ VDDQ FBx_CMD6 A7_A8
121_0402_1% D1 121_0402_1% D1
VDDQ F1 VDDQ F1
VDDQ VDDQ FBx_CMD7 A6_A11
Follow DG FBC_ABI#_L J4 M1 FBC_ABI#_L J4 M1
<27> FBC_ABI#_L FBC_RAS#_L G3 ABI# VDDQ P1 FBC_CAS#_L G3 ABI# VDDQ P1
<27> FBC_RAS#_L RAS# CAS# VDDQ RAS# CAS# VDDQ FBx_CMD8 ABI#
FBC_CS#_L G12 T1 FBC_WE#_L G12 T1
FBC_CLK0 1 2 <27> FBC_CS#_L FBC_CAS#_L L3 CS# WE# VDDQ G2 FBC_RAS#_L L3 CS# WE# VDDQ G2
<27> FBC_CAS#_L CAS# RAS# VDDQ CAS# RAS# VDDQ FBx_CMD9 A12_RFU
RV37 40.2_0402_1% FBC_WE#_L L12 L2 FBC_CS#_L L12 L2
<27> FBC_WE#_L WE# CS# VDDQ B3 WE# CS# VDDQ B3
VDDQ VDDQ FBx_CMD10 A0_A10
2

C
D3 D3 C
VDDQ F3 VDDQ F3
RV155
VDDQ VDDQ FBx_CMD11 A1_A9
160_0402_1% FBC_WCK0_N D5 H3 FBC_WCK1_N D5 H3
<27> FBC_WCK0_N FBC_WCK0 D4 WCK01# WCK23# VDDQ K3 FBC_WCK1 D4 WCK01# WCK23# VDDQ K3
@
<27> FBC_WCK0 WCK01 WCK23 VDDQ WCK01 WCK23 VDDQ FBx_CMD12 RAS#
M3 M3
1

FBC_CLK0# 1 2 FBC_WCK1_N P5 VDDQ P3 FBC_WCK0_N P5 VDDQ P3

<27> FBC_WCK1_N WCK23# WCK01# VDDQ WCK23# WCK01# VDDQ FBx_CMD13 RST#
RV39 40.2_0402_1% FBC_WCK1 P4 T3 FBC_WCK0 P4 T3
<27> FBC_WCK1 WCK23 WCK01 VDDQ E5 WCK23 WCK01 VDDQ E5
VDDQ VDDQ FBx_CMD14 CKE#
N5 N5
VDDQ VDDQ
CV195
0.01U_0402_25V7K

1 +FBC_VREFD_L A10 E10 +FBC_VREFD_L A10 E10 FBx_CMD15 CAS#

U10 VREFD VDDQ N10 U10 VREFD VDDQ N10
+FBC_VREFC0 J14 VREFD VDDQ B12 +FBC_VREFC0 J14 VREFD VDDQ B12
VREFC VDDQ VREFC VDDQ FBx_CMD16 CS#
D12 D12
2 VDDQ F12 VDDQ F12
VDDQ VDDQ FBx_CMD17 A3_BA3
H12 H12
FBC_RST#_L J2 VDDQ K12 FBC_RST#_L J2 VDDQ K12
<27> FBC_RST#_L RESET# VDDQ RESET# VDDQ FBx_CMD18 A2_BA0
M12 M12
VDDQ P12 VDDQ P12
VDDQ VDDQ FBx_CMD19 A4_BA2
T12 T12
+1.5VS_VGA VDDQ G13 VDDQ G13
VDDQ VDDQ FBx_CMD20 A5_BA1
H1 L13 H1 L13
K1 VSS VDDQ B14 K1 VSS VDDQ B14
VSS VDDQ VSS VDDQ FBx_CMD21 WE#
1

B5 D14 B5 D14
G5 VSS VDDQ F14 G5 VSS VDDQ F14
RV159
VSS VDDQ VSS VDDQ FBx_CMD22 A7_A8
549_0402_1% L5 M14 L5 M14
T5 VSS VDDQ P14 T5 VSS VDDQ P14
RV216 VSS VDDQ VSS VDDQ FBx_CMD23 A6_A11
B10 T14 B10 T14
2

1 2 +FBC_VREFC0 D10 VSS VDDQ D10 VSS VDDQ

VSS VSS FBx_CMD24 ABI#
820P_0402_25V7

931_0402_1% G10 G10

VSS VSS
1

CV61

1 L10 A1 L10 A1 FBx_CMD25 A12_RFU

RV160 P10 VSS VSSQ C1 P10 VSS VSSQ C1
T10 VSS VSSQ E1 T10 VSS VSSQ E1
1.33K_0402_1%
VSS VSSQ VSS VSSQ FBx_CMD26 A0_A10
H14 N1 H14 N1
2 K14 VSS VSSQ R1 K14 VSS VSSQ R1 FBx_CMD27 A1_A9
2

+1.5VS_VGA VSS VSSQ U1 +1.5VS_VGA VSS VSSQ U1

VSSQ H2 VSSQ H2
VSSQ VSSQ FBx_CMD28 RAS#
G1 K2 G1 K2
L1 VDD VSSQ A3 L1 VDD VSSQ A3
B VDD VSSQ VDD VSSQ FBx_CMD29 RST# B
G4 C3 G4 C3
L4 VDD VSSQ E3 L4 VDD VSSQ E3
VDD VSSQ VDD VSSQ FBx_CMD30 CKE#
C5 N3 C5 N3
R5 VDD VSSQ R3 R5 VDD VSSQ R3
+1.5VS_VGA VDD VSSQ VDD VSSQ FBx_CMD31 CAS#
C10 U3 C10 U3
R10 VDD VSSQ C4 R10 VDD VSSQ C4
D11 VDD VSSQ R4 D11 VDD VSSQ R4
VDD VSSQ VDD VSSQ
1

G11 F5 G11 F5
RV161 L11 VDD VSSQ M5 L11 VDD VSSQ M5
549_0402_1% P11 VDD VSSQ F10 P11 VDD VSSQ F10
G14 VDD VSSQ M10 G14 VDD VSSQ M10
RV217 L14 VDD VSSQ C11 L14 VDD VSSQ C11
2

1 2 +FBC_VREFD_L VDD VSSQ R11 VDD VSSQ R11

VSSQ VSSQ
820P_0402_25V7

931_0402_1% A12 A12

VSSQ VSSQ
1

CV62

1 C12 C12
RV162 VSSQ E12 VSSQ E12
1.33K_0402_1% VSSQ N12 VSSQ N12
VSSQ R12 VSSQ R12
VSSQ VSSQ
1

D 2 170-BALL U12 170-BALL U12

2

2 VSSQ H13 VSSQ H13

<23,28,29,31> MEM_VREF G SGRAM GDDR5 VSSQ K13 SGRAM GDDR5 VSSQ K13
QV13 VSSQ A14 VSSQ A14
S
3

2N7002W-T/R7_SOT323-3 VSSQ C14 VSSQ C14

VSSQ E14 VSSQ E14
VSSQ N14 VSSQ N14
VSSQ R14 VSSQ R14
VSSQ U14 +1.5VS_VGA VSSQ U14
VSSQ UV8 SIDE VSSQ
X76@ X76@
10U_0603_6.3V6M

1U_0603_25V6

1U_0603_25V6

1U_0603_25V6

1U_0603_25V6

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
+1.5VS_VGA UV7 SIDE
CV207

CV95

CV96

CV93

CV94

CV163

CV161

CV162
H5GQ1H24AFR-T2L_BGA170 2 1 1 1 1 1 1 1 H5GQ1H24AFR-T2L_BGA170
10U_0603_6.3V6M

1U_0603_25V6

1U_0603_25V6

1U_0603_25V6

1U_0603_25V6

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
CV199

CV91

CV92

CV89

CV90

CV160

CV157

CV159

2 1 1 1 1 1 1 1
1 2 2 2 2 2 2 2

A A
1 2 2 2 2 2 2 2

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 N12P-VRAM C Lower

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size
R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-8692P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Tuesday, June 05, 2012 Sheet 30 of 66
5 4 3 2 1
 5 4 3 2 1

Memory Partition C - Upper 32 bits

UV9

MF=0 MF=1 MF=1 MF=0 UV10

A4 FBC_D32 MF=0 MF=1 MF=1 MF=0

FBC_EDC4 C2 DQ24 DQ0 A2 FBC_D33
C13 EDC0 EDC3 DQ25 DQ1 B4 FBC_D34 A4 FBC_D56
FBC_EDC6 R13 EDC1 EDC2 DQ26 DQ2 B2 FBC_D35 FBC_EDC7 C2 DQ24 DQ0 A2 FBC_D57
<27> FBC_D[63..32] R2 EDC2 EDC1 DQ27 DQ3 E4
BYTE4 C13 EDC0 EDC3 DQ25 DQ1 B4
FBC_D36 FBC_D58
EDC3 EDC0 DQ28 DQ4 E2 FBC_D37 FBC_EDC5 R13 EDC1 EDC2 DQ26 DQ2 B2 FBC_D59
DQ29 DQ5 F4 FBC_D38 R2 EDC2 EDC1 DQ27 DQ3 E4 FBC_D60
<27> FBC_EDC[7..4] D2 DQ30 DQ6 F2 EDC3 EDC0 DQ28 DQ4 E2
BYTE7
FBC_DBI4# FBC_D39 FBC_D61
<27> FBC_DBI4# D13 DBI0# DBI3# DQ31 DQ7 A11 DQ29 DQ5 F4 FBC_D62
D DBI1# DBI2# DQ16 DQ8 DQ30 DQ6 D
FBC_DBI6# P13 A13 FBC_DBI7# D2 F2 FBC_D63
<27> FBC_DBI6# P2 DBI2#
DBI3#
DBI1#
DBI0#
DQ17
DQ18
DQ9
DQ10
B11 <27> FBC_DBI7# D13 DBI0#
DBI1#
DBI3#
DBI2#
DQ31
DQ16
DQ7
DQ8
A11 GDDR5
B13 FBC_DBI5# P13 A13
<27> FBC_CLK1
FBC_CLK1
FBC_CLK1#
J12
J11 CK
DQ19
DQ20
DQ11
DQ12
E11
E13
<27> FBC_DBI5# P2 DBI2#
DBI3#
DBI1#
DBI0#
DQ17
DQ18
DQ9
DQ10
B11
B13
Mode H - Mirror Mode Mapping
<27> FBC_CLK1# FBC_CKE_H J3 CK# DQ21 DQ13 F11 FBC_CLK1 J12 DQ19 DQ11 E11
<27> FBC_CKE_H CKE# DQ22 DQ14 F13 FBC_CLK1# J11 CK DQ20 DQ12 E13
DQ23 DQ15 CK# DQ21 DQ13 DATA Bus
U11 FBC_D48 FBC_CKE_H J3 F11
FBC_MA2_BA0_H H11 DQ8 DQ16 U13 FBC_D49 CKE# DQ22 DQ14 F13
<27> FBC_MA2_BA0_H BA0/A2 BA2/A4 DQ9 DQ17 DQ23 DQ15
Address 0..31 32..63
FBC_MA5_BA1_H K10 T11 FBC_D50 U11 FBC_D40
<27> FBC_MA5_BA1_H FBC_MA4_BA2_H K11 BA1/A5 BA3/A3 DQ10 DQ18 T13 FBC_D51 FBC_MA4_BA2_H H11 DQ8 DQ16 U13 FBC_D41
<27> FBC_MA4_BA2_H BA2/A4 BA0/A2 DQ11 DQ19 BA0/A2 BA2/A4 DQ9 DQ17 FBx_CMD0 CS#
FBC_MA3_BA3_H H10 N11 FBC_D52 BYTE6 FBC_MA3_BA3_H K10 T11 FBC_D42
<27> FBC_MA3_BA3_H BA3/A3 BA1/A5 DQ12 DQ20 N13 FBC_D53 FBC_MA2_BA0_H K11 BA1/A5 BA3/A3 DQ10 DQ18 T13 FBC_D43
DQ13 DQ21 BA2/A4 BA0/A2 DQ11 DQ19 BYTE5 FBx_CMD1 A3_BA3
M11 FBC_D54 FBC_MA5_BA1_H H10 N11 FBC_D44
FBC_MA7_MA8_H K4 DQ14 DQ22 M13 FBC_D55 BA3/A3 BA1/A5 DQ12 DQ20 N13 FBC_D45
<27> FBC_MA7_MA8_H A8/A7 A10/A0 DQ15 DQ23 DQ13 DQ21 FBx_CMD2 A2_BA0
FBC_MA1_MA9_H H5 U4 M11 FBC_D46
<27> FBC_MA1_MA9_H FBC_MA0_MA10_H H4 A9/A1 A11/A6 DQ0 DQ24 U2 FBC_MA0_MA10_H K4 DQ14 DQ22 M13 FBC_D47
<27> FBC_MA0_MA10_H A10/A0 A8/A7 DQ1 DQ25 A8/A7 A10/A0 DQ15 DQ23 FBx_CMD3 A4_BA2
FBC_MA6_MA11_H K5 T4 FBC_MA6_MA11_H H5 U4
<27> FBC_MA6_MA11_H FBC_MA12_RFU_H J5 A11/A6 A9/A1 DQ2 DQ26 T2 FBC_MA7_MA8_H H4 A9/A1 A11/A6 DQ0 DQ24 U2
<27> FBC_MA12_RFU_H A12/RFU/NC DQ3 DQ27 A10/A0 A8/A7 DQ1 DQ25 FBx_CMD4 A5_BA1
N4 FBC_MA1_MA9_H K5 T4
A5 DQ4 DQ28 N2 FBC_MA12_RFU_H J5 A11/A6 A9/A1 DQ2 DQ26 T2
VPP/NC DQ5 DQ29 A12/RFU/NC DQ3 DQ27 FBx_CMD5 WE#
U5 M4 N4
2 RV163 1 VPP/NC DQ6 DQ30 M2 A5 DQ4 DQ28 N2
DQ7 DQ31 +1.5VS_VGA VPP/NC DQ5 DQ29 FBx_CMD6 A7_A8
1K_0402_1% U5 M4
J1 +1.5VS_VGA 2 RV164 1 VPP/NC DQ6 DQ30 M2
MF DQ7 DQ31 FBx_CMD7 A6_A11
2 RV165 1 J10 1K_0402_1%
2 RV167 1 J13 SEN B1 J1 +1.5VS_VGA
1K_0402_1%
ZQ VDDQ MF FBx_CMD8 ABI#
121_0402_1% D1 2 RV166 1 J10
VDDQ F1 2 RV168 1 J13 SEN B1
VDDQ
1K_0402_1%
ZQ VDDQ FBx_CMD9 A12_RFU
Follow DG FBC_ABI#_H J4 M1 121_0402_1% D1
<27> FBC_ABI#_H FBC_RAS#_H G3 ABI# VDDQ P1 VDDQ F1
<27> FBC_RAS#_H RAS# CAS# VDDQ VDDQ FBx_CMD10 A0_A10
FBC_CS#_H G12 T1 FBC_ABI#_H J4 M1
FBC_CLK1 1 2 <27> FBC_CS#_H FBC_CAS#_H L3 CS# WE# VDDQ G2 FBC_CAS#_H G3 ABI# VDDQ P1
<27> FBC_CAS#_H CAS# RAS# VDDQ RAS# CAS# VDDQ FBx_CMD11 A1_A9
RV41 40.2_0402_1% FBC_WE#_H L12 L2 FBC_WE#_H G12 T1
<27> FBC_WE#_H WE# CS# VDDQ B3 FBC_RAS#_H L3 CS# WE# VDDQ G2
VDDQ CAS# RAS# VDDQ FBx_CMD12 RAS#
2

D3 FBC_CS#_H L12 L2
VDDQ F3 WE# CS# VDDQ B3
C RV171
VDDQ VDDQ FBx_CMD13 RST# C
160_0402_1% FBC_WCK2_N D5 H3 D3
<27> FBC_WCK2_N FBC_WCK2 D4 WCK01# WCK23# VDDQ K3 VDDQ F3
@
<27> FBC_WCK2 WCK01 WCK23 VDDQ VDDQ FBx_CMD14 CKE#
M3 FBC_WCK3_N D5 H3
1

FBC_CLK1# 1 2 FBC_WCK3_N P5 VDDQ P3 FBC_WCK3 D4 WCK01# WCK23# VDDQ K3

<27> FBC_WCK3_N WCK23# WCK01# VDDQ WCK01 WCK23 VDDQ FBx_CMD15 CAS#
RV48 40.2_0402_1% FBC_WCK3 P4 T3 M3
<27> FBC_WCK3 WCK23 WCK01 VDDQ E5 FBC_WCK2_N P5 VDDQ P3
VDDQ WCK23# WCK01# VDDQ FBx_CMD16 CS#
N5 FBC_WCK2 P4 T3
VDDQ WCK23 WCK01 VDDQ
CV215
0.01U_0402_25V7K

1 +FBC_VREFD_H A10 E10 E5 FBx_CMD17 A3_BA3

U10 VREFD VDDQ N10 VDDQ N5
+FBC_VREFC1 J14 VREFD VDDQ B12 +FBC_VREFD_H A10 VDDQ E10
VREFC VDDQ VREFD VDDQ FBx_CMD18 A2_BA0
D12 U10 N10
2 VDDQ F12 +FBC_VREFC1 J14 VREFD VDDQ B12
VDDQ VREFC VDDQ FBx_CMD19 A4_BA2
H12 D12
FBC_RST#_H J2 VDDQ K12 VDDQ F12
<27> FBC_RST#_H RESET# VDDQ VDDQ FBx_CMD20 A5_BA1
M12 H12
VDDQ P12 FBC_RST#_H J2 VDDQ K12
VDDQ RESET# VDDQ FBx_CMD21 WE#
T12 M12
+1.5VS_VGA VDDQ G13 VDDQ P12
VDDQ VDDQ FBx_CMD22 A7_A8
H1 L13 T12
K1 VSS VDDQ B14 VDDQ G13
VSS VDDQ VDDQ FBx_CMD23 A6_A11
1

B5 D14 H1 L13
G5 VSS VDDQ F14 K1 VSS VDDQ B14
RV175
VSS VDDQ VSS VDDQ FBx_CMD24 ABI#
549_0402_1% L5 M14 B5 D14
T5 VSS VDDQ P14 G5 VSS VDDQ F14
RV218 VSS VDDQ VSS VDDQ FBx_CMD25 A12_RFU
B10 T14 L5 M14
2

1 2 +FBC_VREFC1 D10 VSS VDDQ T5 VSS VDDQ P14

VSS VSS VDDQ FBx_CMD26 A0_A10
820P_0402_25V7

931_0402_1% G10 B10 T14

VSS VSS VDDQ
1

CV63

1 L10 A1 D10 FBx_CMD27 A1_A9

RV176 P10 VSS VSSQ C1 G10 VSS
T10 VSS VSSQ E1 L10 VSS A1
1.33K_0402_1%
VSS VSSQ VSS VSSQ FBx_CMD28 RAS#
H14 N1 P10 C1
2 K14 VSS VSSQ R1 T10 VSS VSSQ E1 FBx_CMD29 RST#
2

+1.5VS_VGA VSS VSSQ U1 H14 VSS VSSQ N1

VSSQ H2 K14 VSS VSSQ R1
VSSQ +1.5VS_VGA VSS VSSQ FBx_CMD30 CKE#
G1 K2 U1
L1 VDD VSSQ A3 VSSQ H2
VDD VSSQ VSSQ FBx_CMD31 CAS#
B
G4 C3 G1 K2 B
L4 VDD VSSQ E3 L1 VDD VSSQ A3
C5 VDD VSSQ N3 G4 VDD VSSQ C3
+1.5VS_VGA R5 VDD VSSQ R3 L4 VDD VSSQ E3
C10 VDD VSSQ U3 C5 VDD VSSQ N3
R10 VDD VSSQ C4 R5 VDD VSSQ R3
VDD VSSQ VDD VSSQ
1

D11 R4 C10 U3
RV177 G11 VDD VSSQ F5 R10 VDD VSSQ C4
549_0402_1% L11 VDD VSSQ M5 D11 VDD VSSQ R4
P11 VDD VSSQ F10 G11 VDD VSSQ F5
RV219 G14 VDD VSSQ M10 L11 VDD VSSQ M5
2

1 2 +FBC_VREFD_H L14 VDD VSSQ C11 P11 VDD VSSQ F10

VDD VSSQ VDD VSSQ
820P_0402_25V7

931_0402_1% R11 G14 M10

VSSQ VDD VSSQ
1

CV64

1 A12 L14 C11

RV178 VSSQ C12 VDD VSSQ R11
1.33K_0402_1% VSSQ E12 VSSQ A12
VSSQ N12 VSSQ C12
VSSQ VSSQ
1

D 2 R12 E12
2

2 170-BALL VSSQ U12 VSSQ N12

<23,28,29,30> MEM_VREF G VSSQ H13 VSSQ R12
QV15 SGRAM GDDR5 VSSQ K13 170-BALL VSSQ U12
S
3

2N7002W-T/R7_SOT323-3 VSSQ A14 VSSQ H13

VSSQ C14 SGRAM GDDR5 VSSQ K13
VSSQ E14 VSSQ A14
VSSQ N14 VSSQ C14
VSSQ R14 VSSQ E14
VSSQ U14 VSSQ N14
VSSQ +1.5VS_VGA VSSQ R14
UV10 SIDE VSSQ U14
X76@
+1.5VS_VGA VSSQ
UV9 SIDE
10U_0603_6.3V6M

1U_0603_25V6

1U_0603_25V6

1U_0603_25V6

1U_0603_25V6

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
H5GQ1H24AFR-T2L_BGA170 X76@
CV227

CV103

CV104

CV101

CV102

CV170

CV168

CV169
2 1 1 1 1 1 1 1
10U_0603_6.3V6M

1U_0603_25V6

1U_0603_25V6

1U_0603_25V6

1U_0603_25V6

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

H5GQ1H24AFR-T2L_BGA170
CV245

CV99

CV100

CV97

CV98

CV167

CV164

CV165

2 1 1 1 1 1 1 1
1 2 2 2 2 2 2 2

1 2 2 2 2 2 2 2
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 N12P-VRAM C Upper

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size
R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-8692P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Tuesday, June 05, 2012 Sheet 31 of 66
5 4 3 2 1
 5 4 3 2 1

SLI SLI_B+

D D
JSLI1

1 2
3 GND GND 4
5 NC GND 6
7 NC GND 8
9 NC GND 10
11 NC +19V 12
13 NC +19V 14
15 NC +19V 16
17 NC +19V 18
PCIE_CTX_GRX_N15 19 GND +19V 20
PCIE_CTX_GRX_P15 21 PEG_RX_N7 +19V 22
23 PEG_RX_P7 +19V 24
PCIE_CTX_GRX_N14 25 GND +19V 26
PCIE_CTX_GRX_P14 27 PEG_RX_N6 GND 28
29 PEG_RX_P6 GND 30
GND GND +5V_SLI

31 32
PCIE_CTX_GRX_N13 33 GND GND 34
PCIE_CTX_GRX_P13 35 PEG_RX_N5 GND 36
37 PEG_RX_P5 GND 38
PCIE_CTX_GRX_N12 39 GND +5V 40
PCIE_CTX_GRX_P12 41 PEG_RX_N4 +5V 42
43 PEG_RX_P4 +5V 44
PCIE_CTX_GRX_N11 45 GND +5V 46
PCIE_CTX_GRX_P11 47 PEG_RX_N3 +5V 48
49 PEG_RX_P3 GND 50
GND GND +3VS_SLI
PCIE_CTX_GRX_N10 51 52
C PCIE_CTX_GRX_P10 53 PEG_RX_N2 GND 54 C
55 PEG_RX_P2 NC 56
PCIE_CTX_GRX_N9 57 GND +3V 58
PCIE_CTX_GRX_P9 59 PEG_RX_N1 +3V 60
61 PEG_RX_P1 GND 62
PCIE_CTX_GRX_N8 63 GND NC 64
PCIE_CTX_GRX_P8 65 PEG_RX_N0 NC 66
PEG_RX_P0 NC SLI_B+_ON# <53>
67 68
GND NC SLI_5V_ON# <53>
69 70
GND NC SUSP# <45,52,56,58,59>
PCIE_CRX_GTX_N15 0.22U_0402_10V6K 2 1 SLI@ CV20 PCIE_CRX_C_GTX_N15 71 72
PCIE_CRX_GTX_P15 0.22U_0402_10V6K 2 1 SLI@ CV22 PCIE_CRX_C_GTX_P15 73 PEG_TX_N7 NC 74 SLI_FAN_SPEED
PEG_TX_P7 TH_TACH SLI_FAN_SPEED <42,45>
75 76 SLI_FAN_PWM SLI_FAN_PWM <42,45>
PCIE_CTX_GRX_N[0..15] PCIE_CRX_GTX_N14 0.22U_0402_10V6K 2 1 SLI@ CV16 PCIE_CRX_C_GTX_N14 77 GND TH_PWN 78
<23,5> PCIE_CTX_GRX_N[0..15] PEG_TX_N6 NC
PCIE_CRX_GTX_P14 0.22U_0402_10V6K 2 1 SLI@ CV18 PCIE_CRX_C_GTX_P14 79 80
PCIE_CTX_GRX_P[0..15] 81 PEG_TX_P6 PEX_STD_SW# 82
<23,5> PCIE_CTX_GRX_P[0..15] GND AC_DC VGA_AC_DET <23,45,59>
PCIE_CRX_GTX_N13 0.22U_0402_10V6K 2 1 SLI@ CV19 PCIE_CRX_C_GTX_N13 83 84 S_DGPU_PWROK
PCIE_CRX_GTX_N[0..15] PEG_TX_N5 PWR_GOOD S_DGPU_PWROK <19>
PCIE_CRX_GTX_P13 0.22U_0402_10V6K 2 1 SLI@ CV14 PCIE_CRX_C_GTX_P13 85 86 S_DGPU_PWR_EN# S_DGPU_PWR_EN# <52>
<23,5> PCIE_CRX_GTX_N[0..15] PEG_TX_P5 PWR_EN
87 88 CLK2_REQ_GPU#_R CLK2_REQ_GPU#_R <15>
PCIE_CRX_GTX_P[0..15] PCIE_CRX_GTX_N12 0.22U_0402_10V6K 2 1 SLI@ CV15 PCIE_CRX_C_GTX_N12 89 GND CLK_REQ# 90 S_NVDD_PWR_EN
<23,5> PCIE_CRX_GTX_P[0..15] PEG_TX_N4 RSVD S_NVDD_PWR_EN <19>
PCIE_CRX_GTX_P12 0.22U_0402_10V6K 2 1 SLI@ CV17 PCIE_CRX_C_GTX_P12 91 92 S_DGPU_RST
PEG_TX_P4 RSVD S_DGPU_RST <15,18>
93 94
GND NC SLAVE_PRESENT# <19>
PCIE_CRX_GTX_N11 0.22U_0402_10V6K 2 1 SLI@ CV12 PCIE_CRX_C_GTX_N11 95 96 PCH_THRMTRIP#_R <19,23>
PCIE_CRX_GTX_P11 0.22U_0402_10V6K 2 1 SLI@ CV13 PCIE_CRX_C_GTX_P11 97 PEG_TX_N3 TH_OVERT# 98 PLT_RST#
PEG_TX_P3 NC PLT_RST# <18,23,38,39,44,45,6>
99 100 GC6_EVENT_SLI# 1 2
GND RSVD S_Toggle_REQ# <19>
PCIE_CRX_GTX_N10 0.22U_0402_10V6K 2 1 SLI@ CV10 PCIE_CRX_C_GTX_N10 101 102 RV158 GC6@ 0_0402_5%
PEG_TX_N2 SMB_DAT EC_SMB_DA2 <15,23,41,45>
PCIE_CRX_GTX_P10 0.22U_0402_10V6K 2 1 SLI@ CV11 PCIE_CRX_C_GTX_P10 103 104
PEG_TX_P2 SMB_CLK EC_SMB_CK2 <15,23,41,45>
105 106

CV296
GND WAKE# 1

0.01U_0402_25V7K
PCIE_CRX_GTX_N9 0.22U_0402_10V6K 2 1 SLI@ CV8 PCIE_CRX_C_GTX_N9 107 108 S_DGPU_GC6_EN
PEG_TX_N1 RSVD S_DGPU_GC6_EN <15>
PCIE_CRX_GTX_P9 0.22U_0402_10V6K 2 1 SLI@ CV9 PCIE_CRX_C_GTX_P9 109 110 S_DGPU_PWR_EN S_DGPU_PWR_EN <19,52>
111 PEG_TX_P1 RSVD 112
PCIE_CRX_GTX_N8 0.22U_0402_10V6K 2 1 SLI@ CV6 PCIE_CRX_C_GTX_N8 113 GND GND 114 CLK_PCIE_2VGA# 2
PEG_TX_N0 CLK_PCIE_N CLK_PCIE_2VGA# <15>
PCIE_CRX_GTX_P8 0.22U_0402_10V6K 2 1 SLI@ CV7 PCIE_CRX_C_GTX_P8 115 116 CLK_PCIE_2VGA
B PEG_TX_P0 CLK_PCIE_P CLK_PCIE_2VGA <15> B
117 118
GND GND
119 120
121 GND GND 122
GND GND

TE_2199022-1

ME@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 DDRIII-SODIMM SLOT1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
LA-8692P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Tuesday, June 05, 2012 Sheet 32 of 66
5 4 3 2 1
 5 4 3 2 1

+3VS_VGA
Physical Logical Logical Logical Logical
Strapping pin Power Rail Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
ROM_SCLK +3VS_VGA PCI_DEVID[4] SUB_VENDOR SLOT_CLK_CFG PEX_PLL_EN_TERM
ROM_SI +3VS_VGA RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0]
ROM_SO +3VS_VGA FB[1] FB[0] SMB_ALT_ADDR VGA_DEVICE

2
@
RV92 RV93 RV94 RV121 RV122 STRAP0 +3VS_VGA USER[3] USER[2] USER[1] USER[0]
45.3K_0402_1% 4.99K_0402_1% 10K_0402_1% 4.99K_0402_1% 20K_0402_1%
@ STRAP1 +3VS_VGA 3GIO_PAD_CFG_ADR[3] 3GIO_PAD_CFG_ADR[2] 3GIO_PAD_CFG_ADR[1] 3GIO_PAD_CFG_ADR[0]
@ SLI@
D D

1
STRAP2 +3VS_VGA PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]
<24> STRAP0 STRAP0
<24> STRAP1 STRAP1 STRAP3 +3VS_VGA SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED
<24> STRAP2 STRAP2
<24> STRAP3 STRAP3 STRAP4 +3VS_VGA RESERVED PCIE_SPEED_ PCIE_MAX_SPEED DP_PLL_VDD33V
STRAP4
<24> STRAP4 CHANGE_GEN3
2

2
OPT@ Pull-up to
@ RV95 RV96 RV97 RV124 RV125 Resistor Values Pull-down to Gnd
45.3K_0402_1% 4.99K_0402_1% 10K_0402_1% 4.99K_0402_1% 45.3K_0402_1%
+3VS_VGA
5K 1000 0000
1

1
10K 1001 0001
15K 1010 0010
Change STRAP1 to 20K 1011 0011
"0000" for N13P-GT
25K 1100 0100
30K 1101 0101
35K 1110 0110
+3VS_VGA RV100 45K
C 1111 0111 C

3GIO_PADCFG XCLK_417
2

4.99K_0402_1%
RV98 RV99 RV100 SLI@ 3GIO_PADCFG[3:0] 0 277MHz (Default)
4.99K_0402_1% 10K_0402_1% 24.9K_0402_1%
@
GC6@ 0000 Notebook Default 1 Reserved
1

RV100

<24> ROM_SI ROM_SI SLOT_CLK_CFG

<24> ROM_SO ROM_SO
<24> ROM_SCLK ROM_SCLK 0 GPU and MCH don't share a common reference clock
4.99K_0402_1%
OPT@
2

1 GPU and MCH share a common reference clock (Default)

2

RV101
X76 30K_0402_1% RV102 RV103
X76@ 30K_0402_1%
@
15K_0402_1%
@ SMBUS_ALT_ADDR VGA_DEVICE
1

0 0x9E (Default) 0 3D Device (Class Code 302h)

B B
1 0x9C (Multi-GPU usage) 1 VGA Device (Default)
X76
USER Straps
GPU FB Memory (GDDR5) ROM_SI ROM_SO ROM_SCLK STRAP0 STRAP1 STRAP2 STRAP3 STRAP4
SUB_VENDOR
User[3:0]
0 No VBIOS ROM
K4G20325FD-FC04 2G PD 30K PU 25K PU 5K 64Mx32
Samsung 1000-1100 Customer defined
GC6@ SLI@ 1 BIOS ROM is present (Default)
N13P-GT1 K4G10325FG-HC04 1G PD 45K 32Mx32
28nm PU 10K PU 45K PD 5K PD 10K PD 45K PEX_PLL_EN_TERM
PD 25K 64Mx32
FB_0_BAR_SIZE
H5GQ2H24AFR-T2C 2G PU 5K 0
Hynix PD 5K Disable (Default)
0 Reserved
H5GQ1H24BFR-T2C 1G PD 35K OPT@,SLI@ OPT@
32Mx32 1 Enable
1 Reserved

2 256MB (Default)
PCIE_MAX_SPEED
0 Limit to PCIE Gen1
3 Reserved
A A
1 PCIE Gen 2/3 Capable

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 N13P_MISC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom
LA-8692P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Thursday, June 07, 2012 Sheet 33 of 66
5 4 3 2 1
 5 4 3 2 1

2A 80mil
+LEDVDD B+
2A 80mil
R813 JLVDS1
1 2
EDID_CLK_CONN 1 2
1 1 R_short 0_0805_5% 1 2
C523 EDID_DATA_CONN 3 4
INVPWM 5 3 4 6
470P_0603_50V8J C524
4.7U_0805_25V6-K LVDS_ACLK#_CONN 7 5 6 8
D
LVDS_ACLK#_CONN 7 8 D
2 2 LVDS_ACLK_CONN 9 10
9/23 EMI Request LVDS_ACLK_CONN 9 10
LVDS_A1_CONN 11 12
LVDS_A1_CONN 11 12
LVDS_A1#_CONN 13 14
LVDS_A1#_CONN 13 14
LVDS_A2_CONN 15 16
LVDS_A2_CONN 15 16
LVDS_A2#_CONN 17 18
LVDS_A2#_CONN 17 18
LVDS_A0_CONN 19 20 ECR_EN <45>
LVDS_A0_CONN 19 20
LVDS_A0#_CONN LVDS_A0#_CONN 21 22
23 21 22 24 DISPOFF#
LVDS_B0_CONN 25 23 24 26
LVDS_B0_CONN 25 26
LVDS_B0#_CONN 27 28 +3VS
LVDS_B0#_CONN LVDS_B1#_CONN 29 27 28 30
INVPWM LVDS_B1#_CONN LVDS_B1_CONN 31 29 30 32 W=60mils
LVDS_B1_CONN 31 32 +LCDVDD_CONN 1
LVDS_B2_CONN 33 34 C528
470P_0402_50V7K

470P_0402_50V7K

680P_0402_50V7K
DISPOFF# LVDS_B2_CONN LVDS_B2#_CONN 35 33 34 36 (60 MIL)
C525 LVDS_B2#_CONN LVDS_BCLK_CONN 37 35 36 38 @
LVDS_BCLK_CONN 37 38 2
1@ 1@ LVDS_BCLK#_CONN
LVDS_BCLK#_CONN 39 40 +LEDVDD
C527 41 39 40 42
GND1 GND2

2 2
ACES_87142-4041-BS
For EMI
ME@

+LCDVDD_CONN

C C
+5VALW +3VS
R816 +3VS
150_0603_1%
W=60mils
1
1

R1467 R817
100K_0402_5% 100K_0402_5%
1
@ C530
6

0.1U_0402_16V4Z
2
2

3 S
Q67A 2
R820 G
2N7002DW-T/R7_SOT363-6 2 LCD_ENVDD# 1 2 2
100K_0402_5% 1 OPT@
D AO3413_SOT23-3 <17> PCH_ENBKL R1212 1 2 0_0402_5%
C1050 1 ENBKL <45>
1

1
0.01U_0402_16V7K

Q68
3

C1046 SLI@
W=60mils
0.1U_0402_16V4Z

@ 2 1

2
2 <23> VGA_ENBKL R1600
R189 SLI@ 0_0402_5%
2 +LCDVDD_CONN R827 +3VS
1 2 5 100K_0402_1%
<23> VGA_ENVDD
0_0402_5% Q67B

1
2N7002DW-T/R7_SOT363-6 @

1
4

1 2
<17> PCH_ENVDD
1

R1195 OPT@
1 1 R822
0_0402_5%
C531
4.7U_0603_6.3V6K

C532 4.7K_0402_5%
R821 R891

2
100K_0402_5% 0.1U_0402_16V4Z EDID_CLK R1210 1 2 0_0402_5% BKOFF# 1 2 DISPOFF#
2 2 <17> EDID_CLK <45> BKOFF#
2

R_short 0_0402_5%
OPT@
<17> EDID_DATA EDID_DATA R1211 1 2 0_0402_5%
R1515
OPT@ 2 1
EC_INVT_PWM <45>
LVDS_ACLK# OPT@ R1255 1 2 0_0402_5% LVDS_ACLK#_CONN R_short 0_0402_5%
<17> LVDS_ACLK# OPT@ VGA_EDID_CLK R1199 1 2 0_0402_5% EDID_CLK_CONN
B LVDS_ACLK R1257 1 2 0_0402_5% LVDS_ACLK_CONN <23> VGA_EDID_CLK @ B
<17> LVDS_ACLK INVPWM 2 1 R824
LVDS_A0# OPT@ R1259 1 2 0_0402_5% LVDS_A0#_CONN VGA_BL_PWM <23>
<17> LVDS_A0# OPT@ SLI@ 0_0402_5%
LVDS_A0 R1261 1 2 0_0402_5% LVDS_A0_CONN
<17> LVDS_A0 <23> VGA_EDID_DATA VGA_EDID_DATA R1200 1 2 0_0402_5% EDID_DATA_CONN
LVDS_A1# OPT@ R1262 1 2 0_0402_5% LVDS_A1#_CONN 2 1 R847
<17> LVDS_A1# OPT@ PCH_PWM <17>
LVDS_A1 R1265 1 2 0_0402_5% LVDS_A1_CONN 0_0402_5%
<17> LVDS_A1 OPT@ SLI@ @
LVDS_A2# R1267 1 2 0_0402_5% LVDS_A2#_CONN
<17> LVDS_A2# OPT@
LVDS_A2 R1269 1 2 0_0402_5% LVDS_A2_CONN
<17> LVDS_A2

PCH
LVDS_BCLK# R1279 1 OPT@ 2 0_0402_5% LVDS_BCLK#_CONN
<17> LVDS_BCLK# OPT@
LVDS_BCLK R1278 1 2 0_0402_5% LVDS_BCLK_CONN
<17> LVDS_BCLK
LVDS_B0# R1277 1 OPT@ 2 0_0402_5% LVDS_B0#_CONN
<17> LVDS_B0#
LVDS_B0 R1281 1 OPT@ 2 0_0402_5% LVDS_B0_CONN
<17> LVDS_B0
LVDS_B1# R1280 1 OPT@ 2 0_0402_5% LVDS_B1#_CONN
<17> LVDS_B1#
LVDS_B1 R1282 1 OPT@ 2 0_0402_5% LVDS_B1_CONN
<17> LVDS_B1
LVDS_B2# R1283 1 OPT@ 2 0_0402_5% LVDS_B2#_CONN
<17> LVDS_B2#
LVDS_B2 R1284 1 OPT@ 2 0_0402_5% LVDS_B2_CONN
<17> LVDS_B2

VGA_TXOUT0+ R1296 1 SLI@ 2 0_0402_5% LVDS_A0_CONN

<24> VGA_TXOUT0+
<24> VGA_TXOUT0- VGA_TXOUT0- R1292 1 SLI@ 2 0_0402_5% LVDS_A0#_CONN

VGA_TXOUT1+ R1299 1 SLI@ 2 0_0402_5% LVDS_A1_CONN

<24> VGA_TXOUT1+
VGA_TXOUT1- R1298 1 SLI@ 2 0_0402_5% LVDS_A1#_CONN
<24> VGA_TXOUT1-
VGA_TXOUT2+ R1301 1 SLI@ 2 0_0402_5% LVDS_A2_CONN
<24> VGA_TXOUT2+
VGA_TXOUT2- R1300 1 SLI@ 2 0_0402_5% LVDS_A2#_CONN
<24> VGA_TXOUT2-
A VGA_TXCLK+ R1295 1 SLI@ 2 0_0402_5% LVDS_ACLK_CONN A
<24> VGA_TXCLK+
VGA_TXCLK- R1293 1 SLI@ 2 0_0402_5% LVDS_ACLK#_CONN
<24> VGA_TXCLK-
VGA <24> VGA_TZOUT0+ VGA_TZOUT0+ R1303 1 SLI@ 2 0_0402_5% LVDS_B0_CONN
VGA_TZOUT0- R1304 1 SLI@ 2 0_0402_5% LVDS_B0#_CONN
<24> VGA_TZOUT0-
VGA_TZOUT1+ R1305 1 SLI@ 2 0_0402_5% LVDS_B1_CONN
<24> VGA_TZOUT1+ SLI@
VGA_TZOUT1- R1310 1 2 0_0402_5% LVDS_B1#_CONN Title
<24> VGA_TZOUT1- Security Classification LC Future Center Secret Data
VGA_TZOUT2+ R1309 1 SLI@ 2 0_0402_5% LVDS_B2_CONN
<24> VGA_TZOUT2+
VGA_TZOUT2- R1307 1 SLI@ 2 0_0402_5% LVDS_B2#_CONN
Issued Date 2012/07/01 Deciphered Date 2014/07/01 LVDS
<24> VGA_TZOUT2-
SLI@ THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
VGA_TZCLK+ R1306 1 2 0_0402_5% LVDS_BCLK_CONN Size Document Number Rev
<24> VGA_TZCLK+
LA-8692P
SLI@ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
VGA_TZCLK- R1308 1 2 0_0402_5% LVDS_BCLK#_CONN Custom 0.2
<24> VGA_TZCLK- DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Tuesday, June 05, 2012 Sheet 34 of 66
5 4 3 2 1
 5 4 3 2 1

D D

No use NVSR chip for DVT

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 NO NVSR

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C LA-8692P 0.2

Date: Tuesday, June 05, 2012 Sheet 35 of 66

5 4 3 2 1
 A B C D E

+5VS +5VS +5VS

3 3 3

VGA_CRT_R R1276 1 2 0_0402_5% 2

1 BLUE

2
1 GREEN

2
1 RED

BAT54S-7-F_SOT23-3
+5VS
D36
+CRT_VCC

F1
CRT Connector
<23> VGA_CRT_R
@ @ @ 2 1 1 2 +CRT_VCC_CONN
SLI@ D31 D32 D33 1
BAT54S-7-F_SOT23-3 BAT54S-7-F_SOT23-3 RB491D_SC59-3 0.5A_8V_KMC3S050RY
VGA_CRT_G R1273 1 2 0_0402_5% C536
<23> VGA_CRT_G
1 SLI@
W=40mils 2
0.1U_0402_16V4Z
1

VGA_CRT_B R1275 1 2 0_0402_5%

<23> VGA_CRT_B
SLI@

JCRT1
6
T75 PAD CRT_TEST 11
DAC_RED_1 L16 1 2 NBQ100505T-800Y_0402 RED 1
7
CRT_DDC_DAT_CONN 12
DAC_GRN_1 L17 1 2 NBQ100505T-800Y_0402 GREEN 2
8
JVGA_HS 13
DAC_BLU_1 L18 1 2 NBQ100505T-800Y_0402 BLUE 3
9

1
1 1 1 1 1 1 JVGA_VS 14
4
R830 R831 R832 C537 C538 C539 C540 C542 C541 10 G 16
150_0402_1% 150_0402_1% 150_0402_1% 10P_0402_50V8J 10P_0402_50V8J CRT_DDC_CLK_CONN 15 G 17
2 2 2 2 2 2 5

2
1
10P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J10P_0402_50V8J C543 SUYIN_070546HR015M22BZR
CLOSE TO CONN
100P_0402_50V8J ME@
2
DAC_RED R1274 1 2 0_0402_5%
<17> DAC_RED
2 OPT@ 2
DAC_GRN R1181 1 2 0_0402_5% +CRT_VCC
<17> DAC_GRN R833
OPT@ 1 2
DAC_BLU R1182 1 2 0_0402_5% 1
<17> DAC_BLU

OE#
C544 1K_0402_5%
OPT@
0.1U_0402_16V4Z
2

1
R840 NBQ100505T-800Y_0402

OE#
P
CRT_HSYNC R1183 1 2 0_0402_5% HSYNC_G 2 4 CRT_HSYNC_1 1 2 CRT_HSYNC_2 1 2 JVGA_HS
<17> CRT_HSYNC A Y
33_0603_5% L19

G
OPT@ U24
VGA_CRT_HSYNC R1184 1 2 0_0402_5% SN74AHCT1G125DCKR_SC70-5 1
<23> VGA_CRT_HSYNC

3
@
D8
SLI@ C545 @
10P_0402_50V8J JVGA_VS 3 6 JVGA_HS
+CRT_VCC 2 I/O2 I/O4

OE#
1 2 5 +5VS
GND VDD
C546
0.1U_0402_16V4Z
CRT_VSYNC R1185 1 2 0_0402_5% 2 CRT_DDC_CLK_CONN 1 4 CRT_DDC_DAT_CONN
<17> CRT_VSYNC I/O1 I/O3
5

1
R839 NBQ100505T-800Y_0402
OPT@
OE#
P
VGA_CRT_VSYNC R1186 1 2 0_0402_5% VSYNC_G 2 4 CRT_VSYNC_1 1 2 CRT_VSYNC_2 1 2 JVGA_VS AZC099-04S.R7G_SOT23-6
3 <23> VGA_CRT_VSYNC A Y 3
33_0603_5% L20
G

SLI@ U25 1
SN74AHCT1G125DCKR_SC70-5
3

@ C547
+3VS 10P_0402_50V8J
+CRT_VCC 2
1

1
5
G

R837 R838
2.2K_0402_5% 2.2K_0402_5%
2

<17> CRT_DDC_DATA CRT_DDC_DATA R1189 1 2 0_0402_5% CRT_DDC_DATA_R 4 3 CRT_DDC_DAT_CONN

OPT@
D
S
2
G

Q73B
2N7002KDW H_SOT363-6
<17> CRT_DDC_CLK CRT_DDC_CLK R1190 1 2 0_0402_5% CRT_DDC_CLK_R 1 6 CRT_DDC_CLK_CONN
OPT@
D
S

1 1
@ @
Q73A C548 C549
<23> VGA_CRT_DATA VGA_CRT_DATA R1191 1 2 0_0402_5% 2N7002KDW H_SOT363-6 100P_0402_50V8J 68P_0402_50V8K
SLI@ 2 2

<23> VGA_CRT_CLK VGA_CRT_CLK R1192 1 2 0_0402_5%

SLI@
4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 CRT Connector
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
LA-8692P 0.2

Date: Tuesday, June 05, 2012 Sheet 36 of 66

A B C D E
 5 4 3 2 1

+3VS +3VS_VGA

2
L23

2
HDMI_CLK+_CK 4 3 HDMI_CLK+_CONN 1 2
4 3 R1468 R1469
C1016 3.3P_0402_50V8C
0_0402_5% 0_0402_5%
@
HDMI_CLK-_CK 1 2 HDMI_CLK-_CONN 1 2 OPT@ SLI@
1 2 C1015 3.3P_0402_50V8C

1
1
W CM-2012-900T_4P @
Q152
L24 BSH111_SOT23-3

2
HDMI_TX0+_CK 1 2 HDMI_TX0+_CONN 1 2 HDMIDAT_R HDMI@
1 2 HDMICLK_R

G
D C1018 3.3P_0402_50V8C VGA_HDMI_CLK R1470 1 SLI@ 2 0_0402_5% D
<24> VGA_HDMI_CLK

2
@ D57
HDMI_TX0-_CK 4 3 HDMI_TX0-_CONN 1 2 <17> HDMICLK HDMICLK R1471 1 OPT@ 2 0_0402_5% 3 1 HDMICLK_R
4 3 C1017 3.3P_0402_50V8C PJSOT24C 3P C/A SOT-23
@

D
W CM-2012-900T_4P @

G
VGA_HDMI_DATA R1472 1 SLI@ 2 0_0402_5%
<24> VGA_HDMI_DATA
L26

1
HDMI_TX1+_CK 4 3 HDMI_TX1+_CONN 1 2 HDMIDAT R1473 1 OPT@ 2 0_0402_5% 3 1 HDMIDAT_R
4 3 C1020 3.3P_0402_50V8C <17> HDMIDAT

D
@
HDMI_TX1-_CK 1 2 HDMI_TX1-_CONN 1 2 Q80
1 2 C1019 3.3P_0402_50V8C
W CM-2012-900T_4P BSH111_SOT23-3
@ HDMI@

L27 +3VS
HDMI_TX2+_CK 1 2 HDMI_TX2+_CONN 1 2 +5VS
1 2 C1022 3.3P_0402_50V8C
@
PMEG2010AEH

2
HDMI_TX2-_CK 4 3 HDMI_TX2-_CONN 1 2 IF=0.1A, 0.29V
4 3 C1021 3.3P_0402_50V8C R862 +5VS
IF=1A, 0.43V

2
W CM-2012-900T_4P 1M_0402_5% HDMI@
@
D37

2
G
Q85 PMEG2010AEH_SOD123

1
OPT@
R1486 1 2 3 1
<17> TMDS_B_HPD

1
S

2
0_0402_5% 2N7002_SOT23

2
R885 @

1
R1587 1 2 20K_0402_5% D38 F2 HDMI@
C
<18> HDMI_HPD C
BAT54S-7-F_SOT23-3 0.5A_8V_KMC3S050RY
R320 0_0402_5%

1
2
499_0402_1% GC6@

1
HDMI_CLK+_CONN SLI@ 1 2 R1598

HDMI_CLK-_CONN SLI@ 1 2
for NVSR 0_0402_5% +5VS_HDMI

R321 499_0402_1% SLI@

1 C561

1
HDMI_TX0+_CONN SLI@ 1 2 0.1U_0402_16V4Z
for NV recommend

2
R322 499_0402_1% HDMI@
HDMI_TX0-_CONN SLI@ 1 2 L67
R323 499_0402_1% BLM18PG181SN1D_0603 R860 R861 2
HDMI_TX1+_CONN SLI@ 1 2 R859 2 1 HDMI_DET_R 2 1 HDMI_DET 2.2K_0402_5% 2.2K_0402_5%
<23> DGPU_HDMI_HPD
R324 499_0402_1% @ HDMI@ HDMI@

1
SLI@

1
HDMI_TX1-_CONN 1 2 1K_0402_5%

R864
100K_0402_5%
R325 499_0402_1% @ 1
HDMI_TX2+_CONN SLI@ 1 2
R326 499_0402_1% C59
HDMI_TX2-_CONN SLI@ 1 2 @ 220P_0402_25V8J JHDMI1

2
R327 499_0402_1% D 2 19
1

18 HP_DET
2 Q114 17 +5V
+3VS DDC/CEC_GND
G 2N7002H 1N_SOT23-3 HDMIDAT_R 16
S HDMI@ HDMICLK_R 15 SDA
3

1 @ 2 14 SCL
R328 100K_0402_5% 13 Reserved
VGA_HDMI_CLK- SLI@ CV254 1 2 0.1U_0402_10V6K HDMI_CLK-_CK R866 1 @ 2 0_0402_5% HDMI_CLK-_CONN 12 CEC 20
<24> VGA_HDMI_CLK- CK- GND
11 21
VGA_HDMI_CLK+ SLI@ CV253 1 2 0.1U_0402_10V6K HDMI_CLK+_CK R865 1 @ 2 0_0402_5% HDMI_CLK+_CONN 10 CK_shield GND 22
<24> VGA_HDMI_CLK+ CK+ GND
<24> VGA_HDMI_TX0- VGA_HDMI_TX0- SLI@ CV256 1 2 0.1U_0402_10V6K HDMI_TX0-_CK R868 1 @ 2 0_0402_5% HDMI_TX0-_CONN 9 23
B 8 D0- GND B
R327 R326
VGA_HDMI_TX0+ SLI@ CV255 1 2 0.1U_0402_10V6K HDMI_TX0+_CK R867 1 @ 2 0_0402_5% HDMI_TX0+_CONN 7 D0_shield
<24> VGA_HDMI_TX0+ D0+
<24> VGA_HDMI_TX1- VGA_HDMI_TX1- SLI@ CV258 1 2 0.1U_0402_10V6K HDMI_TX1-_CK R870 1 @ 2 0_0402_5% HDMI_TX1-_CONN 6
5 D1-
VGA_HDMI_TX1+ SLI@ CV257 1 2 0.1U_0402_10V6K HDMI_TX1+_CK R869 1 @ 2 0_0402_5% HDMI_TX1+_CONN 4 D1_shield
<24> VGA_HDMI_TX1+ D1+
46@ <24> VGA_HDMI_TX2- VGA_HDMI_TX2- SLI@ CV260 1 2 0.1U_0402_10V6K HDMI_TX2-_CK R872 1 @ 2 0_0402_5% HDMI_TX2-_CONN 3
2 D2-
680_0402_1% 680_0402_1% D2_shield
OPT@ OPT@ <24> VGA_HDMI_TX2+ VGA_HDMI_TX2+ SLI@ CV259 1 2 0.1U_0402_10V6K HDMI_TX2+_CK R871 1 @ 2 0_0402_5% HDMI_TX2+_CONN 1
D2+
R324 R323 TAITW _PDVBR0-19FLBS4NN4N0

<17> TMDS_B_CLK#_PCH TMDS_B_CLK#_PCH OPT@ C208 1 2 0.1U_0402_10V6K HDMI_CLK-_CK

HDMI+HDCP <17> TMDS_B_CLK_PCH TMDS_B_CLK_PCH OPT@ C207 1 2 0.1U_0402_10V6K HDMI_CLK+_CK ME@
<17> TMDS_B_DATA0#_PCH TMDS_B_DATA0#_PCH OPT@ C204 1 2 0.1U_0402_10V6K HDMI_TX0-_CK
<17> TMDS_B_DATA0_PCH TMDS_B_DATA0_PCH OPT@ C205 1 2 0.1U_0402_10V6K HDMI_TX0+_CK
<17> TMDS_B_DATA1#_PCH TMDS_B_DATA1#_PCH OPT@ C203 1 2 0.1U_0402_10V6K HDMI_TX1-_CK
680_0402_1% 680_0402_1% TMDS_B_DATA1_PCH OPT@ C206 1 2 0.1U_0402_10V6K HDMI_TX1+_CK
OPT@ OPT@ <17> TMDS_B_DATA1_PCH
<17> TMDS_B_DATA2#_PCH TMDS_B_DATA2#_PCH OPT@ C200 1 2 0.1U_0402_10V6K HDMI_TX2-_CK
<17> TMDS_B_DATA2_PCH TMDS_B_DATA2_PCH OPT@ C201 1 2 0.1U_0402_10V6K HDMI_TX2+_CK
R321 R320

680_0402_1% 680_0402_1%
OPT@ OPT@

R325 R322
A A

680_0402_1% 680_0402_1%
OPT@ OPT@ Title
Security Classification LC Future Center Secret Data
Issued Date 2012/07/01 Deciphered Date 2014/07/01 HDMI CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
LA-8692P 0.2

Date: Tuesday, June 05, 2012 Sheet 37 of 66

5 4 3 2 1
 A B C D E

Mini-Express Card for WLAN/WiMAX(Half) Reserve for SW mini-pcie debug card.

Mini-Express Card for SSD(Full) Series resistors closed to KBC side.
LPC_FRAME#_R R873 1 @ 2 0_0402_5% LPC_FRAME#
9/18 JP1 Pin2,24,52 contact to +3VS_WLAN for AOAC function LPC_AD3_R R874 1 @ 2 0_0402_5% LPC_AD3
LPC_FRAME# <14,45>
LPC_AD3 <14,45>
LPC_AD2_R R875 1 @ 2 0_0402_5% LPC_AD2
1 2 LPC_AD2 <14,45>
LPC_AD1_R R876 @ 0_0402_5% LPC_AD1
+3VS_WLAN +1.5VS LPC_AD1 <14,45>
LPC_AD0_R R878 1 @ 2 0_0402_5% LPC_AD0
LPC_AD0 <14,45>
PCI_RST#_R R879 1 @ 2 0_0402_5% PLT_RST#

For RF request
+1.5VS CLK_PCI_DB CLK_PCI_DB <18>

0.047U_0402_16V4Z

1
Mini-Express Card(WLAN/WiMAX) 1
R1518 1 1

C1071
1 1
R1620 @ 0_0603_5%
@ C564 C565
<39,45> LAN_WAKE# 1 2 0_0402_5% 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z

2
JWLN1 2 2
COMBT@ <16,19,39> PCIE_WAKE# PCIE_WAKE# 1 2
3 WAKE# 3.3V 4
BT_CTRL R897 1 2 0_0402_5% BT_CTRL_R 5 NC GND 6 +1.5VS_WLAN
<15> WLAN_CLKREQ1# WLAN_CLKREQ1# 7 NC 1.5V 8 LPC_FRAME#_R will check on EVT PCB
9 CLKREQ# NC 10 LPC_AD3_R
1 2 BT_DISABLE# 11 GND NC 12 LPC_AD2_R
<15> CLK_PCIE_WLAN1# REFCLK- NC
13 14 LPC_AD1_R
R1556 <15> CLK_PCIE_WLAN1 15 REFCLK+ NC 16 LPC_AD0_R
1K_0402_5% PCI_RST#_R 17 GND NC 18 R1541 2 @ 1 0_0402_5%
19 NC GND 20 EC_WL_OFF#_R <45>
COMBT@ CLK_PCI_DB WL_OFF# R880 1 2 0_0402_5%
NC NC PCH_WL_OFF# <18>
21 22 PLT_RST#
GND PERST# PLT_RST# <18,23,32,38,39,44,45,6>
For isolate Intel Rainbow Peak and <15> PCIE_PRX_DTX_N2
23
PERn0 +3.3Vaux
24 R881 1 2 @ 0_0402_5%
+3VALW
25 26 R882 1 2 R_short 0_0402_5%
Compal debug card. <15> PCIE_PRX_DTX_P2
27 PERp0 GND 28
+3VS_WLAN
29 GND +1.5V 30 SMB_CLK_S3_R R883 1 2 @ 0_0402_5%
GND SMB_CLK SMB_CLK_S3 <12,13,15,46>
31 32 SMB_DATA_S3_R R884 1 2 @ 0_0402_5% SMB_DATA_S3 <12,13,15,46>
<15> PCIE_PTX_C_DRX_N2 PETn0 SMB_DATA
33 34
<15> PCIE_PTX_C_DRX_P2 35 PETp0 GND 36
+3VS_WLAN GND USB_D- USB20_N10 <18>
37 38
39 NC USB_D+ 40 USB20_P10 <18>
41 NC GND 42
43 NC LED_WWAN# 44
100_0402_1% 45 NC LED_WLAN# 46
R887 47 NC LED_WPAN# 48
EC_TX 1 2 49 NC +1.5V 50
<45> EC_TX NC GND
EC_RX 1 2 BT_DISABLE# 51 52
<45> EC_RX NC +3.3V +3VS +3VS_WLAN
WLAN&BT Combo module circuits R888
100_0402_1% 53 54 J8

@
GND GND
BT on module BT on module 1 2
1 2
Enable Disable TAITW_PFPET0-AFGLBG1ZZ4N0

2
For EC to detect JUMP_43X79
R889
2 BT_CRTL H L debug card insert. 100K_0402_5%
ME@ +3VALW
2
Q104 AO3413_SOT23-3
AOAC@

1
PCH_BT_ON# L H

D
3 1 1
AOAC@
1 C533
R1557 1 0.1U_0402_16V4Z

G
2
0_0402_5% C526 2
1 2 BT_CTRL 0.1U_0402_16V4Z AOAC@ C1048
<19> PCH_BT_DISABLE#
2 0.01U_0402_25V7K
COMBT@ 2
R436
6

D D 1 2 AOAC@
<52> AOAC_ON# 1
<19,47> PCH_BT_ON# 2 5 SUSP <10,52,56,58> @
100K_0402_5%
Q157A

Q157B

G G C1055
2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6

AOAC@ 0.1U_0402_16V4Z
2
S S
1

AOAC@ AOAC@

softstart (RC) will check on EVT PCB

Q157 is AOAC+COMBT need to stuff
only AOAC or only COMBT is un-stuff
9/18 Increase for Intel AOAC function

Mini-Express Card(SSD) SSD Active:4.5W(1.5A)

3
+3VS_SSD +3VS_SSD
Mini-Express Card(TV) 3
+3VS
J5 +3VS_TV
0.1U_0402_16V4Z 10U_0805_10V4Z
1 2 JTV1
1 2 1 2 +1.5VS_TV
1 1 1 1 3 WAKE# 3.3V 4
@ NC GND
C566 C567 C568 C569 JUMP_43X79 5 6
CLKREQ_TV# 7 NC 1.5V 8
@ <15> CLKREQ_TV#
2 2 2 2 9 CLKREQ# NC 10
JSSD1 GND NC
1 2 CLK_PCIE_TV# 11 12
WAKE# 3.3V <15> CLK_PCIE_TV# 13 REFCLK- NC 14
0.01U_0402_25V7K 10U_0805_10V4Z 3 4 CLK_PCIE_TV
NC GND <15> CLK_PCIE_TV REFCLK+ NC
5 6 15 16
NC 1.5V 17 GND NC 18
7 8 NC GND
9 CLKREQ# NC 10 19 20
GND NC 21 NC NC 22 PLT_RST#
11 12 GND PERST# PLT_RST# <18,23,32,38,39,44,45,6>
13 REFCLK- NC 14 23 24
REFCLK+ NC <15> PCIE_PRX_DTX_N3 PERn0 +3.3Vaux
15 16 25 26
GND NC <15> PCIE_PRX_DTX_P3 PERp0 GND
17 18 27 28
NC GND 29 GND +1.5V 30 +3VS_TV +3VS
19 20 GND SMB_CLK
0.01U_0402_16V7K 21 NC NC 22 PCIE_PTX_C_DRX_N3 31 32
<15> PCIE_PTX_C_DRX_N3 R1204 2

4.7U_0603_6.3V6K
GND PERST# PCIE_PTX_C_DRX_P3 33 PETn0 SMB_DATA 34 1
SATA_DTX_C_IRX_P0 2 1 C572 SATA_DTX_IRX_P0 23 24 <15> PCIE_PTX_C_DRX_P3 PETp0 GND
<14> SATA_DTX_C_IRX_P0 SATA_DTX_C_IRX_N0 2 1 C573 SATA_DTX_IRX_N0 25 PERn0 +3.3Vaux 26 35 36 1C902
<14> SATA_DTX_C_IRX_N0 PERp0 GND +3VS_TV GND USB_D- USB20_N12 <18> R_short 0_0805_5%
27 28 37 38
GND +1.5V 39 NC USB_D+ 40 USB20_P12 <18>
0.01U_0402_16V7K 29 30 NC GND
GND SMB_CLK 41 42 TV@
<14> SATA_ITX_DRX_N0 SATA_ITX_DRX_N0 31 32 NC LED_WWAN# 2
SATA_ITX_DRX_P0 33 PETn0 SMB_DATA 34 43 44
<14> SATA_ITX_DRX_P0 PETp0 GND 45 NC LED_WLAN# 46
35 36 NC LED_WPAN#
37 GND USB_D- 38 47 48
NC USB_D+ 49 NC +1.5V 50
+3VS_SSD 39 40
NC GND 51 NC GND 52 +1.5VS_TV +1.5VS
41 42 NC +3.3V
43 NC LED_WWAN# 44
NC LED_WLAN# R1206
45 46 53 54 1 2
NC LED_WPAN# GND GND
47 48 1 C901 R_short 0_0603_5%

4.7U_0603_6.3V6K
49 NC +1.5V 50
SATA_DET# 1 2 51 NC GND 52 TAITW_PFPET0-AFGLBG1ZZ4N0
<14> SATA_DET# R896 0_0402_5% NC +3.3V TV@
2
For SSD use: @ 53 54 ME@
4 GND GND 4

TAITW_PFPET0-AFGLBG1ZZ4N0

ME@

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 Mini-Card

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C LA-8692P 0.2

Date: Tuesday, June 05, 2012 Sheet 38 of 66

A B C D E
 5 4 3 2 1

+3VALW +3V_LAN
Atheros request can't disable LAN power
J10
+LX
LX Voltage Configure
1 2 Close together <Pin 40>
1 2
+1.7V

@
Layout Notice : Place as close +1.7_VDDCT
JUMP_43X79 AR8151 <VDDCT> R1356,C955
chip as possible. R1356 8151@ 0_0402_5% L74
1 2 +LX_R 1 2 +LX +1.1V
Q70

1000P_0402_50V7K
AR8161 R1357,R1372,L76

10U_0805_10V4Z
4.7UH_SIA4012-4R7M_20%

0.1U_0402_16V4Z
3 1 <DVDDL,AVDDL>

@ C935

C936

C937
R1357 8161@ 0_0402_5% 1 1
+1.1_DVDDL 1 2
1 1 Note: Place Close to LAN chip L75 L76
C552 LP2301ALT1G_SOT-23

G
L39 DCR< 0.15 ohm

2
0.1U_0402_16V4Z C1047 2 2 FBMA-L11160808601LMA10T_2P FBMA-L11160808601LMA10T_2P
D D
0.01U_0402_25V7K Rate current > 1A +1.1_AVDDL_L 1 2 +1.1_AVDDL 1 2 +1.1_DVDDL
2 2

0.1U_0402_16V4Z

1U_0402_6.3V4Z

4.7U_0603_6.3V6K
2 R59 1
LAN_PWR_ON# 8161@
<45> LAN_PWR_ON#

C967

C980

C278
100K_0402_5% 1 1 1
1
C1056 Close to 2 2 2
0.1U_0402_16V4Z
@ 2 Pin40
Vendor recommand reseve the
PU resistor close LAN chip Place close to Pin34

+3V_LAN R345 1 2 4.7K_0402_5%

@
PLT_RST#
<18,23,32,38,44,45,6> PLT_RST#

H --> Overclocking mode

L --> Not overclocking mode
Place Close to Chip U63

C
<15> PCIE_PRX_DTX_N1 C946 1 2 0.1U_0402_16V7K PCIE_PRX_C_DTX_N1 29 38 ACTIVITY# C
TX_N LED_0 39 ACTIVITY# <40>
LAN_LINK#
C947 1 2 0.1U_0402_16V7K PCIE_PRX_C_DTX_P1 30
Atheros LED_1 23 LAN_CLK_SEL R58 2 1 LAN_LINK# <40>
<15> PCIE_PRX_DTX_P1 TX_P LED_2
AR8151/AR8161
36
@ 10K_0402_5% 2011103 for vendor comment
<15> PCIE_PTX_C_DRX_N1 RX_N 12 MDI0-
35 TRXN0 11 MDI0- <40>
MDI0+
<15> PCIE_PTX_C_DRX_P1 RX_P TRXP0 15 MDI1-
MDI0+ <40> Place Close to LAN chip
32 TRXN1 14 MDI1- <40>
MDI1+
<15> CLK_PCIE_LAN# REFCLK_N TRXP1 MDI1+ <40>
33 18 MDI2- 8151@ 49.9_0402_1%
<15> CLK_PCIE_LAN REFCLK_P TRXN2 17 MDI2- <40>
MDI2+ MDI0+ R1358 1 2 1@ 2 C938 1000P_0402_50V7K
2 TRXP2 21 MDI2+ <40>
PLT_RST# MDI3- 8151@ 49.9_0402_1% 8151@
PERST# TRXN3 MDI3- <40>
20 MDI3+ MDI0- R1359 1 2 1 2 C939 0.1U_0402_16V4Z
R1369 1 @ 2 0_0402_5% PCIE_WAKE#_R 3 TRXP3 MDI3+ <40> Place Close to PIN1 8151@ 49.9_0402_1%
<16,19,38> PCIE_WAKE# W AKE#
<38,45> LAN_WAKE# R1370 1 2 MDI1+ R1360 1 2 1@ 2 C940 1000P_0402_50V7K
25 10 LAN_RBIAS 1 2 +3V_LAN 8151@ 49.9_0402_1% 8151@
R_short 0_0402_5% SMCLK RBIAS
26 R1371 2.37K_0402_1% MDI1- R1361 1 2 1 2 C941 0.1U_0402_16V4Z
SMDATA 8151@ 49.9_0402_1%
Place Close to PIN10
28 1 +3V_LAN MDI2+ R1362 1 2 1@ 2 C942 1000P_0402_50V7K
NC VDD33

1000P_0402_50V7K
27

10U_0805_10V4Z

10U_0805_10V4Z
8151@ 49.9_0402_1% 8151@

0.1U_0402_16V4Z

1U_0402_6.3V4Z
TESTMODE 1 1 1 1

@
@ MDI2- R1363 1 2 1 2 C943 0.1U_0402_16V4Z
40 +LX R1372 8161@ 30K_0402_5% 8151@ 49.9_0402_1%
LX +LX

C950

C951

C952

C953

C954
LAN_XTALO 7 1 2 MDI3+ R1364 1 2 1@ 2 C944 1000P_0402_50V7K
+3VS

1
LAN_XTALI 8 XTLO 8151@ 2 2 2 2 8151@ 49.9_0402_1% 8151@
XTLI 5 +1.7_VDDCT 1 2 MDI3- R1365 1 2 1 2 C945 0.1U_0402_16V4Z
VDDCT/ISOLAN C955 0.1U_0402_16V4Z
4 Note : C938, C940, C942, 944, reserved for EMI.
<15> CLKREQ_LAN# CLKREQ# 24 +1.1_DVDDL_R R1366 1 2 0_0402_5% +1.1_DVDDL
DVDDL/PPS 37
+1.1_AVDDL 13 DVDDL_REG/DVDDL +1.1_DVDDL 8151@
B
+1.1_AVDDL 19 AVDDL B
AVDDL For AR8151: Stuff 49.9K and 0.1u
+1.1_AVDDL 31 16 +AVDDH_AVDD3.3
+1.1_AVDDL_L 34 AVDDL AVDDH/AVDD33 22 +2.7_AVDDH For AR8161: NC
+1.1_AVDDL 6 AVDDL AVDDH 9 +2.7_AVDDH
AVDDL_REG/AVDDL AVDDH_REG
1U_0402_6.3V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1U_0402_6.3V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C956

C957

C958

C959

C960
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1U_0402_6.3V4Z
1 1 1 1 1
C961

C962

C963

C966
41 1 1 1 2
GND +3V_LAN

C964

C965
1 1
AR8161-BL3A-R_QFN40_5X5 8151@
2 2 2 2 2 8161@ +2.7_AVDDH
U63 2 2 2 1 R1367 1 2 0_0402_5%
8161@ 2 2
8151@
For AR8151: Stuff C966,R1366 +AVDDH_AVDD3.3 R1368 1 2 0_0402_5% +2.7_AVDDH
For AR8161: NC
Near
Near Near Near Near SA00003LE2J Near Near Near

1U_0402_6.3V4Z
0.1U_0402_16V4Z
Pin9
Pin13 Pin19 Pin31 Pin6 Pin22 Pin37 Pin24

C948

C949
8151@ 1 1
8161@

LAN_XTALI 2 2

Y6 LAN_XTALO
4 3
NC OSC
Place close to Pin16
1 2
OSC NC
A 1 25MHZ_12PF_X3G025000DC1H~D 1 For AR8151: Stuff R1368 for +AVDD3.3 A

C968 C969
For AR8161: Stuff R1367,C949 for +AVDDH
15P_0402_50V8J 15P_0402_50V8J
2 2

Security Classification LC Future Center Secret Data Title

Change C968, C969 value of Cap from 33pF to 15pF
for TXC recommend Issued Date 2012/07/01 Deciphered Date 2014/07/01 LAN-AR8151/8161
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-8692P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Tuesday, June 05, 2012 Sheet 39 of 66
5 4 3 2 1
 5 4 3 2 1

+1.7_VDDCT
8151@
Place close to TCT pin R1374
R1373 T49
2 1 +1.7_VDDCT_R 1 24 MCT3 2 1
0_0603_5% TCT1 MCT1
2
1 MDI3+ 2 1:1 23 MDO3+
<39> MDI3+ TD1+ MX1+ 0_0402_5%
@ C976 C970
0.1U_0402_16V4Z
1
1U_0402_6.3V4Z 2
D 8151@ MDI3- 3 22 MDO3- D
<39> MDI3- TD1- MX1- R1375
4 21 MCT2 2 1
6/23 update TCT2 MCT2
2
MDI2+ 5 1:1 20 MDO2+
<39> MDI2+ TD2+ MX2+ 0_0402_5%
C972
C970 C972 C974 C975
0.1U_0402_16V4Z
1

8151@ MDI2- 6 19 MDO2-

<39> MDI2- TD2- MX2- R1377
7 18 MCT1 2 1
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z TCT3 MCT3
8161S@ 8161S@ 8161S@ 8161S@ 2
MDI1+ 8 1:1 17 MDO1+
<39> MDI1+ TD3+ MX3+ 0_0402_5%
C974
0.1U_0402_16V4Z
1
Place Close to T49
8151@ MDI1- 9 16 MDO1-
<39> MDI1- TD3- MX3- R1376
10 15 MCT0 2 1
MDI3- TCT4 MCT4
2
MDI0+ 11 1:1 14 MDO0+
<39> MDI0+ TD4+ MX4+ 0_0402_5%

2
C
C975 C
MDI3+ 0.1U_0402_16V4Z R1194
D68 1
75_0402_5%

TCLAMP3302N.TCT_SLP2626P10-10 8151@ MDI0- 12 13 MDO0-

<39> MDI0-

1
TD4- MX4-
10
6
7
8
9

NS892402 1G
1
6
7
8
9
10

11 R02
GND C973
10P_1206_2KV7K
2
5
4
3
2
1
5
4
3
2
1

JRJ1
LAN_LINK# 9
<39> LAN_LINK# Green LED-
1 220_0402_5%
MDI2- @ 2 1 10 Place Close to T49
+3V_LAN Green LED+
C978 R1378 MCT3
MDI2+ 470P_0402_50V7K MDO0+ 1
2 PR1+
MCT2
MDO0- 2
8151S@ PR1-
MCT1
MDO1+ 3
PR2+
MCT0
B MDO2+ 4 B
MDI1- PR3+

LSE-200NX3216TRLF_1206-2

LSE-200NX3216TRLF_1206-2

LSE-200NX3216TRLF_1206-2

LSE-200NX3216TRLF_1206-2
MDO2- 5
PR3-

2
MDI1+ MDO1- 6
D67 PR2-

F6

F3

F4

F5
MDO3+ 7 14
TCLAMP3302N.TCT_SLP2626P10-10 PR4+ G2
MDO3- 8 13
10

PR4- G1
6
7
8
9

SURGE@ @ @ @

1
ACTIVITY# 11
6
7
8
9
10

<39> ACTIVITY# Yellow LED-

11 R02
GND 12
Yellow LED+
5
4
3
2
1

1 SANTA_130456-111
@ R1442
5
4
3
2
1

C979 +3V_LAN 2 1 ME@ Reserve for EMI go rural solution

470P_0402_50V7K
2 220_0402_5%
MDI0- BOM option: for GDTx1
for GDTx4 R1374/R1375/R1376/R1377=0 ohm
MDI0+
R1374/R1375/R1376/R1377=75 ohm R1194=75 ohm
R1194=0 ohm MCT0=Mount
A 8151S@ A
MCT0~3=Mount MCT1~3=Un mount
Reserve D67,D68 for EMI go rural solution
Security Classification LC Future Center Secret Data Title
Issued Date 2012/07/01 Deciphered Date 2014/07/01 LAN_Transformer
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B LA-8692P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Tuesday, June 05, 2012 Sheet 40 of 66
5 4 3 2 1
 5 4 3 2 1

D Close U29 SMSC thermal sensor D

REMOTE1+
1
+3VS placed near by VRAM REMOTE1+
Under VRAM
C449 1

1
2200P_0402_50V7K U29 @ C
2 REMOTE1- C982 2 Q137
100P_0402_50V8J B MMST3904-7-F_SOT323-3
+VDD 1 10 EC_SMB_CK2 2 E
EC_SMB_CK2 <15,23,32,45>

3
VDD SMCLK REMOTE1-
REMOTE1+ 2 9 EC_SMB_DA2
DP1 SMDATA EC_SMB_DA2 <15,23,32,45>
REMOTE2+ 2
1 REMOTE1- 3 8
DN1 ALERT# R624
C443
C658 0.1U_0402_16V4Z REMOTE2+ 4 7 2 1
2200P_0402_50V7K 1 DP2 THERM# +3VS Close to SSD side
2 REMOTE2- REMOTE2- 5 6 REMOTE2+
DN2 GND 10K_0402_5%
1

1
@ @ C
C984 2 Q138
EMC1403-2-AIZL-TR_MSOP10 100P_0402_50V8J B MMST3904-7-F_SOT323-3
FAN_PWM & TACH 2 E

3
for PWM FAN Address 1001_101xb REMOTE2-

REMOTE2+/-:
internal pull up 1.2K to 1.5V
C
Trace width/space:10/10 mil C
R for initial thermal
Trace length:<8"
shutdown temp

B B

FAN1 Conn

+5VS

2 2
C1109

0.1U_0402_16V4Z
C986 @ JFAN1
10U_0805_10V4Z 1
1 1 2 1
<45> EC_FAN_SPEED 2
<45> EC_FAN_PW M 3
4 3
5 4
6 G5
G6
ACES_85205-04001
ME@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 EMC1403/2103_Thermal sensor/FAN

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
LA-8692P 0.2

Date: Tuesday, June 05, 2012 Sheet 41 of 66

5 4 3 2 1
 A B C D E F G H

1 1

SATA HDD Conn.

JHDD1
2 1 2
SATA_ITX_DRX_P1 2 GND
<14>
<14>
SATA_ITX_DRX_P1
SATA_ITX_DRX_N1
SATA_ITX_DRX_N1 3
4
A+
A-
SATA ODD Conn.
SATA_DTX_C_IRX_N1 C627 1 2 0.01U_0402_16V7K SATA_DTX_IRX_N1 5 GND
<14> SATA_DTX_C_IRX_N1 SATA_DTX_C_IRX_P1 C628 1 2 0.01U_0402_16V7K SATA_DTX_IRX_P1 6 B-
<14> SATA_DTX_C_IRX_P1 7 B+ JODD1
GND
1
8 SATA_ITX_DRX_P2_CONN 2 GND
V33 <14> SATA_ITX_DRX_P2_CONN A+
9 SATA_ITX_DRX_N2_CONN 3
V33 <14> SATA_ITX_DRX_N2_CONN A-
10 4
11 V33 SATA_DTX_C_IRX_N2 C629 1 2 0.01U_0402_16V7K SATA_DTX_IRX_N2 5 GND
12 GND <14> SATA_DTX_C_IRX_N2 SATA_DTX_C_IRX_P2 C630 1 2 0.01U_0402_16V7K SATA_DTX_IRX_P2 6 B-
13 GND <14> SATA_DTX_C_IRX_P2 7 B+
@ J12 14 GND <32,45> SLI_FAN_SPEED R1516 1 2 R_short 0_0402_5% GND
1 2 15 V5 @R1476
@R1476 1 2 0_0402_5%
+5VS_HDD <19> ODD_DETECT#
+5VS 1 2 16 V5 @R710
@ R710 1 2 0_0402_5% 8
17 V5 9 DP
JUMP_43X79 18 GND +5VS_ODD 10 +5V
19 Reserved 1 2 ODD_DA# 11 +5V
GND +3VS MD
20 R921 10K_0402_5% 12 15
21 V12 24 13 GND GND 14
+5VS 22 V12 GND 23 GND GND
ODD_DA#_R 1 2
V12 GND <18> ODD_DA#_R R922 @ 0_0402_5%
SANTA_202404-1
1 1 1 1 1 SANTA_191201-1
R1517 1 2 R_short 0_0402_5%
<32,45> SLI_FAN_PWM ME@
C631 C632 C633 C634 C635
10U_0603_6.3V6M 10U_0603_6.3V6M ME@
1000P_0402_50V7K 0.1U_0402_16V4Z 1U_0603_10V4Z
2 2 2 2 2

3 ODD Power Control 3

@ J6 AO3413
1 2 VGS= -4.5V, Id=-3A, Rds<97m ohm
1 2
+5VS
JUMP_43X79 +5VS_ODD
+5VALW Q88 AO3413_SOT23-3

3 1

D
1

1
R1496 1

1
100K_0402_5% 1 2
R923 C637

G
2
C638 0.1U_0402_16V4Z R1477
100K_0402_5% C1049 470_0603_5%
2
0.1U_0402_16V4Z 0.01U_0402_16V7K @
1

2
@ 2

2
1

2
2 R1110 1 ODD_EN# C639

3
10U_0603_6.3V6M D
100K_0402_5%

6
D 2 Q89B 5 ODD_EN#
2
2 Q89A 2N7002KDWH_SOT363-6 G
<19> ODD_EN G C1057
2N7002KDWH_SOT363-6
1

@ 0.01U_0402_16V7K S

4
1
1 S
R1478
100K_0402_5%
2

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 HDD/ODD Connector

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B LA-8692P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Tuesday, June 05, 2012 Sheet 42 of 66
A B C D E F G H
 A B C D E F G H

+5VS_AVDD +3VS +3VS_DVDD +3VS_DVDD +3VS_DVDDIO

L10
1 2 +5VS_AVDD 1 R1355 2 +3VS_DVDD 1 RA6 2 +3VS_DVDDIO
+5VS

4.7U_0805_10V4Z

0.1U_0402_16V4Z

10U_0603_6.3V6M

0.1U_0402_16V4Z
FBMA-L11160808601LMA10T_2P
0_0603_5% 0_0402_5%
600ohms @100MHz 1A

0.1U_0402_16V4Z
1 1 1 1

CA13

CA14
+MIC1_VREFO_L

CA17

CA18
1U_0603_10V4Z
P/N: SM01000BU00 1 1 P/N: SM01000DI0J

CA15

CA16
2 2 2 2
@ @
2 2

2
1 Place near UA8.Pin1 1
RA1622 RA1623 Place near UA8.Pin25
2.2K_0402_5% 2.2K_0402_5% Place near UA8.Pin1
11/07 -->
Change CA17 type to 0603

1
MIC2_R RA1634 2 1 1K_0402_5% EXT_MIC_R
EXT_MIC_R <49>
MIC1_RRA1633 2 1 1K_0402_5% EXT_MIC_L
EXT_MIC_L <49>

+5VS_AVDD

RA5
+5VS
1 2 +5VS_PVDD +5VS_AVDD 30 mils JSPK1
0_0805_5% SPKOUT_L1+ RA56 1 2 0_0603_5% SPK_L1 1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
+3VS_DVDDIO
SPKOUT_L2- RA58 1 2 0_0603_5% SPK_L2 2 1

+3VS_DVDD
2 1 1 1 2 2
2 0_0603_5%

C648
600ohms @100MHz 2A SPKOUT_R1+ RA60 1 SPK_R1 3
2 0_0603_5% 3

CA6

CA7

CA8

C293
SPKOUT_R2- RA61 1 SPK_R2 4
P/N: SM01000EE00 5 4
+3VALW 1 2 2 2 1 G5
6
G6
ACES_85205-04001
2

ME@

39

46

25

38

9
R1407 UA8 Place near UA8.Pin38
10K_0402_5% Place near UA8.Pin39, Pin46

DVDD-IO
PVDD1

PVDD2

AVDD1

AVDD2

DVDD1
@
1

EC_MUTE# SPK_R1 @ CA9 1 2 1000P_0402_50V7K~N

47 24
DAPD/COMB_JACK LINE1-R(PORT-C-R) SPK_R2 @ CA10 1 2 1000P_0402_50V7K~N
2 EC_MUTE# 4 23 2
<45> EC_MUTE# PD# LINE1-L(PORT-C-L) SPK_L1 @ CA11 1 2 1000P_0402_50V7K~N
HDA_SDOUT_AUDIO 5 22 C_MIC2 CA1277 2 1 2.2U_0603_6.3V6K MIC2_R
<14> HDA_SDOUT_AUDIO SDATA-OUT MIC1-R(PORT-B-R)
Ext. MIC SPK_L2 @ CA12 1 2 1000P_0402_50V7K~N
HDA_BITCLK_AUDIO 6 21 C_MIC1 CA1276 2 1 2.2U_0603_6.3V6K MIC1_R
+3VS <14> HDA_BITCLK_AUDIO BIT-CLK MIC1-L(PORT-B-L)
10 mils

2
HDA_SDIN0 2 1 HDA_SDIN0_R 8 17
<14> HDA_SDIN0 SDATA-IN MIC2-R(PORT-F-R) @
RA1637
2

AZ5125-02S.R7G_SOT23-3

AZ5125-02S.R7G_SOT23-3
16
22_0402_5% MIC2-L(PORT-F-L)
RA475 D62 @ D61
@ 4.7K_0402_5% HDA_SYNC_AUDIO 10 15
<14> HDA_SYNC_AUDIO SYNC LINE2-R(PORT-E-R)
HDA_RST_AUDIO# HDA_RST_AUDIO# 11 14
<14> HDA_RST_AUDIO#
1

RESET# LINE2-L(PORT-E-L)
PC_BEEP 12 30 mils

1
PCBEEP
@ CA1368 40 SPKOUT_L1+
100P_0402_50V8J~N 2 RA1640 1 JDREF 19 SPK-OUT-L+
MIC Sense --> RA1639 place near pin13 JDREF 41 SPKOUT_L2-
Capless HP Sense --> RA1638 place near pin34 20K_0402_1% 20 SPK-OUT-L-
MONO-OUT(PORT-H) 44 SPKOUT_R2-
MIC_JD RA1639 2 1 20K_0402_1% SENSEA 13 SPK-OUT-R-
<49> MIC_JD Sense A Reserve for ESD request.
45 SPKOUT_R1+
PLUG_IN RA1638 2 1 39.2K_0402_1% 18 SPK-OUT-R+
<49> PLUG_IN Sense-B 10 mils
1 2 CBN 35 33 HPOUTR_R R3 2 1 75_0402_5% HP_OUTR
CBN HPOUT-R(PORT-A-R) HP_OUTR <49>
CA1288 2.2U_0603_6.3V6K HeadPhone
CBP 36 32 HPOUTL_R R4 2 1 75_0402_5% HP_OUTL
CBP HPOUT-L(PORT-A-L) HP_OUTL <49>
2 1 CPVEE 34 48 SPDIF R945 1 2 SPDIF_OUT SPDIF
CPVEE SPDIF-OUT SPDIF_OUT <49>
C673 2.2U_0603_6.3V6K FBMA-10-100505-301T_2P
2 1 LDO_CAP 28 EMI Request
3 C291 4.7U_0603_6.3V6K LDO-CAP 3 DMIC_CLK_R R955 1 2 DMIC_CLK 3
GPIO1/DMIC-CLK DMIC_CLK <50>
FBMA-10-100505-301T_2P Int. MIC
29 2 DMIC_DATA_R R954 2 1 0_0402_5% DMIC_DATA
MIC2-VREFO GPIO0/DMIC-DATA DMIC_DATA <50>
30 10 mils
MIC1-VREFO-R
10 mils 31
+MIC1_VREFO_L MIC1-VREFO-L

For EMI 42 27 AC97_VREF 10 mils

PVSS1 VREF

1U_0603_10V4Z

0.1U_0402_16V4Z
43 26 2 1
PVSS2 AVSS1

CA1290

CA1291
HDA_SYNC_AUDIO HDA_SDOUT_AUDIO
2 2 7 37
DVSS AVSS2
CA1278 @ CA1285 49 1 2
10P_0402_50V8J 10P_0402_50V8J Thermal PAD
1 1
Close to UA8.Pin27
ALC269Q-VC2-GR_QFN48_6X6 AGND
RA1635 1
@ 2 HDA_BITCLK_AUDIO
1 0_0402_5%
@ CA1282
22P_0402_50V8J~N
2

Pin Assignment Location Function

PC Beep SPK-OUT (Pin40/41/44/45) Internal Int Speaker
4 1 2 4
EC Beep <45> BEEP#
CA4 0.1U_0402_16V4Z Capless HP-OUT (Pin32/33) External Headphone out
RA1
PCH Beep <14> 1 2 PC_BEEP1 1 2 PC_BEEP MIC1(Pin21/22) External Mic in
HDA_SPKR
CA5 0.1U_0402_16V4Z 33_0402_5%
@ 1 RA1647 2
1

0_0402_5% Security Classification LC Future Center Secret Data Title

@ RA2
10K_0402_5% Issued Date 2014/07/01 HD Audio ALC269/Audio Jack
2012/07/01 Deciphered Date
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
DGND AGND Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-8692P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Tuesday, June 05, 2012 Sheet 43 of 66
A B C D E F G H
 5 4 3 2 1

R1458
2 1
+3VS +3VS_CARD
0_0603_5%
close to JREAD1 pin 9 @
MDIO5_R R1459 2 @ 1 C1023 1 2

close to JREAD1 pin 17 100_0402_5% 100P_0402_50V8J

@
U71 CLK_PCIE_CARD_PCH# MDIO5_R R1460 2 @ 1 C1024 1 2
D CLK_PCIE_CARD_PCH# <15> D
CLK_PCIE_CARD_PCH
5
JMB389 CLK_PCIE_CARD_PCH <15>
100_0402_5% 100P_0402_50V8J
+1.8VS_CARD
10 APVDD close to JREAD1 pin 36 @
36 APV18 3 1 R1461 2 MDIO5_RR R1462 2 @ 1 C1025 1 2
+3VS_CARD TAV33 APCLKN
19 4 12K_0402_1%
20 DV33 APCLKP 7 APREXT 100_0402_5% 100P_0402_50V8J
DV33 APREXT

Power
44 9 PCIE_PTX_C_DRX_N4

PCIE
18 DV33 APRXN 8 PCIE_PTX_C_DRX_N4 <15>
+1.8VS_CARD PCIE_PTX_C_DRX_P4
DV18 APRXP PCIE_PTX_C_DRX_P4 <15>
37 11 PCIE_PRX_C_DTX_N4 C1026 1 2 .1U_0402_16V7K PCIE_PRX_DTX_N4 Close to connector for EMI request.
1 2 43 DV18 APTXN 12 PCIE_PRX_DTX_N4 <15>
PCIE_PRX_C_DTX_P4 C1028 1 2 .1U_0402_16V7K PCIE_PRX_DTX_P4
SDDV33_18 APTXP PCIE_PRX_DTX_P4 <15>
C1027 2.2U_0603_6.3V6K
Please close to pin43
+CRD_POWER
48 MDIO0
MDIO0 47 MDIO1
MDIO1

System
1 46 MDIO2 (40mil)

Card Reader
6> PLT_RST# 2 XRSTN MDIO2 45 MDIO3 +CRD_POWER
13 XTEST MDIO3 41 MDIO4 R1463 R1464
CPPE_N MDIO4 800mA
21 42 MDIO5 1 2 MDIO5_R 1 2 MDIO5_RR
17 CR1_LEDN MDIO5 24 MDIO6 JREAD1
+CRD_POWER CR1_PCTLN MIDO6 R_short 0_0402_5% R_short 0_0402_5% 1 (40mil)
SD_CD# 16 40 MDIO7 C1029 22 11
MS_CD# 15 CR1_CD0N/WAKEN MDIO7 29 MDIO8 XD-VCC SD4-VDD 18
CR1_CD1N MDIO8 1 MS9-VCC
XD_CD# 14 28 MDIO9 10U_0805_10V4Z~D MDIO0 30 (40mil)
33 CR2_CD2N MDIO9 27 MDIO10 C1031 2 MDIO1 29 XD10-D0 9 MDIO5_R
C
34 SPI_CSN MDIO10 26 MDIO11
Close to CONN. MDIO2 28 XD11-D1 SD5-CLK 4 MDIO0
C
@ 22P_0402_50V8J
35 SPI_SO MDIO11 25 2 27 XD12-D2 SD7-DAT0 3

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
MDIO12 1 MDIO3 MDIO1 1 1
30 SPI_SI MDIO12 23 MDIO13 MDIO8 26 XD13-D3 SD8-DAT1 21 MDIO2
SPI_SCK MDIO13 XD14-D4 SD9-DAT2

C1030

C1032

C1033
39 22 MDIO14 MDIO9 25 19 MDIO3
TXIN MDIO14 MDIO10 24 XD15-D5 SD1-DAT3 16 MDIO4
2 MDIO11 23 XD16-D6 SD2-CMD 1 SD_CD# 2 2
XD17-D7 SD-CD 2 MDIO6
MDIO4 33 SD-WP
MDIO6 32 XD07-WE 6
6 MDIO14 34 XD08-WP SD6-VSS 13
31 APGND XD_CD# 39 XD06-ALE SD3-VSS
GND XD01-CD
GND

32 MDIO13 38
38 GND MDIO12 37 XD02-R/B
GND MDIO5_RR 36 XD03-RE 17 MDIO5_R
MDIO7 35 XD04-CE MS8-SCLK 10 MDIO0
JMB389-LGAZ0C_LQFP48_7X7 XD05-CLE MS4-DATA0 8 MDIO1
31 MS3-DATA1 12 MDIO2
40 XD GND MS5-DATA2 15 MDIO3
XD GND MS7-DATA3 14 MS_CD#
MS6-INS 7 MDIO4
MS2-BS 5
41 MS1-VSS 20
+1.8VS_CARD 42 SD CD/WP GND MS10-VSS
SD CD/WP GND
B B
T-SOL_144-1313002600_40P_NR-T
ME@
+3VS_CARD
10U_0805_10V4Z
0.1U_0402_16V4Z

0.1U_0402_16V4Z

1 1 1
C1034

C1036

C1037

+1.8VS_CARD

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
2 2 2
1 1 1 1

C1038

C1039

C1040

C1041
2 2 2 2
Close to pin10 @ @ 1 1
C1042 C1043
Close to pin5->1000P->0.1u->10u
0.1U_0402_16V4Z 10U_0805_10V4Z
2 2

XD_CD#
Close to pin 19,20 Close to pin 36 Close to pin 37 Close to pin 18
Close to pin 44
SD_CD# +CRD_POWER
A A
1 1
C1044 C1045
MDIO6 1 R1465 2 Title
0.1U_0402_16V4Z 0.1U_0402_16V4Z 1K_0402_5% Security Classification LC Future Center Secret Data
@ 2 @ 2
Issued Date 2012/07/01 Deciphered Date 2014/07/01 Card reader JMB389
MDIO13 1 R1466 2
1K_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B LA-8692P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Tuesday, June 05, 2012 Sheet 44 of 66
5 4 3 2 1
 All capacitors close to EC

L80 +3VS
BLM18PG181SN1D_0603
R1524 +3VALW_R 1 2
+3VALW_EC 1

0.1U_0402_16V4Z
C1075
2 1 1 1
close EC +3VALW C1072 C1073
0_0603_5% 0.1U_0402_16V4Z
EC_SCI#/ EC_SMI# pull up to PCH 1000P_0402_50V7K 2
C1082 2 1 1 2 ECAGND 2 2
+3VL
1 2 VCOREVCC
+3VS R1542 0_0603_5% L81
@ BLM18PG181SN1D_0603
D70 2 1 EC_SMI#_R .1U_0402_16V7K
<19> EC_SMI# RB751V-40_SOD323-2 For S3.5

1
D71 2 1 EC_SCI#_R R1535 +3VALW +3VL
<19> EC_SCI# RB751V-40_SOD323-2 minimum trace width 12 mil

0_0603_5%
@ +3VALW_R

1
+RTCBATT R1519 2 1

2
1 1 1 1 1 1 R1543 R1544
+3VALW_EC

C1081
0.1U_0402_16V4Z

C1080
0.1U_0402_16V4Z

C1079
0.1U_0402_16V4Z

C1078
0.1U_0402_16V4Z

C1077
0.1U_0402_16V4Z

C1076
0.1U_0402_16V4Z
0_0402_5% +5VALW
R_short 0_0603_5% @ 0_0603_5%
R1520 2 1 R1482
2 2 2 2 2 2 USB_CH# 1 2
R_short 0_0402_5%

2
2
10K_0402_5% R1417
EC_SMB_CK1 2 1
R1409
2.2K_0402_5%

114
121
127
USB_ON# 1 2

12

11

18
26
50
92

74
U70 R1424

3
EC_SMB_DA1 2 1
10K_0402_5%

VBAT/VCC

VCORE/VCC

VCC/VCC

VSTBY/VCC
VSTBY/VCC
VSTBY/VCC
VSTBY/VCC
VSTBY/VCC
VSTBY/VCC
VSTBY/VCC

AVCC
2.2K_0402_5%
+3VS
+3VS
R1423
EC_SMB_CK2 2 1
TP_CLK R1410 1 2 4.7K_0402_5%
2.2K_0402_5%
KBRST# 4 24 EC_SMB_DA2 2 1
<19> KBRST# KBRST#/GPB6 PWM0/GPA0 PWR_LED# <47> TP_DATAR1412 1 2 4.7K_0402_5%
pull up to PCH <14> SERIRQ
SERIRQ 5
SERIRQ/GPM6 PWM1/GPA1
25 BATT_CHG_LED#
BATT_CHG_LED# <47> 2.2K_0402_5% R1422
LPC_FRAME# 6 28 BATT_LOW_LED#
<14,38> LPC_FRAME# 7 LFRAME#/GPM5 PWM2/GPA2 29 BATT_LOW_LED# <47>
LPC_AD3 LED_KB_PWM
<14,38> LPC_AD3 LAD3/GPM3 PWM3/GPA3 LED_KB_PWM <51>
LPC_AD2 8 PWM PWM4/GPA4 30 SLI_FAN_PWM +3VS
<14,38> LPC_AD2 9 LAD2/GPM2 31 SLI_FAN_PWM <32,42>for 2nd fan
LPC_AD1 EC_FAN_PWM
<14,38> LPC_AD1
LPC_AD0 10 LAD1/GPM1 PWM5/GPA5 32 BEEP#
EC_FAN_PWM <41> for fan
<14,38> LPC_AD0
13 LAD0/GPM0 PWM6/SSCK/GPA6 34 EC_INVT_PWM
BEEP# <43> for EC beep EC_FAN_SPEED 2
R1431
1
R1404 <18> CLK_PCI_EC LPCCLK/GPM4 LPC PWM7/RIG1#/GPA7 EC_INVT_PWM <34>
+3VALW 1 2 WRST# 14 120 ACIN
WRST# TMRI0/WUI2/GPC4 ACIN <63> 10K_0402_5%
100K_0402_5% EC_SMI#_R 15 124 VGA_AC_DET
+3VL ECSMI#/GPD4 TMRI1/WUI3/GPC6 VGA_AC_DET <23,32,59>
1U_0402_6.3V6K
C999

1 BATT_LEN# 16 R1485
<54> BATT_LEN# PWUREQ#/BBO/SMCLK2ALT/GPC7 SLI_FAN_SPEED 2 1
1 @ 2 17 66 VGA_IMON VGA_IMON <59>
22 NC ADC0/GPI0 67 10K_0402_5%
R1545 100K_0402_5% <18,23,32,38,39,44,6> PLT_RST# SA_PGOOD <57>
EC_SCI#_R 23 LPCRST#/WUI4/GPD2 ADC1/GPI1 68 BATT_TEMP
For S3.5 2 ECSCI#/GPD3 ADC2/GPI2 BATT_TEMP <54>
GATEA20 126 ADC 69
<19> GATEA20 GA20/GPB5 ADC3/GPI3 70 IMVP_IMON <60>
LAN_WAKE#
ADC4/WUI28/GPI4 71
ADC5/DCD1#/WUI29/GPI5 ADP_I <54,63> +3VS
72 AD_ID AD_ID <54>
ADC6/DSR1#/WUI30/GPI6 73 LID_SW# @ R1402
ADC7/CTS1#/WUI31/GPI7 LID_SW# <46> EC_FAN_PWM 2 1
KSI0 58
KSI1 59 KSI0/STB# 78 10K_0402_5%
KSI1/AFD# DAC2/TACH0B/GPJ2 SUSWARN# <16>
KSO[0..17] KSI2 60 79 AC_PRESENT <16>
KSI3 61 KSI2/INIT# DAC3/TACH1B/GPJ3 80
<46> KSO[0..17] KSI3/SLIN# DAC DAC4/DCD0#/GPJ4 DRAMRST_CNTRL_EC <7>
KSI[0..7] KSI4 62 81 EC_WL_OFF#_R
KSI4 DAC5/RIG0#/GPJ5 EC_WL_OFF#_R <38>
<46> KSI[0..7] KSI5 63
KSI6 64 KSI5 85 USB_CH#
KSI6 PS2CLK0/TMB0/GPF0 USB_CH# <49>
KSI7 65 PS2 86
KSI7 PS2DAT0/TMB1/GPF1 PBTN_OUT# <16,6>
KSO0 36 87 PM_SLP_SUS# <16,52>
KSO1 37 KSO0/PD0 PS2CLK1/DTR0#/GPF2 88 SUSACK# +3VS
KSO1/PD1 Int. K/B PS2DAT1/RTS0#/GPF3 SUSACK# <16>
KSO2 38 89 TP_CLK
Matrix TP_CLK <46>

EXTERNAL SERIAL FLASH

KSO3 39 KSO2/PD2 PS2CLK2/WUI20/GPF4 90 TP_DATA
KSO3/PD3 PS2DAT2/WUI21/GPF5 TP_DATA <46> LPC_FRAME# R1521 1 2 10K_0402_5%
KSO4 40
KSO5 41 KSO4/PD4 96 CAPS_LED#
42 KSO5/PD5 WUI19/GPH3/ID3 97 CAPS_LED# <47>
KSO6 PCH_PWR_EN
KSO6/PD6 GPH4/ID4 PCH_PWR_EN <52>
KSO7 43 98 ACOFF
44 KSO7/PD7 GPH5/ID5 99 ACOFF <63>
KSO8 PCH_PWROK
KSO8/ACK# GPH6/ID6 PCH_PWROK <16>
KSO9 45
KSO10 46 KSO9/BUSY 101 GPG3
R1433 1 @ 2 10K_0402_5%
KSO11 51 KSO10/PE GPG3 102 GPG4
KSO12 52 KSO11/ERR# GPG4 103 GPG5 GPG5 PAD IT0
KSO12/SLCT SPI Flash ROM GPG5
KSO13 53 105 CMOS_ON# CMOS_ON# PAD IT1
Reserved SMBus channel 0 for debugging KSO14 54 KSO13 GPG7 CMOS_ON# <50>
KSO14 GPG3 PAD IT2
KSO15 55
EC_SMB_CK1 KSO16 56 KSO15 108 EC_RX GPG4 PAD IT3
<49,54,63> EC_SMB_CK1 KSO16/SMOSI/GPC3 RXD/SIN0/GPB0 EC_RX <38>
EC_SMB_DA1 KSO17 57 UART 109 EC_TX H_PROCHOT#_EC PAD IT4
<49,54,63> EC_SMB_DA1 KSO17/SMISO/GPC5 TXD/SOUT0/GPB1 EC_TX <38>
PAD IT5
EC_SMB_CK2 110 82 SYSON PAD IT6
<15,23,32,41> EC_SMB_CK2 111 SMCLK0/GPB3 EGAD/WUI25/GPE1 83 SYSON <56> PAD IT7
EC_SMB_DA2 SM Bus SUSP#
<15,23,32,41> EC_SMB_DA2 SMDAT0/GPB4 EGCS#/WUI26/GPE2 SUSP# <32,52,56,58,59>
Please place R1435 close to EC with in 790mil EC_SMB_CK1 115 84
116 SMCLK1/GPC1 EGCLK/WUI27/GPE3 VR_ON <60>
EC_SMB_DA1
H_PECI 43_0402_1% 2 1 R1435 PECI_EC 117 SMDAT1/GPC2 77 WRST# PAD IT8
<6> H_PECI SMCLK2/PECI/WUI22/GPF6 GPJ1 EC_MUTE# <43>
LAN_PWR_ON# 118 100 ENBKL ENBKL <34>
<39> LAN_PWR_ON# 94 SMDAT2/PECIRQT#/WUI23/GPF7 SSCE0#/GPG2 106
GPIO H_PROCHOT#_EC R1429 2 @ 1 0_0402_5%
<16> PM_SLP_S3# WUI17/CRX1/SIN1/SMCLK3/GPH1/ID1 SSCE1#/GPG0 PROCHOT <54>
<16> PM_SLP_S4# 95 104 For factory EC flash
WUI18/CTX1/SOUT1/GPH2/SMDAT3/ID2 DSR0#/GPG6 107 ME_FLASH <14>
EC_ON
DTR1#/SBUSY/GPG1/ID7 EC_ON <51,55>
119 BKOFF#
CRX0/GPC0 BKOFF# <34>
112 123 AOAC_ON
<16> EC_RSMRST# 125 RING#/PWRFAIL#/CK32KOUT/LPCRST#/GPB7 CTX0/TMA0/GPB2 AOAC_ON <52>
<51> ON/OFF PWRSW/GPE4 A_DET# <47>
WAKE UP R1619 @
76 A_DET# 1 2 0_0402_5%
TACH2/GPJ0 A_DET#_R <49>
48 SLI_FAN_SPEED
TACH1A/TMA1/GPD7 SLI_FAN_SPEED <32,42> R1427
<51> NOVO# NOVO# 19 47 EC_FAN_SPEED
USB_ON# 33 BAO/WUI24/GPE0 TACH0A/GPD6 EC_FAN_SPEED <41> VR_HOT# 1 2 H_PROCHOT# <54,6>
<48> USB_ON# <60> VR_HOT#
35 GINT/CTS0#/GPD5
<16> DPWROK_EC RTS1#/WUI5/GPE5 GPIO R_short 0_0402_5%
NUM_LED# 93

1
<47> NUM_LED# CLKRUN#/WUI16/GPH0/ID0 D
H_PROCHOT#_EC 2 1
EC_LID_OUT# 2 G
<19> EC_LID_OUT# R1539 1 CK32KE/GPJ7 Q141 S C1004
2 ECR_EN_R 128 Clock

3
<34> ECR_EN CK32K/GPJ6 2N7002H_SOT23-3 47P_0402_50V8J
R_short 0_0402_5% 2
1

BATT_TEMP 1 2
AVSS/AGND

R1540 1 2 EMC Request

<10> CPU1.5V_S3_GATE C1000 100P_0402_50V8J
0_0402_5%
VSS/GND
VSS/GND
VSS/GND
VSS/GND
VSS/GND
VSS/GND
VSS/GND
VSS/GND

100K_0402_5% SYSON ACIN 1 2

@ R1102
For Deep S3 C1001 100P_0402_50V8J

C1007
2

0.1U_0402_10V6K
+3VALW
1
1
20
21
27
49
91
113
122

75

2
IT8580E-HX_LQFP128
ECAGND

2 R1434
10K_0402_5%

1
LAN_WAKE#
LAN_WAKE# <38,39>

SUSP# SYSON

1
1
100K_0402_5% 100K_0402_5%
R1101 R1522

2
2
Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 BIOS & EC I/O Port

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C LA-8692P 0.2

Date: Tuesday, June 05, 2012 Sheet 45 of 66

 5 4 3 2 1

15" INT_KBD Conn.

KSI[0..7]
KSI[0..7] <45> JKB1
KSO[0..17] 1
KSO[0..17] <45> 2 1
3 2
4 3
KSO17 5 4
D KSO16 C794 1 2 @ 100P_0402_50V8J KSO16 6 5 D
KSO15 7 6
KSO17 C795 1 2 @ 100P_0402_50V8J KSO10 8 7
KSO11 9 8
KSO2 C734 1 2 @ 100P_0402_50V8J KSO1 C735 1 2 @ 100P_0402_50V8J KSO14 10 9
KSO13 11 10
KSO15 C736 1 2 @ 100P_0402_50V8J KSO7 C737 1 2 @ 100P_0402_50V8J KSO12 12 11
KSO3 13 12
KSO6 C738 1 2 @ 100P_0402_50V8J KSI2 C739 1 2 @ 100P_0402_50V8J KSO6 14 13
KSO8 15 14
KSO8 C740 1 2 @ 100P_0402_50V8J KSO5 C741 1 2 @ 100P_0402_50V8J KSO7 16 15
KSO4 17 16
KSO13 C742 1 2 @ 100P_0402_50V8J KSI3 C743 1 2 @ 100P_0402_50V8J KSO2 18 17
KSI0 19 18
KSO12 C744 1 2 @ 100P_0402_50V8J KSO14 C745 1 2 @ 100P_0402_50V8J KSO1 20 19
KSO5 21 20
KSO11 C746 1 2 @ 100P_0402_50V8J KSI7 C747 1 2 @ 100P_0402_50V8J KSI3 22 21
KSI2 23 22
KSO10 C748 1 2 @ 100P_0402_50V8J KSI6 C749 1 2 @ 100P_0402_50V8J KSO0 24 23
KSI5 25 24
KSO3 C750 1 2 @ 100P_0402_50V8J KSI5 C751 1 2 @ 100P_0402_50V8J 25

KSO4 C752 1 2 @ 100P_0402_50V8J KSI4 C753 1 2 @ 100P_0402_50V8J

KSI4
KSO9
KSI6
26
27
28
26
27
Lid Switch
KSI7 29 28 31
KSI0 C754 1 2 @ 100P_0402_50V8J KSO9 C755 1 2 @ 100P_0402_50V8J KSI1 30 29 G1 32
30 G2
KSO0 C756 1 2 @ 100P_0402_50V8J KSI1 C757 1 2 @ 100P_0402_50V8J ACES_85202-3005N R1002
+3VALW 1 2 +VCC_LID R1003 1 2 100K_0402_5%

C ME@ R_short 0_0402_5% C

CONN PIN define need double check

2
5711ACDL-M3T1S SOT-23

VDD
1
3
OUTPUT LID_SW # <45>
C758
To TP/B Conn. 0.1U_0402_16V4Z 2

GND
2
C759
U37 10P_0402_50V8J

1
JTP1 1
SMB_DATA_S3 1
<12,13,15,38> SMB_DATA_S3 1
SMB_CLK_S3 2
<12,13,15,38> SMB_CLK_S3 2
3
TP_DATA 4 3
<45> TP_DATA 4
TP_CLK 5
<45> TP_CLK 5
1 1 +3VS 6
@ @ 6
C761 C762 C760 7
100P_0402_50V8J 100P_0402_50V8J 8 GND
2 2 0.1U_0402_16V4Z GND

ACES_88514-00601-071
ME@

D58

B 4 1 B
I/O3 I/O1
+3VALW

5 2
VDD GND

6 3
I/O4 I/O2

AZC099-04S.R7G_SOT23-6
@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 KB /SW /LPC Debug Conn.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
B
LA-8692P 0.2

Date: Tuesday, June 05, 2012 Sheet 46 of 66

5 4 3 2 1
 +3VALW
+3VALW
PWR_LED#_R
LED

1
BATT_CHG_LED#_R

1
R1559
White

2N7002KDWH_SOT363-6
6
100K_0402_5% D
R1558
2
Amber LED2

6
D

2N7002KDWH_SOT363-6
100K_0402_5%

Q159A
2
2 G BATT_LOW_LED#_R 2 1 3
1

Q158A
2

0.1U_0402_16V4Z
G 470_0402_5% R1012

C1099
1 S 1

0.1U_0402_16V4Z

1
+5VALW

C1098

2N7002KDWH_SOT363-6
S 2

1
BATT_CHG_LED#_R 2 1 2

2N7002KDWH_SOT363-6

3
D
2 470_0402_5% R1014
5

3
D
White

Q159B
<45> PWR_LED#
5 G

Q158B
<45> BATT_CHG_LED# 12-22-S2ST3D-C30-2C_WHI-ORG
G
S LED3

4
S PWR_LED#_R 1 2 2 1
<51> PWR_LED#_R +5VALW

4
300_0402_5% R1013
12-21SYGCS530-E1S155TR8_W

1 2 White
1 2 R1560 0_0402_5%
R1561 0_0402_5% @
@ LED1
1 2 2 1
<45> CAPS_LED# +5VS
300_0402_5% R1322
12-21SYGCS530-E1S155TR8_W

LED4
HDD_LED#_R 1 2 2 1
+5VS
300_0402_5% R1323
12-21SYGCS530-E1S155TR8_W
+3VALW

BATT_LOW_LED#_R
1

LED5
1 2 2 1
+5VS <45> NUM_LED# +5VS
R1562 300_0402_5% R1563
+5VS
6

100K_0402_5% D 12-21SYGCS530-E1S155TR8_W
2
2N7002KDWH_SOT363-6
Q160A
2

1
G

1
1
0.1U_0402_16V4Z
C1100

S R1490
1

10K_0402_1% R1491 LED3 LED2 LED4 LED1 LED5

2N7002KDWH_SOT363-6

2 10K_0402_1%
@

2
3

D
@

2
5
Q160B

<45> BATT_LOW_LED# HDD_LED#_R power

G R1621 battery HDD CAPS NUM
1 2
<45> A_DET#
S
4

6
0_0402_5% D D
1 2 5 2

2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6
Q151B

Q151A
<14> HDD_LED#
G G
R1622
0_0402_5% S S
1 2

1
R1564 0_0402_5% @ @ @
@
FD1 FD2 FD3 FD4
1 1 1 1

1 2
R1492 0_0402_5% CPU:H_3P8X 3 GPU:H_3P8 X 3
H10 H11 H12 H13 H14 H15
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA

1
MIN PCIE:H_3P3 X 3 H_3P0 X 9
H22 H17 H16 H18 H23 H24 H25 H26 H27 H28 H29
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA

1
1

1
1

1
H35
HOLEA
H_4P0X2P8N X 2
H20
HOLEA H21

1
HOLEA

+3VS +3VS_BT

1
BT@
Q154 AO3413_SOT23-3
30mils Keyboad:H_2P8X3
3 1
S

0.01U_0402_16V7K

BT@ 1 1
1
C1085 0.1U_0402_16V4Z H31
C1083 H32 H33 H34
G

HOLEA
C1086

0.1U_0402_16V4Z
2

1 R1526 2 2 BT@ HOLEA HOLEA HOLEA

<19,38> PCH_BT_ON# 2
100K_0402_5% 2
BT@
BT@ JBT1

1
1

1
1

1
2 1
C1084 USB20_P13 3 2
<18> USB20_P13 3
0.1U_0402_16V4Z <18> USB20_N13 USB20_N13 4
2 4
@
5 Title
6 GND Security Classification LC Future Center Secret Data
GND
Issued Date 2012/07/01 Deciphered Date 2014/07/01 LED/EC SPI ROM/BT
ACES_50209-0040N-001
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
ME@
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B LA-8692P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Tuesday, June 05, 2012 Sheet 47 of 66
 A B C D E

LEFT SIDE USB3.0 PORT X1

+5VALW +USB_VCCA
U39
1 8
C767 0.1U_0402_16V4Z 2 GND VOUT 7
2 1 3 VIN VOUT 6
USB_ON# 4 VIN VOUT 5 USB_OC1#
1 <45> USB_ON# EN FLG USB_OC1# <18> 1
G547I2P81U_MSOP8 1
C904
Low Active 2A @ 1000P_0402_50V7K
2 +USB_VCCA
C814 220U_6.3V_M
1 2

+
For EMI request 1 2
C816 470P_0402_50V7K
USB2.0 choke --> SM070000I00
USB3.0 Choke --> SM070001U00
JUSB1
1
USB20_N2 R1162 1 2 0_0402_5% USB20_N2_R 2 VBUS
<18> USB20_N2 D-
USB20_P2 R1163 1 2 0_0402_5% USB20_P2_R 3
<18> USB20_P2 4 D+
L68 @
USB30_RX_N3 2 1 USB30_RX_R_N3 USB30_RX_N3 R1154 1 @ 2 0_0402_5% USB30_RX_R_N3 5 GND_1
2 1 <18> USB30_RX_N3 SSRX-
USB30_RX_P3 R1155 1 2 0_0402_5% USB30_RX_R_P3 6 13
<18> USB30_RX_P3 7 SSRX+ GND_6 12
@ GND_2 GND_5
USB30_RX_P3 3 4 USB30_RX_R_P3 USB30_TX_N3 C300 1 2 0.1U_0402_10V6K USB30_TX_C_N3 R1156 1 @ 2 0_0402_5% USB30_TX_R_N3 8 11
3 4 <18> USB30_TX_N3 USB30_TX_P3 C299 1 2 0.1U_0402_10V6K SSTX- GND_4
USB30_TX_C_P3 R1157 1 2 0_0402_5% USB30_TX_R_P3 9 10
<18> USB30_TX_P3 SSTX+ GND_3
WCM-2012-900T_4P @
@ SANTA_370300-1
L70
USB30_TX_C_N3 2 1 USB30_TX_R_N3 ME@
2 1
For ESD request
USB30_TX_C_P3 3 4 USB30_TX_R_P3
2 3 4 D27 D24 2
@ @
WCM-2012-900T_4P USB30_RX_R_N3 9 10 1 1 USB30_RX_R_N3 USB20_N2_R 3 6
I/O2 I/O4
L72 USB30_RX_R_P3 8 9 2 2 USB30_RX_R_P3
USB20_N2 2 1 USB20_N2_R
2 1 USB30_TX_R_N3 7 4 USB30_TX_R_N3 2 5
7 4 +5VALW
GND VDD
USB20_P2 3 4 USB20_P2_R USB30_TX_R_P3 6 6 5 5 USB30_TX_R_P3
3 4
WCM-2012-900T_4P 3 3 1 4 USB20_P2_R
I/O1 I/O3
8
AZC099-04S.R7G_SOT23-6

YSCLAMP0524P_SLP2510P8-10-9

+USB_VCCA @
C815 220U_6.3V_M
1 2
For EMI request

+
1 2 USB2.0 choke --> SM070000I00
C817 470P_0402_50V7K
USB3.0 Choke --> SM070001U00
3 3

L69
JUSB2 USB30_RX_N4 2 1 USB30_RX_R_N4
1 2 1
USB20_N3 R1165 1 2 0_0402_5% USB20_N3_R 2 VBUS
<18> USB20_N3 D-
USB20_P3 R1164 1 2 0_0402_5% USB20_P3_R 3 USB30_RX_P4 3 4 USB30_RX_R_P4
<18> USB20_P3 4 D+ 3 4
@ GND_1
USB30_RX_N4 R1158 1 @ 2 0_0402_5% USB30_RX_R_N4 5 WCM-2012-900T_4P
<18> USB30_RX_N4 SSRX-
USB30_RX_P4 R1159 1 2 0_0402_5% USB30_RX_R_P4 6 13
<18> USB30_RX_P4 7 SSRX+ GND_6 12
@ GND_2 GND_5 L71
USB30_TX_N4 C301 1 2 0.1U_0402_10V6K USB30_TX_C_N4 R1161 1 @ 2 0_0402_5% USB30_TX_R_N4 8 11 USB30_TX_C_N4 2 1 USB30_TX_R_N4
<18> USB30_TX_N4 SSTX- GND_4 2 1
USB30_TX_P4 C302 1 2 0.1U_0402_10V6K USB30_TX_C_P4 R1160 1 2 0_0402_5% USB30_TX_R_P4 9 10
<18> USB30_TX_P4 SSTX+ GND_3
@
@ SANTA_370300-1 USB30_TX_C_P4 3 4 USB30_TX_R_P4
3 4
For ESD request ME@ WCM-2012-900T_4P
L79
D28 D25 USB20_N3 2 1 USB20_N3_R
@ @
USB30_RX_R_N4 9 10 1 USB30_RX_R_N4 USB20_N3_R 3 6 2 1
1
I/O2 I/O4
USB30_RX_R_P4 8 9 2 2 USB30_RX_R_P4 USB20_P3 3 4 USB20_P3_R
3 4
USB30_TX_R_N4 7 7 4 4 USB30_TX_R_N4 2 5 WCM-2012-900T_4P
GND VDD +5VALW
USB30_TX_R_P4 6 6 5 5 USB30_TX_R_P4

3 3 1 4 USB20_P3_R
I/O1 I/O3
8
AZC099-04S.R7G_SOT23-6
4 4
YSCLAMP0524P_SLP2510P8-10-9

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 USB3.0 ports

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-8692P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Tuesday, June 05, 2012 Sheet 48 of 66
A B C D E
 5 4 3 2 1

+5VS
+5V_CHGUSB

JSB1
1
2 1
3 2
4 3
5 4
D 6 5 D
7 6
USB20_P9_C 8 7
USB20_N9_C 9 8
10 9
11 10
EXT_MIC_L 12 11
<43> EXT_MIC_L 12
EXT_MIC_R 13
<43> EXT_MIC_R 13
<43> MIC_JD MIC_JD 14
HP_OUTR 15 14
<43> HP_OUTR 15
HP_OUTL 16
<43> HP_OUTL 16
SPDIF_OUT 17 19
<43> SPDIF_OUT 17 G1
<43> PLUG_IN PLUG_IN 18 20
18 G2
ACES_50505-0184N-001

ME@

+5VALW +3VALW

+5V_CHGUSB
C C

2
1U_0402_6.3V6K

0.1U_0402_16V4Z
1 2

C1093
R1599

C1094
10K_0402_5%
@
2 1

1
Del C1095
A_DET#_R
<45> A_DET#_R

9
U8

2
VDD
+5VALW 7 R1583
VS1 3
1 1 VBUS1 10K_0402_5%
10U_0603_6.3V6M

0.01U_0402_16V7K

8 4
VS2 VBUS2
C1096

C1097

1
2 2 USB20_P9 14 17 USB20_P9_C
<18> USB20_P9 DPIN DPOUT
USB20_N9 15 16 USB20_N9_C
<18> USB20_N9 DMIN DMOUT
USB_CH# 10 18 A_DET#_R
<45> USB_CH# PWR_EN A_DET# 13
ALERT# USB_OC4# <18>
EM_EN 19 11 EC_SMB_DA1
EM_EN SMDATA/LATCH EC_SMB_DA1 <45,54,63>
12 EC_SMB_CK1
SMCLK/S0 EC_SMB_CK1 <45,54,63>
CH_M1 1 6 CH_SEL 1 2
M1 SEL
GND FLAG

B CH_M2 2 5 CH_ILIM 1 2 R1553 B

M2 COMM_SEL/ILIM R1555 10K_0402_5%
33K_0402_5%
GND

UCS1002-1-BP-TR_QFN20_4X4
21

20

@ R1584
ILIM SETTING SEL Pin Decode
R1551 Pull Low Pull Low
1 2 EM_EN 2 1 OR-500mA 0R-1010_1110
+5VALW
10K_0402_5% 10K_0402_5%
Active Mode Selection: 10K-900mA * 10K-1010_1100
12K-1000mA 12K-1010_1010
@ R1552 R1585 M1 M2 EM_EN ACTIVE MODE 15K-1200mA 15K-1010_1000
1 2 CH_M1 2 1 18K-1500mA 18K-0110_0000
10K_0402_5% 0 0 1 Dedicated Charger Emulation Cycle 22K-1800mA 22K-0110_0010
10K_0402_5% 0 1 0 Date Pass-through 27K-2000mA 27K-0110_0100
@ R1554 R1586 0 1 1 BC1.2 DCP * 33K-2500mA 33K-0110_0110
1 2 CH_M2 2 1 1 0 0 BC1.2 SDP
10K_0402_5%
1 0 1 Dedicated Charger Emulation Cycle
10K_0402_5% 1 1 0 Date Pass-through
*1 1 1 BC1.2 CDP
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 USB charger
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
LA-8692P 0.2

Date: Tuesday, June 05, 2012 Sheet 49 of 66

5 4 3 2 1
 5 4 3 2 1

C1070 For RF request

@
2 1

0.047U_0402_16V4Z
JCMOS1
CMOS 1
+CMOS_PW 1
W=40mils <18> USB20_N0 USB20_N0 2
USB20_P0 3 2
<18> USB20_P0 3
+3VS 4
5 4
D D
<43> DMIC_CLK 5
<43> DMIC_DATA 6
7 6
USB30_RX_N1 R1565 1 2 0_0402_5% USB30_RX_N1_R R1579 1 2 0_0402_5% B_INn 8 7
<18> USB30_RX_N1 R1566 8
USB30_RX_P1 1 2 0_0402_5% USB30_RX_P1_R R1580 1 2 0_0402_5% B_INp 9
<18> USB30_RX_P1 9
10
USB30_TX_N1 R1567 1 2 0_0402_5% USB30_TX_N1_C C304 1 2 0.1U_0402_10V6K A_OUTn 11 10
<18> USB30_TX_N1 R1568 C303 11
USB30_TX_P1 1 2 0_0402_5% USB30_TX_P1_C 1 2 0.1U_0402_10V6K A_OUTp 12
<18> USB30_TX_P1 12
13 15
14 13 GND1 16
14 GND2
I-PEX_20374-014E-31

ME@

+3VS

For ESD request

@
D69 DMIC_CLK 1 2
@

100P_0402_50V8J
1 1 B_INn 9 10 1 1 B_INn R1498
0_0402_5% 1

C934
C1101 C1102 B_INp 8 9 2 2 B_INp @
@
0.01U_0402_16V7K

0.1U_0402_16V7K
2 2 A_OUTn 7 4 A_OUTn
@ 7 4 2
U75 @
C A_OUTp 6 6 5 5 A_OUTp C
25 @ For EMI
1 EPAD 24
VDD 12C_EN 3 3
B_EQ0 2 23 B_OUTn 0.1U_0402_16V7K 2 1 C1104 USB30_RX_N1
B_DE0 3 B_EQ0 B_OUTn 22 B_OUTp 0.1U_0402_16V7K 2 1 C1103@ USB30_RX_P1 8
B_EQ1 4 I2C_R0 B_OUTp 21
5 I2C_R1 GND 20 A_INn 0.1U_0402_16V7K 2 1 C1105@USB30_TX_N1
PD# A_INn D55
B_DE1 6 19 A_INp 0.1U_0402_16V7K 2 1 C1106 USB30_TX_P1 YSCLAMP0524P_SLP2510P8-10-9
7 B_DE1 A_INp 18 A_DE1 USB20_P0 4 1 DMIC_DATA
B_INn R1581 @ 1 2 0_0402_5% B_INn_C 8 REXT A_DE1 17 A_EQ0 @ I/O3 I/O1
1

B_INp R1582 @ 1 2 0_0402_5% B_INp_C 9 B_INn A_EQ0 16 A_DE0

R1569 10 B_INp SCL_CTL 15 A_EQ1
2.49K_0402_1% A_OUTn C1107 @ 1 2 0.1U_0402_10V6K A_OUTn_C 11 GND SDA_CTL 14 TEST 5 2
A_OUTn TEST close to IC +3VS VDD GND
@ A_OUTp C1108 @ 1 2 0.1U_0402_10V6K A_OUTp_C 12 13
A_OUTp VDD
2

PS8710BTQFN24GTR2-A0_TQFN24_4X4 USB20_N0 6 3 DMIC_CLK

I/O4 I/O2

AZC099-04S.R7G_SOT23-6
@
Equalizer control and program for channel A
+3VS 3.3V tolerant. Internally pulled down at ~150K
[A_EQ1, A_EQ0] == ESD request
LL: adaptive EQ enable
LH: program EQ for channel loss up to 7dB
A_EQ0R1570 1 @ 2 4.7K_0402_5% HL: program EQ for channel loss up to 14.5dB
HH: program EQ for channel loss up to 11.5dB
B * B
A_EQ1R1572 1 @ 2 4.7K_0402_5%
Programmable output pre-emphasis level setting for channel A
3.3V tolerant. Internally pulled down at ~150K
CMOS Camera
[A_DE1, A_DE0] ==
LL: 3.5dB de-emphasis (40 MIL)
A_DE0R1574 1 @ 2 4.7K_0402_5% * LH: No de-emphasis
HL: 7dB de-emphasis Q94 AO3413_SOT23-3 +CMOS_PW
HH: 5dB with boost output swing (40 MIL) R432
A_DE1R1576 1 @ 2 4.7K_0402_5% 3 1 1 2

D
+3VS +CMOS_PW_R
Chip test mode enable. 1 R_short 0_0603_5% 1

10U_0603_6.3V6M
C519
CMOS@
3.3V tolerant. Internally pulled down at ~150K. C518

0.01U_0402_16V7K
1

2
TEST == 1 0.1U_0402_16V4Z
C1051 CMOS@
TEST R1578 1 @ 2 4.7K_0402_5% * L: Normal operation (default)
H: Test mode enable C1052 2
CMOS@
2 @
0.1U_0402_16V4Z CMOS@
2 2

R435
1 2
+3VS <45> CMOS_ON#
100K_0402_5% 1
Equalizer control and program for channel B @
3.3V tolerant. Internally pulled down at ~150K CMOS@ C520
B_EQ0R1571 1 @ 2 4.7K_0402_5% [B_EQ1, B_EQ0] == 0.1U_0402_16V4Z
LL: adaptive EQ enable 2
LH: program EQ for channel loss up to 7dB
B_EQ1R1573 1 @ 2 4.7K_0402_5% HL: program EQ for channel loss up to 14.5dB
A HH: program EQ for channel loss up to 11.5dB A
*
Programmable output pre-emphasis level setting for channel B
B_DE0R1575 1 @ 2 4.7K_0402_5% 3.3V tolerant. Internally pulled down at ~150K
[B_DE1, B_DE0] == Security Classification LC Future Center Secret Data Title
B_DE1R1577 1 @ 2 4.7K_0402_5%
* LL: 3.5dB de-emphasis
LH: No de-emphasis Issued Date 2012/07/01 Deciphered Date 2014/07/01 USB3.0 Redriver and Camera
HL: 7dB de-emphasis
HH: 5dB with boost output swing
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom
LA-8692P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Tuesday, June 05, 2012 Sheet 50 of 66
5 4 3 2 1
 ON/OFF switchSW2 +3VALW +3VL
Power Button/B link to Function/B Conn. 10pin KB Lighting CONN.4pin
1 3

2
Power Button 2 4 +VCC_KB_LED 1
JKBL1
100K_0402_5% 100K_0402_5% 1
SMT1-05_4P 2
R1116 R1546

0.1U_0402_10V6K
3 2

C905
6
5
@ 2 3
4
4

1
TOP Side J7 JPWR1
@
5
6 G1
1 2 1 @ 2
For S3.5 8 1 G2
7 GND
R1547 0_0603_5% ACES_85201-04051
SHORT PADS GND
Bottom Side @ For S3.5
+5VALW 6 ME@
D72 6
5
3 ON/OFF NOVO_BTN# 4 5
ON/OFF <45> 4 +5VS
ON/OFFBTN# 1 <47> PWR_LED#_R 3
2 51_ON# ON/OFFBTN# 2 3 AO3413
51_ON# <53> 2 VGS= -4.5V, Id=-3A, Rds<97m ohm
1
DAN202UT106_SC70-3 1 +VCC_KB_LED
D Q121 AO3413_SOT23-3

1
1 ACES_88514-00601-071

1
EC_ON 2 @ C551 KBL@
<45,55> EC_ON

D
G 3 1
ME@
2

Q153 100P_0402_50V8J R1229

S 2

3
R1523 2N7002_SOT23-3 10K_0402_5%
KBL@

G
10K_0402_5%

2
1

+3VALW +3VL
2
2

1
R1118 R1548
100K_0402_5% <45> LED_KB_PWM 2 Q122
100K_0402_5%
G 2N7002_SOT23
@

1
S KBL@

3
1
1

For S3.5 R1480

D56 100K_0402_5%
NOVO# 2
<45> NOVO# KBL@

2
1 NOVO_BTN#
51_ON# R19 1 2 3
R_short 0_0402_5%
DAN202UT106_SC70-3
R1549 0_0402_5%
ON/OFF @ 1 2
For S3.5

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 other IO connector
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
LA-8692P 0.2

Date: Tuesday, June 05, 2012 Sheet 51 of 66

 A B C D E

+5VALW TO +5VS +3VALW TO +3VS AP4800BGM

+1.5V_CPU_VDDQ
+1.5VS
AP4800BGM VGS=10V, ID=9A, Rds=18m ohm J15
VGS=10V, ID=9A, Rds=18m ohm +3VALW U47 +3VS VGS=+-25V +1.5V to +1.5VS 1 2
VGS=+-25V AP4800BGM-HF 1 2
+5VALW U46 +5VS +1.5V +1.5VS
8 1

@
AP4800BGM-HF JUMP_43X79
7 2

1
1 1 1

S
8 1 3 1

D
10U_0603_6.3V6M
6 3 C840
1 7 2 1 1 1 1 1

1
C839 5 C841

1
10U_0603_6.3V6M

10U_0603_6.3V6M
6 3 C837 R1474 Q120 C857 @
10U_0805_10V4Z 1U_0603_10V4Z
C836 5 C838 2 2 2 470_0603_5% C856 @ @ C835 @

G
2
R1475 R1481 @

4
10U_0805_10V4Z 1U_0603_10V4Z @ 10U_0805_10V4Z 1U_0603_10V4Z

2
2 2 2 470_0603_5% 2 2 2 470_0603_5%
+VSB

4
@ LP2301ALT1G 1P SOT-23-3

3 2

2
+VSB

3
D D

1
5 SUSP Q100B 5 SUSP
Q99B

3
1 +3VALW D 1
G 2N7002KDWH_SOT363-6 G
2N7002KDWH_SOT363-6 1.5VS_GATE 5 Q101B @
R1086 G
470K_0402_5% S

1
4

2N7002KDWH_SOT363-6
R1085 S @

4
R1089
150K_0402_5%

2
3VS_GATE 2 1 3VS_GATE_R S

4
100K_0402_5%
5VS_GATE 2 R1088 15VS_GATE_R R_short 0_0402_5% 1 R1087

6
D

1
1 SUSP 2 Q100A C843 R1090 @

2
82K_0402_5% G R1483 2 1 1.5VS_GATE
0.01U_0402_25V7K
6

D
1

C842 0_0402_5%

2N7002KDWH_SOT363-6
820K_0402_5% 2 1

6
SUSP 2 Q99A R1484 D

2N7002KDWH_SOT363-6
0.01U_0402_25V7K @
G 820K_0402_5% 2 S

1
SUSP# 2 Q101A @ C845 @
2N7002KDWH_SOT363-6

2
@ G .1U_0402_16V7K
S 2
1

1
+5VALW
+0.75VS
+3V_DSW to +3V_PCH +5VALW to +5V_PCH +5VALW

1
JUMP_43X79 JUMP_43X79

1
1
100K_0402_5% +3VALW +3V_PCH +5VALW +5V_PCH
R60 J11 J14
100K_0402_5% R1120
1 2 R1097 R1094
DS3@ 1 2
DS3@ 1 2 1 2 22_0603_5%
2

PCH_PWR_EN#_R 1 2 PCH_PWR_EN# 100K_0402_5%

3 2
2
SUSP D
Q148 Q149 <10,38,56,58> SUSP
1

D
AO3413_SOT23 AO3413_SOT23 Q107B 5 SUSP
<45> PCH_PWR_EN PCH_PWR_EN R117 1 2 2 Q118 G
2N7002_SOT23

2N7002KDWH_SOT363-6
G

D
R_short 0_0402_5% 3 1 3 1
1

S S
3

2 DS3@ 2

0.01U_0402_16V7K

4
PM_SLP_SUS# 2 1 DS3@ 1 1 DS3@

0.01U_0402_16V7K
1 1 1

6
<16,45> PM_SLP_SUS# C38 @ D
100K_0402_5% C1087 DS3@ 1 C39 @

G
R1448 0_0402_5% 0.1U_0402_16V4Z 2 Q107A

2
R1121 0.1U_0402_16V4Z

0.1U_0402_16V4Z
<32,45,56,58,59> SUSP#

C1088
G

C1090
@ 0.1U_0402_16V4Z 2N7002KDWH_SOT363-6
2 2 2 2
2

C1089
2 S

1
DS3@ DS3@ DS3@ DS3@

PCH_PWR_EN#_R
For Intel S3 Power Reduction.
12/13 add for Deep S3
+5VALW
+3VALW +3VS to +3VS_VGA
+3VS +3VS_VGA
1

1
R6
100K_0402_5% @
R1529 100K_0402_5%
+5VALW
AOAC@ Q145
2

2
<38> AOAC_ON# AOAC_ON# AO3413_SOT23
<58> 0.75VR_EN#

1
1

R1530 AOAC@ D

3
D

D
3 1 2 1
<45> AOAC_ON AOAC_ON 1 2 2 Q155 2 10.75VR_EN 5 Q144B R1449 1

1
0_0402_5% G 2N7002_SOT23 <57,58> +V1.05S_VCCP_PWRGOOD C1058 1
G 2N7002KDWH_SOT363-6 47K_0402_5% C37 10U_0603_6.3V6M
1

S R8 0.1U_0402_16V4Z C1059

G
3

2
AOAC@ 100K_0402_5% R1450
S <25> DGPU_PWR_EN# 2

0.01U_0402_25V7K
100K_0402_5% 1 2 2 470_0603_5%
AOAC@ R1531 @ @
6

2
R1451

6
2 D

C1011
SUSP R1452 10K_0402_5% 1
2

3
G 2 1 2 D
Q144A <18,23> DGPU_PWR_EN

0.1U_0402_10V7K
3 G 5 DGPU_PWR_EN# 3
2N7002KDWH_SOT363-6 R_short 0_0402_5% @

2N7002KDWH_SOT363-6
Q146A G

2N7002KDWH_SOT363-6
@ S
1

S 2

1
1
S Q146B

4
For S3 CPU Power Saving
R1454
100K_0402_5%

2
+3VS to +3VS_SLI
+3VS +3VS_SLI
+5VALW
Q147
AO3413_SOT23
1

SLI@
S

3 1
R1594 SLI@ 1 1
47K_0402_5% C1062
0.1U_0402_16V4Z C1063 2
G

SLI@
1
2

2 SLI@
0.01U_0402_25V7K

1 2 2 C48
<32> S_DGPU_PWR_EN# R1595
R1513 SLI@ 10U_0603_6.3V6M
1
6

R1596 D 470_0603_5%
10K_0402_5% 1 SLI@
@
C1110
1110

2 1 2
2

<19,32> S_DGPU_PWR_EN
0.1U_0402_10V7K

G
R_short 0_0402_5% @
@C
Q162A
2N7002KDWH_SOT363-6

4 2 4
S
3
1

SLI@ D
1

S_DGPU_PWR_EN# 5
2N7002KDWH_SOT363-6

R1597 G
100K_0402_5%
SLI@ Q162B S
4
2

SLI@
Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 DC Interface

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom LA-8692P 0.2

Date: Tuesday, June 05, 2012 Sheet 52 of 66

A B C D E
 5 4 3 2 1

TP41 TP40 TP42

DC030006J00 VIN B+ to SLI_B+

B+ SLI_B+

1
PF1 PL1
12A_65V_451012MRL SMB3025500YA_2P PQ69
4 APDIN 1 2 1 2 AON7403L_DFN8-5
4 1
3
3 2 5 +5VS to +5V_SLI

0.1U_0603_25V7K
3

1
1000P_0402_50V7K

1000P_0402_50V7K
100P_0402_50V8J

100P_0402_50V8J

PC515
2 JUMP_43X79
2 +5VS +5V_SLI
PJ19

@
D D

0.22U_0603_25V7K
1

2
1 1 2
1 2

2
@ 4602-Q04C-09R 4P P2.5

PC1

PC2

PC3

PC4

PC516
JDCIN1 PR398 SLI@ PQ70 AO6409AL 1P TSOP-6
200K_0402_1% SLI@

D
1
6

S
SLI@ 4 5

1
2

0.01U_0402_16V7K
1

0.1U_0402_16V4Z
1 1

2
SLI@

G
1
PR399 PC519

PC518
200K_0402_1%
2012/03/02 SLI@
SLI@ SLI@ 2 2
10U_0603_6.3V6M

PC517
TP43 TP44 TP45 2 SLI@
SLI@
add TP40~45(HW request)

1
PR400
47K_0402_1%
1 2
<32> SLI_B+_ON#
PR401
47K_0402_1%
1 2
<32> SLI_5V_ON#
SLI@
VIN SLI@

LL4148_LL34-2
2
2012/05/25

PD1
change Netname from +5VALW
PD2 <BOM Structure> to +5VS

1
C LL4148_LL34-2 PJ1 51ON-1 C

BATT+ 2 1 @ JUMP_43X39

1
68_1206_5%

68_1206_5%
1 2
1 2

PR1

PR2
PQ1
PR3 @ TP0610K-T1-E3_SOT23-3

2
200_0402_1%
1 2 51ON-2 3 1
VS
0.22U_0603_25V7K
1

100K_0402_1%

0.1U_0603_25V7K
2

1
PR4

PC5

PC6
1

PR5 2
2

22K_0402_1%
1 2 51ON-3

+3VLP
<51> 51_ON#
- JRTC1 + PR6
560_0603_5%
PR7
560_0603_5%
PD3
2 1 1 2 1 2 2 1
+RTCBATT

RB751V-40_SOD323-2
2

0_0402_5%

@ MAXEL_ML1220T10 1 2 +CHGRTC
+CHGRTC
PR8

PD4
@ PU1 PR9 RB751V-40_SOD323-2
@ 200_0603_5%
RTC Battery
1

APL5156-33DI-TRL_SOT89-3
3.3V
2

3 2 CHGRTCIN
B VOUT VIN B
1

GND PC8
PC7 1U_0805_25V6K
10U_0603_6.3V6M 1
@
2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 Vin Detector

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-8692P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Tuesday, June 05, 2012 Sheet 53 of 66
5 4 3 2 1
 5 4 3 2 1

VMB2 VMB
PF2 PL2
JBATT1 12A_65V_451012MRL SMB3025500YA_2P
1 1 2 1 2
1 2 BATT+
2 3 EC_SMCA
3 4 EC_SMDA
4 5
5

1
D 6 D
6

1
7 PC9 PC10
7

100_0402_1%

100_0402_1%
8 1000P_0402_50V7K 0.01U_0402_25V7K

2
GND 9
GND PR10

PR11
TYCO_1775789-1
2

2
@

For KB930 --> Keep PU1 circuit

PH1 under CPU botten side :
(Vth = 0.825V)
EC_SMB_CK1 <45,49,63> CPU thermal protection at 92+-3 degree C
For KB9012 (Red square) --> Remove PU1 circuit, but keep PR206
Recovery at 56 +-3 degree C
EC_SMB_DA1 <45,49,63> PH201, PR205,PR211,PQ201,PR208,PR212
1 2
+3VALW
VL
PR12 +3VLP PR15

0.1U_0603_25V7K
6.49K_0402_1%
<45,63> ADP_I
4.42K(SD000004J8J) :90W

2
16.5K_0402_1%

13.7K_0402_1%

21.5K_0402_1%
PC11

1
1 2
BATT_TEMP <45> A/D 9.1K(SD03491018J):120W

PR15

@ PR16

PR17
PR14

2
10K_0402_5% 16.5k(SD03416528J):170w
+3VS

1
PU2

2
1 8
VCC TMSNS1

100K_0402_1%
C 2 7 OTP_N_002 2 1 C
GND RHYST1 PR19

100K_0402_1%_NCP15WF104F03RC
1
PR18

PH1
3 6 Turbo_V 10K_0402_1%
<45,6> H_PROCHOT# OT1 TMSNS2
4 5 ADP_OCP_2 1 2

1
OT2 RHYST2

2
D

10K_0402_1%
G718TM1U_SOT23-8 PR20

2
PR21
PQ3 2 ADP_OCP_1 76.8K_0402_1%

OTP_N_003

Turbo_V
2N7002KW_SOT323-3 G
S

NTC_V
for power adapter ID

1
PR22 @
3V--- 90W 0_0402_5% PR23
1.5V--- 120W <45> PROCHOT 1 2 2 1
+3VALW MAINPWON <55>
0V--- 170W PR20
0_0402_5%
57.6K:90W (SD03457628J)
PR396
2 1 AD_ID <45>
82.5k:120W (SD00000278J)
76.8k:170w (SD03476828J)
100K_0402_5%

2 1

PR397
100K_0402_5%

+3VALW
B B

P2
100K_0402_1%
2

PQ4
+3VALW
PR25
0.01U_0402_25V7K

TP0610K-T1-E3_SOT23-3
1

100K_0402_1%
PC12

3 1
B+ +VSBP
1
2

VMB2

100K_0402_1%
PR24

0.22U_0603_25V7K
2

1
PR26

PC13
PR27 PR28
2

768K_0402_1% 10M_0402_5% PC14

1

1 2 0.1U_0603_25V7K
BATT_OUT <63>

2
PR29 PQ5

2
10K_0402_1% 2N7002KW_SOT323-3 PR30
8

1 2 VL 22K_0402_1%
1

3 D 1 2
P

+ 1 2
O
2

PR31 2 G
-
G
2

221K_0402_1% PU3A S PR32

3

AS393MTR-E1 SO 8P OP 100K_0402_1%
4

+3VALW PR33 PQ6

1

1K_0402_1% D PJ2
1

1 2 2 2N7002KW_SOT323-3 @ JUMP_43X39
<55> SPOK
100K_0402_1%

2 1 G 1 2
+CHGRTC +VSBP 1 2 +VSB
2

1U_0402_6.3V6K

S
3
1
PR35

PC15

PR34 @
10K_0402_1%
2

2 1
2VREF_8205
1

A PQ7 A
PR37
1

PR36 D 2N7002KW_SOT323-3
10K_0402_1% 2 1 2
<45> BATT_LEN#
G
10K_0402_1% S
3

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 BATTERY CONN/OTP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-8692P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Tuesday, June 05, 2012 Sheet 54 of 66
5 4 3 2 1
 5 4 3 2 1

Note:
Use TPS51125 IC can remove RTC refernece LDO
Use TPS51427 IC must keep RTC refernece LDO

2VREF_8205 PJ3
+3VALWP 2 1 +3VALW
2 1
@ JUMP_43X118

1U_0603_10V6K
D D

1
PC16
PJ4
+5VALWP 2 1 +5VALW

2
2 1
@ JUMP_43X118

PR38 PR39
13K_0402_1% 30K_0402_1%
1 2 1 2

PR40 PR41
RT8205_B+ 20K_0402_1% 20K_0402_1% RT8205_B+
1 2 1 2
PJ5 Typ: 175mA
B+ 2 1 +3VLP
0.1U_0603_25V7K

2 1

ENTRIP2

ENTRIP1
PC22

@ JUMP_43X118 PR43 PR42

2200P_0402_50V7K

2200P_0402_50V7K
0.1U_0603_25V7K

0.1U_0603_25V7K
4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
1

154K_0402_1% 88.7K_0402_1%
1 2 1 2
PC17

PC26
4.7U_0805_10V6K
1

1
PC18

PC19

PC20

PC21

PC23

PC25
2

8
7
6
5

5
6
7
8
PU4
2

2
PC24
PQ9

ENTRIP2

FB2

TONSEL

FB1

ENTRIP1
REF
1
C PQ8 AO406AL_SO8 C
25
AO4466L_SO8 P PAD

2
4 4
7 24
VO2 VO1 SPOK <54>
8 23 PR45 PC28
PR44 VREG3 PGOOD 2.2_0603_5% 0.1U_0603_25V7K
1
2
3

3
2
1
1 2 1 2 BST_3V 9 22 BST_5V 1 2 1 2
2.2_0603_5% BOOT2 BOOT1
PL3 PC27 UG_3V 10
VFB=2.0V 21 UG_5V PL4
3.3UH +-20% PCMC063T-3R3MN 6A 0.1U_0603_25V7K UGATE2 UGATE1 4.7UH_VMPI1004AR-4R7M-Z01_10A_20% +5VALWP
1 2 LX_3V 11 20 LX_5V 1 2
+3VALWP PHASE2 PHASE1
1

8
7
6
5

1
LG_3V 12 19 LG_5V
4.7_1206_5%

4.7_1206_5%
LGATE2 LGATE1

5
6
7
8
PR46

PQ10

PR47
SKIPSEL
AO4712_SO8 PQ11

VREG5
GND

150U_B2_6.3VM_R35M

150U_B2_6.3VM_R35M
VIN
RT8205LZQW_WQFN24_4X4

NC
EN
1 1
150U_B2_6.3VM_R35M

2
2012/02/29 4

@ 1U_0603_10V6K
1

1
4 + +

PC31

PC32

PC34
13

14

15

16

17

18
1

1
change PC29, PC32, +
PC29

PC30

PR48
680P_0603_50V7K

499K_0402_1% AO4456_SO8

680P_0603_50V7K
PC34 from

2
1 2 2 2

PC33
2

1
2
3

2
2
SGA00001E0J to B+

3
2
1
1
SGA00002N8J
100K_0402_1%

1U_0603_10V6K
VL

1
PC35

1
PR49

PC36
Typ: 175mA

4.7U_0805_10V6K
B B

2
ENTRIP1 ENTRIP2
2

2
PQ12B RT8205_B+
6

2N7002KDW-2N_SOT363-6
PR50
PQ12A 0_0402_5% RT8205

0.1U_0603_25V7K
2N7002KDW-2N_SOT363-6 2 5 2 1
2VREF_8205 TONSEL=VREF (1)SMPS1=300KHZ (+5VALWP)

PC37
PR52 @ (2)SMPS2=375KHZ(+3VALWP)
1

PR51 0_0402_5% TPS51125A

2
0_0402_5% 2 1 TONSEL=VREF (1)SMPS1=245KHZ (+5VALWP)
<54> MAINPWON 2 1 VL
PR54 @ (2)SMPS2=305KHZ(+3VALWP)
PR53 0_0402_5%
100K_0402_1% 2 1
2 1
VL
@ PR55
<45,51,55> EC_ON 0_0402_5% +3.3VALWP Imax=7.5A ; Ipeak=9A +5VALWP Imax=11.1A ; Ipeak=13.32A
2 1
1/2 Delta I=1.113A (F=375K Hz) 1/2 Delta I=1.33A (F=300K Hz)
1

Vtrip=0.169V Vtrip=0.098V
PQ14
PR56 2N7002KW_SOT323-3
Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical) Rds(on)=7.0m ohm(max) ; Rds(on)=5.1m ohm(typical)
D
1

200K_0402_1% Ilimit_min=0.169/18m=9.388A Ilimit_min=0.098/7m=14.03A

ACPRN 2 1 2 1 2 2 PQ13
G VS DTC115EUA_SC70-3
Ilimit_max=0.169/15=11.26A Ilimit_max=0.098/5.1m=19.21A
S PR57 Iocp=Ilimit+1/2Delta I=10.5A~12.373A Iocp=Ilimit+1/2Delta I=15.36A ~ 20.54A
40.2K_0402_1%

2.2U_0603_10V7K
3

A A
1

100K_0402_1%
1

1
PR58

PC38

3
2

<45,51,55> EC_ON
2

2 Title
PQ15 Security Classification LC Future Center Secret Data
DTC115EUA_SC70-3 3VALWP/5VALWP
Issued Date 2012/07/01 Deciphered Date 2014/07/01
3

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
LA-8692P 0.2

Date: Tuesday, June 05, 2012 Sheet 55 of 66

5 4 3 2 1
 A B C D

PJ6
1.5V_B+ 2
2 1
1 B+
Freq= 266~314KHz , 290KHz(typ)

470P_0603_50V7K
2200P_0402_50V7K
10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6
5
6
7
8
@ JUMP_43X118

1
PC39

PC40

PC41

PC42

PC43
PQ16 <BOM Structure>
Iocp=13.58A~23.10A

2
4 AO4406AL 1N SO8
PR59
0_0402_5%
1 2
<45> SYSON

3
2
1
2
47K_0402_5%
PR61 PC45 PL5

.1U_0402_16V7K
1 1

PC44 @
PR60
PU5 2.2_0603_5% 0.22U_0603_16V7K S COIL 1UH +-20% VMPI0703AR-1R0M-Z01 11A
+1.5VP

1
1 10 BST_1.5V 1 2BST_1.5V-1 1 2 1 2
PGOOD VBST
2 9 DH_1.5V

2
TRIP DRVH
3 8 LX_1.5V

4.7_1206_5%

220U_B2_6.3VM_R15M
EN SW

PR62 @
1

5
6
7
8
4 7
VFB V5IN +5VALW +

PC46
PQ17

1
5 6 DL_1.5V
RF DRVL PC47

84.5K_0402_1%

2
1
11 1U_0603_10V6K 2

470K_0402_1%

2
TP

2
PR63
4

1000P_0603_50V7K
PC48 @
TPS51212DSCR_SON10_3X3 PJ7 +1.5V

1
PR64
VFB=0.7V +1.5VP 2 1
2 1

2
AO4456 1N SO8 @ JUMP_43X118

3
2
1

2
PR65
1 2
PJ8
11.5K_0402_1%
1.5VSP_VGA_B+ 2
2 1
1 B+
1

470P_0603_50V7K
2200P_0402_50V7K
10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6
5
@ JUMP_43X118

1
PC49

PC50

PC51

PC52

PC53
PR66 PQ18 <BOM Structure>
PR67 10K_0402_1%
2
0_0402_5% MDV1525URH 1N PDFN33-8 2
2

2
FBVDDQ_PWR_EN 1 2
4
PR68
@ 0_0402_5%
1 2
5,52,56,58,59> SUSP#

3
2
1
2
PR69 @
47K_0402_5%

PR70 PC55 PL6

.1U_0402_16V7K
PC54 @

PU6 2.2_0603_5% 0.22U_0603_16V7K 1UH_PCMC063T-1R0MN_11A_20%

+1.5VSP_VGA
1

1 10 1
BST_1.5VSP_VGA 2BST_1.5VSP_VGA-1
1 2 1 2
PGOOD VBST
2 9 DH_1.5VSP_VGA
1

TRIP DRVH
3 8 LX_1.5VSP_VGA

4.7_1206_5%

220U_B2_6.3VM_R15M
EN SW

1
1
4 7

PR71

0.1U_0402_10V7K
VFB V5IN +5VALW

2
+

PC56
1
5 6 DL_1.5VSP_VGA
RF DRVL

PC58
75K_0402_1%

PC57

1
1

11 1U_0603_10V6K 2
470K_0402_1%

2
TP
2
PR72

1000P_0603_50V7K
TPS51212DSCR_SON10_3X3 4 PJ9 +1.5VS_VGA

1
PR73

PC59
VFB=0.7V +1.5VSP_VGA 2 1
2 1
2

PQ19 @ JUMP_43X118
1

2
S TR AON6784 1N DFN

3
2
1
PR75
PR74
0_0402_5%
1 2 2 1
VDDQ_SENSE <25>
1

3 3

11.5K_0402_1%
Freq= 266~314KHz , 290KHz(typ) PR76
10K_0402_1% PJ10
2 1
+1.05VS +1.05VS_VGA
2

Iocp=12.25A~20.77A 2 1
AO4456 1N SO8 @ JUMP_43X118
+1.05VS +1.05VS_VGA
PQ20

8 1

10U_0805_25V6K
+5VALW 7 2

@ 470K_0603_5%
1U_0603_10V6K
10U_0805_25V6K

2
+5VALW 6 3
1
PC60

PC61

PC62

PR77
1

2
1

PR78

1
10K_0402_1% PR79
100K_0402_1% PR80 PQ21 @
2

1
@ 0_0402_5% D
PR81
2

1 2 2 2N7002KW _SOT323-3
PR82 1 2 <10,38,52,58> SUSP G
PQ22B

0_0402_5% S
2N7002KDW-2N_SOT363-6

2N7002KDW-2N_SOT363-6

3
1

<19,27,59> DGPU_PWROK 1 2
100K_0402_1%
PR84
3

6
PQ22A

PC63 @ 0_0402_5%
PR83 0.01u_0603_10V6K 1 2
2

@ 0_0402_5%
1 2 5 2
<32,45,52,56,58,59> SUSP#
4

1
@ 1U_0603_10V6K
1
PC64

4 4
2

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 1.5VP/1.5VSP_VGA/1.05VSP_VGA

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
LA-8692P 0.2

Date: Tuesday, June 05, 2012 Sheet 56 of 66

A B C D
 5 4 3 2 1

+3VS PR85
1K_0402_1%
2 1
VID [0] VID[1] VCCSA Vout PJ11
+VCC_SAP

100K_0402_5%
0 0 0.9V H_VCCSA_VID1 <10> +VCCSAP 1 2 +VCCSA

1
TDC 4.2A
0 1 0.8V PAD-OPEN 4x4m

PR86
Peak Current 6A
1 0 0.725V OCP current 7.2A

2 +VCCSA_PWRGD
H_VCCSA_VID0 <10>
1 1 0.675V
PR87
<45> SA_PGOOD
1K_0402_1%
output voltage adjustable network 2 1
D D
The 1k PD on the VCCSA VIDs are empty.
These should be stuffed to ensure that

+VCCSA_VID0
+VCCSA_VID1
+5VALW

+VCCSA_PWRGD
VCCSA VID is 00 prior to VCCIO stability.

1U_0603_10V6K
2

PC65
PR88 PR89
10_0402_1% 0_0402_5%

1
2 1 +VCCSA_EN 1 2
+V1.05S_VCCP_PWRGOOD <52,58>
PC66
2.2U_0603_10V7K
1 2

18

17

16

15

14

13
PU7
PR90 PC67

VID1

VID0
PGOOD

EN
V5FILT
V5DRV
2.2_0603_5% 0.22U_0603_16V7K
12 +VCCSA_BT 1 2+VCCSA_BT_1 1 2
19 BST PL7
PGND 0.47UH_FDVE0630-H-R47M=P3_17.7A_20%
SW
11 +VCCSA_PHASE 1 2 +VCCSAP
20
PGND

22U_0805_6.3V6M

22U_0805_6.3V6M

0.1U_0402_10V7K
10

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
2200P_0402_50V7K
SW

1
21
2200P_0402_50V7K

PC68 @ @ @ @
0.1U_0603_25V7K

PGND

2
10U_0805_6.3V6M

10U_0805_6.3V6M
1000P_0603_50V7K

PC69

PC70

PC72

PC73

PC75

PC76
TPS51461RGER_QFN24_4X4 9

PC71

PC74
1 2
22 SW
PC78

1 2 2

1
VIN
2
PC77

PC79

PC80

8 PR91
23 SW 4.7_1206_5%
1

2 1 1 VIN
PJ12 7
+3VALW

2
2 1 +VCCSA_PWR_SRC +VCCSA_PWR_SRC 24 SW
2 1 VIN
C @ JUMP_43X118 25 C

COMP

MODE
TP

SLEW

VOUT
VREF
GND
1

6
@ PR92
2 1

33K_0402_5%
PC81 PR93
2 1 100_0402_5%
2 1
0.22U_0402_10V6K

0.01U_0402_25V7K
2
2 1 2 1
PR95

PC83
PC82 PR94 0_0402_5%

1
3300P_0402_50V7K 4.99K_0402_1% 2 1
+VCCSA_SENSE <10>

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 VCCSAP/1.05S_VCCPP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C LA-8692P 0.2

Date: Tuesday, June 05, 2012 Sheet 57 of 66

5 4 3 2 1
 5 4 3 2 1

PL8 PU8 SY8033BDBC_DFN10_3X3 PL9

4
HCB1608KF-121T30_0603 1UH_PH041H-1R0MS_3.8A_20%
1 2 1.8VSP_VIN 10 2 1.8VSP_LX 1 2
+5VALW

PG
PVIN LX +1.8VSP
9 3

68P_0402_50V8J
PVIN LX

1
680P_0603_50V7K 4.7_1206_5%
1

1
PC84 8

PC85
22U_0805_6.3VAM SVIN

PR96
D PR97 D
6 20K_0402_1%

2
5 FB

22U_0805_6.3VAM

22U_0805_6.3VAM
1 2

2
EN

1
PJ13

NC

NC
TP
FB=0.6Volt 2 1

PC87

PC88
+1.8VSP +1.8VS
2 1
<32,45,52,56,58,59> SUSP# PR98

PC86
11

2
1 2 EN_1.8VSP @ JUMP_43X118

2
0_0402_5%
+1.5V

0.1U_0402_10V7K
2

PC89 @
1.8VSP_FB PJ14

1
PR99 +0.75VSP 2 1 +0.75VS
2 1

1
1M_0402_5%

1
@ JUMP_43X118

2
PJ15 PR100

1
1
JUMP_43X118 10K_0402_1%
@ PJ16

2
2
2 1
2 1

2
PU9 @ JUMP_43X118
1
VIN NC
8 +3VALW +1.05VS_VCCPP PJ17 +1.05VS
2 1
PC90 2 7 2 1
GND NC

1
4.7U_0805_6.3V6K @ JUMP_43X118

1
3 6 PC91
PR101 VREF VCNTL

2
PR102 1K_0402_1% 4 5 1U_0603_10V6K
@ 0_0402_5% VOUT NC B+
<52> 0.75VR_EN# 1 2 9

2
TP

68U_25V_M_R0.36
C APL5336KAI-TRL_SOP8P8 1 C

PR103 +

PC92
0.1U_0402_16V4Z
D
+0.75VSP

1
47K_0402_1% PQ23

10U_0603_6.3V6M
@
<10,38,52,56> SUSP 1 2 2 2N7002KW_SOT323-3

PC95
1K_0402_1%

10U_0603_6.3V6M
1

1
2

PC93

PC94
PR104
G

2
S
0.1U_0402_10V7K

2
1
PC96

PR105
32,45,52,56,58,59> SUSP# 0_0402_5%
1 2
@ 10K_0402_1%

+3VS
2

+1.05VS_VCCPP OCP(min)=22.38A
@.1U_0402_16V7K
1
PR106

PC97

100K_0402_1%
2

PJ18
100K_0402_1%
1

1.05VS_B+ 2 1
PR107

2200P_0402_50V7K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
2 1
B+

0.1U_0402_25V6
2

@ JUMP_43X118
PR109

1
PR108

PC99

PC102
1

5
0_0402_5% PR110 PC103

PC98
PC101
1 2 0_0603_5% 0.1U_0603_25V7K PQ24
<52,57> +V1.05S_VCCP_PWRGOOD

2
1
BST_1.05VS_VCCP 2 1 2
1

B B
17

16

15

14

13

PU10 4
10.7K_0402_1%

PAD

PGOOD

EN
MODE

BST
2

AON6428L_DFN8-5
PR111

1 12 LX_1.05VS_VCCP PL10
0.1U_0402_25V6

3
2
1
VREF SW 1UH_PCMB062D-1R0MS_9A_20%
+1.05VS_VCCPP
1

1 2
1
PC100

2 11 DH_1.05VS_VCCP
2

REFIN DH
2

1
PQ25
PR112

1000P_0603_50V7K 4.7_1206_5%
5
PC104
12K_0402_1%

AON6504 1N DFN
TPS51219RTER_QFN16_3X3

PR113
0.01U_0402_25V7K 1
1

330U_D2_2VM_R6M
3 10 DL_1.05VS_VCCP
GSNS DL

PC105
+
1

2
4
4 9 2 3
VSNS V5 +5VALW
COMP

1
PGND

PC106
TRIP

GND

3
2
1

2
5

PC107
1
54.9K_0402_1%

PR114
2 PR115 1

1 2 PC108
<9> VCCIO_SENSE 1 2 1U_0603_10V6K
2
2
PR116 @

0.01U_0402_25V7K
0_0402_5%

A A
10_0402_1%
1000P_0402_50V7K
2
PC109

PR117
1

Security Classification LC Future Center Secret Data Title

1 2
Issued Date 2012/07/01 Deciphered Date 2014/07/01 1.8VSP/0.75VSP/1.05VS_VCCPP
2

10_0402_1%
PC110
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
1000P_0402_50V7K Size Document Number Rev
1

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
LA-8692P 0.2

Date: Tuesday, June 05, 2012 Sheet 58 of 66

5 4 3 2 1
 A B C D

+VDD33MISC

10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%
2

2
GL1:0.9V(110000) +VGA_B+ PL22
GT:0.975V(101010) HCB4532KF-800T90_1812
1 2

PR300

PR301

PR302

PR303

PR304

PR305

PR306

PR307

PR308

PR309

PR310

PR311
B+

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6

2200P_0402_50V7K
GPU_VID5

GPU_VID4

GPU_VID3

GPU_VID2

GPU_VID1

GPU_VID0

GPU_VID5

GPU_VID4

GPU_VID3

GPU_VID2

GPU_VID1

GPU_VID0
2012/04/26 PQ801@GL1

1
PC347

PC348

PC349

PC350
1
change PC352 from @ @ @ @ @ @ @ PQ802@GL1 1

to Mount

2
5
2012/04/26 PQ51

2
change PR313 from 0 PR313 PR312
to 75K 75K_0402_1% 0_0402_5%
1 2VRON_VGA 4

GPU_VID5

GPU_VID4

GPU_VID3

GPU_VID2

GPU_VID1

GPU_VID0
<23>

<23>

<23>

<23>

<23>

<23>
<18> NVDD_PWR_EN

1
PR314 @
0_0402_5% PR315 PC351 AON6428L_DFN8-5
1 2 2.2_0603_5% 0.22U_0603_10V7K

3
2
1
<32,45,52,56,58> SUSP# BOOT2_VGA 2 1 BOOT2_2_VGA 1 2
PR316 @ 1 2 PL23
<23,59> DPRSLPVR_VGA 1 2 UGATE2_VGA 0.36UH_VMPI1004AR-R36M-Z03_30A_20% +VGA_CORE
PC352 .1U_0402_16V7K
0_0402_5% PHASE2_VGA 1 4
PR317
1 2 DPRSLPVR_VGA-1 PQ52 LF2_VGA 2 3 V2N_VGA

10K_0402_1%
3.65K_0402_1%
2

1
10K_0402_1% PQ53

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

4.7_1206_5%

10K_0402_1%
AON6504 1N DFN

PR324 @
+3VS PR329 @ PR328

PR318

PR319

PR320

PR321

PR322

PR323

PR325

PR327
1 1 1

470U_D2_2VM_R9M
GPU_VID6

470U_D2_2VY_R9M

470U_D2_2VY_R9M
AON6504 1N DFN
1.91K_0402_1% 1_0402_1%

PR326
1 2 CLK_ENABLE#_VGA + + +

PC353

PC354

PC355
2
LGATE2_VGA 4 4
1.91K_0402_1%

2
1

1
2 2 2

ISEN1_VGA
VSUM+_VGA
SNUB2_VGA

ISEN2_VGA
PR330

PR331 PD8 @

3
2
1

3
2
1
0_0402_5% RB751V-40_SOD323-2
2

1 2 PR332 2 1 VSUM-_VGA
100K_0402_1%
+3VS 1 2

680P_0402_50V7K
DGPU_PWROK

PC356 @

1
1 2
<23,59> DPRSLPVR_VGA PR333 0_0402_5%

2
PR334 +VGA_CORE Under VGA Core
PSI#_VGA

2 2

147K_0402_1%
2 1 +VGA_CORE Near VGA Core
PC357
PR335 1U_0603_10V6K
40
39
38
37
36
35
34
33
32
31

@ 100K_0402_5% PU18 1 2
1 2
CLK_EN#

VID6
VID5
VID4
VID3
VID2
VID1
VID0
DPRSLPVR
VR_ON

+3VS

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M
RBIAS_VGA

22U_0805_6.3V6M

47U_0805_6.3V6M

4.7U_0805_6.3V6K
1

1
1 2 30

PC358

PC359

PC360

PC361

PC362

PC363

PC364

PC365
1 1

22U_0805_6.3V6M
<23,32,45> VGA_AC_DET BOOT2

1
29

PC366

PC367

PC368

PC369
PR336 @ 1 UGATE2 28

2
0_0402_5% 2 PGOOD PHASE2 27

2
PR337 470K_0402_5%_TSM0B474J4702RE 3 PSI# VSSP2 26 2 2
1 2 1 2 4 RBIAS LGATE2 25
5 VR_TT# VCCP 24
NTC PWM3 +5VS
4.02K_0402_1% PH8 VW_VGA 6 23
COMP_VGA 7 VW LGATE1 22
FB_VGA 8 COMP VSSP1 21

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0805_6.3V6K

4.7U_0805_6.3V6K

4.7U_0805_6.3V6K

4.7U_0805_6.3V6K
1 2ISEN3_VGA 9 FB PHASE1
ISEN3
1

1
UGATE1

10 PC371

PC372

PC373

PC374

PC375

PC376

PC377

PC378

PC379

PC380

PC381

PC382
BOOT1
ISUM+

ISEN2
ISEN1

ISUM-
VSEN

IMON

PC370 1U_0603_10V6K
8.06K_0402_1%

VDD
1000P_0402_50V7K

RTN

VIN

22P_0402_50V8J 41
249K_0402_1%

2
AGND
2

1
PR338 @

PC383

ISL62883CHRTZ-T_TQFN40_5X5
PR339

11
12
13
14
15
16
17
18
19
20

PR340
2

499_0402_1% PC384
1 2FB1_VGA1 2
ISUM-_VGA
1

VDD_VGA
RTN_VGA

390P_0402_50V7K
PC385 PR341 PR342 @ 0_0402_5%

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
47P_0402_50V8J 1.58K_0402_1% 1 2
+5VS PC818

1
1 2 1 2 VSEN_VGA

PC386

PC389

PC390

PC391

PC387

PC388

PC392

PC393
PR343 0_0402_5% PC825,PC827,PC828,PC829
11.8K_0402_1%
0.068U_0402_16V7K
2

VIN_VGA 1 2 VGA_IMON <45>

2
PC839,PC841,PC844,PC845
1

ISEN2_VGA
PC395

PR345

+VGA_B+
1 2FB2_VGA1 2 PR346
ISEN1_VGA 1_0402_5%
2

3
PC394 PR344 1 2 +VGA_B+ 3
0.22U_0402_10V6K

0.22U_0402_10V6K

1
1

150P_0402_50V8J 267K_0402_1% +5VS

1

1
PC396

PC397

PC398

PC399
1U_0603_10V6K

0.22U_0603_25V7K

PR347
75K_0402_1%
PQ806@GL1

2200P_0402_50V7K
2

BOOT1_VGA

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
1000P_0402_50V7K
2

5
PQ808@GL1 PQ54

1
PC520

PC400

PC401

PC402

PC403
2

2
VSUM-_VGA VSUM+_VGA UGATE1_VGA 4

1 2
82.5_0402_5%

+VGA_CORE
PR349 @

PR350 PC404
1
@

PR348 2.2_0603_5% 0.22U_0603_10V7K AON6428L_DFN8-5

3
2
1
1

10_0402_1% 2 1 BOOT1_1_VGA 1 2
2.61K_0402_1%

PL24
PR351

0.36UH_VMPI1004AR-R36M-Z03_30A_20%
1 2
<24> VCCSENSE_VGA
2

PHASE1_VGA 1 4
+VGA_CORE
2

PR352
VSUM_VGA_N001

0.22U_0603_10V7K

0.022U_0603_25V7K
1

0_0402_5% PQ55 LF1_VGA 2 3

<BOM V1N_VGA
Structure>

1
NTC_VGA

PC405 PQ56

10K_0402_1%
1

1
330P_0402_50V7K
PC406

PC407

10K_0402_1%
3.65K_0402_1%
2

1
AON6504 1N DFN

PR353

PR354

1_0402_1%
1 1

4.7_1206_5%

470U_D2_2VM_R9M

470U_D2_2VM_R9M
PR355 @

PR357
2

AON6504 1N DFN
+ +

PR356

PC408

PC409
0.01U_0402_25V7K

2
PC412 @

LGATE1_VGA 4 4
330P_0402_50V7K

2
1

1
PC411 @

11K_0402_1%

VSUM-_VGA 2
1

2 2

ISEN1_VGA

ISEN2_VGA
PC410 PH9
PR358

VSUM+_VGA
PR359 1000P_0402_50V7K 10K_0402_1%_TSM0A103F34D1RZ

1 SNUB1_VGA
0_0402_5%
2

3
2
1

3
2
1
1 2
<24> VSSSENSE_VGA
2

Layout Note:
Place near Phase1 Choke
@

PR360 PR361

680P_0402_50V7K
PC413 @
10_0402_1% 1.33K_0402_1%
4
1 2 1 2 VSUM-_VGA 4

2
1

PC414
0.1U_0402_16V7K
2

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 VGA_COREP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C LA-8692P 0.2

Date: Tuesday, June 05, 2012 Sheet 59 of 66

A B C D
 5 4 3 2 1

PR190
PR192

PR186 PC174
10_0402_1% 0.033u_0402_16V7K PC175 GFX@ GFX@

1200P_0402_50V7K
1 2 FBA3 1 2 0_0402_1% 1 2

330P_0402_50V8J
D GFX@ SLI@ GFX@ PUT COLSE 0_0402_1% D

75K_0402_1%
.1U_0402_16V7K SLI@
TO GT

1
PR188 PR189 1 PR190 2

PC176

PC177

PR191
TRBSTA# 1 2 GFX@ FBA1 1 2 GFX@ PH4 Inductor GFX@ GFX@

0.033u_0402_16V7K
2P: 24K 24K_0402_1% PR192 PC179

1
1
8.06K_0402_1% 806_0402_1% GFX@ GFX@ GFX@ 220K_0402_5%_ERTJ0EV224J CSCOMPA 1 2 DROOPA 1 2 CSREFA
1P: 24.9K

PC178
GFX@ GFX@

2
GFX@ PR193 PC180 PC181 GFX@ 2 PR194 1 NTC_PH203 1.65K_0402_1% 1000P_0402_50V7K

2
1 2 FBA2 1 2 1 2 165K_0402_1%

2 PR197 1
SLI@ 0_0402_5%
10_0402_1% GFX@ 2P: 1.65K
GFX@ 560P_0402_50V7K PR196 10P_0402_50V8J PC182 PR198 2P: install
1 PR195 2 1 2 COMPA1 1 2 1 2 SWN2A 1P: 1K
GFX@ 1P: @
1K_0402_1% 5.11K_0402_1% 2200P_0402_50V7K 91K_0603_1% CSREFA
GFX@ GFX@ 1 2 PC183 TSENSEA

2
GFX@ 0_0402_5% 1 PR200 2 SWN1A 0.047U_0402_16V7K

2 GFX@
SLI@ PR199 GFX@
2P: 21.5K 91K_0603_1% GFX@ GFX@ PR201 5.49K_0402_1%

1
CSP1A 1 2
1P: 15.8K SWN1A <61>

2
21.5K_0402_1%
PC185 GFX@

CSCOMPA
1000P_0402_50V7K
<10> VCC_AXG_SENSE

2
8.25K_0402_1%
1PR203
1PR202 2 2 PR204 1 CSREFA

1
PC184 0_0402_5% 0_0402_5% SLI@ 2P: install PH5

PR206
1000P_0402_50V7K SLI@ CSREFA <61> 1P: @

1
2 PR205 1 PC186 100K_0402_1%_TSM0B104F4251RZ
<10> VSS_AXG_SENSE 0.047U_0402_16V7K
PR207 0_0402_5% SLI@

1
+3VS

CSP2A
CSP1A
GFX@ 1 SLI@ 2 2 PR208 1 SLI@ CSP2A 1 2
+5VS SWN2A <61>

TRBSTA#

DROOPA

CSSUMA
0_0402_5% 0_0402_5% PR209 @

COMPA

TSENSEA
IMONA
FBA
1 2 GFX@ GFX@ 5.49K_0402_1% GFX@

DIFFA

ILIMA
1

PC187 GFX@
PR210 .1U_0402_16V7K
10K_0402_1% PR212 2P: 36K
2 PR211 1 1 2 PUT COLSE
0_0402_5% 36K_0402_1% 1P: 26.1K

61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
TO V_GT
2

+5VS 1 PR213 2 PU14 SLI@

C VR_RDYA C
2_0603_5% HOT SPOT

VSNA
VSPA
DIFFA

FBA
COMPA
IOUTA
ILIMA
DROOPA
CSCOMPA
CSSUMA
CSREFA
CSP2A
CSP1A
TSNSA
PAD

TRBSTA#
+1.05VS GFX@ 6132_PWMA <61>
PC188
1 2 6132_VCC
.1U_0402_16V7K

.1U_0402_16V7K

1 45 PR214 PC189
2.2U_0603_10V7K 2 VCC PWMA 44 BSTA1 1 2 BSTA1_12 1
VDDBP BSTA +5VS
130_0402_1%

54.9_0402_1%

PR217 VR_RDYA 3 43 2.2_0603_5% GFX@

VRDYA HGA HG1A <61>
1

PR215 2

1 2VR_ON_CPU 4 42 GFX@ 0.22U_0603_10V7K

<45> VR_ON EN SWA SW1A <61>
PR216

PC190 PC191 0_0402_5% VR_SVID_DAT1 5 41 PC192

SDIO LGA LG1A <61>
VR_SVID_ALRT# 6 40 BST2 1 PR218 2 BST2_1 2 1 2Phase: @
2

PR221 PR219 VR_SVID_CLK 7 ALERT# BST2 39 4.7_0603_5%

SCLK HG2 HG2 <61> 1Phase: install

0_0402_5%
PR224 @
0_0402_5% 95.3K_0402_1% 1 2 VBOOT 8 38 0.22U_0603_10V7K Option for
SW2 <61>
1

1 PR220 2VR_SVID_DAT1 1 2 10K_0402_1% ROSC_CPU 9 VBOOT NCP6132AMNR2G_QFN60_7X7 SW2 37

<9> VR_SVID_DAT ROSC LG2 LG2 <61> 1 phase GFX
CPU_B+ 1 2 VRMP 10 36 6132P_VCCP 1 PR223 2 2 1
<9> VR_SVID_ALRT# VRMP PVCC
VR_HOT# 11 35 0_0402_5%
<9> VR_SVID_CLK VRHOT# PGND
0.01U_0402_25V7K

PR222 1K_0402_1% VGATE 12 34 PC193

LG1 <61> +5VS

2
VRDY LG1
1

13 33 2.2U_0603_10V7K CSP2A
+1.05VS VSN SW1 SW1 <61>
PC194 14 32
+3VS VSP HG1 HG1 <61>
DIFF_CPU 15 31 BST1 1 PR225 2 BST1_1 2 1

CSCOMP
2

DIFF BST1

TRBST#
4.7_0603_5%

DROOP

CSSUM

DRVEN
CSREF
1

COMP
75_0402_1%

TSNS
PC195 0.22U_0603_10V7K

CSP3
CSP2
CSP1

PWM
IOUT
ILIM
1
PR226

FB
PR227 PC200 +5VS
PC196 @ 10K_0402_5% PR228

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
43P_0402_50V7K 3P: 73.2K
2

1 2 10P_0402_50V8J 1 PR228 2
<45> VR_HOT# 2P: 41.2K
2

COMP_CPU

0_0402_5%
CPU2@ FB_CPU 73.2K_0402_1% 41.2K_0402_1% Option for 3Phase: @
TRBST#
<16,6> VGATE

PR230
CPU2@
PR229 CPU2@ 2 phase CPU

DROOP
CPU3@

TSENSE
ILIM_CPU
1 2 VSN 3P: 22p 2Phase: install
<9> VSSSENSE 6132_PWM <61>
1

0_0402_5% CPU3@
PC197 2P: 10p
DRVEN <61>

2
PR232 1000P_0402_50V7K CSP3 1 PR2312 CSP3
SWN3 <61>
2

1
21K_0402_1%
1 2 VSP PC198 6.98K_0402_1%
<9> VCCSENSE
2
21K_0402_1%

@ PR268
0_0402_5% 1 2 PC199 3P: install
0.047U_0402_16V7K
CPU3@

.1U_0402_16V7K
2P: @

2
B B
CPU3@ PC200 CSP1 PR233 CSREF TSENSE

1
1 PR234 2 2 1 CSP2 PC208
1

1K_0402_1% CSP3 CSP2 1 PR235 2

SWN2 <61>

1
21K_0402_1%
22P_0402_50V8J 6.98K_0402_1%
PR233

@ PR269
PC201
PR236 PC202 PR237 PC203 3P: 21K 0.047U_0402_16V7K

2
1 2FB_CPU1 1 2 2 1COMP_CPU1 2 1 12.4K_0402_1%
PR238 PC204 49.9_0402_1% 6.04K_0402_1% 2P: 12.4K CPU2@ 1200P_0402_50V7K CSREF

8.25K_0402_1%
1 2FB_CPU3 1 2 470P_0402_50V7K 2200P_0402_50V7K CPU2@

PR240 1

2
10_0402_1% CSP1 1 PR239 2
CSREF <61> SWN1 <61>
CSCOMP

1
21K_0402_1%
0.033u_0402_16V7K 6.98K_0402_1% PH6

@ PR270
PR241 PR242 PC205 PC206
TRBST# 1 2 FB_CPU2 1 2 1000P_0402_50V7K 3P: 1500p 0.047U_0402_16V7K 100K_0402_1%_TSM0B104F4251RZ
1

2
0.033u_0402_16V7K

2P: 1200p

1
1

8.06K_0402_1% 806_0402_1%

1
PC207 CSREF @
CSSUM
2

PR243
CPU3@ PC208 CPU3@
PR244 1 2 1 2 SWN1
23.7K_0402_1%

1500P_0402_50V7K 130K_0603_1% PUT COLSE

2

.1U_0402_16V7K

PC969@QC PR245
TO VCORE
PC209

3P: 23.7K 1 2 SWN2

PR244

1 2 PC210 130K_0603_1% HOT SPOT

2P: 24.9K
1

330P_0402_50V7K PR246
24.9K_0402_1% 1 2 SWN3
1

CPU2@ 130K_0603_1%
CPU3@ PR247 PC212 1 2 PC211 CPU3@
CSCOMP 1 2 DROOP 1 2 CSREF 330P_0402_50V7K 3P: install
PUT COLSE 2P: @
PR247 806_0402_1% 1000P_0402_50V7K PR248 PR249
3P: 806 <45> IMVP_IMON TO VCORE 1 2
NTC_PH201 1 2
2P: 1K Phase 1 75K_0402_1%
165K_0402_1%
A Inductor PH7 A

1K_0402_1% 2 1
CPU2@
220K_0402_5%_ERTJ0EV224J
<BOM Structure>

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 CPU_CORE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
LA-8692P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Tuesday, June 05, 2012 Sheet 60 of 66
5 4 3 2 1
 5 4 3 2 1

CPU_B+ 2012/03/02 CPU_B+

change PC222 from OS-cap to D2 size

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
B+

0.1U_0402_25V6

0.1U_0402_25V6
1000P_0402_50V7K

2200P_0402_25V7K

2200P_0402_25V7K
5

5
PL14
PQ27 HCB4532KF-800T90_1812 PQ28

1
1 2

PC521

PC213

PC214

PC215

PC216

PC217

PC218

PC219

PC220
CPU_B+
1 1

470P_0603_50V7K

470P_0603_50V7K
68U_25V_M_R0.36

1000P_0603_50V7K

68U_25V_M_R0.36
2

2
4 4
<60> HG1 <60> HG2

1
+ +

PC221

PC222

PC223

PC224

PC225
+VCC_CORE +VCC_CORE
AON6428L_DFN8-5 AON6428L_DFN8-5

2
PL15 2 2

3
2
1

3
2
1
D D
0.36UH_VMPI1004AR-R36M-Z03_30A_20% PL16
0.36UH_VMPI1004AR-R36M-Z03_30A_20%
1 4 1 4
<60> SW1 <60> SW2

1
2 3 2 3

5
PR250 PR251
4.7_1206_5% 4.7_1206_5%
PQ29 PQ30

2
AON6504 1N DFN PR252 AON6504 1N DFN
4 V1N_CPU2 1 4 V2N_CPU 2 PR253 1 CSREF
<60> LG1 CSREF <60> <60> LG2

1SNUB_CPU1

SNUB_CPU2
10_0402_1%
10_0402_1%

SWN1 <60> SWN2 <60>

3
2
1

3
2
1
PC226
680P_0402_50V7K

1
PC227

2
680P_0402_50V7K

2
CPU_B+
PR254
BST3 1 2 BST3_1

10U_0805_25V6K

10U_0805_25V6K
4.7_0603_5%

0.1U_0402_25V6

2200P_0402_25V7K
5
CPU3@
2

1
PQ31

PC229

PC230

PC231

PC232
PC228
0.22U_0603_10V7K CPU3@
1

2
CPU3@
4
PU15 CPU3@ CPU3@ CPU3@ CPU3@ +VCC_CORE
1 9
BST FLAG AON6428L_DFN8-5
C C
CPU3@ 2 8 HG3 PL17
<60> 6132_PWM
3
2
1

PWM DRVH CPU3@

2 PR255 1EN_CPU3 3 7 SW3 1 4
QC 45W CPU DC 35W CPU
<60> DRVEN EN SW VID1=0.9V VID1=1.05V
2K_0402_1%

1
+5VS 2 1VCC_CPU3 4 6 2 3
VCC GND IccMax=94A IccMax=53A
5

PR256 0.36UH_VMPI1004AR-R36M-Z03_30A_20%
1

0_0402_5% CPU3@
DRVL
5 LG3 PR257 Icc_Dyn=66A Icc_Dyn=43A
PQ32 CPU3@ 4.7_1206_5%
PC233 NCP5911MNTBG_DFN8_2X2
Icc_TDC=52A Icc_TDC=36A
2

2.2U_0603_10V7K CPU3@ AON6504 1N DFN R_LL=1.9m ohm R_LL=1.9m ohm

4 V3N_CPU 2 PR258 1 CSREF
CPU3@ CPU3@ OCP~110A OCP~65A
SNUB_CPU3

10_0402_1%
CPU3@
SWN3 <60>
3
2
1

PC234
680P_0402_50V7K
3Phase: install
2

2Phase:: @
CPU3@

CPU_B+ CPU_B+

2Phase: install
10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6

0.1U_0402_25V6
2200P_0402_25V7K

2200P_0402_25V7K
B 1Phase:: @ B
1

1
PC235

PC236

PC237

PC238

PC241

PC239

PC242

PC243
2

2
5

5
BSTA2 1 PR259 2 BSTA2_1
PQ33 PQ34

2
2.2_0603_5%
GFX@ PC240 GFX@
0.22U_0603_10V7K

1
4 4
GFX@

<60> HG1A GFX@ GFX@

GFX@

GFX@

GFX@ GFX@
GFX@

GFX@
PU16
AON6428L_DFN8-5 1 9 AON6428L_DFN8-5
+VCC_GFXCORE_AXG BST FLAG
3
2
1

3
2
1
PL18 2 8 HG2A PL19
<60> 6132_PWMA PWM DRVH
0.36UH 20% PDME064T-R36MS1R405 24A GFX@ 0.36UH 20% PDME064T-R36MS1R405 24A
GFX@ 1 2 DRVEN 2 PR260 1EN_GFX2 3 7 SW2A 1 2 +VCC_GFXCORE_AXG
<60> SW1A EN SW
2K_0402_1% GFX@
1

+5VS 2 1VCC_GFX2 4 6
@ 4.7_1206_5%

VCC GND
5

5
PR262 GFX@
PR261

1
0_0402_5% 5 PQ36
GFX@

0_0402_5%
PQ35 DRVL

PR264
GFX@

1
NCP5911MNTBG_DFN8_2X2 AON6504 1N DFN PR263 @
2

AON6504 1N DFN PC244 4.7_1206_5% PR266

0_0402_5%

GFX@
4 2.2U_0603_10V7K LG2A 4 2 1 CSREFA
PR265

<60> LG1A
2

2
10_0402_1%
SNUB_GFX1

SNUB_GFX2
GFX@ GFX@ GFX@
2

2 PR267 1
CSREFA <60>
3
2
1

3
2
1
@ 680P_0402_50V7K

SWN2A <60>
GFX@

10_0402_1%
GFX@

GFX@
1

1
PC246 @
PC245

SWN1A <60>
2

680P_0402_50V7K

2
A A

QC 45W GT2 DC 35W GT2

VID1=1.23V VID1=1.23V
IccMax=46A IccMax=33A
Security Classification LC Future Center Secret Data Title
Icc_Dyn=37A Icc_Dyn=20.2A
Icc_TDC=38A Icc_TDC=21.5A Issued Date 2012/07/01 Deciphered Date 2014/07/01 CPU_CORE
R_LL=3.9m ohm R_LL=3.9m ohm THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
OCP~55A OCP~40A AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C LA-8692P 0.2

Date: Tuesday, June 05, 2012 Sheet 61 of 66

5 4 3 2 1
 5 4 3 2 1

+VCC_CORE Below is 458544_CRV_PDDG_0.5 Table 5-8.

+CPU_CORE +VCC_GFXCORE_AXG
1 1 1 1 1
5 x 22 F (0805)
PC247
Socket Bottom 5 x (0805) no-stuff
PC248 PC249 PC250 PC251 +VCC_GFXCORE_AXG
2
10U_0805_6.3VAM
2
10U_0805_6.3VAM
2
10U_0805_6.3VAM
2
10U_0805_6.3VAM
2
10U_0805_6.3VAM sites

D
7 x 22 F (0805) D
Socket Top 2 x (0805) no-stuff

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1 1 1 1 1 1 1 1
sites

PC258

PC259

PC260

PC261

PC262

PC263

PC264

PC265
1 1 1 1 1 1
PC252 PC253 PC254 PC255 PC256 PC257
10U_0805_6.3VAM 10U_0805_6.3VAM 10U_0805_6.3VAM 10U_0805_6.3VAM 10U_0805_6.3VAM 10U_0805_6.3VAM 2 2 2 2 2 2 2 2
2 2 2 2 2 2
+1.05VS
+VCC_CORE +1.05VS

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 GFX@ GFX@ GFX@ GFX@ GFX@ GFX@ GFX@ GFX@

PC271

PC272

PC273

PC274

PC275

PC276

PC277

PC278

PC279

PC280

PC281
22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
PC266 PC267 PC268 PC269 PC270 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2

PC282

PC283

PC284

PC285

PC286

PC287

PC288

PC289
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
2 2 2 2 2

2 2 2 2 2 2 2 2

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1 1 1 1 1 1 1 1
1 1 1 1 1

PC295

PC296

PC297

PC298

PC299

PC300

PC301

PC302
PC290 PC291 PC292 PC293 PC294 GFX@ GFX@ GFX@ GFX@ GFX@ GFX@ GFX@ GFX@
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 2 2 2 2 2 2 2 2
2 2 2 2 2 1 1 1

330U_D2_2VM_R9M

330U_D2_2VM_R9M

330U_D2_2VM_R9M
PC303

PC304

PC305
+ + +

C C
2 3 2 3 2 3
1 1

330U_D2_2VM_R6M

330U_D2_2VM_R6M
1 1 1 1 1

PC311

PC312
+ +
PC306 PC307 PC308 PC309 PC310
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
2 2 2 2 2 2 3 2 3
GFX@ GFX@ GFX@

1 1 1 1
PC313 PC314 PC315 PC316
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
2 2 2 2

+VCC_CORE
PC318 CPU3@

330U_D2_2VM_R9M

330U_D2_2VM_R9M

330U_D2_2VM_R9M

330U_D2_2VM_R9M

1 1 1 1 1 1
330U_D2_2VM_R9M

330U_D2_2VM_R9M

+ + + + + +
PC317

PC319

PC320

PC321

PC322

B 2 2 3 2 3 @ 2 3 2 3 2 B

2012/02/29
DC:PC317, PC319, PC321, PC322 (330uF/9m +-20% *4)
QC:PC317, PC318, PC319, PC321, PC322 (330uF/9m +-20% *5)
P/N:SGA0000610J (no link)

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 CPU_CORE1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
LA-8692P 0.2

Date: Tuesday, June 05, 2012 Sheet 62 of 66

5 4 3 2 1
 5 4 3 2 1

Charge Option() bit[8]=1

2012/02/29
P3 change PR362 from 1206 B+
P2 to 2512 size
PQ57 PQ58
AO4423L 1P SO8 AO4423L 1P SO8 PL25
8 1 1 8
VIN 7 2 2 7 0.01_2512_1% PR362 1UH_PCMB061H-1R0MS_7A_20% CHG_B+
6 3 3 6
5 5 1 4 1 2 PQ59
AO4423L 1P SO8

@ 10U_0805_25V6K

@ 10U_0805_25V6K
2 3 SH00000AA0J 1 8

4
D D
2 7

2
PC491 3 6

2200P_0402_50V7K
PC492

PC493
PQ60 5600P_0402_25V7K 5

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
1 2
47K_0402_5%

1
1

2
200K_0402_1%
0.1U_0603_25V7K

PC495

4
1
PR363

PC494

PC499

PC500
DTA144EUA_SC70-3 DISCHG_G
3

PC496

PR364
1 2

1
PR365
PC497 @ 47K_0402_1%
2

2
2 0.1U_0603_25V7K 1 2

2
ACN VIN

2ACOFF-1

1SS355_SOD323-2
2
1

ACP PR366

1DISCHG_G-1
10K_0402_1%
1

2
PD9
P2-1 PR367

0.1U_0603_25V7K

1
2 200K_0402_1%
PQ61 PQ62

1
PC501 PC502 DTC115EUA_SC70-3

1
DTC115EUA_SC70-3 +3VALW P
PR368 <55,63> ACPRN 1 2 2 1 PD10
3

20K_0402_1% +3VALW P 1SS355_SOD323-2

0.1U_0603_25V7K 2 1 2

100K_0402_1%
6 2
6

@ 10K_0603_1%
1

1
PR370 @
PQ64A PC503
150K_0402_1%

2
PR369

PR371
PQ63A
2 2N7002KDW -2N_SOT363-6 2N7002KDW -2N_SOT363-6 0.1U_0603_25V7K

6
2 PQ65A

0.1U_0603_25V7K
BATT_OUT <54,63> 2 1
1

1
PC504
VIN PR372 @ PR373 @ 2N7002KDW -2N_SOT363-6
1

1
C 2 1 1 2 2 PACIN C

10K_0402_5%

10K_0402_5%
2

2
PR375 @

PR376 @
4.7M_0603_1% P2
390K_0603_1%

2
1
P2-2

39.2K_0402_1%

1
5
6
7
8
PR374
2N7002KDW-2N_SOT363-6

1
PR377 PQ66
3
PQ63B

10_1206_5% AO4406AL_SO8

ACOK

CMPIN

CMPOUT

ACP

ACN
1

1
PR378 PR379 <45,54> ADP_I 1 2
2

47K_0402_1% 64.9K_0603_1% 21
PACIN 1 2 5 1 2 6 TP 4
<63> PACIN ACDET PC506
20 1 2
SH000005Y8J
PC507 .1U_0603_25V7K PC505
4

2 1 1 2 7 VCC PL26
PR380 IOUT

3
2
1
1U_0603_25V6
1

PQ67 0_0402_5% 100P_0603_50V8 19 4.7UH_PCMB104E-4R7MS_10A_20%

PHASE
DTC115EUA_SC70-3 <45,49,54> EC_SMB_DA1 1 2 8
SDA
PU19 PR381 BATT+
PR383 BQ24737RGRR_VQFN20_3P5X3P5 LX_CHG 1 2 1
CHG 4
PR382 0_0402_5% 18 DH_CHG
HIDRV

5
6
7
8
1 2ACOFF-12 <45,49,54> EC_SMB_CK1 1 2 9 2 0.01_2512_1%
3
<45> ACOFF SCL

1
10K_0402_5% PR385 PC508 PQ68

4.7_1206_5%
PR386
PR384 4.7_0603_5% 0.047U_0603_16V7K
1

1 2 10 17 BST_CHG 1 2 2 1

10U_0805_25V6K

10U_0805_25V6K
TPC8A03-H 1N SO8
+3VALW P ILIM BTST
1

16251_SN
PR387 147K_0402_1% PD11
3

RB751V-40_SOD323-2 4

LODRV
0_0402_5%

1
16 2 1

PC509

PC510
PR388

GND
SRN

SRP
REGN
BM
100K_0402_1%
2

2N7002KDW-2N_SOT363-6

2
680P_0603_50V7K
BQ24737_VDD
11

1 12

13

14

15

3
2
1
3

1
PQ64B

PC511
10_0603_5%
6.8_0603_5%

2
1
PR390
BM#
PR389
PC512
5
10K_0402_5%

<54,63> BATT_OUT 1U_0603_25V6

2
2
PR391 @

B B
2

2012/02/29
4

PC513 DL_CHG
0.1U_0603_25V7K change PR381 from 1206
2 1 to 2512 size
1

+3VS PC514
0.1U_0603_25V7K
2

BQ24737_VDD

PR392
10K_0402_1%
1

1
1 2
ACIN <45>
PR394
PR393 10K_0402_1%
47K_0402_1%
PACIN <63>
2

1
2N7002KDW-2N_SOT363-6
3
PQ65B

PR395
ACPRN <55,63> 12K_0402_1%
5 2 <BOM Structure>
4

A A

For disable pre-charge circuit.

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 CHARGER

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
LA-8692P 0.2

Date: Tuesday, June 05, 2012 Sheet 63 of 66

5 4 3 2 1
 5 4 3 2 1

D D

PCH_PWR_EN# 2
U14,+3VALW_PCH

V
AC A1
MODE VIN QH4,+5VALW_PCH

V V
A2 A3 B5

VV
PU2 A5 2

V
PU3

V
B+ +3VALW_PCH
+3VALW B7 2 3
BATT V +5VALW_PCH
BATT
MODE
B1
B2
B+ B4 V
V

V
EC 4 SYS_PWROK
13
PQ2 PCH_RSMRST# PM_DRAM_PWRGD

V
V V PCH
B3 A5 B7 5 14
PBTN_OUT# H_CPUPWRGD
CPU

V V
V
51ON# EC_ON
PM_SLP_S3#
PM_SLP_S4# PLT_RST# 15
C C
PM_SLP_S5#
A4 B6 PM_SLP_A# 6
PM_SLP_SUS#

V
V
ON/OFF V
SYSON 7 SYSON# +1.5V

V
PU5
DGPU_PWR_EN 8a (DIS) VGA_ON
+3VSDGPU

V
8
Q6 11
SUSP#,SUSP U49

V
VGATE
+5VS

V
+1.5VSDGPU
U40

V
U20

V
+3VS +1.8VSDGPU VGA
U37
B B

V
U13

V
+1.5VS +1.0VSDGPU
PU28

V
PU8

V
+0.75V +VGA_CORE
VCCPPWRGOOD
PU998
V

V
PU9 PU7
+1.05VS_VCCP +VCCSA 8b (DIS)
VGA_PWROK

U47
CK505
VR_ON 9 PU1000
V
10
V

+CPU_CORE

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 Power sequence

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-8692P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Tuesday, June 05, 2012 Sheet 64 of 66
5 4 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List) Page 1 of 1

for PWR
Item Reason for change PG# Modify List Date Phase

1 Reserve 0.1uF for Charger IC 51 Reserve PC321 201109/27 B test

D
change PR322,PR407,PR408,PR503,PR511,PR606,PR804,PR827 to 2.2 ohm D

2 EMI Request
add PC526,PC527,PC970,PC971(470uF) 201109/27 B test
Remove one power rail +V1.05S_VCCPP
3 Combine 1.05V 51 B test
Pop PR722,PR712,PR718 201109/27

4 Discharge for +1.05VS_VGA by NV Request 53 Reserve PR528 201109/27 B test

unpop PR806
5 Set VGA_CORE VBOOT voltage 56
change PR813 to 147K ohm 201109/27 B test
6
For VGA_CORE power saving by NV Request 56 add PR838 0ohm 201109/27 B test

7 for CPU_CORE load line adjust 57 add PC969 201109/27 B test

8
to prevent MOS over temperature 55/58 change PQ702,PQ901,PQ902,PQ905 TPCA8065 201109/27 B test
C C
9 for CPU_CORE test 59 Reserve PC77,PC78 201109/27 B test

10 for VGA VID R-short 59 change PR318,PR319,PR320,PR321,PR322,PR323 footprint 201205/31 B test

11 Charger boost resistor For EMI 63 Change PR385 from 2.2ohm to 4.7ohm 201206/04 B test

12

13

14

B B

15

16

17
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 PIR (PWR)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
LA-8692P 0.2

Date: Tuesday, June 05, 2012 Sheet 65 of 66

5 4 3 2 1
 5 4 3 2 1

QIWY3 HW PIR List

NO DATE PAGE MODIFICATION LIST PURPOSE
EVT TO DVT
1 P7 Reserve R64 Reserve EC DRAMRST control pin for Deep S3
2 P16 Reserve R1457,R1455,R1447 Reserve SUSACK#,SUSWARN#,SLP_SUS# control signal for Deep S3
D 3 P16 Reserve Q118,R1120,R1121 Reverse SLP_SUS# to control +3V_PCH&+5V_PCH D

4 P16 Change AC_PRESENT Pull high source to +3V_DSW For Deep S3 function
5 P21 Remove R289 +5V_PCH control circuit change for Deep S3
6 P36 Reserve J8,Q104,C533,C526,R436 Reserve for AOAC function
7 P36 Change JP1 pin2,24,52 power source to +3VS_WLAN_AOAC Reserve for AOAC function
8 P42 Change EC GPIO pin setting (Impact pin 18,71,72,126,128) For DeepS3/AOAC function
9 P48 Reserve J11,J14,Q148,Q149,C38,C39 +3V_PCH&+5V_PCH control circuit for Deep S3
10 P45 change U49 symbol (without GND pad) For DFx issue
11 P46 change U40,U69 symbol (without GND pad) For DFx issue
12 P47 change JP10 type to SP01001B800 For DFx issue
13 P19 Reserve R207,R224 to contact WLAN wake even Reserve for AOAC function
14 P41 Change JSPK1 type to SP02000H700 For DFx issue
14 P19 Reserve R704 and R706 for GPIO69 PU&PD For SKU ID
15 P23 Change CV37,CV38 to 22P For Crystal EA request
16 P37 Change C968,C969 to 33P For Crystal EA request

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 PIR (HW)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
LA-8692P 0.2

Date: Tuesday, June 05, 2012 Sheet 66 of 66

5 4 3 2 1