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# Aim:

## To Study Binary Phase Shift Keying (BPSK) modulation and demodulation.

Apparatus:
1. Fixed output DC regulated power supplies of 12V & 5V.
2. Built-in carrier wave generator using IC 555.
3. Built-in data generator using IC 7490.
4. IC 4051 is used to build the PSK modulator.
5. Built in PSK Demodulator using IC TL084 & IC 7486.
6. The front panel of the instrument is printed circuit board (PCB). IC's are placed on the
front panel and important connections are brought on sockets.
7. Matlab
8. Comm.Sine Software

Theory:

In Binary Phase Shift Keying (BPSK) , the frequency of the sinusoidal carrier is shifted
according to the binary symbol. In other words, the frequency of a sinusoidal carrier is shifted
between two discrete values. However, the phase and the amplitude of the carrier is
unaffected. This means that we have two different frequency signals according to the binary
symbols.
Generation of BPSK signal
BPSK Transmitter

Figure 3.1

## BPSK generator scheme

A binary data sequence (101101) is applied as input to the Bipolar NRZ level Encoder which
gives the output as b (t). The NRZ level encoder converts the binary data sequence into
bipolar NRZ signal.
The output of the Bipolar NRZ level Encoder b (t) is fed to the Balanced Modulator in
The final output of the Balanced modulator is the required BPSK signal.

S.No. Input Digital Signal Biploar NRZ signal b(t) BPSK output signal

## 1 Binary 0 B(t) =-1 - 2 P cos ct

2 Binary 1 B(t)=+1 + 2 P cos ct

## Table 1: Shows input digital and corresponding Bipolar NRZ Signal

Balanced Ring Modulator:
In the BPSK generator we have a product modulator which is actually a balanced ring
modulator with two inputs. One input is the carrier while other input is the digital data.

Figure 3.2

## Graphical Representation of BPSK Signal

Figure 3.3
The figure 3.3(A) illustrates the Binary sequence 101101 and the figure 3.3(B) its equivalent
bipolar signal b(t).It may be overserved from the figure 3.3(B) that the signal b(t) is a NRZ
BIPOLAR SIGNAL. In fact, this signal directly modulates the carrier signal cos (2fct).

Principle of BPSK:
In binary phase shift keying (BPSK), binary symbol '1' and '0' modulate the phase of the
carrier. Let the carrier be,

## s(t) = Acos(2 f0t) (1)

'A' represents peak value of the sinusoidal carrier. In the standard 1 load register, the
power dissipated will be,
1
A 2
P= 2

A = 2 P (2)

When the symbol is changed, then the phase of the carrier is changed by 180 degrees (
For example,

## Symbol '1' => s1(t) = 2 P cos (2f0t) (3)

If next symbol is 0,

## s2(t) = - 2 P cos (2f0 t) + (5)

With the above equation we can define BPSK signals,

## s(t) = b(t) 2 P cos 2(f0t) + (6)

Here b(t) = +1 when binary '1' is to be transmitted 1 when binary '0' is to be transmitted.
Reception of BPSK signal

## Figure 3.4 Reception BPSK scheme

Waveforms:
Figure shows the input output waveforms for the diode ring modulator circuit.
Figure 3.5

1. Phase shift in received signal: This signal undergoes the phase change
depending upon the time delay from transmitter to receiver. This phase change is
normally fixed phase shift in the transmitted signal. Let the phase shift be O.
Therefore the signal at the input of the receiver is,

## s(t) = b(t) 2 P cos (2f0t + ) (7)

2. Square law device: Now from the received signal, a carrier is separated since this is
coherent detection. The received signal is passed through a square law device. At the output
of the square law device the signal will be,
cos2(2f0t+)

Here we have neglected the amplitude, because we are only interested in the
carrier of the signal.
We know that,
1+cos 2
cos 2 =
2

## 1+cos 2(2 f 0 t+)

2
cos (2f0t+ ) = 2

1 1
cos 2 ( 2 f 0 t+ )
= cos2 = 2 + 2

1
Here 2 is a DC level.

3. Bandpass filter:This signal is the passed through a bandpass filter whose passband is
1
centred around 2f0. Bandpass filter removes the dc level of 2 and its output we get,

cos 2 ( 2 f o t + )

## this signal has frequency of 2fo.

4. Frequency divider:The above signal is passed through a frequency divider by two.
Therefore the output of the frequency divider we get a carrier signal whose frequency is f o i.e.
cos ( 2 f o t+ )

## 5. Synchronous demodulator:The synchronous (coherent) demodulator multiplies the

input signal and the recovered carrier. At the output of multiplier we get,

## b(t) 2P cos (2f0t + ) cos (2f0t + ) = b(t) 2P cos2 (2f0t + )

1
= b(t) 2P * 2 * [1+ cos 2(2f0t + )

## = b(t) P /2[1+cos 2 ( 2 f 0 t + ) ] (8)

6. Bit synchronizer and integrator: The above signal is then applied to the bit
synchronizer and integrator. The integrator integrates the signal over one bit period. The bit
synchronizer takes care of starting and ending times of a bit.
At the end of the bit duration Tb, the bit synchronizer closes switch 52 temporarily.
This connects the output of the integrator to the decision device. It is equivalent to
sampling the output of the integrator.
The synchronizer then opens switch S2 and switch Si is closed temporarily. This
resets the integrator voltage to zero. The integrator then integrates next bit.
Let us assume that one bit period 'Tb' contains integral number of cycles of the carrier.
That is the phase change occurs in the carrier only at zero crossing. Thus BPSK
waveform has full cycles of sinusoidal carrier.

## To show that output of integrator depends upon transmitted bit

In the kth bit interval we can write output signal as,
kT b

## S0(kTb)= b(kTb) P /2 [1+cos 2 ( 2 f 0 t + ) ]dt

(k1 )T b

from equation 8

The above equation gives the output of an interval for kth bit. Therefore integration is
performed from (k-1)Tb to kTb . Here Tb is one bit period.

[ ]
kT b

( k1) T b
kT b

## Here [ 1+cos 2 ( 2 f 0 t+ ) ] = 0, because average value of sinusoidal waveform is

( k1 ) T b

zero if integration is performed over full cycles. Therefor above equation can be written as,
kT b

[ 1+cos 2 ( 2 f 0 t+ ) ] dt
so(kTb) = b(kTb) ( k1 ) T b

P/2

## Therefore, so(kTb) = b(kTb) P /2 Tb (9)

This equation shows that the output receiver depends on input i.e.
so(kTb) b(kTb)
Depending upon the values of b(kTb) ,the output of So (kTb) is generated in the receiver. This
signal is then given to a decision device which decides whether transmitted symbol was zero
or one.

## Bandwidth of BPSK Signal

1
The spectrum of the BPSK signal is centred around the carrier frequency fo. If fb = Eb

then for BPSK the maximum frequency in the baseband signal will be fb as shown in the
figure.
Figure 3.6
In this figure the main lobe is centered on carrier frequency fo + fb to fo fb.
Therefore, bandwidth of BPSK signal is, BW =Highest frequency Lowest
frequency in the main lobe =fo+fb(fofb)
BW = 2fb
Plot of Power Spectral Density

Figure 3.7

## Geometrical Representation of BPSK Signals

We know that BPSK signal carries the information about two symbols. Those are symbol '1'
and symbol '0'. We can represent BPSK signal geometrically to show those two symbols. We
know BPSK signal is given as,
s(t) = b(t) 2P cos (2f0t) (10)
Rearranging the above equation as,

## s(t) =b(t) PTb 1 (t)

(12)
The bit energy Eb is defined in terms of power `P' and bit duration Tb as,
Eb = PTb (13)

## thus on single axis of 1 (t)there will be two points.

One point will be located at + Eb and other point will be located at Eb :. This is
shown in the figure below.

## Figure 3.8 Geometrical representation of BPSK signal

At the receiver the point at + Eb represents symbol '1' and point Eb represents
symbol '0'. The separation between these two points represents the isolation in symbol/1' and
'0' in BPSK signal. This separation is normally called distance 'd'. It is clear distance between
the two points is,

D= + Eb -(- Eb

## Therefore, d=2 Eb (15)

As this distance 'd' increases, the isolation between symbols in BPSK signal is more.
Therefore probability of errors reduces.
Digital communication became important with the expansion of the use of computer
and data processing, and have continued to develop to a major industry providing the
interconnection of computer peripherals and transmission of data between distance
sites. Phase shift keying (PSK) is relatively new system, in which the carrier may be
phase shifted to 90 degree for a mark and by -90 degree for a space. PSK has a
number of similarities to FSK in many aspects, as an FSK frequency of the carrier is
shifted according to the modulating square wave.
The circuit diagram of the phase shift keying modulation and demodulation is
printed on the front panel. In this IC 8038 is basic waveform generator which
generates sine, triangular and square waveforms. The square wave generated by IC
8038 is at +15 V or -15V level. So this is converted into 5V Signal with the help of
transistor and diode. The square wave is used clock input at a decade counter
(IC7490) which generate the modulating data outputs. IC CD4051 is an analog
multiplexer to which carrier is applied with and without 180 degree phase shift to the
two multiplexer to which carrier is applied with or without phase shift is steered to the
output. The 180 degree Phase shift to the carrier signal created by an operational
amplifier using IC 741. During the demodulation, the PSK signal is converted into a
+5V square wave signal using a transistor and is applied to 1 input of an EX-OR gate.
To the second input of the gate, carrier signal is applied after conversion into a +5V
signal. So the EX-OR gate output is equivalent to the modulating data signal.

## Figure 3.9 BPSK KIT

8038 IC:
The 8038 waveform generator is a monolithic integrated circuit,capable of producing
sine,square,triangular sawtooth and pulse waveform of high accuracy with a minimum
of external component. The frequency can be selected externally over a range from
less than 1/1000hz to more than 1Mhz and is highly stable over a wide temp and
supply voltage range. Frequency modulation and sweeping can be accomplished with
an external voltage and the freq can be programmed digitally through the use of either
resistor or capacitor .The waveform generator utilises advanced monolithic
technology such as thin film resistor and schottky barrier diode. The 8038 voltage
controlled oscillator can be interfaced with phase lock loop circuitry to reduced temp
drift to below 50ppm/degreecelsius.
Pin Configuration

## PIN NUMBER DESCRIPTION

2 SWO- SINE WAVE OUTPUT
3 TO- TRIANGLE WAVE OUTPUT
4 DCFA1-DUTY CYCLE FREQUENCY
5 DCFA2- DUTY CYCLE FREQUENCY
6 V+ - POSITIVE SUPPLY
7 FM BIAS- FREQUENCY MODULATION
BIAS
8 FM SWEEP- FM SWEEP INPUT
9 SQ OUT- SQUARE WAVE OUTPUT
10 TC- TIMING CAPACITOR
11 V- - V-//GROUND
12 SW AJ- SINE WAVE ADJUST
13 NC-NOT CONNECTED
7490 IC:
The 90 is 4 stage ripple counter containing a high speed flip-flop
acting as a devide-by-2 and 3flip-flop connected as a divide-by-5
counter flip flop. It can be connects to provide a 50% duty cycle
output. In the BCD mode, HIGH signals on the master set inputs set
the output to BCD 9, HIGH signals on the master reset inputs force
all outputs LOW.

PIN DIAGRAM:

## PIN FUNCTION NAME

1 Clock input 2 Input2
2 Reset1 R1
3 Reset2 R2
4 Not Connected NC
5 Supply Voltage VCC
6 Reset3 R3
7 Reset5 R4
8 Output3 QC
9 Output2 Q3
10 Ground GROUND
11 Output4 Q0
12 Output1 Q4
13 Not Connected NC
14 Clock Input 1 INPUT1

CD4051 IC:
In digital modulation techniques a set of basis functions are chosen for a
particular modulation scheme.Generally the basis functions are orthogonal to
each other. Basis functions can be derived using Gram Schmidt
orthogonalization procedure.Once the basis function are chosen, any vector
in the signal space can be represented as a linear combination of the basis
functions.

In Binary Phase Shift Keying (BPSK) only one sinusoid is taken as basis
function modulation. Modulation is achieved by varying the phase of the basis
function depending on the message bits. The following equation outlines BPSK
modulation technique.

## $$\begin{array}{l} S_{0}(t) = A cos (\omega t) \rightarrow \mbox{represents 0}\\ S_{1}(t) = A cos (\omega t+\pi ) \rightarrow \mbox{represents 1}\\ \end{array}$$

The constellation diagram of BPSK will show the constellation points lying
entirely on the x axis. It has no projection on the y axis. This means that the
BPSK modulated signal will have an in-phase component (I) but no quadrature
component (Q). This is because it has only one basis function.

## A BPSK modulator can be implemented by NRZ coding the message bits (1

represented by +ve voltage and 0 represented by -ve voltage) and multiplying
the output by a reference oscillator running at carrier frequency .

PIN DESCRIPTION
PIN No. SYMBOL NAME AND FUNCTION
3 X Common Input/output
6 INH Inhibit Inputs
7 VEE Supply Voltage
8 VSS Ground
11,10,9 A,B,C Binary Control Inputs
13,14,15,12,1,5,2,4 X0~X7 Independent Inputs/Outputs
16 VX Positive Supply Voltage

## 7486 PSK Demodulator

The BPSK generation and demodulation parts of the set-up can be represented
by the block diagram in Fig.1. The second Multiplier and the Tuneable Low-
pass filter module are used to implement a product detector to recover the
digital data from the BPSK.
Fig.1 Diagram of set up of this experiment.

In phase shift keying (PSK), the phase of a carrier is changed according to the
modulating waveform which is a digital signal. In BPSK modulator the
transmitted signal is a sinusoid of fixed amplitude. It has one fixed phase
when the data is at one level and when the data is at the other level, phase is
different by 180 . A Binary Phase Shift Keying ( BPSKD ) signal can be defined
as:

## The demodulation of a BPSK modulated signal, the carrier must be in phase

and frequency synchronism with the carrier available at the transmitter. The
carrier for the purpose of demodulation can either be transmitted along with
the modulated signal or extracted from the modulated signal at the receiver.
Two commonly used techniques of carrier recovery are signal squaring and
Costas loop .

message waveform

## 2. Regeneration from the bandlimited waveform back to the binary

message bit stream.

## Translation back to baseband requires a local, synchronized carrier.

Stage 1
Translation back to baseband is achieved with a synchronous
demodulator. This requires a local synchronous carrier. In this
experiment a stolen carrier will be used.

Stage 2
The translation process does not reproduce the original binary
sequence, but a band limited version of it. The original binary sequence
can be regenerated with a detector. This requires information regarding
the bit clock rate. If the bit rate is a sub-multiple of the carrier frequency
then bit clock regeneration is simplified.

PIN DIAGRAM:

## Pin Name Purpose

1 GND Ground reference voltage, low level (0 V)
2 TRIG Pin goes high and a timing interval starts when this input falls below 1/2 of
CTRL voltage (which is typically 1/3 of Vcc, when CTRL is open).
3 OUT This output is driven to approximately 1.7V below +Vcc or GND.
4 RESET A timing interval may be reset by driving this input to GND, but the timing
does not begin again until RESET rises above approximately 0.7 volts.
Overrides TRIG which overrides THR.
5 CTRL Provides "control" access to the internal voltage divider (by default, 2/3
Vcc)
6 THR The timing (OUT high) interval ends when the voltage at THR is greater
than that at CTRL.
7 DIS Opencollector output which may discharge a capacitor between intervals. In
phase with output.
8 VCC Positive supply voltage, which is usually between 3 and 15 V depending on
the variation.
Internal Configuration of 555 timer IC

PROCEDURE:
FOR MODULATION
1. Connect the carrier output of the carrier generator (IC 8038) to the carrier input of
the PSK modulator through patch chord. Also connect any data output from the
data outputs of the data generator to the data input of the PSK modulator.
2. Connect the channel "1" of CRO across PSK output & channel "2" across data
input on a dual trace oscilloscope.
3. Switch ON the instrument using ON/OFF toggle switch provided on the front
panel.
4. Observe the output wave shapes on CRO.
5. Change the data inputs and observe the PSK output on CRO.

FOR DEMODULATION:
1. Connect the PSK output to the PSK input of the PSK demodulator.
2. Connect the carrier to the carrier input of the PSK demodulator.
3. Connect the channel 1 of the CRO across output of demodulator.
4. Observe the demodulated output on the CRO.

PRECAUTIONS:
1. Connections should be made properly.
2. Analyse the output waveforms carefully.

MATLAB CODE
CODE MNEMONICS
1. clc; %clear command window
2. clear all; %clear all variable
3. b = input('Enter the bit stream = '); %x=
4. n = length(b); %define length of bit stream
5. t = 0:0.01:n; %time interval
6. x = 1:1:(n+1)*100;
7. for i = 1:n %loop start for i
8. if (b(i)== 0) %conditional statement
9. u(i)= -1;
10. else
11. u(i)=1;
12. end %end of if loop
13. for j = i:0.1:i+1 %executes statements specific no. of times
14. bw(x(i*100:(i+1)*100)) = u(i);
15. end %end of i loop
16. end %end of j loop
17. bw = bw(100:end);
18. sint = sin(2*pi*t);
19. st = bw.*sint;
20. subplot(3,1,1); %create axis in tiled position
21. plot(t,bw);
22. xlabel('n ---->');
23. ylabel('Amplitude ---->');
24. title('Input Bit Stream'); %add title to current axis
25. grid on ;
26. axis([0 n -2 +2]);
27. subplot(3,1,2);
28. plot(t,sint);
29. xlabel('Time ---->');
30. ylabel('Amplitude ---->');
31. title('Carrier Wave'); % add title to current axis
32. grid on ; %add major grid line to current axis
33. axis([0 n -2 +2]);
34. subplot(3,1,3);
35. plot(t,st); %plot the column of Y versus the index of each value
36. xlabel('Time ---->'); %label the x-axis of current axis with string
37. ylabel('Amplitude ---->'); %label the y-axis of current axis with string
38. title('BPSK Wave');
39. grid on ;
40. axis([0 n -2 +2]);

OUTPUT WAVEFORM
Figure 3.11 Output Waveforms