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Instructions for Course and Assignments

Course Resources
In addition to the course lectures, it is highly recommended to use other reference materials including
books and some best papers available.

These resources are put together to enable better learning for Verification Excellence online courses on SystemVerilog and
other Verification topics

Language Reference Manual

1) Free download of latest LRM 1800-2012

2) System Verilog online reference Guide Very useful reference guide from Aldec

Books: (Google these and you might be lucky to find a free copy for download for some)

1) Writing Testbenches using SystemVerilog Janick Bergeron

2) SystemVerilog for Verification Chris Spear

3) Principles of Functional Verification Andreas Meyer

4) Verilog and System Verilog Gotchas Stuart Southerland

5) SystemVerilog Assertions Handbook: for Formal and Dynamic Verification By Ben Cohen, Srinivasan Venkataramanan,
Ajeetha Kumari

6) System Verilog Assertions and Functional Coverage Guide to Language Methodology and Applications by Ashok B


1) Verification Excellence Q & A Forums

2) Verification Academy Forums

3) Verification Guild Forums

4) Accelera Forums

Blogs to Follow:

1) Mentor Graphics blogs on Verification Horizon

2) Verification On Web Blog from CVC

3) SystemVerilog Blogs on blog-spot on SystemVerilog Blog Spot

Reference Websites:

1) Testbench in Good collection of reference material for SV, OVM, UVM etc

2) Doulos SystemVerilog Another Good collection of reference material for SV, OVM, UVM etc
- See more at: http://www.verificationexcellence.in/references/course-resources-systemverilog-general/#sthash.jFaCz4zX.dpuf

Of all the most important would be to download a copy of the IEEE spec (1800-2012) for which a link is
provided above.

Please also follow some of the blogs and also make best use of the Q&A forums for general questions.

Please follow the link below to have a list of reference examples and also a reference to the course project.

1) Assignment - Buliding SystemVerilog testbench for an Ethernet switch

To make your learning thorough, it is recommended to do a complete project by applying the various
concepts learned through out the course.
You can either do parts of the assignment as you keep learning different sections or attempt the project
together at end of the course

Reference Code:
Reference code is available for assignment on following URL. However it is highly recommended that
students take their own initiative to understand the details and do the assignment on their own.
1. https://github.com/VerificationExcellence/SystemVerilogReference/tree/master/projects/ethernet
2. http://www.edaplayground.com/x/4dD

Following is what you need to do:

1. Understand details about the DUT to be verified from the first exercise/lecture

This is a simple 2x2 ethernet switch as shown below. Packet format is also shows as below.

2. Think about how you will approach verifying this design and come up with a testbench
architecture and stimulus needs. Follow more details as per the Assignment Lecture

3. You can either write the full design RTL for the switch or just use it from reference code on github
or edaplayground and just focus more on building testbenches

4. Code a SystemVerilog interface file that can be used to connect the testbench to design
5. You can use the sample input and output signals as shown below or refer to the reference code
6. Now you need to start building testbench components and here is how a testbench would look
like. Basically you would need a Packet generator that can randomly generate packets (SV class objects)
and those can be send to the driver following the actual interface protocol. You would also need monitors
at input and output and a scoreboard/checker component to check for correctness. More details are
available in the corresponding lecture.
7. Once you implement all of these you can build a top level module and instantiate DUT and
testbench top and then try to run basic simulations.